Task processing method and device based on heterogeneous chip, storage medium, and electronic device

Abstract

The present disclosure relates to a task processing method and device based on heterogeneous chips, a storage medium, and an electronic device, and relates to the field of computer technology. The method includes: preprocessing original data to be processed to obtain data processing tasks and task categories included in the original data to be processed; controlling task processing units to execute data processing tasks and obtain task processing results; calculating current parameter values ​​of field programmable logic gate arrays based on the task processing time and current load data of the field programmable logic gate arrays included in the task processing results; determining the current operating state of the field programmable logic gate array based on the current parameter values, and adjusting the operating frequency of the field programmable logic gate array and / or the number of task processing units based on the current operating state and a preset task execution strategy. The present disclosure improves the processing efficiency of data processing tasks.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of computer technology, and in particular, to a task processing method based on heterogeneous chips, a task processing device based on heterogeneous chips, a computer-readable storage medium, and an electronic device. Background Art

[0002] In some terminal devices, heterogeneous chips are needed to perform data analysis and / or data processing on the business data generated by certain applications during operation; at the same time, in the specific data analysis process, business data with different data volumes and different business functions need to be processed according to different business scenarios.

[0003] However, the inherent heterogeneous chip-based system computing architecture cannot adaptively allocate corresponding computing resources to the business data according to the specific business scenario and data volume during the process of processing business data, which leads to the following problems: On the one hand, when the data volume is large, the corresponding computing resources cannot be allocated to it in a timely manner, resulting in low processing efficiency of the data processing task; on the other hand, when the data volume is small, most of the computing resources are idle, resulting in a waste of resources.

[0004] Therefore, it is necessary to provide a new task processing method and device based on heterogeneous chips.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention

[0006] The purpose of the present disclosure is to provide a task processing method based on heterogeneous chips, a task processing device based on heterogeneous chips, a computer-readable storage medium and an electronic device, thereby at least to a certain extent overcoming the problem of low processing efficiency of data processing tasks caused by the limitations and defects of related technologies.

[0007] According to one aspect of the present disclosure, a task processing method based on heterogeneous chips is provided, comprising:

[0008] Preprocessing the original data to be processed to obtain data processing tasks included in the original data to be processed and task categories of the data processing tasks;

[0009] Allocating a task processing unit corresponding to the task category to the data processing task in a field programmable logic gate array, and controlling the task processing unit to execute the data processing task and obtain a task processing result;

[0010] Calculating a current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array;

[0011] The current working state of the field programmable logic gate array is determined according to the current parameter value, and the working frequency of the field programmable logic gate array and / or the number of the task processing units are adjusted according to the current working state and a preset task execution strategy.

[0012] In an exemplary embodiment of the present disclosure, calculating a current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array includes:

[0013] parsing the task processing result to obtain the task execution result, task processing time, and current load data of the field programmable logic gate array of the data processing task; wherein the current load data includes the number of unprocessed data processing tasks and the number of occupied task processing units;

[0014] The current parameter value of the field programmable logic gate array is calculated based on the number of unprocessed data processing tasks, the occupied number of task processing units and the task processing time; wherein the current parameter value includes multiple ones of current power consumption, current resource usage, current latency rate, current load rate and current data concurrency rate.

[0015] In an exemplary embodiment of the present disclosure, calculating the current parameter value of the field programmable gate array according to the number of unprocessed data processing tasks, the number of occupied task processing units, and the task processing time includes:

[0016] Calculating the current power consumption and current resource usage of the field programmable logic gate array according to the occupied number of the task processing units;

[0017] Calculating a current delay rate of the field programmable logic gate array according to the task processing time;

[0018] According to the number of the unprocessed data processing tasks, a current load rate and a current data concurrency rate of the field programmable logic gate array are calculated.

[0019] In an exemplary embodiment of the present disclosure, the preset task execution strategy includes at least one of the following strategies:

[0020] The standard power consumption of the field programmable logic gate array is greater than a first preset threshold and less than a second preset threshold;

[0021] The standard resource usage of the field programmable logic gate array is greater than a third preset threshold and less than a fourth preset threshold;

[0022] The current delay rate of the field programmable logic gate array is greater than a fifth preset threshold and less than a sixth preset threshold;

[0023] The standard load rate of the task processing unit included in the field programmable logic gate array is greater than a seventh preset threshold and less than an eighth preset threshold;

[0024] The current data concurrency rate of the field programmable logic gate array is greater than a ninth preset threshold and less than a tenth preset threshold.

[0025] In an exemplary embodiment of the present disclosure, adjusting the operating frequency of the field programmable logic gate array and / or the number of the task processing units according to the current working state and a preset task execution strategy includes:

[0026] Determine whether the current power consumption, current resource usage, current latency rate, current load rate, and current data concurrency rate included in the current working state meet the threshold conditions included in the preset task execution strategy;

[0027] If the current power consumption and / or the current resource usage is less than the first preset threshold and / or the third preset threshold, and the current latency rate and / or the current data concurrency rate is greater than the sixth preset threshold and / or the tenth preset threshold, increasing the operating frequency of the field programmable logic gate array and / or the number of the task processing units;

[0028] If the current power consumption is greater than the second preset threshold, and the current delay rate and / or the current load rate and / or the current concurrency rate is less than the fifth preset threshold and / or the seventh preset threshold and / or the ninth preset threshold, the operating frequency of the field programmable logic gate array and / or the number of task processing units are reduced.

[0029] In an exemplary embodiment of the present disclosure, the task processing method further includes:

[0030] If the current power consumption and / or the current resource usage is less than the first preset threshold and / or the third preset threshold, the current latency rate and / or the current data concurrency rate is greater than the sixth preset threshold and / or the tenth preset threshold, and there is an idle task processing unit among the task processing units processing the first task category, and the task processing units processing the second task category are all in working state, then the operating frequency of the field programmable logic gate array is increased, the number of task processing units processing the first task category is reduced, and the number of task processing units processing the second task category is increased.

[0031] In an exemplary embodiment of the present disclosure, increasing the operating frequency of the field programmable logic gate array and / or the number of the task processing units includes:

[0032] A preset bitstream loading file is called to adjust the programmable logic circuit of the field programmable logic gate array to increase the operating frequency and / or increase the number of task processing units.

[0033] In an exemplary embodiment of the present disclosure, the heterogeneous chip-based task processing method further includes:

[0034] Calculating a first difference and / or a second difference between the first preset threshold and / or the third preset threshold and the current power consumption and / or the current resource usage;

[0035] Calculating a third difference and / or a fourth difference between the current latency rate and / or the current data concurrency rate and the sixth preset threshold and / or the tenth preset threshold;

[0036] The operating frequency value and the number of task processing units that need to be increased for the field programmable logic gate array are calculated according to the first difference and / or the second difference, the third difference and / or the fourth difference.

[0037] In an exemplary embodiment of the present disclosure, before allocating a task processing unit corresponding to the task category to the data processing task in the field programmable gate array, the heterogeneous chip-based task processing method further includes:

[0038] The registers of the field programmable logic gate array are configured; wherein the registers include one or more of a reset signal of the task processing unit, a signal indicating whether the task processing unit is in an idle state, a task category that the task processing unit can support, and a data service identification signal included in a data processing task that the task processing unit can process.

[0039] In an exemplary embodiment of the present disclosure, preprocessing is performed on original data to be processed to obtain data processing tasks included in the original data to be processed and task categories of the data processing tasks, including:

[0040] Based on the preset upper-layer application requirement interface, call the interface function corresponding to the front-end application and receive the original data to be processed sent by the front-end application;

[0041] The original data to be processed is parsed to obtain data processing tasks included in the original data to be processed and task categories of the data processing tasks; wherein the task categories include at least one of face recognition, data encryption, and data decryption.

[0042] In an exemplary embodiment of the present disclosure, when the task category is face recognition, controlling the task processing unit to execute the data processing task and obtain the task processing result includes:

[0043] Controlling the task processing unit to process the face image to be identified included in the data processing task using a preset convolutional neural network model to obtain a feature value of the face to be identified;

[0044] Performing feature comparison on the facial feature values ​​to be identified and the original facial feature values ​​in a preset feature value library to obtain a task execution result;

[0045] The task processing result is generated according to the task execution result, the task processing time consumed for identifying the facial features to be identified, and the current load data of the field programmable logic gate array.

[0046] In an exemplary embodiment of the present disclosure, performing feature comparison on the facial features to be identified and the original facial features in a preset feature value library to obtain a task execution result includes:

[0047] Calculating the Euclidean distance between the facial feature value to be identified and the original facial feature value in the feature value library in the field programmable logic gate array;

[0048] A similarity comparison result between the facial features to be identified and the original facial features is obtained based on the Euclidean distance.

[0049] In an exemplary embodiment of the present disclosure, when the task category is data encryption and / or decryption, controlling the task processing unit to execute the data processing task and obtain the task processing result includes:

[0050] Controlling the task processing unit to encrypt and / or decrypt the data to be encrypted and / or the data to be decrypted included in the data processing task using a preset encryption algorithm and / or a preset decryption algorithm to obtain a task execution result;

[0051] The task processing result is generated according to the task execution result, the task processing time consumed for encrypting and / or decrypting the data to be encrypted and / or the data to be decrypted, and the current load data of the field programmable logic gate array.

[0052] According to one aspect of the present disclosure, a task processing device based on a heterogeneous chip is provided, comprising:

[0053] A data preprocessing module is used to preprocess the original data to be processed to obtain the data processing tasks included in the original data to be processed and the task categories of the data processing tasks;

[0054] a data processing task execution module, configured to allocate a task processing unit corresponding to the task category to the data processing task in a field programmable logic gate array, and control the task processing unit to execute the data processing task and obtain a task processing result;

[0055] a parameter value calculation module, configured to calculate a current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array;

[0056] an adjustment module, configured to determine a current operating state of the field programmable logic gate array according to the current parameter value, and to adjust an operating frequency of the field programmable logic gate array and / or the number of task processing units according to the current operating state and a preset task execution strategy.

[0057] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the heterogeneous chip-based task processing method described above is implemented.

[0058] According to one aspect of the present disclosure, there is provided an electronic device, including:

[0059] processor; and

[0060] a memory for storing executable instructions of the processor;

[0061] The processor is configured to execute any one of the above-mentioned heterogeneous chip-based task processing methods by executing the executable instructions.

[0062] The embodiment of the present disclosure provides a task processing method based on heterogeneous chips. On the one hand, the method allocates task processing units corresponding to task categories to data processing tasks in a field programmable logic gate array, controls the task processing units, executes the data processing tasks, and obtains task processing results. Then, the current parameter value of the field programmable logic gate array is calculated based on the task processing time and the current load data of the field programmable logic gate array included in the task processing results. Finally, the current working state of the field programmable logic gate array is determined based on the current parameter value, and the working frequency of the field programmable logic gate array and / or the number of task processing units are adjusted according to the current working state and the preset task execution strategy, thereby realizing adaptive adjustment of the working frequency of the field programmable logic gate array and the number of task processing units. On the other hand, since the current working state can be adjusted according to the current The parameter value determines the current working state of the field programmable logic gate array, and adjusts the working frequency and / or the number of task processing units of the field programmable logic gate array according to the current working state and the preset task execution strategy, so that when there are more data processing tasks, the working frequency of the field programmable logic gate array and the number of task processing units can be increased, and when there are fewer data processing tasks, the working frequency and the number of task processing units of the field programmable logic gate array can be reduced. This solves the problem in the prior art that when the amount of data is large, the corresponding computing resources cannot be allocated to it in time, resulting in low processing efficiency of the data processing task, and when the amount of data is small, most of the computing resources are idle, resulting in waste of resources. This can reduce the waste of resources while improving the processing efficiency of the data processing task.

[0063] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0065] Figure 1 A flowchart schematically illustrates a task processing method based on heterogeneous chips according to an exemplary embodiment of the present disclosure.

[0066] Figure 2 A block diagram schematically illustrates a task processing system based on heterogeneous chips according to an example embodiment of the present disclosure.

[0067] Figure 3The following schematically shows an example structure diagram of an ARM parser and an FPGA according to an example embodiment of the present disclosure.

[0068] Figure 4 A diagram schematically illustrates an example scenario of controlling a task processing unit to perform a data processing task according to an example embodiment of the present disclosure.

[0069] Figure 5 A flowchart schematically illustrates a method for calculating a current parameter value of a field programmable logic gate array according to a task processing time included in a task processing result and current load data of the field programmable logic gate array according to an example embodiment of the present disclosure.

[0070] Figure 6 A flowchart schematically illustrates a method for adjusting the operating frequency of the field programmable logic gate array and / or the number of task processing units according to the current operating state and a preset task execution strategy according to an example embodiment of the present disclosure.

[0071] Figure 7 A flowchart schematically illustrates a method for controlling the task processing unit, executing the data processing task, and obtaining a task processing result when the task category is face recognition according to an exemplary embodiment of the present disclosure.

[0072] Figure 8 A schematic diagram shows an example structure of a preset convolutional neural network according to an example embodiment of the present disclosure.

[0073] Figure 9 A flowchart schematically illustrates a method for controlling the task processing unit, executing the data processing task, and obtaining a task processing result when the task category is data encryption and / or decryption according to an exemplary embodiment of the present disclosure.

[0074] Figure 10 A flowchart schematically illustrates another method for processing tasks based on heterogeneous chips according to an exemplary embodiment of the present disclosure.

[0075] Figure 11 A block diagram schematically illustrates a task processing device based on heterogeneous chips according to an example embodiment of the present disclosure.

[0076] Figure 12 An electronic device for implementing the above-mentioned heterogeneous chip-based task processing method according to an exemplary embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0077] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or that other methods, components, devices, steps, etc. may be employed. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0078] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0079] In some terminal devices, heterogeneous chips can be used to analyze and process the business data generated by some applications during operation. At the same time, during the specific data analysis and processing process, different task processing units can be assigned according to different business scenarios. However, in different business scenarios, the amount of business data that needs to be processed in real time varies. Therefore, when the original fixed system computing architecture is adapted to different business scenarios, the system will not achieve the ideal results in terms of speed, resources, power consumption, etc. For example, when the data volume is greater than the standard value, the system processing delay is too high; when the system data volume is less than the standard value, system resources and power consumption will be wasted.

[0080] Based on this, this exemplary embodiment first provides a task processing method based on heterogeneous chips, which can be run on terminal devices, servers, server clusters or cloud servers equipped with heterogeneous chips; of course, those skilled in the art can also run the method disclosed in this disclosure on other platforms as needed, and this exemplary embodiment does not specifically limit this. Figure 1 As shown, the task processing method based on heterogeneous chips may include the following steps:

[0081] Step S110. Preprocessing the original data to be processed to obtain the data processing tasks included in the original data to be processed and the task categories of the data processing tasks;

[0082] Step S120. Allocate a task processing unit corresponding to the task category to the data processing task in a field programmable logic gate array, control the task processing unit, execute the data processing task, and obtain a task processing result;

[0083] Step S130. Calculate the current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array;

[0084] Step S140. Determine the current working state of the field programmable logic gate array according to the current parameter value, and adjust the working frequency of the field programmable logic gate array and / or the number of the task processing units according to the current working state and a preset task execution strategy.

[0085] In the above-mentioned task processing method based on heterogeneous chips, on the one hand, by allocating task processing units corresponding to task categories to data processing tasks in the field programmable logic gate array, and controlling the task processing units to execute data processing tasks, the task processing results are obtained; then, according to the task processing time included in the task processing results and the current load data of the field programmable logic gate array, the current parameter value of the field programmable logic gate array is calculated; finally, the current working state of the field programmable logic gate array is determined according to the current parameter value, and according to the current working state and the preset task execution strategy, the working frequency of the field programmable logic gate array and / or the number of task processing units are adjusted, thereby realizing adaptive adjustment of the working frequency of the field programmable logic gate array and the number of task processing units; on the other hand, since the current parameter value can be determined according to the current parameter value, the working state of the field programmable logic gate array and the number of task processing units are adjusted. The present invention determines the current working state of a field programmable logic gate array, and adjusts the working frequency and / or the number of task processing units of the field programmable logic gate array according to the current working state and a preset task execution strategy, so that when there are many data processing tasks, the working frequency of the field programmable logic gate array and the number of task processing units can be increased, and when there are fewer data processing tasks, the working frequency of the field programmable logic gate array and the number of task processing units can be reduced. This solves the problem in the prior art that when the amount of data is large, the corresponding computing resources cannot be allocated to it in time, resulting in low processing efficiency of the data processing task, and when the amount of data is small, most of the computing resources are idle, resulting in waste of resources. This can improve the processing efficiency of the data processing task while reducing the waste of resources.

[0086] Hereinafter, the task processing method based on heterogeneous chips according to an exemplary embodiment of the present disclosure will be explained and illustrated in detail with reference to the accompanying drawings.

[0087] First, the purpose of the invention of the exemplary embodiment of the present disclosure is explained and illustrated. Specifically, the exemplary embodiment of the present disclosure provides a task processing method based on heterogeneous chips, which can adjust the working frequency of the field programmable logic gate array and the task processing unit according to the amount of business data in the current business scenario and the preset working strategy, thereby achieving an ideal working module, thereby balancing system indicators such as speed, power consumption, and resources, and achieving an efficient balance of system indicators such as speed, power consumption, and resources; ultimately, the terminal equipment carried by the system can achieve the effect of balancing power consumption resources and speed when processing various business scenarios. When the amount of data is large, the system working delay can be reduced by increasing the computing resources of the field programmable logic gate array and increasing the clock frequency. When the amount of data is small, the system power consumption can be reduced by reducing the computing resources of the field programmable logic gate array and reducing the clock frequency.

[0088] Next, the heterogeneous chip-based task processing system involved in the exemplary embodiments of the present disclosure is explained and illustrated. Figure 2 As shown, the task processing system based on heterogeneous chips may include an upper-layer application requirement interface 210, a data processing system (PS) 220 and a programmable logic (PL) 230; wherein the upper-layer application requirement interface, the data processing system and the programmable logic are connected in sequence via a network.

[0089] In the specific application process, the upper-level application requirement interface is used to receive the original data to be processed sent by the application; that is, the upper-level application requirement interface can be used to connect with business needs and develop the API (Application Programming Interface) functions and other interface contents of this system to the upper-level application, which is used to send data, call functions, configure the system, etc. of this system; among them, the API function can be packaged differently according to the category of the application scenario (application), and the API function can encapsulate the corresponding communication protocol according to the scenario of the application and the functions performed by the application.

[0090] At the same time, the data processing system is used to pre-process the original data to be processed, control the task processing units to perform data processing tasks, and adjust the operating frequency of the programmable logic and the number of task processing units. The data processing system can be an ARM (Advanced RISC Machines) processor; the programmable logic can be used to perform specific data processing tasks, that is, to complete the task of data acceleration calculation; at the same time, different types of parallel acceleration units can be configured and deployed according to different applications. The programmable logic can be, for example, an FPGA (Field Programmable Gate Array).

[0091] For further reference, Figure 3 As shown, the data processing system may include a register configuration module 301, a programmable logic loading module 302, a system policy setting module 303, a system resource monitoring module 304, and an application data processing module 305; the field programmable logic gate array may include a calculation control module 306, a data input processing module 307, multiple task processing units 308 that perform data task processing in parallel, a data output processing module 309, and a system clock management module 310. Figure 3 The specific functions of each module shown in will be listed one by one in the specific embodiments below and will not be repeated here.

[0092] The following will be combined Figure 3 right Figure 1 The task processing method based on heterogeneous chips shown in is explained and illustrated.

[0093] In step S110 , the original data to be processed is pre-processed to obtain data processing tasks included in the original data to be processed and task categories of the data processing tasks.

[0094] In this example embodiment, first, based on the preset upper-level application requirement interface, the interface function corresponding to the front-end application is called to receive the original data to be processed sent by the front-end application; secondly, the original data to be processed is parsed to obtain the data processing tasks included in the original data to be processed and the task categories of the data processing tasks; wherein the task categories include at least one of face recognition, data encryption, and data decryption.

[0095] For example, in a specific application process, when an application needs to send a data processing request to a data processing system, it needs to call the interface function corresponding to the application in the upper-level application requirement interface, and then receive the original data to be processed through the communication protocol encapsulated in the interface function, and parse the original data to be processed through the application data processing module included in the data processing system, and then obtain the corresponding data processing task and task category.

[0096] It should be noted here that after obtaining the data processing task and task category, the application data processing module also needs to send the data processing task and task category to the data input processing module in the FPGA, and then control the data input processing module to assign the data processing task to the task processing unit corresponding to the task category for task processing.

[0097] Furthermore, after obtaining the data processing task and the task category of the data processing task, the heterogeneous chip-based task processing method further includes: configuring the registers of the field programmable gate array; wherein the registers include one or more of the following: a reset signal of the task processing unit, a signal indicating whether the task processing unit is in an idle state, a task category supported by the task processing unit, and a data service identification signal included in the data processing task that the task processing unit can process. Specifically, since the FPGA portion of the system is responsible for accelerating the computing process, and the acceleration unit is configurable, it is necessary to configure the parameters of the task processing unit included in the FPGA by the register configuration module included in the ARM processor before starting the accelerated computing process (executing the data processing task), such as: a reset signal of the task processing unit, a signal indicating whether the task processing unit is in an idle state, a type of accelerated computing service that the task processing unit can support, an enable signal indicating whether the task processing unit can support the accelerated computing unit, a data service identification signal included in the data processing task that the task processing unit can process, etc.; the data service identification signal may include a key, plaintext, ciphertext, real-time facial features, and a facial feature library, etc.

[0098] In step S120, a task processing unit corresponding to the task category is allocated to the data processing task in a field programmable logic gate array, and the task processing unit is controlled to execute the data processing task to obtain a task processing result.

[0099] Specifically, refer to Figure 4As shown, if the task category is face recognition, task processing unit 1, task processing unit 2, ..., task processing unit 5, etc. can be assigned to the data processing task; if the task category is data encryption, task processing unit 6, task processing unit 7, ..., task processing unit 10, etc. can be assigned to the data processing task; if the task category is data decryption, task processing unit 11, task processing unit 12, ..., task processing unit 15, etc. can be assigned to the data processing task. After the task assignment is completed, the task processing unit can be controlled based on the function of the task processing unit to perform the data processing task (such as face feature matching, data encryption or data decryption, etc.), thereby obtaining the corresponding task processing result. It should be noted here that the number of task processing units included in the FPGA can be determined according to the specific performance of the FPGA. The higher the performance, the higher the number of task processing units that can be equipped; the lower the performance, the lower the number of task processing units that can be equipped; and the task category corresponding to each task processing unit can be determined according to the category of the data processing task included in the actual scenario. This example does not make any special restrictions on this.

[0100] It should be further explained that each task processing unit is in a parallel computing state; that is, each task processing unit performs independent calculations when executing data processing tasks. At the same time, multiple different task processing units can execute multiple data processing tasks of the same task category or different task categories. This method can solve the problem of low task processing efficiency caused by the need for linear processing when executing data processing tasks by the CPU in the prior art.

[0101] In step S130 , current parameter values ​​of the field programmable logic gate array are calculated according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array.

[0102] In this example embodiment, reference Figure 5 As shown, calculating the current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array may include the following steps:

[0103] Step S510: parsing the task processing result to obtain the task execution result, task processing time, and current load data of the field programmable gate array of the data processing task; wherein the current load data includes the number of unprocessed data processing tasks and the number of occupied task processing units;

[0104] Step S520, calculate the current parameter value of the field programmable logic gate array based on the number of the unprocessed data processing tasks, the occupied number of task processing units and the task processing time; wherein the current parameter value includes multiple ones of current power consumption, current resource usage, current latency rate, current load rate and current data concurrency rate.

[0105] Calculating the current parameter value of the field programmable gate array based on the number of unprocessed data processing tasks, the occupied number of task processing units, and the task processing time may include: first, calculating the current power consumption and current resource usage of the field programmable gate array based on the occupied number of task processing units; second, calculating the current latency rate of the field programmable gate array based on the task processing time; and finally, calculating the current load rate and current data concurrency rate of the field programmable gate array based on the number of unprocessed data processing tasks.

[0106] For example, the current resource usage can be obtained based on the proportion of the number of occupied task processing units (that is, the number of task processing units in processing use) in all task processing units, and the current power consumption of the FPGA can be obtained based on the number of occupied task processing units and the power consumption used by each task processing unit; then, the current latency rate is obtained by dividing the difference between the task processing time and the processing time of the historical tasks by the task processing time; finally, the current load rate and the current data concurrency rate are obtained based on the number of unprocessed data processing tasks and the task processing units in the idle state. It should be noted here that in the process of performing specific calculations on the current power consumption, current resource usage, current latency rate, current load rate and current data concurrency rate, other calculation standards can also be referred to, and this example does not impose special restrictions on this.

[0107] In step S140, the current working state of the field programmable logic gate array is determined according to the current parameter value, and the working frequency of the field programmable logic gate array and / or the number of the task processing units are adjusted according to the current working state and a preset task execution strategy; wherein the preset task execution strategy includes at least one of the following strategies: the standard power consumption of the field programmable logic gate array is greater than a first preset threshold and less than a second preset threshold; the standard resource usage of the field programmable logic gate array is greater than a third preset threshold and less than a fourth preset threshold; the current latency rate of the field programmable logic gate array is greater than a fifth preset threshold and less than a sixth preset threshold; the standard load rate of the task processing units included in the field programmable logic gate array is greater than a seventh preset threshold and less than an eighth preset threshold; the current data concurrency rate of the field programmable logic gate array is greater than a ninth preset threshold and less than a tenth preset threshold.

[0108] Specifically, the corresponding task execution strategy can be configured through the system strategy setting module; the threshold conditions included in the task execution strategy can be configured according to the performance parameters of the FPGA, or based on the number of specific data processing tasks. This example does not impose any special restrictions on this.

[0109] For further reference, Figure 6 As shown, adjusting the operating frequency of the field programmable logic gate array and / or the number of the task processing units according to the current working state and the preset task execution strategy may include the following steps:

[0110] Step S610 , determining whether the current power consumption, current resource usage, current latency rate, current load rate, and current data concurrency rate included in the current working state meet the threshold conditions included in the preset task execution strategy.

[0111] Step S620: If the current power consumption and / or the current resource usage is less than the first preset threshold and / or the third preset threshold, and the current latency rate and / or the current data concurrency rate is greater than the sixth preset threshold and / or the tenth preset threshold, then increase the operating frequency of the field programmable logic gate array and / or the number of task processing units.

[0112] Increasing the operating frequency of the field programmable logic gate array and / or the number of task processing units can be achieved by calling a preset bitstream loading file to adjust the programmable logic circuit of the field programmable logic gate array to increase the operating frequency and / or increase the number of task processing units. At the same time, the increased operating frequency and / or the number of task processing units can be determined by:

[0113] First, calculate the first difference and / or second difference between the first preset threshold and / or the third preset threshold and the current power consumption and / or the current resource usage; secondly, calculate the third difference and / or fourth difference between the current latency rate and / or the current data concurrency rate and the sixth preset threshold and / or the tenth preset threshold; finally, calculate the operating frequency value that needs to be increased for the field programmable logic gate array and the number of task processing units based on the first difference and / or the second difference, the third difference and / or the fourth difference.

[0114] Step S630: If the current power consumption is greater than the second preset threshold, and the current delay rate and / or the current load rate and / or the current concurrency rate is less than the fifth preset threshold and / or the seventh preset threshold and / or the ninth preset threshold, then reduce the operating frequency of the field programmable logic gate array and / or the number of task processing units.

[0115] Reducing the operating frequency of the field programmable logic gate array and / or the number of task processing units can be achieved by calling a preset bitstream loading file to adjust the programmable logic circuit of the field programmable logic gate array to reduce the operating frequency and / or reduce the number of task processing units. At the same time, the reduced operating frequency and / or the number of task processing units can be determined by:

[0116] First, the fifth difference between the current power consumption and the second preset threshold is calculated; secondly, the sixth difference and / or the seventh difference and / or the eighth difference between the fifth preset threshold and / or the seventh preset threshold and / or the ninth preset threshold and the current delay rate and / or the current load rate and / or the current concurrency rate is calculated; finally, based on the fifth difference and the sixth difference and / or the seventh difference and / or the eighth difference, the operating frequency value and the number of task processing units that need to be reduced of the field programmable logic gate array are calculated.

[0117] Furthermore, if the current power consumption and / or the current resource usage is less than the first preset threshold and / or the third preset threshold, the current latency rate and / or the current data concurrency rate is greater than the sixth preset threshold and / or the tenth preset threshold, and there is an idle task processing unit among the task processing units processing the first task category, and the task processing units processing the second task category are all in working state, then the operating frequency of the field programmable logic gate array is increased (implemented by the system clock management module), the number of task processing units processing the first task category is reduced, and the number of task processing units processing the second task category is increased (implemented by the computing control module). Among them, the number of task processing units processing the first task category that is reduced and the number of task processing units processing the second task category that is increased can be the same or different, and can be determined according to actual needs. This example does not make special restrictions on this.

[0118] Below, steps S610-S630 will be further explained and illustrated. Specifically, as a programmable logic resource, the FPGA can load bitstream program files in real time through the programmable logic loading module to reload the corresponding logic circuit. Therefore, when the business scenario or business data processing task changes, the ARM processor can be used for master control to re-burn the FPGA logic circuit to adjust the task processing unit and the FPGA's operating frequency, thereby achieving the purpose of enabling a new accelerated computing parallel architecture and realizing the effect of real-time updating of system operation. For example, when the system's upper layers receive more business data, such as in face matching scenarios, adding multiple channels of facial data (increasing the number of camera recognition lines or the number of faces recognized per camera), the amount of data required to complete face matching calculations per unit time increases. Therefore, by reloading the FPGA's logic circuitry, the number of parallel processing acceleration units (the number of task processing units) can be increased, shortening calculation time and improving computational efficiency. Alternatively, when the system's upper layers receive less business data, in the same face matching scenario, the amount of facial data required to complete face matching calculations per unit time decreases. Therefore, by reloading the FPGA's logic circuitry, the number of parallel processing acceleration units can be reduced, saving real-time system power consumption. Furthermore, when the system reloads, it can select from a variety of pre-set bitstream programs. These programs match the system's various operating strategies: different programs have different numbers of parallel face matching units and encryption / decryption units, allowing for flexible selection based on the current system's operating status.

[0119] Furthermore, the system resource monitoring module can monitor the current power consumption, current resource usage, current latency, current load rate, and current data concurrency rate included in the current working state of the FPGA, and determine whether the operating frequency and task processing unit of the FPGA need to be adjusted based on the current power consumption, current resource usage, current latency, current load rate, and current data concurrency rate and the threshold conditions included in the preset task execution policy. Specifically, the judgment rule is to determine whether the FPGA is in the following states: high power consumption (greater than the second preset threshold) / low power consumption (less than the first preset threshold), high latency (greater than the sixth preset threshold) / low latency (less than the fifth preset threshold), high resource usage (greater than the fourth preset threshold) / low resource usage (less than the third preset threshold), high data concurrency (greater than the tenth preset threshold) / low data concurrency (less than the ninth preset threshold), high computing unit load (greater than the eighth preset threshold) / low computing unit load (less than the seventh preset threshold), and determine whether to initiate logic reloading to optimize the current system data processing flow based on the state and the user-set policy parameters.

[0120] For example, the first state is: if the current policy parameters are compared with those set by the user and the judgment is in a state of high data concurrency, high latency, low resource usage, and low power consumption, the system determines that the current computing power is insufficient and the resources are sufficient, and the logic circuit configuration can be reloaded. By increasing the number of parallel computing units and increasing the system operating frequency, at the cost of appropriately increasing resource utilization and increasing power consumption, the data processing speed can be accelerated, the system latency can be reduced, and the real-time performance of the system can be improved.

[0121] For example, the second state is: if the current policy parameters are compared with those set by the user and the judgment is in a state of lower data concurrency, lower latency, lower computing unit load, and higher power consumption, the system determines that the current computing power is excessive and the resource usage is too high. The logic circuit configuration can be reloaded, the number of parallel computing units can be reduced, and the system operating frequency can be reduced to appropriately increase the system latency or not increase the latency cost, thereby reducing power consumption and logic consumption.

[0122] For another example, since the system can process multiple business data in parallel, such as face matching and encryption and decryption, when different businesses are processed concurrently, if one business is in the first or second state mentioned above while other tasks are in the second or first state, the resource balance can be completed by reducing the resource amount of the parallel computing unit of the low-load acceleration computing module and increasing the resource amount of the parallel computing unit of the high-load acceleration computing module, so that the overall system is in a more balanced state. This method can improve task processing efficiency and reduce resource waste.

[0123] It should be further explained here that after the operating frequency of the field programmable logic gate array and / or the number of task processing units are adjusted, a corresponding system optimization strategy can be generated based on the adjusted operating frequency of the field programmable logic gate array and / or the number of task processing units. Then, when the next data processing task comes, the bit stream can be called to set the operating frequency of the FPGA and the number of task processing units based on the optimization strategy and the task flow of the data processing task, thereby achieving the purpose of optimizing the system.

[0124] Figure 7 The following schematically illustrates a method flow chart of controlling the task processing unit, executing the data processing task, and obtaining the task processing result when the task category is face recognition according to an exemplary embodiment of the present disclosure. Figure 7 As shown, the following steps may be included:

[0125] Step S710, controlling the task processing unit to process the face image to be recognized included in the data processing task using a preset convolutional neural network model to obtain a feature value of the face to be recognized;

[0126] Step S720, performing feature comparison on the facial feature values ​​to be identified and the original facial feature values ​​in a preset feature value library to obtain a task execution result;

[0127] Step S730 , generating the task processing result according to the task execution result, the task processing time consumed for identifying the facial features to be identified, and the current load data of the field programmable logic gate array.

[0128] Among them, feature comparison is performed on the facial feature values ​​to be identified and the original facial feature values ​​in a preset feature value library to obtain the task execution result, including: first, calculating the Euclidean distance between the facial feature values ​​to be identified and the original facial feature values ​​in the feature value library in the field programmable logic gate array; second, based on the Euclidean distance, obtaining the similarity comparison result between the facial features to be identified and the original facial features.

[0129] Below, steps S710 to S730 will be explained and illustrated. In detail, the task processing unit can be controlled to use a preset convolutional neural network model to process the face image to be identified included in the data processing task to obtain the face feature value to be identified; wherein, the preset convolutional neural network model can include an input layer 801, a plurality of feature extraction units 802 composed of convolutional layers and pooling layers, a feature fusion unit 803 composed of one or more fully connected layers, and an output layer 404; wherein, the feature extraction unit can be used to extract local features of the face image to be identified, and the feature fusion unit can be used to perform feature fusion (full connection) on each local feature, thereby obtaining a multi-dimensional data sequence, and outputting it through the output layer to obtain the face feature value to be identified.

[0130] Furthermore, the calculation method of Euclidean distance can be specifically shown as the following formula (1):

[0131]

[0132] Where X represents the original facial feature value, Y represents the feature value of the face to be identified, and n represents the number of feature points in the original facial feature value and the feature value of the face to be identified. It should be noted that compared to using other methods to calculate the similarity between the features of the face to be identified and the original facial features, using the Euclidean distance method can reduce computational efficiency while ensuring accuracy, thereby reducing the burden on the system and improving the user experience.

[0133] Figure 9 The following schematically illustrates a method flow for controlling the task processing unit, executing the data processing task, and obtaining the task processing result when the task category is data encryption and / or decryption according to an exemplary embodiment of the present disclosure. Figure 9 As shown, the following steps may be included:

[0134] Step S910: Control the task processing unit to encrypt and / or decrypt the data to be encrypted and / or the data to be decrypted included in the data processing task using a preset encryption algorithm and / or a preset decryption algorithm to obtain a task execution result;

[0135] Step S920: Generate the task processing result according to the task execution result, the task processing time consumed for encrypting and / or decrypting the data to be encrypted and / or decrypted, and the current load data of the field programmable logic gate array.

[0136] Below, steps S910 to S920 will be explained and illustrated. Specifically, when encrypting encrypted data or decrypting decrypted data, it can be based on the corresponding encryption algorithm or decryption algorithm, which can include a symmetric encryption and decryption algorithm, an asymmetric encryption and decryption algorithm, or a homomorphic encryption and decryption algorithm, etc. This example does not impose any special restrictions on this. Furthermore, after obtaining the task execution result, the corresponding task processing result can be generated by the data output processing module, and the task processing result can be fed back to the application data processing module.

[0137] It should be noted here that, in a specific application process, by monitoring the current system status, it can be considered that the current system face matching process has a high latency and low power consumption, and the delay judgment parameters can be reduced. The system will reload the system logic resources before a new round of calculations begins, increase the number of parallel face matching calculation units, and increase the system operating frequency, thereby reducing the system delay effect; for example, by monitoring the current system status, the user may consider that the current system encryption and decryption matching process has a high power consumption and low latency, and the power consumption judgment parameters can be reduced. The system will reload the system logic resources before a new round of calculations begins, reduce the number of parallel encryption and decryption matching calculation units, and reduce the system operating frequency, thereby reducing the system power consumption effect.

[0138] The following, combined Figure 10 The task processing method based on heterogeneous chips according to the exemplary embodiment of the present disclosure is further explained and illustrated. Figure 10 As shown, the task processing method based on heterogeneous chips may include the following steps:

[0139] Step S1001: The upper-layer application calls the upper-layer application requirement interface to start the task processing process;

[0140] Step S1002: The ARM parser receives the business data sent by the application through the upper-layer application requirement interface, and parses it to obtain the data processing task and task category;

[0141] Step S1003: The ARM parser loads the bitstream program according to the application's business requirements and the system optimization strategy, and configures the FPGA's registers. The system optimization strategy is generated based on the adjusted operating frequency of the field programmable gate array and / or the number of task processing units.

[0142] Step S1004: FPGA parses the register configuration information sent by the ARM parser and configures the operating parameters of each module;

[0143] Step S1005: The ARM parser sends the data processing task to the data input processing module;

[0144] Step S1006: The data input processing module sends the data processing task to the task processing unit corresponding to the task category. The task processing unit processes the data processing task and obtains the task execution result.

[0145] Step S1007: The data output processing module integrates the task execution result and the current load data to obtain the task processing result;

[0146] Step S1008: The ARM parser performs a business analysis based on the task processing result, and performs a quantitative analysis of the current working state of the FPGA based on the task processing time and power consumption included in the analysis result.

[0147] Step S1009, determine whether the current working state of the FPGA matches the preset task execution strategy; if so, jump to step S1010; if not, jump to step S1005;

[0148] Step S1010, determine whether the data processing task is completed; if so, jump to step S1011; if not, jump to step S1003;

[0149] Step S1011, ending the processing flow of the data processing task and feeding back the task execution result to the application.

[0150] The heterogeneous chip-based task processing method provided by the example embodiments of the present disclosure enables the system to automatically determine whether the current working status is satisfied based on the policy parameters set by the user, and choose to reload the FPGA computing module program to achieve an adaptive adjustment effect.

[0151] The exemplary embodiment of the present disclosure also provides a task processing device based on heterogeneous chips. Figure 11 As shown, the heterogeneous chip-based task processing device may include a data preprocessing module 1110, a data processing task execution module 1120, a parameter value calculation module 1130, and an adjustment module 1140.

[0152] The data preprocessing module 1110 may be used to preprocess the original data to be processed to obtain the data processing tasks and task categories of the data processing tasks included in the original data to be processed;

[0153] The data processing task execution module 1120 may be configured to allocate a task processing unit corresponding to the task category to the data processing task in the field programmable logic gate array, and control the task processing unit to execute the data processing task and obtain a task processing result;

[0154] The parameter value calculation module 1130 may be configured to calculate a current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array;

[0155] The adjustment module 1140 can be used to determine the current working state of the field programmable logic gate array based on the current parameter value, and adjust the working frequency of the field programmable logic gate array and / or the number of the task processing units based on the current working state and a preset task execution strategy.

[0156] In an exemplary embodiment of the present disclosure, calculating a current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array includes:

[0157] parsing the task processing result to obtain the task execution result, task processing time, and current load data of the field programmable logic gate array of the data processing task; wherein the current load data includes the number of unprocessed data processing tasks and the number of occupied task processing units;

[0158] The current parameter value of the field programmable logic gate array is calculated based on the number of unprocessed data processing tasks, the occupied number of task processing units and the task processing time; wherein the current parameter value includes multiple ones of current power consumption, current resource usage, current latency rate, current load rate and current data concurrency rate.

[0159] In an exemplary embodiment of the present disclosure, calculating the current parameter value of the field programmable gate array according to the number of unprocessed data processing tasks, the number of occupied task processing units, and the task processing time includes:

[0160] Calculating the current power consumption and current resource usage of the field programmable logic gate array according to the occupied number of the task processing units;

[0161] Calculating a current delay rate of the field programmable logic gate array according to the task processing time;

[0162] According to the number of the unprocessed data processing tasks, a current load rate and a current data concurrency rate of the field programmable logic gate array are calculated.

[0163] In an exemplary embodiment of the present disclosure, the preset task execution strategy includes at least one of the following strategies:

[0164] The standard power consumption of the field programmable logic gate array is greater than a first preset threshold and less than a second preset threshold;

[0165] The standard resource usage of the field programmable logic gate array is greater than a third preset threshold and less than a fourth preset threshold;

[0166] The current delay rate of the field programmable logic gate array is greater than a fifth preset threshold and less than a sixth preset threshold;

[0167] The standard load rate of the task processing unit included in the field programmable logic gate array is greater than a seventh preset threshold and less than an eighth preset threshold;

[0168] The current data concurrency rate of the field programmable logic gate array is greater than a ninth preset threshold and less than a tenth preset threshold.

[0169] In an exemplary embodiment of the present disclosure, adjusting the operating frequency of the field programmable logic gate array and / or the number of the task processing units according to the current working state and a preset task execution strategy includes:

[0170] Determine whether the current power consumption, current resource usage, current latency rate, current load rate, and current data concurrency rate included in the current working state meet the threshold conditions included in the preset task execution strategy;

[0171] If the current power consumption and / or the current resource usage is less than the first preset threshold and / or the third preset threshold, and the current latency rate and / or the current data concurrency rate is greater than the sixth preset threshold and / or the tenth preset threshold, increasing the operating frequency of the field programmable logic gate array and / or the number of the task processing units;

[0172] If the current power consumption is greater than the second preset threshold, and the current delay rate and / or the current load rate and / or the current concurrency rate is less than the fifth preset threshold and / or the seventh preset threshold and / or the ninth preset threshold, the operating frequency of the field programmable logic gate array and / or the number of task processing units are reduced.

[0173] In an exemplary embodiment of the present disclosure, the adjustment module 1140 can also be configured as follows: if the current power consumption and / or the current resource usage is less than the first preset threshold and / or the third preset threshold, the current latency rate and / or the current data concurrency rate is greater than the sixth preset threshold and / or the tenth preset threshold, and there are task processing units in an idle state among the task processing units processing the first task category, and the task processing units processing the second task category are all in a working state, then the operating frequency of the field programmable logic gate array is increased, the number of task processing units processing the first task category is reduced, and the number of task processing units processing the second task category is increased.

[0174] In an exemplary embodiment of the present disclosure, increasing the operating frequency of the field programmable logic gate array and / or the number of the task processing units includes:

[0175] A preset bitstream loading file is called to adjust the programmable logic circuit of the field programmable logic gate array to increase the operating frequency and / or increase the number of task processing units.

[0176] In an exemplary embodiment of the present disclosure, the adjustment module 1140 can also be configured to: calculate the first difference and / or second difference between the first preset threshold and / or the third preset threshold and the current power consumption and / or the current resource usage; calculate the third difference and / or fourth difference between the current latency rate and / or the current data concurrency rate and the sixth preset threshold and / or the tenth preset threshold; and calculate the required increased operating frequency value of the field programmable logic gate array and the number of task processing units based on the first difference and / or the second difference, the third difference and / or the fourth difference.

[0177] In an exemplary embodiment of the present disclosure, the heterogeneous chip-based task processing device further includes:

[0178] A register configuration module can be used to configure the registers of the field programmable logic gate array; wherein the registers include one or more of the reset signal of the task processing unit, the signal indicating whether it is in an idle state, the task category that the task processing unit can support, and the data service identification signal included in the data processing tasks that the task processing unit can process.

[0179] In an exemplary embodiment of the present disclosure, preprocessing is performed on original data to be processed to obtain data processing tasks included in the original data to be processed and task categories of the data processing tasks, including:

[0180] Based on the preset upper-layer application requirement interface, call the interface function corresponding to the front-end application and receive the original data to be processed sent by the front-end application;

[0181] The original data to be processed is parsed to obtain data processing tasks included in the original data to be processed and task categories of the data processing tasks; wherein the task categories include at least one of face recognition, data encryption, and data decryption.

[0182] In an exemplary embodiment of the present disclosure, when the task category is face recognition, controlling the task processing unit to execute the data processing task and obtain the task processing result includes:

[0183] Controlling the task processing unit to process the face image to be identified included in the data processing task using a preset convolutional neural network model to obtain a feature value of the face to be identified;

[0184] Performing feature comparison on the facial feature values ​​to be identified and the original facial feature values ​​in a preset feature value library to obtain a task execution result;

[0185] The task processing result is generated according to the task execution result, the task processing time consumed for identifying the facial features to be identified, and the current load data of the field programmable logic gate array.

[0186] In an exemplary embodiment of the present disclosure, performing feature comparison on the facial feature values ​​to be identified and the original facial feature values ​​in a preset feature value library to obtain a task execution result includes:

[0187] Calculating the Euclidean distance between the facial feature value to be identified and the original facial feature value in the feature value library in the field programmable logic gate array;

[0188] A similarity comparison result between the facial features to be identified and the original facial features is obtained based on the Euclidean distance.

[0189] In an exemplary embodiment of the present disclosure, when the task category is data encryption and / or decryption, controlling the task processing unit to execute the data processing task and obtain the task processing result includes:

[0190] Controlling the task processing unit to encrypt and / or decrypt the data to be encrypted and / or the data to be decrypted included in the data processing task using a preset encryption algorithm and / or a preset decryption algorithm to obtain a task execution result;

[0191] The task processing result is generated according to the task execution result, the task processing time consumed for encrypting and / or decrypting the data to be encrypted and / or the data to be decrypted, and the current load data of the field programmable logic gate array.

[0192] The specific details of each module in the above-mentioned task processing device based on heterogeneous chips have been described in detail in the corresponding task processing method based on heterogeneous chips, so they will not be repeated here.

[0193] It should be noted that although several modules or units of the device for action execution are mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0194] Furthermore, although the steps of the method of the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0195] In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0196] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods, or program products. Therefore, various aspects of the present disclosure may be implemented in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which may be collectively referred to herein as "circuits," "modules," or "systems."

[0197] Refer to the following Figure 12 12 is a diagram to describe the electronic device 1200 according to this embodiment of the present disclosure. Figure 12 The electronic device 1200 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0198] like Figure 12As shown, electronic device 1200 is implemented as a general-purpose computing device. Components of electronic device 1200 may include, but are not limited to, the aforementioned at least one processing unit 1210, the aforementioned at least one storage unit 1220, a bus 1230 connecting various system components (including storage unit 1220 and processing unit 1210), and a display unit 1240.

[0199] The storage unit stores program codes, which can be executed by the processing unit 1210, so that the processing unit 1210 performs the steps described in the "Exemplary Method" section of the present disclosure according to various exemplary embodiments. For example, the processing unit 1210 can perform the following steps: Figure 1 Step S110 shown in: pre-processing the original data to be processed to obtain the data processing tasks included in the original data to be processed and the task categories of the data processing tasks; step S120: allocating a task processing unit corresponding to the task category to the data processing task in the field programmable logic gate array, and controlling the task processing unit to execute the data processing task to obtain a task processing result; step S130: calculating the current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array; step S140: determining the current working state of the field programmable logic gate array according to the current parameter value, and adjusting the working frequency of the field programmable logic gate array and / or the number of the task processing units according to the current working state and a preset task execution strategy.

[0200] The storage unit 1220 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 12201 and / or a cache memory unit 12202 , and may further include a read-only memory unit (ROM) 12203 .

[0201] The storage unit 1220 may also include a program / utility 12204 having a set (at least one) of program modules 12205, such program modules 12205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0202] The bus 1230 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0203] The electronic device 1200 can also communicate with one or more external devices 1300 (e.g., a keyboard, a pointing device, a Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 1200, and / or any device that enables the electronic device 1200 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication can occur via an input / output (I / O) interface 1250. Furthermore, the electronic device 1200 can communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter 1260. As shown, the network adapter 1260 communicates with other modules of the electronic device 1200 via a bus 1230. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 1200, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0204] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0205] In exemplary embodiments of the present disclosure, a computer-readable storage medium is also provided, on which is stored a program product capable of implementing the aforementioned methods of this specification. In some possible implementations, various aspects of the present disclosure may also be implemented in the form of a program product comprising program code. When the program product is executed on a terminal device, the program code is configured to cause the terminal device to execute the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present disclosure.

[0206] According to an embodiment of the present disclosure, a program product for implementing the above-mentioned method can be a portable compact disc read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0207] The program product may be implemented in any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0208] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0209] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0210] The program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0211] Furthermore, the figures above are merely illustrative of the processes included in the methods according to exemplary embodiments of the present disclosure and are not intended to be limiting. It is readily understood that the processes illustrated in the figures above do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0212] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow from the general principles of the present disclosure and include common knowledge or customary techniques in the art not invented herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A task processing method based on heterogeneous chips, characterized in that: include: Preprocessing the original data to be processed to obtain data processing tasks included in the original data to be processed and task categories of the data processing tasks; Allocating a task processing unit corresponding to the task category to the data processing task in a field programmable logic gate array, and controlling the task processing unit to execute the data processing task and obtain a task processing result; Calculating a current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array; The current working state of the field programmable logic gate array is determined according to the current parameter value, and the working frequency of the field programmable logic gate array and / or the number of the task processing units are adjusted according to the current working state and a preset task execution strategy.

2. The task processing method based on heterogeneous chips according to claim 1, characterized in that: Calculating a current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and current load data of the field programmable logic gate array includes: parsing the task processing result to obtain the task execution result, task processing time, and current load data of the field programmable logic gate array of the data processing task; wherein the current load data includes the number of unprocessed data processing tasks and the number of occupied task processing units; The current parameter value of the field programmable logic gate array is calculated based on the number of unprocessed data processing tasks, the occupied number of task processing units and the task processing time; wherein the current parameter value includes multiple ones of current power consumption, current resource usage, current latency rate, current load rate and current data concurrency rate.

3. The task processing method based on heterogeneous chips according to claim 2, characterized in that: Calculating a current parameter value of the field programmable logic gate array according to the number of unprocessed data processing tasks, the number of occupied task processing units, and the task processing time, including: Calculating the current power consumption and current resource usage of the field programmable logic gate array according to the occupied number of the task processing units; Calculating a current delay rate of the field programmable logic gate array according to the task processing time; According to the number of the unprocessed data processing tasks, a current load rate and a current data concurrency rate of the field programmable logic gate array are calculated.

4. The task processing method based on heterogeneous chips according to claim 1, characterized in that: The preset task execution strategy includes at least one of the following strategies: The standard power consumption of the field programmable logic gate array is greater than a first preset threshold and less than a second preset threshold; The standard resource usage of the field programmable logic gate array is greater than a third preset threshold and less than a fourth preset threshold; The current delay rate of the field programmable logic gate array is greater than a fifth preset threshold and less than a sixth preset threshold; The standard load rate of the task processing unit included in the field programmable logic gate array is greater than a seventh preset threshold and less than an eighth preset threshold; The current data concurrency rate of the field programmable logic gate array is greater than a ninth preset threshold and less than a tenth preset threshold.

5. The task processing method based on heterogeneous chips according to claim 4, characterized in that: Adjusting the operating frequency of the field programmable logic gate array and / or the number of the task processing units according to the current working state and a preset task execution strategy includes: Determine whether the current power consumption, current resource usage, current latency rate, current load rate, and current data concurrency rate included in the current working state meet the threshold conditions included in the preset task execution strategy; If the current power consumption and / or the current resource usage is less than the first preset threshold and / or the third preset threshold, and the current latency rate and / or the current data concurrency rate is greater than the sixth preset threshold and / or the tenth preset threshold, increasing the operating frequency of the field programmable logic gate array and / or the number of the task processing units; If the current power consumption is greater than the second preset threshold, and the current delay rate and / or the current load rate and / or the current concurrency rate is less than the fifth preset threshold and / or the seventh preset threshold and / or the ninth preset threshold, the operating frequency of the field programmable logic gate array and / or the number of task processing units are reduced.

6. The task processing method based on heterogeneous chips according to claim 5, characterized in that: The task processing method further includes: If the current power consumption and / or the current resource usage is less than the first preset threshold and / or the third preset threshold, the current latency rate and / or the current data concurrency rate is greater than the sixth preset threshold and / or the tenth preset threshold, and there is an idle task processing unit among the task processing units processing the first task category, and the task processing units processing the second task category are all in working state, then the operating frequency of the field programmable logic gate array is increased, the number of task processing units processing the first task category is reduced, and the number of task processing units processing the second task category is increased.

7. The task processing method based on heterogeneous chips according to claim 5, characterized in that: Increasing the operating frequency and / or number of task processing units of a field programmable gate array, including: A preset bitstream loading file is called to adjust the programmable logic circuit of the field programmable logic gate array to increase the operating frequency and / or increase the number of task processing units.

8. The task processing method based on heterogeneous chips according to claim 5, characterized in that: The heterogeneous chip-based task processing method further includes: Calculating a first difference and / or a second difference between the first preset threshold and / or the third preset threshold and the current power consumption and / or the current resource usage; Calculating a third difference and / or a fourth difference between the current latency rate and / or the current data concurrency rate and the sixth preset threshold and / or the tenth preset threshold; The operating frequency value and the number of task processing units that need to be increased for the field programmable logic gate array are calculated according to the first difference and / or the second difference, the third difference and / or the fourth difference.

9. The task processing method based on heterogeneous chips according to claim 1, characterized in that: Before allocating a task processing unit corresponding to the task category to the data processing task in the field programmable logic gate array, the heterogeneous chip-based task processing method further includes: The registers of the field programmable logic gate array are configured; wherein the registers include one or more of a reset signal of the task processing unit, a signal indicating whether the task processing unit is in an idle state, a task category that the task processing unit can support, and a data service identification signal included in a data processing task that the task processing unit can process.

10. The task processing method based on heterogeneous chips according to claim 1, characterized in that: Preprocessing the original data to be processed to obtain data processing tasks included in the original data to be processed and task categories of the data processing tasks, including: Based on the preset upper-layer application requirement interface, call the interface function corresponding to the front-end application and receive the original data to be processed sent by the front-end application; The original data to be processed is parsed to obtain data processing tasks included in the original data to be processed and task categories of the data processing tasks; wherein the task categories include at least one of face recognition, data encryption, and data decryption.

11. The task processing method based on heterogeneous chips according to claim 10, characterized in that: When the task category is face recognition, controlling the task processing unit to execute the data processing task and obtain a task processing result includes: Controlling the task processing unit to process the face image to be identified included in the data processing task using a preset convolutional neural network model to obtain a feature value of the face to be identified; Performing feature comparison on the facial feature values ​​to be identified and the original facial feature values ​​in a preset feature value library to obtain a task execution result; The task processing result is generated according to the task execution result, the task processing time consumed for identifying the facial features to be identified, and the current load data of the field programmable logic gate array.

12. The task processing method based on heterogeneous chips according to claim 11, characterized in that: Performing feature comparison on the facial feature values ​​to be identified and the original facial feature values ​​in a preset feature value library to obtain a task execution result, including: Calculating the Euclidean distance between the facial feature value to be identified and the original facial feature value in the feature value library in the field programmable logic gate array; A similarity comparison result between the facial features to be identified and the original facial features is obtained based on the Euclidean distance.

13. The task processing method based on heterogeneous chips according to claim 10, characterized in that: When the task category is data encryption and / or decryption, controlling the task processing unit to execute the data processing task and obtain a task processing result includes: Controlling the task processing unit to encrypt and / or decrypt the data to be encrypted and / or the data to be decrypted included in the data processing task using a preset encryption algorithm and / or a preset decryption algorithm to obtain a task execution result; The task processing result is generated according to the task execution result, the task processing time consumed for encrypting and / or decrypting the data to be encrypted and / or the data to be decrypted, and the current load data of the field programmable logic gate array.

14. A task processing device based on heterogeneous chips, characterized in that: include: A data preprocessing module is used to preprocess the original data to be processed to obtain the data processing tasks included in the original data to be processed and the task categories of the data processing tasks; a data processing task execution module, configured to allocate a task processing unit corresponding to the task category to the data processing task in a field programmable logic gate array, and control the task processing unit to execute the data processing task and obtain a task processing result; a parameter value calculation module, configured to calculate a current parameter value of the field programmable logic gate array according to the task processing time included in the task processing result and the current load data of the field programmable logic gate array; an adjustment module, configured to determine a current operating state of the field programmable logic gate array according to the current parameter value, and to adjust an operating frequency of the field programmable logic gate array and / or the number of task processing units according to the current operating state and a preset task execution strategy.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the heterogeneous chip-based task processing method according to any one of claims 1 to 13 is implemented.

16. An electronic device, characterized in that: include: processor; as well as a memory for storing executable instructions of the processor; The processor is configured to execute the heterogeneous chip-based task processing method according to any one of claims 1 to 13 by executing the executable instructions.

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