A method for manufacturing SDB FinFET by cutting first

Abstract

The invention provides a manufacturing method of SDB FinFET in advance, which comprises the following steps: forming a plurality of Fin structures arranged in a longitudinal interval on a substrate, and forming a SiN layer on the Fin structure; depositing a thin oxide layer; annealing after depositing a dielectric layer; grinding to expose the upper surface of the SiN layer; forming an SDB photoresist pattern on the SiN layer; etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove; forming silicon nitride at the bottom of the SDB groove; forming silicon oxide at the top of the SDB groove; removing the SiN layer to expose the upper surface of the Fin structure; forming a plurality of pseudo gates arranged in a transverse interval on the Fin structure and the SDB groove; forming a SiP epitaxial structure on the Fin structure between two adjacent pseudo gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between two adjacent pseudo gates on the other side of the SDB groove; depositing an interlayer dielectric layer to cover the pseudo gate; grinding the interlayer dielectric layer until the top of the pseudo gate is exposed; removing the pseudo gate to form a groove; and forming an HK metal gate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a pre-cut SDB FinFET. Background Art

[0002] Logic designs in logic standard cells are created using standard cells. The height of a cell is the number of tracks multiplied by the metal pitch (Pitch), and tracks and pitch are measured using Metal Layer 2 (M2). Figure 1 Shown as a schematic diagram of 7.5 rail units, half the height of the power rail (Power) and the ground rail (Ground) are located in the upper unit and the lower unit respectively.

[0003] The cell width is related to the contact poly pitch (CPP), and the number of CPPs that make up the cell width depends on the cell type and whether the cell has a double diffusion break (DDB) or a single diffusion break (SDB).

[0004] One DDB adds one and a half CPP on each side of the cell. For practical cells, such as NAND gates and cell scan flip-flops, the number of CPPs across the cell width is large, and SDB has little effect on DDB.

[0005] In the SDB-first process, after the ILD filling is formed and planarized, the dummy gate will be removed and then the HK metal gate stack will be filled. This will cause two problems: 1) Around the SDB, the spacing between the epitaxial layer and the polysilicon is very small, and the interaction between the two is also very strong; 2) After the dummy gate is removed, the SiGe or SiP pressure is released, which will weaken the device performance; 3) After the HK metal gate stack is filled with grooves, the metal gate and tungsten electrode pressure will react to the SiGe or SiP pressure, which will be beneficial to PMOS or NMOS, but will reduce the performance of the other; 4) Taking the above problems into consideration, the SDB device will be very different in the actual circuit according to the actual situation. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for manufacturing SDB FinFET first-cut, which is used to solve the problem that in the SDB first-cut process in the prior art, the pressure of the metal gate and tungsten electrode reacts to the pressure of SiGe or SiP, thereby causing the device performance to deteriorate.

[0007] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing a pre-cut SDB FinFET, which at least comprises:

[0008] Step 1, providing a substrate, forming a plurality of Fin structures arranged in a longitudinal direction at intervals on the substrate, wherein the length direction of the Fin structure is a transverse direction perpendicular to the longitudinal direction; forming a SiN layer on the Fin structure; and forming a first hard mask layer on the SiN layer;

[0009] Step 2: depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the Fin structure;

[0010] Step 3, depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, and then annealing;

[0011] Step 4: grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed;

[0012] Step 5, forming a SDB photoresist pattern on the SiN layer of the Fin structure;

[0013] Step 6: etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove;

[0014] Step 7: forming silicon nitride at the bottom of the SDB groove;

[0015] Step eight, forming silicon oxide on the silicon nitride in the SDB groove;

[0016] Step nine, removing the SiN layer;

[0017] Step 10: removing the dielectric layer covering the Fin structure to expose the Fin structure;

[0018] Step 11, forming a plurality of dummy gates arranged in a lateral direction and spaced apart from each other on the Fin structure and the SDB groove and sidewalls attached to the dummy gates;

[0019] Step 12: forming a SiP epitaxial structure on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove;

[0020] Step 13: depositing an interlayer dielectric layer to cover the dummy gates and fill the spaces between the dummy gates; then grinding the interlayer dielectric layer until the tops of the dummy gates are exposed;

[0021] Step 14: remove the dummy gate to form a groove; then fill the groove with HK metal to form an HK metal gate.

[0022] Preferably, in step 2, the method for depositing the thin oxide layer on the upper surface of the substrate and the sidewall of the Fin structure is an atomic layer deposition method or an in-situ water vapor generation method.

[0023] Preferably, the method for depositing the dielectric layer in step three is FCVD.

[0024] Preferably, the grinding in step 4 is chemical mechanical grinding.

[0025] Preferably, in step eight, upper surface grinding is performed after silicon oxide is formed on the silicon nitride layer in the SDB groove.

[0026] Preferably, in step twelve, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates on one side of the SDB groove is two.

[0027] Preferably, in step twelve, the number of the SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove is two.

[0028] As described above, the manufacturing method of the SDB FinFET cut first of the present invention has the following beneficial effects: the present invention uses the FCVD method to fill silicon nitride at the bottom of the SDB groove, and its filling ability is good; filling silicon oxide at the top of the SDB groove can avoid the problem of film loss due to the subsequent removal of the SiN layer; two layers of thin film stacks are formed in the SDB groove of the present invention, so that the risk of pressure release of the SiP epitaxial layer and the SiGe epitaxial layer is reduced; because the SiP epitaxial layer and the SiGe epitaxial layer are separated independently, the pressure released by the HK metal gate will not affect the SiP epitaxial layer and the SiGe epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shown is a schematic diagram of a 7.5 track unit;

[0030] Figure 2a It is a schematic cross-sectional view of a Fin structure formed on a substrate in the present invention;

[0031] Figure 2b It is a schematic longitudinal cross-sectional view showing a Fin structure formed on a substrate in the present invention;

[0032] Figure 3a It is a schematic cross-sectional view of a thin oxide layer formed on a substrate in the present invention;

[0033] Figure 3b It is a schematic longitudinal cross-sectional view of a thin oxide layer formed on a substrate in the present invention;

[0034] Figure 4aIt is a schematic diagram of the transverse cross-sectional structure after a dielectric layer is formed on a substrate in the present invention;

[0035] Figure 4b It is a schematic diagram of a longitudinal cross-sectional structure after a dielectric layer is formed on a substrate in the present invention;

[0036] Figure 5a It is a schematic diagram of the transverse cross-sectional structure of the SiN layer exposed after grinding in the present invention;

[0037] Figure 5b It is a schematic diagram of the longitudinal cross-sectional structure of the SiN layer exposed after grinding in the present invention;

[0038] Figure 6a It is a schematic diagram of the transverse cross-sectional structure after forming the SDB photoresist pattern in the present invention;

[0039] Figure 6b It is a schematic diagram of the longitudinal cross-sectional structure after forming the SDB photoresist pattern in the present invention;

[0040] Figure 7a It is a schematic diagram of the transverse cross-sectional structure after the SDB groove is formed in the present invention;

[0041] Figure 7b It is a schematic diagram of the longitudinal cross-sectional structure after the SDB groove is formed in the present invention;

[0042] Figure 8 It is a schematic diagram of the transverse cross-sectional structure after silicon nitride is formed at the bottom of the SDB groove in the present invention;

[0043] Fig. 9 It is a schematic diagram of the transverse cross-sectional structure after silicon oxide is formed on the top of the SDB groove in the present invention;

[0044] Fig.10 It is a schematic diagram of the transverse cross-sectional structure after the SiN layer is removed in the present invention;

[0045] Fig.11 It is a schematic diagram of the transverse cross-sectional structure after the upper surface of the Fin structure is exposed in the present invention;

[0046] Fig.12 It is a schematic diagram of the transverse cross-sectional structure after forming a dummy gate in the present invention;

[0047] Fig.13 It is a schematic diagram of the transverse cross-sectional structure after the epitaxial structure is formed in the present invention;

[0048] Fig.14 It is a schematic diagram of the transverse cross-sectional structure after the interlayer dielectric layer is deposited to cover the dummy gate in the present invention;

[0049] Fig.15 It is a schematic diagram of the lateral cross-sectional structure after forming the HK metal gate in the present invention;

[0050] Fig.16 It is a flow chart of the method for manufacturing the pre-cut SDB FinFET of the present invention. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] Please refer to Figures 2 to Fig.16 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0053] The present invention provides a method for manufacturing SDB FinFET first, such as Fig.16 As shown, Fig.16 The flowchart of the method for manufacturing the pre-cut SDB FinFET of the present invention is shown, and the method comprises at least the following steps:

[0054] Step 1: providing a substrate, forming a plurality of Fin structures arranged in a longitudinal direction on the substrate, wherein the length direction of the Fin structures is a transverse direction perpendicular to the longitudinal direction; forming a SiN layer on the Fin structures; and forming a first hard mask layer on the SiN layer; Figure 2a and Figure 2b As shown, Figure 2a It is a schematic cross-sectional view of a Fin structure formed on a substrate in the present invention; Figure 2b It shows a schematic longitudinal cross-sectional view of a Fin structure formed on a substrate in the present invention; in step one, a plurality of Fin structures 02 are formed on the substrate 01 and arranged at intervals along the longitudinal direction, and the length direction of the Fin structure 02 is a lateral direction perpendicular to the longitudinal direction; a SiN layer 03 is formed on the Fin structure 02; and a first hard mask layer 04 is formed on the SiN layer 03.

[0055] Step 2: depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the Fin structure; Figure 3a and Figure 3b As shown, Figure 3aIt is a schematic cross-sectional view of a thin oxide layer formed on a substrate in the present invention; Figure 3b It is a schematic longitudinal cross-sectional view after a thin oxide layer is formed on a substrate in the present invention; the second step is to deposit the thin oxide layer 05 , and the thin oxide layer 05 covers the upper surface of the substrate 01 and the Fin structure 02 .

[0056] Furthermore, in the present invention, in step 2 of this embodiment, the method for depositing the thin oxide layer 05 on the upper surface of the substrate 01 and the sidewall of the Fin structure 02 is an atomic layer deposition method or an in-situ water vapor generation method.

[0057] Step 3: depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, and then annealing; Figure 4a and Figure 4b As shown, Figure 4a It is a schematic diagram of the transverse cross-sectional structure after a dielectric layer is formed on a substrate in the present invention; Figure 4b The figure shows a schematic diagram of the longitudinal cross-sectional structure after a dielectric layer is formed on a substrate in the present invention. In step three, a dielectric layer 06 is deposited on the substrate 01 to cover the upper surface of the substrate 01 and the thin oxide layer 05, and then annealing is performed.

[0058] In the present invention, further, in step three of this embodiment, the method for depositing the dielectric layer 06 is FCVD method.

[0059] Step 4: Grind the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed; Figure 5a and Figure 5b As shown, Figure 5a It is a schematic diagram of the transverse cross-sectional structure of the SiN layer exposed after grinding in the present invention;

[0060] Figure 5b The figure shows the longitudinal cross-sectional structure of the SiN layer exposed after grinding in the present invention. In step 4, the dielectric layer 06 and the thin oxide layer 05 are ground until the upper surface of the SiN layer 03 is exposed.

[0061] Furthermore, in the present invention, the polishing in step 4 of this embodiment is chemical mechanical polishing.

[0062] Step 5: forming a SDB photoresist pattern on the SiN layer of the Fin structure; Figure 6a and 6b As shown, Figure 6a6b shows a schematic diagram of the transverse cross-sectional structure after the SDB photoresist pattern is formed in the present invention; 6b shows a schematic diagram of the longitudinal cross-sectional structure after the SDB photoresist pattern is formed in the present invention. In step five, an SDB photoresist pattern 07 is formed on the SiN layer 03 of the Fin structure 02.

[0063] Step 6: Etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove; Figure 7a and Figure 7b As shown, Figure 7a It is a schematic diagram of the transverse cross-sectional structure after the SDB groove is formed in the present invention; Figure 7b The figure shows a schematic diagram of the longitudinal cross-section structure after the SDB groove is formed in the present invention. In step six, the SiN layer 03 and the Fin structure 02 are etched along the SDB photoresist pattern 07 to form the SDB groove 08 .

[0064] Step 7: forming silicon nitride at the bottom of the SDB groove; Figure 8 As shown, Figure 8 The figure shows the cross-sectional structure of the present invention after silicon nitride is formed at the bottom of the SDB groove. In step seven, the silicon nitride 09 is formed at the bottom of the SDB groove 08.

[0065] Step eight, forming silicon oxide on the silicon nitride in the SDB groove; Fig. 9 As shown, Fig. 9 The figure shows a schematic diagram of the transverse cross-sectional structure after silicon oxide is formed on the top of the SDB groove in the present invention. In step eight, silicon oxide 10 is formed on the silicon nitride 09 in the SDB groove.

[0066] The present invention further comprises that in step eight of this embodiment, the upper surface is ground after silicon oxide is formed on the silicon nitride layer in the SDB groove.

[0067] Step nine, removing the SiN layer; Fig.10 As shown, Fig.10 It shows a schematic diagram of the transverse cross-sectional structure after the SiN layer is removed in the present invention;.

[0068] Step 10: removing the dielectric layer covering the Fin structure to expose the Fin structure; Fig.11 As shown, Fig.11 It is a schematic diagram of the transverse cross-sectional structure after the upper surface of the Fin structure is exposed in the present invention.

[0069] Step 11: forming a plurality of dummy gates arranged in a lateral direction and spaced apart from each other on the Fin structure and the SDB groove and sidewalls attached to the dummy gates; Fig.12 As shown, Fig.12 The figure shows a schematic diagram of the lateral cross-sectional structure after forming the dummy gate in the present invention. In step 11, a plurality of dummy gates 12 arranged in a lateral direction and spaced apart from each other and a sidewall 13 attached to the dummy gates 12 are formed on the Fin structure 02 and the SDB groove.

[0070] According to the present invention, in step 11 of the present embodiment, the dummy gate 12 includes a polysilicon layer and a second hard mask layer located on the polysilicon layer.

[0071] Step 12: forming a SiP epitaxial structure on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove; Fig.13 As shown, Fig.13 The schematic diagram of the transverse cross-sectional structure after the epitaxial structure is formed in the present invention is shown. In step 12, a SiP epitaxial structure 14 is formed on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; and a SiGe epitaxial structure 15 is formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove.

[0072] Further, in the step twelve of this embodiment, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates on one side of the SDB groove is two.

[0073] Further, in the present invention, in step twelve of this embodiment, the number of the SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove is two.

[0074] Step 13: depositing an interlayer dielectric layer to cover the dummy gates and fill the spaces between the dummy gates; then grinding the interlayer dielectric layer until the top of the dummy gates is exposed; Fig.14 As shown, Fig.14 The schematic diagram of the cross-sectional structure after depositing the interlayer dielectric layer to cover the dummy gate in the present invention is shown. In step thirteen, the interlayer dielectric layer 16 is deposited to cover the dummy gate 12 and fill the space between the dummy gates; then the interlayer dielectric layer 16 is polished until the top of the dummy gate is exposed.

[0075] Step 14: remove the dummy gate to form a groove; then fill the groove with HK metal to form a HK metal gate. Fig.15 As shown, Fig.15 It is a schematic diagram of the lateral cross-sectional structure after forming the HK metal gate in the present invention.

[0076] In summary, the present invention uses the FCVD method to fill silicon nitride at the bottom of the SDB groove, which has good filling capacity; filling silicon oxide at the top of the SDB groove can avoid the problem of film loss due to the subsequent removal of the SiN layer; two layers of film stacks are formed in the SDB groove of the present invention, so that the risk of pressure release of the SiP epitaxial layer and the SiGe epitaxial layer is reduced; because the SiP epitaxial layer and the SiGe epitaxial layer are separated independently, the pressure released by the HK metal gate does not affect the SiP epitaxial layer and the SiGe epitaxial layer. . Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a SDB FinFET first cut, characterized in that: At least: Step 1, providing a substrate, forming a plurality of Fin structures arranged in a longitudinal direction at intervals on the substrate, wherein the length direction of the Fin structure is a transverse direction perpendicular to the longitudinal direction; forming a SiN layer on the Fin structure; and forming a first hard mask layer on the SiN layer; Step 2: depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the Fin structure; Step 3, depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, and then annealing; Step 4: grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed; Step 5, forming a SDB photoresist pattern on the SiN layer of the Fin structure; Step 6: etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove; Step 7: forming silicon nitride at the bottom of the SDB groove; Step eight, forming silicon oxide on the silicon nitride in the SDB groove; Step nine, removing the SiN layer; Step 10: removing the dielectric layer covering the Fin structure to expose the Fin structure; Step 11, forming a plurality of dummy gates arranged in a lateral direction and spaced apart from each other on the Fin structure and the SDB groove and sidewalls attached to the dummy gates; Step 12: forming a SiP epitaxial structure on the Fin structure between two adjacent dummy gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between two adjacent dummy gates on the other side of the SDB groove; Step 13: depositing an interlayer dielectric layer to cover the dummy gates and fill the spaces between the dummy gates; then grinding the interlayer dielectric layer until the tops of the dummy gates are exposed; Step 14: remove the dummy gate to form a groove; then fill the groove with HK metal to form an HK metal gate.

2. The method for manufacturing a pre-cut SDB FinFET according to claim 1, wherein: In step 2, the thin oxide layer is deposited on the upper surface of the substrate and the sidewall of the Fin structure by atomic layer deposition or in-situ water vapor generation.

3. The method for manufacturing a pre-cut SDB FinFET according to claim 1, wherein: The method for depositing the dielectric layer in step three is FCVD.

4. The method for manufacturing a pre-cut SDB FinFET according to claim 1, wherein: The grinding in step 4 is chemical mechanical grinding.

5. The method for manufacturing a pre-cut SDB FinFET according to claim 1, wherein: In step eight, after silicon oxide is formed on the silicon nitride layer in the SDB groove, the upper surface is ground.

6. The method for manufacturing a pre-cut SDB FinFET according to claim 1, wherein: In step 12, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates on one side of the SDB groove is two.

7. The method for manufacturing a pre-cut SDB FinFET according to claim 1, wherein: In step 12, the number of the SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove is two.

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