Power protection device and method

Abstract

The present application discloses a power protection device and method. The power protection device is applied to a device including a main power supply system. The main power supply system includes a system power supply, a switching circuit, a control circuit, and a supercapacitor circuit. The switching circuit is configured to conduct when the device is powered on, so that the main power supply system charges the capacitor in the supercapacitor circuit; conduct when the output voltage of the main power supply system sags, so that the supercapacitor in the supercapacitor circuit discharges to the main power supply system; and be turned off under the control of the control circuit. The control circuit is configured to control the switching circuit to turn off when the output voltage of the main power supply system is zero. The power protection device and method can solve the problem of affecting the operation of the device due to voltage sag or interruption, and improve the anti-interference ability of the power supply.

Description

Technical Field

[0001] This application relates to the field of power technologies, and particularly to a power protection device and method. Background Art

[0002] In the application scenarios of industrial equipment or power equipment, due to faults in power facilities or power grids, or sudden large changes in electrical loads, the supply voltage experiences two or more consecutive sags or interruptions, which can easily affect the stability of the operating equipment, causing the equipment to reset or even have a permanent failure. One current solution is to add many large capacitors in the equipment to maintain the stability of the system power supply, but this has a large volume and cannot meet the power supply requirements of the equipment. Another solution is to monitor the supply voltage. When a voltage sag is detected, the equipment is turned off and reset, or a backup power supply is turned on to supply power to the equipment. This solution requires the main control chip of the equipment to continuously monitor the power supply voltage, imposing an operating burden on the main control chip. Summary of the Invention

[0003] This application provides a power protection device and method, which can solve the problem of equipment operation affected by voltage sags or interruptions and improve the anti-interference ability of the power supply.

[0004] A power protection device provided by this application is applied to an equipment including a main power supply system, and the main power supply system includes a system power supply.

[0005] It includes a switch circuit, a control circuit, and a supercapacitor circuit;

[0006] The switch circuit is configured to conduct when the equipment is powered on, so that the main power supply system charges the capacitor in the supercapacitor circuit; conduct when the output voltage of the main power supply system sags, so that the supercapacitor in the supercapacitor circuit discharges to the main power supply system; and be turned off under the control of the control circuit;

[0007] The control circuit is configured to control the switch circuit to turn off when the output voltage of the main power supply system is zero.

[0008] In an exemplary embodiment, the supercapacitor circuit includes a current-limiting resistor and N supercapacitor groups; where N is an integer greater than or equal to 1;

[0009] Each supercapacitor group includes a charging balancing resistor and a supercapacitor, where the charging balancing resistor and the supercapacitor are in parallel;

[0010] The N supercapacitor groups are connected in series;

[0011] The first end of the current-limiting resistor is connected to the switching circuit; the second end of the current-limiting resistor is connected in series with the first end of the N series-connected supercapacitor banks; the second end of the N series-connected supercapacitor banks is grounded.

[0012] In an exemplary embodiment, the switching circuit includes a PMOS transistor, a first resistor, and a second resistor;

[0013] Wherein, the drain of the PMOS transistor is connected to the system power supply; the first resistor is connected across the gate and the source of the PMOS transistor;

[0014] The source of the PMOS transistor is connected to the supercapacitor circuit;

[0015] The first resistor is connected in series with the second resistor;

[0016] The first end of the second resistor is connected to the gate of the PMOS transistor;

[0017] The second end of the second resistor is connected to the control circuit;

[0018] The source of the PMOS transistor is connected to the current-limiting resistor of the supercapacitor circuit.

[0019] In an exemplary embodiment, the control circuit includes an NMOS transistor, a third resistor, and a fourth resistor;

[0020] The drain of the NMOS transistor is connected to the second end of the second resistor; the source of the NMOS transistor is grounded;

[0021] The first end of the third resistor is connected to the system power supply; the first end of the fourth resistor is grounded; the second end of the third resistor is connected to the second end of the fourth resistor;

[0022] The gate of the NMOS transistor is connected to the second end of the third resistor.

[0023] In an exemplary embodiment, the device further includes a main control chip;

[0024] The gate of the NMOS transistor is connected to the main control chip for controlling the switching circuit.

[0025] In an exemplary embodiment, the switching circuit further includes a first diode;

[0026] The anode of the first diode is connected to the drain of the PMOS transistor;

[0027] The cathode of the first diode is connected to the source of the PMOS transistor.

[0028] In an exemplary embodiment, the control circuit further includes a first capacitor;

[0029] The first capacitor is connected across the source and gate of the NMOS transistor.

[0030] In an exemplary embodiment, the supercapacitor circuit further includes a second diode;

[0031] The second diode is connected in parallel with the current-limiting resistor;

[0032] The cathode of the second diode is connected to the system power supply.

[0033] In an exemplary embodiment, the capacitance of the supercapacitor is determined according to the average operating current of the main power supply system and a preset discharge time.

[0034] A power protection method provided by the present application is applied to a device including a main power supply system, and includes:

[0035] When the device is powered on, the main power supply system charges the supercapacitor; when the duration of the temporary voltage drop of the output voltage of the main power supply system is within a preset first duration, the supercapacitor discharges to the main power supply system; when the duration of the temporary voltage drop of the output voltage of the main power supply system exceeds the preset first duration or the output voltage of the main power supply system is zero, the supercapacitor stops discharging to the main power supply system.

[0036] Other features and advantages of the present application will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0038] Figure 1 It is a schematic diagram of the power protection device according to the embodiment of the present application;

[0039] Figure 2 It is an example of the switching circuit and the control circuit according to the embodiment of the present application;

[0040] Figure 3 It is an example of the supercapacitor circuit according to the embodiment of the present application;

[0041] Figure 4 It is an example of the power protection device according to the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] Figure 1 Schematic diagram of the power protection device according to the embodiment of the present application, as Figure 1 shown, the power protection device of this embodiment includes a switch circuit, a control circuit, and a supercapacitor circuit.

[0043] The switch circuit is set to conduct when the device is powered on, so that the main power system charges the capacitor in the supercapacitor circuit; when the output voltage of the main power system sags, it conducts, so that the supercapacitor in the supercapacitor circuit discharges to the main power system; and is turned off under the control of the control circuit;

[0044] The control circuit is set to control the switch circuit to turn off when the output voltage of the main power system is zero.

[0045] In an exemplary embodiment, the supercapacitor circuit includes a current-limiting resistor and N groups of supercapacitor banks; where N is an integer greater than or equal to 1;

[0046] Each group of supercapacitor banks includes a charging balancing resistor and a supercapacitor, where the charging balancing resistor and the supercapacitor are connected in parallel;

[0047] The N groups of supercapacitor banks are connected in series;

[0048] The first end of the current-limiting resistor is connected to the switch circuit; the second end of the current-limiting resistor is connected in series with the first end of the N groups of supercapacitor banks connected in series; the second end of the N groups of supercapacitor banks connected in series is grounded.

[0049] In an exemplary embodiment, the resistance value of the current-limiting resistor can be a few ohms. The number of supercapacitor banks can be selected according to actual conditions.

[0050] In an exemplary embodiment, the switch circuit includes a PMOS transistor, a first resistor, and a second resistor;

[0051] Among them, the drain of the PMOS transistor is connected to the system power supply; the first resistor is connected across the gate and the source of the PMOS transistor;

[0052] The source of the PMOS transistor is connected to the supercapacitor circuit;

[0053] The first resistor is connected in series with the second resistor;

[0054] The first end of the second resistor is connected to the gate of the PMOS transistor;

[0055] The second end of the second resistor is connected to the control circuit;

[0056] The source electrode of the PMOS transistor is connected to the current-limiting resistor of the supercapacitor circuit.

[0057] In an exemplary embodiment, the source electrode of the PMOS transistor may be connected to the first end of the current-limiting resistor of the supercapacitor circuit.

[0058] In an exemplary embodiment, the first resistor and the second resistor ensure that the PMOS transistor realizes switch biasing. As a conducting switch transistor, a PMOS transistor with high current-carrying capacity can be used, and the voltage drop is low during normal conduction.

[0059] In an exemplary embodiment, the control circuit includes an NMOS transistor, a third resistor, and a fourth resistor;

[0060] The drain electrode of the NMOS transistor is connected to the first end of the second resistor; the source electrode of the NMOS transistor is grounded;

[0061] The first end of the third resistor is connected to the system power supply; the first end of the fourth resistor is grounded; the second end of the third resistor is connected to the second end of the fourth resistor;

[0062] The gate electrode of the NMOS transistor is connected to the second end of the third resistor.

[0063] In an exemplary embodiment, an NMOS transistor with a smaller turn-on voltage is used for the NMOS transistor, and resistors with higher precision are used for the third resistor and the fourth resistor. The magnitude of the system detection voltage can be adjusted by adjusting the resistance value.

[0064] In an exemplary embodiment, the device further includes a main control chip;

[0065] The gate electrode of the NMOS transistor is connected to the main control chip to control the switching circuit.

[0066] In an exemplary embodiment, the switching circuit further includes a first diode; the function of this diode is to provide a path when the system power supply charges the supercapacitor, preventing the current from being too large and burning out the PMOS transistor. A Schottky diode with a very small voltage drop can be used for this diode.

[0067] The anode of the first diode is connected to the drain electrode of the PMOS transistor;

[0068] The cathode of the first diode is connected to the source electrode of the PMOS transistor.

[0069] In an exemplary embodiment, the control circuit further includes a first capacitor; the main function of this first capacitor is to filter, reducing the malfunction of the NMOS transistor caused by external interference.

[0070] The first capacitor is connected between the source and the gate of the NMOS tube.

[0071] In an exemplary embodiment, the supercapacitor circuit also includes a second diode; the diode is cut off when the system power supply charges the supercapacitor, ensuring that the power passes through the resistor in parallel with the supercapacitor to ensure the balance of the supercapacitor charging voltage; when the supercapacitor is discharging, the diode provides a discharge path.

[0072] The second diode is connected in parallel with the current limiting resistor;

[0073] A cathode of the second diode is connected to a system power supply.

[0074] In an exemplary embodiment, the diode is a low-voltage-drop Schottky diode to ensure that the voltage drop of the system power after passing through D1 is small.

[0075] The voltage protection device of the embodiment of the present application is turned on when the device is powered on, so that the main power system charges the capacitor in the supercapacitor circuit; it is turned on when the output voltage of the main power system temporarily drops, so that the supercapacitor in the supercapacitor circuit discharges to the main power system; when the output voltage of the main power system is zero, the switch circuit is controlled to be closed, so that the supercapacitor is prohibited from outputting voltage. This solves the problem of device reset caused by voltage drop and temporary drop during EMC testing and actual application, and can realize fast power on and off, maintain stable operation of the device, and has low cost and simple circuit.

[0076] Figure 2 Examples of switch circuits and control circuits in the embodiments of the present application are as follows: Figure 2 As shown, it includes a PMOS tube (P-type metal oxide semiconductor field effect tube), a resistor R2, a resistor R3, an NMOS tube (N-type metal oxide semiconductor field effect tube), a resistor R4, a resistor R5, a first diode (i.e. Figure 2 D1 in), capacitor. Figure 2 The diode connected to the source of the NMOS tube and the drain of the NMOS tube is a diode provided by the NMOS tube, and the switching circuit and the control circuit do not have the diode.

[0077] The drain of the PMOS tube is connected to the system power supply; the resistor R2 (i.e. the first resistor) is connected across the gate of the PMOS tube and the source of the PMOS tube;

[0078] The source of the PMOS tube is connected to the supercapacitor circuit;

[0079] The resistor R2 (i.e. the first resistor) and the resistor R3 (i.e. the second resistor) are connected in series;

[0080] The first end of resistor R3 is connected to the gate of the PMOS transistor;

[0081] The second end of resistor R3 is connected to the drain of the NMOS transistor;

[0082] The source of the PMOS transistor is connected to the current-limiting resistor of the supercapacitor circuit.

[0083] The drain of the NMOS transistor is connected to the second end of resistor R3; the source of the NMOS transistor is grounded;

[0084] The first end of resistor R4 (i.e., the above-mentioned third resistor) is connected to the system power supply; the first end of resistor R5 (i.e., the above-mentioned fourth resistor) is grounded; the second end of resistor R4 is connected to the second end of resistor R5;

[0085] The gate of the NMOS transistor is connected to the second end of resistor R4.

[0086] A capacitor is connected between the gate and the source of the NMOS transistor;

[0087] The anode of the first diode is connected to the drain of the PMOS transistor; the first diode can be a Schott diode.

[0088] The cathode of the first diode is connected to the source of the PMOS transistor.

[0089] Port1 is a reserved spare port, which can be connected to the main control MCU chip of the device, and the switching circuit is controlled through the GPIO of the MCU.

[0090] The source of the PMOS transistor is connected to the input end of the subsequent supercapacitor circuit.

[0091] The system power supply is the power supply in the main power supply system of the device.

[0092] Figure 2 The working principle of the circuit is that when the device is powered on and works normally, the first diode (i.e., Figure 2 D1 in it), the PMOS transistor conducts, the NMOS transistor conducts, and the system power supply charges the supercapacitor, so that the voltage of the supercapacitor is equal to the voltage of the system power supply. When the supply voltage of the system power supply sags, and the voltage division of the system power supply through R4 and R5 does not turn off the NMOS transistor, at this time the PMOS transistor conducts, the NMOS transistor conducts, the first diode is cut off, and the second diode conducts, and the supercapacitor discharges to the system power supply.

[0093] If the sag time is too long, the voltage division of R4 and R5 turns off the NMOS transistor. At this time, the PMOS transistor is turned off, the NMOS transistor is turned off, the supercapacitor cannot discharge to the system power supply, and the system power supply quickly loses power, which will not affect the next quick power-on.

[0094] When the system power supply is normal, the supercapacitor only charges and does not discharge, and remains charged when full.

[0095] When the system power supply is interrupted, the NMOS transistor is turned off, the PMOS transistor is turned off, the first diode is turned off, and the supercapacitor cannot discharge to the system power supply.

[0096] Figure 3 An example of the supercapacitor circuit according to the embodiment of the present application is as Figure 3 shown. The supercapacitor circuit includes C2 (i.e., the supercapacitor in the above-mentioned supercapacitor bank), C3 (i.e., the supercapacitor in the above-mentioned supercapacitor bank), D2 (i.e., the above-mentioned second diode), R7 (i.e., the above-mentioned current-limiting resistor), R1 (i.e., the charging balance resistor in the above-mentioned supercapacitor bank), and R6 (i.e., the charging balance resistor in the above-mentioned supercapacitor bank).

[0097] The supercapacitor circuit includes R7 and two groups of supercapacitor banks;

[0098] Each group of supercapacitor banks includes a charging balance resistor and a supercapacitor, wherein the charging balance resistor and the supercapacitor are connected in parallel;

[0099] The two groups of supercapacitor banks are connected in series;

[0100] The first end of the current-limiting resistor is connected to the switching circuit (actually connected to the source of the PMOS transistor of the switching circuit); the second end of the current-limiting resistor is connected in series with the first end after the two groups of supercapacitor banks are connected in series; the second end after the two groups of supercapacitor banks are connected in series is grounded.

[0101] Figure 4 An example of the power protection device according to the embodiment of the present application. Figure 4 Includes Figure 2 the switching circuit and the control circuit, and Figure 3 the supercapacitor circuit.

[0102] The present application also provides a power protection method, which is applied to a device including a main power supply system, and includes:

[0103] When the device is powered on, the main power supply system charges the supercapacitor; when the duration of the temporary voltage drop of the output voltage of the main power supply system is within a preset first duration, the supercapacitor discharges to the main power supply system; when the duration of the temporary voltage drop of the output voltage of the main power supply system exceeds the preset first duration or the output voltage of the main power supply system is zero, the supercapacitor stops discharging to the main power supply system.

[0104] In the embodiments of the present application, during EMC testing and actual use, in the case of voltage dips and short interruptions, by using a supercapacitor as a backup circuit, short-term power supply to the device can be achieved, maintaining the normal operation of the device without reset and downtime. After power supply for a certain period of time, the circuit can quickly cut off the power to the device without the need for an additional discharge circuit. After the device loses power, the device can start quickly without the situation that the device cannot start immediately or operates abnormally due to the slow discharge of the backup battery. This extremely low-cost voltage drop protection circuit meets the EMC testing and actual application requirements and can achieve normal and fast power-on and power-off of the device, which has a positive impact on the R & D testing, passing inspection, and productization of power and industrial equipment.

[0105] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0106] The present application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in the present application can also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application can be implemented alone or in any suitable combination. Therefore, the embodiments are not subject to other restrictions except those made according to the appended claims and their equivalents. In addition, various modifications and changes can be made within the scope of protection of the appended claims.

[0107] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process does not depend on a particular order of the steps described herein, the method or process should not be limited to the particular order of steps described. As will be understood by those of ordinary skill in the art, other orders of steps are possible. Accordingly, the particular order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, as those skilled in the art can readily understand that such orders may vary and still remain within the spirit and scope of the embodiments of the present application.

[0108] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and their appropriate combinations. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be executed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that a communication medium typically contains computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

Claims

1. A power protection device is applied to an equipment including a main power system, and the main power system includes a system power supply. Characterized in that, it includes a switching circuit, a control circuit, and a supercapacitor circuit; The switching circuit is set to conduct when the equipment is powered on, so that the main power system charges the capacitor in the supercapacitor circuit; conduct when the output voltage of the main power system sags, so that the supercapacitor in the supercapacitor circuit discharges to the main power system; and is turned off under the control of the control circuit; The control circuit is set to control the switching circuit to turn off when the output voltage of the main power system is zero; Wherein, the supercapacitor circuit includes a current-limiting resistor and N groups of supercapacitor groups; where N is an integer greater than or equal to 1; Each group of supercapacitor groups includes a charging balancing resistor and a supercapacitor, wherein the charging balancing resistor and the supercapacitor are connected in parallel; The N groups of supercapacitor groups are connected in series; The first end of the current-limiting resistor is connected to the switching circuit; the second end of the current-limiting resistor is connected in series with the first end of the N groups of supercapacitor groups connected in series; the second end of the N groups of supercapacitor groups connected in series is grounded; The switching circuit includes a PMOS transistor, a first resistor, and a second resistor; Wherein, the drain of the PMOS transistor is connected to the system power supply; the first resistor is connected across the gate and the source of the PMOS transistor; The source of the PMOS transistor is connected to the supercapacitor circuit; The first resistor is connected in series with the second resistor; The first end of the second resistor is connected to the gate of the PMOS transistor; The second end of the second resistor is connected to the control circuit; The source of the PMOS transistor is connected to the current-limiting resistor of the supercapacitor circuit; The control circuit includes an NMOS transistor, a third resistor, and a fourth resistor; The drain of the NMOS transistor is connected to the second end of the second resistor; the source of the NMOS transistor is grounded; The first end of the third resistor is connected to the system power supply; the first end of the fourth resistor is grounded; the second end of the third resistor is connected to the second end of the fourth resistor; The gate of the NMOS transistor is connected to the second end of the third resistor.

2. The device according to claim 1, Characterized in that, the equipment further includes a main control chip; The gate of the NMOS transistor is connected to the main control chip for controlling the switching circuit.

3. The device according to claim 1, Characterized in that, the switching circuit further includes a first diode; The anode of the first diode is connected to the drain of the PMOS transistor; The cathode of the first diode is connected to the source of the PMOS transistor.

4. The device according to claim 1, Characterized in that, the control circuit further includes a first capacitor; The first capacitor is connected across the source and the gate of the NMOS transistor.

5. The device according to claim 1, Characterized in that, the supercapacitor circuit further includes a second diode; The second diode is connected in parallel with the current-limiting resistor; The cathode of the second diode is connected to the system power supply.

6. The device according to claim 1, Characterized in that, The capacitance of the super capacitor is determined according to the average working current of the main power supply system and a preset discharge time.

7. A power supply protection method applied to a device including a main power supply system, characterized in that, when the device is powered on, the main power supply system charges the super capacitor, wherein the device includes the power supply protection device according to any one of claims 1 to 6; when the output voltage of the main power supply system drops for a duration within a preset first duration, the super capacitor discharges to the main power supply system; when the output voltage of the main power supply system drops for a duration exceeding the preset first duration or the output voltage of the main power supply system is zero, the super capacitor stops discharging to the main power supply system.

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