A charge pump parasitic capacitance charge recovery circuit
By introducing a switch φ3 into the charge pump and controlling its opening and closing timing, the problem of additional power consumption caused by parasitic capacitance was solved, and the conversion efficiency of the charge pump was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEW VISION MICROELECTRONICS INC
- Filing Date
- 2021-10-19
- Publication Date
- 2026-06-23
Smart Images
Figure CN114301276B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of charge pump technology, and in particular to a charge recovery circuit for a charge pump with parasitic capacitance. Background Technology
[0002] A charge pump, also known as a switched-capacitor voltage converter, is a DC-DC converter that uses a capacitor (rather than an inductor or transformer) to store energy, either "flying" or "pumping." A charge pump is a DC-DC converter that uses capacitors as energy storage elements, often to generate an output voltage higher than the input voltage or a negative output voltage. Charge pump circuits are highly efficient, around 90-95%, and the circuitry is quite simple. Charge pumps use switching elements to control the voltage connected to the capacitor. For example, a two-stage cycle can be used to generate a higher pulse voltage output from a lower input voltage. In the first stage of the cycle, the capacitor is connected to the power supply and thus charged to the same voltage. In the second stage, the circuit configuration is adjusted so that the capacitor and the power supply voltage are connected in series. Ignoring leakage current effects and assuming no load, the output voltage will be twice the input voltage.
[0003] Because Cfly1 and Cfly2 are integrated into the IC, in actual layout implementation, the upper and lower plates of Cfly1 and Cfly2 will have varying degrees of parasitic capacitances Cpara11, Cpara12, Cpara21, and Cpara22 with other layers (CMOS devices and metal interconnect layers). When the charge pump charges and discharges Cfly1 and Cfly2, additional power consumption is generated on the parasitic capacitances, thus reducing the conversion efficiency of the charge pump. Especially in processes with small capacitance values per unit area, in order to ensure that the designed capacitance value remains unchanged, the layout needs to be larger, which further increases the size of the parasitic capacitance, thereby greatly reducing the conversion efficiency of the charge pump.
[0004] Currently, there is no technical solution that can solve the above-mentioned technical problems. Specifically, there is no charge recovery circuit for the parasitic capacitor of the charge pump. Summary of the Invention
[0005] To address the technical shortcomings of existing capacitor circuits under heavy load conditions, this invention provides a charge pump parasitic capacitance charge recovery circuit, comprising at least a first unit circuit, a second unit circuit, a first switch group, and a second switch group.
[0006] The first switch group includes at least φ11, φ12, φ13, and φ14, and the second switch group includes at least φ21, φ22, φ23, and φ24.
[0007] The first unit circuit includes a first capacitor Cfly1, and the two ends of the first capacitor Cfly1 are respectively provided with a C1P node and a C1N node. The C1P node is connected to the input voltage VDD through a φ11 switch and to the output voltage VSP through a φ21 switch. The C1N node is connected to ground through a φ13 switch and to the input voltage VDD through a φ23 switch.
[0008] The second unit circuit includes a second capacitor Cfly2. The two ends of the second capacitor Cfly2 are respectively provided with a C2P node and a C2N node. The C2P node is connected to the input voltage VDD through a φ22 switch and connected to the output voltage VSP through a φ12 switch. The C2N node is connected to ground through a φ24 switch and connected to the input voltage VDD through a φ14 switch.
[0009] The C1P node and the C2P node are connected by a φ3 switch;
[0010] Specifically, the opening and closing of the first switch group, the second switch group, and the φ3 switch are controlled by timing sequence T1, T2, T3, and T4, and parasitic capacitance charge recovery is achieved through the following control timing sequence:
[0011] - T1 is the non-overlapping switching time of the first switch group and the second switch group;
[0012] - The duration of timing T2 is equal to the duration of timing T4, which is the non-overlapping time of switching of φ3 with the first switch group and the second switch group;
[0013] - T3 is the closing time of the switch with a diameter of φ3;
[0014] Specifically, when φ11, φ12, φ13, φ14 of the first switch group, φ21, φ22, φ23, φ24 of the second switch group, and φ3 are at a high level, the first and second switch groups are defined as closed, that is, when the above switches are at a high level, these switches are in a closed state; when φ11, φ12, φ13, φ14 of the first switch group, φ21, φ22, φ23, φ24 of the second switch group, and φ3 are at a low level, the first and second switch groups are defined as open.
[0015] Preferably, the first capacitor Cfly1 and the second capacitor Cfly2 are integrated inside the IC chip. In actual operation, the upper and lower plates of the first capacitor Cfly1 have parasitic capacitances Cpara11 and Cpara12 with the CMOS device and metal interconnection, and the upper and lower plates of the second capacitor Cfly2 have parasitic capacitances Cpara21 and Cpara22 with the CMOS device and metal interconnection.
[0016] Preferably, when the first switch group and the second switch group are in the open state, and the first capacitor Cfly1 has completed charging, the voltage of the C1P node is the operating voltage VDD, and the voltage of the C1N node is GND; when the second capacitor Cfly2 has completed discharging, the voltage of the C2P node is twice the operating voltage VDD, and the voltage of the C2N node is VDD.
[0017] When the switch φ3 is closed, the charge loss of the parasitic capacitors Cpara11, Cpara12, Cpara21, and Cpara22 is reduced by 50%.
[0018] Based on existing technology, the charge pump of this invention introduces a switch φ3 between the first power supply circuit and the second unit circuit, and uses timing control to control the opening and closing of the first switch group, the second switch group, and the φ3 switch, thereby realizing the function of recovering parasitic capacitance charge. This invention can reduce parasitic capacitance charge loss by about 50% and can be applied to any circuit topology using a complementary structure charge pump to achieve the goal of reducing parasitic capacitance charge loss. This invention has a simple structure, powerful function, and significant commercial value. Attached Figure Description
[0019] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0020] Figure 1 The diagram illustrates a connection schematic of a charge pump parasitic capacitor charge recovery circuit under ideal operating conditions, according to a specific embodiment of the present invention.
[0021] Figure 2 This invention provides a schematic diagram of the connection of a charge pump parasitic capacitor charge recovery circuit under actual working conditions, according to a first embodiment of the present invention.
[0022] Figure 3 The diagram illustrates a control timing diagram for controlling the opening and closing of the first switch group, the second switch group, and the φ3 switch, according to a second embodiment of the present invention.
[0023] Figure 4 The equivalent circuit diagram of the third embodiment of the present invention when switch φ3 is not closed is shown; and
[0024] Figure 5 The equivalent circuit diagram of the fourth embodiment of the present invention when switch φ3 is closed is shown. Detailed Implementation
[0025] To better illustrate the technical solution of the present invention, the present invention will be further described below with reference to the accompanying drawings.
[0026] Figure 1 This invention illustrates a connection diagram of a charge pump parasitic capacitance charge recovery circuit under ideal operating conditions, representing a specific embodiment of the invention. The charge pump parasitic capacitance charge recovery circuit provided by this invention includes at least a first unit circuit, a second unit circuit, a first switch group, and a second switch group. The first unit circuit is located at... Figure 1 On the left, the second unit circuit is located Figure 1 On the right side, the first switch group includes at least φ11, φ12, φ13, and φ14, and the second switch group includes at least φ21, φ22, φ23, and φ24. The first switch group controls the linkage of φ11, φ12, φ13, and φ14, and the second switch group controls the linkage of φ21, φ22, φ23, and φ24.
[0027] Furthermore, the first unit circuit includes a first capacitor Cfly1, with a C1P node and a C1N node respectively located at its two ends. The C1P node is connected to the input voltage VDD via a φ11 switch and to the output voltage VSP via a φ21 switch; the C1N node is connected to ground via a φ13 switch and to the input voltage VDD via a φ23 switch.
[0028] The second unit circuit includes a second capacitor Cfly2. The two ends of the second capacitor Cfly2 are respectively provided with a C2P node and a C2N node. The C2P node is connected to the input voltage VDD through a φ22 switch and connected to the output voltage VSP through a φ12 switch. The C2N node is connected to ground through a φ24 switch and connected to the input voltage VDD through a φ14 switch.
[0029] The C1P node and the C2P node are connected by a φ3 switch.
[0030] Those skilled in the art will understand that, in this application Figure 1 as well as Figure 2There are two C1P nodes and two C2P nodes in the diagram. The two C1P nodes on the left are equivalent nodes, and the two C2P nodes on the right are also equivalent nodes. To avoid ambiguity for those skilled in the art, they are all labeled the same way. That is, two C1P nodes can be equivalent to one node, and two C2P nodes can also be equivalent to one node. For better understanding of the connection structure of the φ3 switch in the diagram, this is marked, and will not be elaborated further here.
[0031] The basic principle of a charge pump is that capacitors are charged and discharged using different connection methods, such as parallel charging and series discharging, or series charging and parallel discharging, to achieve voltage conversion functions such as boosting, bucking, and negative voltage. (This is in conjunction with the present application.) Figure 1 as well as Figure 2 Currently, there is no φ3 in the existing technology. The charge pump currently uses a complementary topology technology, utilizing non-overlapping switching clocks of the first and second switch groups to control the switching and charge / discharge different capacitors, thereby obtaining a smaller output voltage (VSP) ripple. To reduce the ripple on the output voltage, the first and second unit circuits are designed with the exact same dimensions; the only difference between the two units is the control timing. Specifically, when the first and second switch groups are high, the switches are closed; when the first and second switch groups are low, the switches are open. In the first switch group phase, Cfly1 is in the charging state and Cfly2 is in the discharging state; in the second switch group phase, Cfly1 is in the discharging state and Cfly2 is in the charging state; the cycle repeats from first switch group → second switch group → first switch group → second switch group →… After several cycles, VSP eventually rises to a voltage of 2*VDD.
[0032] Figure 2The diagram illustrates a connection schematic of a charge pump parasitic capacitance charge recovery circuit according to a first embodiment of the present invention, in actual operation. The first capacitor Cfly1 and the second capacitor Cfly2 are integrated within an IC chip. In actual operation, the upper and lower plates of the first capacitor Cfly1 have parasitic capacitances Cpara11 and Cpara12 with the CMOS device and metal interconnects, respectively. Similarly, the upper and lower plates of the second capacitor Cfly2 have parasitic capacitances Cpara21 and Cpara22 with the CMOS device and metal interconnects. Because Cfly1 and Cfly2 are integrated into the IC, in actual layout implementation, the upper and lower plates of Cfly1 and Cfly2 will have varying degrees of parasitic capacitances Cpara11, Cpara12, Cpara21, and Cpara22 with other layers (CMOS device and metal interconnect layers). When the charge pump charges and discharges Cfly1 and Cfly2, additional power consumption is generated on these parasitic capacitances, thereby reducing the conversion efficiency of the charge pump. Especially in processes with small capacitance per unit area, in order to ensure that the designed capacitance remains unchanged, the layout needs to cover a larger area, which further increases the size of parasitic capacitance, thereby greatly reducing the conversion efficiency of the charge pump.
[0033] In order to solve the problem of additional power consumption caused by parasitic capacitances Cpara11, Cpara12, Cpara21, and Cpara22, the present invention preferably adds φ3 between node C2P and node C1P. After closing switch φ3, the charge loss of parasitic capacitances Cpara11, Cpara12, Cpara21, and Cpara22 is reduced by 50%.
[0034] Figure 3 The diagram illustrates a control timing diagram for controlling the opening and closing of the first switch group, the second switch group, and the φ3 switch, according to a second embodiment of the present invention.
[0035] Furthermore, the opening and closing of the first switch group, the second switch group, and the φ3 switch are controlled by timing sequence T1, T2, T3, and T4. Parasitic capacitance charge recovery is achieved through the following control timing sequence: when the first switch group, the second switch group, and φ3 are at a high level, the switch is closed; when the first switch group, the second switch group, and φ3 are at a low level, the switch is open. T1 is the non-overlapping time of the first and second switch groups; T2 = T4, which is the non-overlapping time of φ3 with the first and second switch groups; and T3 is the closing time of the φ3 switch.
[0036] Figure 4The equivalent circuit diagram of the third embodiment of the present invention when switch φ3 is not closed is shown. Figure 5 The equivalent circuit diagram of the fourth embodiment of the present invention when switch φ3 is closed is shown. When the first switch group and the second switch group are in the open state, and the first capacitor Cfly1 has been fully charged, the voltage of the C1P node is the operating voltage VDD, and the voltage of the C1N node is GND; the second capacitor Cfly2 has been fully discharged, the voltage of the C2P node is twice the operating voltage VDD, and the voltage of the C2N node is VDD. When switch φ3 is closed, the charge loss of the parasitic capacitors Cpara11, Cpara12, Cpara21, and Cpara22 is reduced by 50%.
[0037] Furthermore, such as Figure 4 As shown, the charge on Cpara11 is Cpara11*VDD, the charge on Cpara12 is Cpara11*GND, the charge on Cpara21 is Cpara21*2*VDD, and the charge on Cpara22 is Cpara22*VDD. Since the first unit circuit is exactly the same as the second unit circuit, Cfly1 = Cfly2, Cpara11 = Cpara21, and Cpara12 = Cpara22. Let Cfly1 = Cfly2 = C1, Cpara11 = Cpara21 = C2, and Cpara12 = Cpara22 = C3. Figure 5 As shown, when switch φ3 is closed, the capacitors of the first and second unit circuits share charge. After sharing, the voltage across capacitor Cpara12 is... The voltage across capacitor Cpara22 is, The voltage across capacitor Cpara11 is approximately 1.5 x VDD, and the voltage across capacitor Cpara21 is approximately 1.5 x VDD. Since C1 >> C3, the voltage across capacitors Cpara12 and Cpara22 is approximately 0.5 x VDD.
[0038] Based on the above calculations, it can be seen that during the transition from the charging state to the discharging state in the first unit circuit, after adding the φ3 switch, the charge saved by parasitic capacitor C3 is approximately 0.5 x VDD*C3, and the charge saved by parasitic capacitor C2 is approximately 0.5 x VDD*C2; during the transition from the discharging state to the charging state in the second unit circuit, after adding the φ3 switch, the charge saved by parasitic capacitor C3 is approximately 0.5 x VDD*C3, and the charge saved by parasitic capacitor C2 is approximately 0.5 x VDD*C2.
[0039] In summary, we can conclude that by adding a φ3 switch between the first unit circuits of the charge pump and through reasonable timing control, parasitic capacitance charge loss can be reduced by about 50%. This invention can be applied to any circuit topology of the above-mentioned charge pump with complementary structure, and can achieve the purpose of reducing parasitic capacitance charge loss.
[0040] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.
Claims
1. A charge pump parasitic capacitance charge recovery circuit, characterized in that, It includes at least a first unit circuit, a second unit circuit, a first switch group, and a second switch group. The first switch group includes at least φ11, φ12, φ13, and φ14, and the second switch group includes at least φ21, φ22, φ23, and φ24. The first unit circuit includes a first capacitor Cfly1, and the two ends of the first capacitor Cfly1 are respectively provided with a C1P node and a C1N node. The C1P node is connected to the input voltage VDD through a φ11 switch and to the output voltage VSP through a φ21 switch. The C1N node is connected to ground through a φ13 switch and to the input voltage VDD through a φ23 switch. The second unit circuit includes a second capacitor Cfly2. The two ends of the second capacitor Cfly2 are respectively provided with a C2P node and a C2N node. The C2P node is connected to the input voltage VDD through a φ22 switch and connected to the output voltage VSP through a φ12 switch. The C2N node is connected to ground through a φ24 switch and connected to the input voltage VDD through a φ14 switch. The C1P node and the C2P node are connected by a φ3 switch; Specifically, the opening and closing of the first switch group, the second switch group, and the φ3 switch are controlled by timing sequence T1, T2, T3, and T4, and parasitic capacitance charge recovery is achieved through the following control timing sequence: - T1 is the non-overlapping switching time of the first switch group and the second switch group; - The duration of timing T2 is equal to the duration of timing T4, which is the non-overlapping time of switching of φ3 with the first switch group and the second switch group; - T3 is the closing time of the switch with a diameter of φ3; Specifically, when φ11, φ12, φ13, φ14 of the first switch group, φ21, φ22, φ23, φ24 of the second switch group, and φ3 are at a high level, the first switch group and the second switch group are defined as closed; when φ11, φ12, φ13, φ14 of the first switch group, φ21, φ22, φ23, φ24 of the second switch group, and φ3 are at a low level, the first switch group and the second switch group are defined as open.
2. The charge recovery circuit according to claim 1, characterized in that, The first capacitor Cfly1 and the second capacitor Cfly2 are integrated inside the IC chip. In actual operation, the upper and lower plates of the first capacitor Cfly1 have parasitic capacitances Cpara11 and Cpara12 with the CMOS device and metal connection, and the upper and lower plates of the second capacitor Cfly2 have parasitic capacitances Cpara21 and Cpara22 with the CMOS device and metal connection.
3. The charge recovery circuit according to claim 1, characterized in that, When the first and second switch groups are in the open state, and the first capacitor Cfly1 has finished charging, the voltage at node C1P is the operating voltage VDD, and the voltage at node C1N is GND; when the second capacitor Cfly2 has finished discharging, the voltage at node C2P is twice the operating voltage VDD, and the voltage at node C2N is VDD. When the switch φ3 is closed, the charge loss of the parasitic capacitors Cpara11, Cpara12, Cpara21, and Cpara22 is reduced by 50%.