A switching lookup table circuit configuration method and switching lookup table circuit

Abstract

The application discloses a switching lookup table circuit configuration method, a switching lookup table circuit, an error correction code memory and electronic equipment. First, input contents of multiple input addresses of a lookup table circuit are acquired, then, the multiple input addresses are divided into address combinations of a first number, and each address combination is divided into address units of a second number according to input contents of corresponding input positions in the address combination, wherein the second number of the address units divided by different address combinations is the same or different, further, based on the address units of the second number divided by each address combination, the switching lookup table circuit with a hierarchy of the first number is configured. Therefore, the number of transistors is greatly reduced, so that the area of the lookup table synthesis circuit is greatly reduced. Meanwhile, there is no power-to-ground path in the circuit obtained based on the above lookup table circuit configuration method, so that the static power consumption caused by the leakage of transistor devices can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memory, and in particular to a switching lookup table circuit configuration method, a switching lookup table circuit, an error correction code memory and an electronic device. Background Art

[0002] Lookup table circuits have a wide range of applications. Current lookup table architectures are mainly synthesized using RTL (Register Transfer Level) code or ROM (Read-Only Memory).

[0003] However, combined Figure 1 The RTL code shown synthesizes a lookup table circuit consisting of multiple logic gates. As can be seen, this RTL code-synthesized lookup table circuit suffers from large logic gate area and high static power consumption. Furthermore, during the Place & Route process (placing and connecting logic gates), the area utilization is very low, typically less than 80%. Consequently, the chip area using this type of lookup table circuit is significantly increased.

[0004] Combine Figure 2 As shown in the lookup table circuit using ROM, it can be seen that although ROM has a smaller area, it can solve the problem of large area of ​​the lookup table circuit synthesized using RTLCode. However, ROM is a read-only memory, but the addressing space of ROM must be continuous. Therefore, due to the limitations of the ROM structure, there is still a large waste of area and high power consumption for the use scenarios of ECC (Error Correction Code) or other non-continuous lookup table circuits. In addition, whether it is 1 or 0 in the ROM, a transistor needs to be configured, which occupies the area of ​​​​a transistor.

[0005] It should be noted that Figure 1 The wasted area and Figure 2 The unused addresses are just for illustration. Figure 1 The locations processed by VIA (via) and W / O DiffusioIN (cancel channel connection) are all wasted areas. Figure 2 The locations that are processed in the same way as the unused addresses in the dotted box are also unused addresses, which will cause a large waste of chip area. Summary of the Invention

[0006] In order to solve the above problems, embodiments of the present invention creatively provide a switching lookup table circuit configuration method, a switching lookup table circuit, an error correction code memory, and an electronic device.

[0007] According to a first aspect of the present invention, a method for configuring a switching lookup table circuit is provided, the method comprising: obtaining input contents of a plurality of input addresses of a lookup table circuit; dividing the plurality of input addresses into a first number of address combinations; dividing the address combinations into a second number of address units according to the input contents of the corresponding input positions in each of the address combinations, wherein the second numbers of the address units divided by different address combinations are the same or different; and configuring a switching lookup table circuit having a first number of levels based on the second number of address units divided by each of the address combinations.

[0008] According to one embodiment of the present invention, the multiple input addresses are divided into a first number of address combinations, including: dividing the multiple input addresses in multiple forms according to the number of the input addresses, wherein the multiple address combinations obtained by dividing in the same form have the same number of input addresses; and determining the address combination with the highest probability that the input contents of the corresponding input positions of adjacent input addresses are the same as the final divided address combination.

[0009] According to an embodiment of the present invention, dividing the address combination into a second number of address units according to the input content of the corresponding input position in each address combination includes: treating the input positions with the same input content in each address combination as one address unit.

[0010] According to one embodiment of the present invention, based on the second number of address units divided by each of the address combinations, a switching lookup table circuit having a hierarchy of the first number is configured, including: for the address combination with the smallest second number, the address combination is configured according to the input content of each address unit in the address combination, and a plurality of address combinations are configured in sequence according to the second number of the address units of the address combination; wherein, configuring the address combination according to the input content of each address unit in the address combination includes: for an input position with an input content of 1, configuring a transistor on the positive signal input line of the corresponding input address; and for an input position with an input content of 0, configuring a transistor on the negative signal input line of the corresponding input address.

[0011] According to one embodiment of the present invention, a switching lookup table circuit having a first number of levels is configured based on the second number of address units divided by each of the address combinations, and further includes: sequentially connecting the first number of address combinations according to the order in which the multiple address combinations are configured; connecting the transistors configured at the first input address in the first address combination to the reset transistor at the power supply end; and connecting the transistors configured at the last input address in the last address combination to the ground end.

[0012] According to a second aspect of an embodiment of the present invention, a switching lookup table circuit is further provided. The switching lookup table circuit is configured using the switching lookup table circuit configuration method described above.

[0013] According to one embodiment of the present invention, the transistors configured at the first input address in the first address combination in the switching lookup table circuit are all connected to the reset transistor at the power supply end; and the transistors configured at the last input address in the last address combination are all connected to the ground end.

[0014] According to a third aspect of an embodiment of the present invention, an error correction code memory is further provided. The error correction code memory includes the switching lookup table circuit as described above.

[0015] According to an embodiment of the present invention, the ECC memory is a 64-bit south bridge two-way ECC memory.

[0016] According to a fourth aspect of the embodiments of the present invention, an electronic device is further provided, comprising the error correction code memory as described above.

[0017] Embodiments of the present invention provide a method for configuring a switchable lookup table circuit, a switchable lookup table circuit, an error correction code memory, and an electronic device. First, the input contents of multiple input addresses of the lookup table circuit are obtained. Then, the multiple input addresses are divided into a first number of address combinations. The address combinations are divided into a second number of address units based on the input contents of the corresponding input positions in each address combination. The second number of address units divided by different address combinations may be the same or different. Furthermore, a switchable lookup table circuit having a first number of levels is configured based on the second number of address units divided by each address combination. Thus, during the configuration of transistors in the lookup table circuit, input positions with the same input contents can be merged, significantly reducing the number of transistors and thus the area of ​​the lookup table synthesis circuit. Furthermore, the circuit obtained based on the above lookup table circuit configuration method does not have a path from power to ground, effectively reducing static power consumption caused by transistor device leakage.

[0018] It should be understood that the teachings of the present invention do not necessarily achieve all of the beneficial effects described above, but specific technical solutions can achieve specific technical effects, and other embodiments of the present invention can also achieve beneficial effects not mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily apparent by reading the following detailed description with reference to the accompanying drawings, in which several embodiments of the present invention are shown by way of example and not limitation, in which:

[0020] The same or corresponding reference numerals in the drawings denote the same or corresponding parts.

[0021] Figure 1 A lookup table circuit schematic diagram including multiple logic gates in the prior art RTL Code synthesis is shown;

[0022] Figure 2 A lookup table circuit schematic diagram using ROM in the prior art is shown;

[0023] Figure 3 An implementation flowchart of the switching lookup table circuit configuration method of the embodiment of the present application is shown;

[0024] Figure 4 An input address table and circuit architecture schematic diagram of the application example of the switching lookup table circuit of the embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] The principles and spirits of the present application will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are given only to enable those skilled in the art to better understand and implement the present application, and do not limit the scope of the present application in any way. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0026] The technical solutions of the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0027] Figure 3 An implementation flowchart of the switching lookup table circuit configuration method of the embodiment of the present application is shown;

[0028] Reference Figure 3 The switching lookup table circuit configuration method of the embodiment of the present application at least includes the following operation flow: operation 301, obtaining the input content of multiple input addresses of the lookup table circuit; operation 302, dividing the multiple input addresses into address combinations of a first number; operation 303, dividing the address combinations into address units of a second number according to the input content of the corresponding input positions in each address combination, wherein the second number of the address units divided by different address combinations is the same or different; operation 304, based on the second number of the address units divided by each address combination, configuring the switching lookup table circuit with a hierarchy of the first number.

[0029] In operation 301, the input content of multiple input addresses of the lookup table circuit is obtained.

[0030] In one embodiment of the present invention, the lookup table may have multiple input addresses, for example, 6, 8, 10, or 12 input addresses. The number of bits of the input position on each input address is generally the same, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0031] In this embodiment of the present invention, multiple input addresses can be divided into multiple forms according to the number of input addresses, and the address combination with the highest probability that the input content of the corresponding input positions of adjacent input addresses is the same is determined as the final divided address combination. In this case, multiple address combinations obtained by using the same division form have the same number of input addresses.

[0032] For example, the input addresses include IN[0], IN[1], IN[2], IN[3], IN[4], and IN[5]. Each input address includes 8 input positions. For example, the input content of IN[0] includes 8 input positions, which is "0 00 0 0 0 1 1".

[0033] In operation 302, a plurality of input addresses are divided into a first number of address combinations.

[0034] In this embodiment of the present invention, each address combination includes the same number of input addresses.

[0035] For example, a lookup table with six input addresses, IN[0], IN[1], IN[2], IN[3], IN[4], and IN[5], can be divided into two address combinations, one of which is IN[0], IN[1], and IN[2], and the other is IN[3], IN[4], and IN[5]. Similarly, the six input addresses, IN[0], IN[1], IN[2], IN[3], IN[4], and IN[5], can be divided into three address combinations, the first of which is IN[0] and IN[1], the second is IN[2] and IN[3], and the third is IN[4] and IN[5].

[0036] In operation 303 , the address combination is divided into a second number of address units according to the input content of the corresponding input position in each address combination, wherein the second number of address units divided by different address combinations is the same or different.

[0037] In one embodiment of the present invention, the address combination is divided into a second number of address units according to the input content of the corresponding input position in each address combination, including: treating input positions with the same input content in each address combination as one address unit.

[0038] For example, the input contents of the input addresses IN[0], IN[1], IN[2], IN[3], IN[4] and IN[5] are respectively as follows:

[0039] IN[0]: 0 0 0 0 0 0 1 1;

[0040] IN[1]: 0 0 0 0 1 0 1 1;

[0041] IN[2]: 0 0 0 0 1 1 1 0;

[0042] IN[3]: 0 0 1 1 0 0 0 0;

[0043] IN[4]: 0 1 0 1 1 0 0 1;

[0044] IN[5]: 0 0 1 0 0 1 1 1.

[0045] If IN[0] and IN[1] are taken as the first address combination, IN[2] and IN[3] are taken as the second address combination, and IN[4] and IN[5] are taken as the third address combination, the input contents of the first four input positions of IN[0] and IN[1] are all the same, and thus the input contents of the four input positions can be taken as an address unit "IN[0]=0 IN[1]=0".

[0046] In operation 304, a switchable lookup table circuit with a first number of levels is configured based on the second number of address units of each address combination.

[0047] In an embodiment of the present application, for the address combination with the second number being the smallest, a plurality of address combinations are configured according to the input contents of each address unit in the address combination, and the address combinations are configured in sequence according to the second number of address units of the address combination. For the input position with the input content being 1, a transistor is configured on the forward signal input line of the corresponding input address, and for the input position with the input content being 0, a transistor is configured on the reverse signal input line of the corresponding input address.

[0048] For example, for the address unit "IN[0]=0 IN[1]=0" determined in operation 303, a transistor can be configured on the reverse signal input lines INB[0] and INB[1] of the input address IN[0] respectively.

[0049] In an embodiment of the present application, the transistor can be PMOS or NMOS.

[0050] In one embodiment of the present application, the address combination of the first number is sequentially connected according to the order of configuring the plurality of address combinations, and the transistor configured at the first input address in the first address combination is connected to the reset transistor at the power supply end, and the transistor configured at the last input address in the last address combination is connected to the ground end.

[0051] For example, the first input address of the first address combination IN[0] and IN[1] is N[0]. Taking the transistor configured at the input address according to the address unit "IN[0]=0 IN[1]=0" as an example. The collector of the transistor configured at the input address IN[0] is connected to the emitter of the reset transistor at the power supply end. The base of the transistor configured at the input address IN[0] is connected to the reverse signal input line INB[0] of IN[0]. The emitter of the transistor configured at the input address IN[0] is connected to the collector of the transistor configured at the reverse signal input line INB[1] of IN[1].

[0052] The last address of the third address combination IN[4] and IN[5] is N[5]. Taking the transistor configured at the input address according to the address unit "IN[4]=0 IN[5]=0" as an example. The collector of the transistor configured at the input address IN[5] is connected to the emitter of the transistor configured at the reverse signal input line INB[4] of IN[4]. The base of the transistor configured at the input address IN[5] is connected to the reverse signal input line INB[5] of IN[5]. The emitter of the transistor configured at the input address IN[5] is connected to the ground end.

[0053] Figure 4 The input address table and the circuit architecture schematic diagram of the application example of the switching lookup table circuit are shown.

[0054] Reference Figure 4 The embodiment of the present application also provides a switching lookup table circuit configured by using the switching lookup table circuit configuration method.

[0055] In this embodiment of the present application, the transistor configured at the first input address in the first address combination in the switching lookup table circuit is connected to the reset transistor at the power supply end, and the transistor configured at the last input address in the last address combination is connected to the ground end.

[0056] As Figure 4As shown in (a), the input contents of input addresses IN[0], IN[1], IN[2], IN[3], IN[4] and IN[5] are:

[0057] IN[0]:0 0 0 0 0 0 1 1;

[0058] IN[1]:0 0 0 0 1 0 1 1;

[0059] IN[2]:0 0 0 0 1 1 1 0;

[0060] IN[3]:0 0 1 1 0 0 0 0;

[0061] IN[4]:0 1 0 1 1 0 0 1;

[0062] IN[5]:0 0 1 0 0 1 1 1.

[0063] These 6 input addresses can be divided into Figure 4 (b) shows three address units: IN[0] and IN[1] as the first address combination, IN[2] and IN[3] as the second address combination, and IN[4] and IN[5] as the third address combination.

[0064] Furthermore, according to the input contents of the six input addresses, the address units are further divided into Figure 4 (b) shows multiple address units. Figure 4 The address units shown in (b) are merely exemplary notations of the address units.

[0065] Further, according to Figure 4 The address unit obtained in (b) is constructed as follows Figure 4 (c) shows a switching lookup table circuit. Here, INB[X] is the inverted signal of IN[X], where X∈(0-5). RSTB is the reset terminal of the switching lookup table circuit. DOUT is the output terminal of the switching lookup table circuit.

[0066] Based on the above switching lookup table circuit configuration method, an embodiment of the present invention further provides an error correction code memory, which includes the above switching lookup table circuit.

[0067] In one embodiment of the present invention, the ECC memory is a 64-bit BCH 2-bit ECC memory (64-bit south bridge two-way ECC memory).

[0068] According to a fourth aspect of the embodiments of the present invention, an electronic device is further provided. The electronic device includes the above error correction code memory.

[0069] Embodiments of the present invention provide a method for configuring a switchable lookup table circuit, a switchable lookup table circuit, an error correction code memory, and an electronic device. First, the input contents of multiple input addresses of the lookup table circuit are obtained. Then, the multiple input addresses are divided into a first number of address combinations. The address combinations are divided into a second number of address units based on the input contents of the corresponding input positions in each address combination. The second numbers of the address units divided by different address combinations may be the same or different. Furthermore, based on the second number of address units divided by each address combination, a switchable lookup table circuit having a first number of levels is configured. Thus, during the configuration of transistors in the lookup table circuit, input positions with the same input contents can be merged, significantly reducing the number of transistors and thus the area of ​​the lookup table synthesis circuit. Furthermore, the circuit obtained based on the above lookup table circuit configuration method does not have a path from power to ground, effectively reducing static power consumption caused by leakage in transistor devices.

[0070] It should be noted that the above description of the switching lookup table circuit, error correction code memory and electronic device embodiments is different from the above description of the switching lookup table circuit, error correction code memory and electronic device embodiments. Figure 3 The description of the method embodiment shown is similar, with the same Figure 3 For technical details not disclosed in the embodiments of the present invention, please refer to the aforementioned embodiments of the present invention. Figure 3 The description of the method embodiment shown in the figure is understood, and in order to save space, it is not repeated here.

[0071] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0072] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0073] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0074] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0075] Those skilled in the art will understand that all or part of the steps of the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, and other media that can store program codes.

[0076] Alternatively, if the above-mentioned integrated unit of the present invention is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods of each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0077] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for configuring a switching lookup table circuit, characterized in that: The method comprises: obtaining input contents of a plurality of input addresses of a lookup table circuit; Dividing the plurality of input addresses into a first number of address combinations; Dividing the address combination into a second number of address units according to the input content of the corresponding input position in each address combination, wherein the second numbers of the address units divided by different address combinations are the same or different; Based on the second number of address cells divided by each of the address combinations, a switching lookup table circuit having a first number of levels is configured; The step of dividing the address combination into a second number of address units according to the input content of the corresponding input position in each address combination includes: Taking the input positions with the same input content in each of the address combinations as an address unit; The second number of address units divided based on each of the address combinations is configured with a switching lookup table circuit having a first number of levels, including: For the address combination with the smallest second number, configure the address combination according to the input content of each address unit in the address combination, and sequentially configure multiple address combinations according to the second numbers of the address units of the address combination; The address combination is configured according to the input content of each address unit in the address combination, including: For the input position where the input content is 1, a transistor is configured on the positive signal input line of the corresponding input address; For the input position where the input content is 0, a transistor is configured on the inverting signal input line of the corresponding input address; The switching lookup table circuit having the first number of levels is configured based on the second number of address units divided by each address combination, further comprising: According to the order of configuring multiple address combinations, connect the address combinations of the first number in sequence; Connecting the transistors configured at the first input address in the first address combination to the reset transistor at the power supply end; The transistors configured for the last input address in the last address combination are all connected to the ground terminal.

2. The method according to claim 1, characterized in that Dividing the plurality of input addresses into a first number of address combinations includes: According to the number of the input addresses, the multiple input addresses are divided into multiple forms, wherein the multiple address combinations obtained by dividing in the same form have the same number of input addresses; The address combination with the highest probability that the input contents of the corresponding input positions of adjacent input addresses are the same is determined as the address combination finally divided.

3. A switching lookup table circuit, characterized in that: The switching lookup table circuit is configured using the switching lookup table circuit configuration method according to any one of claims 1 to 2.

4. The switching lookup table circuit according to claim 3, wherein: The transistors configured at the first input address in the first address combination in the switching lookup table circuit are all connected to the reset transistor at the power supply end; The transistors configured for the last input address in the last address combination are all connected to the ground terminal.

5. An error correction code memory, characterized in that: The error correction code memory includes the switching lookup table circuit according to claim 4.

6. The error correction code memory according to claim 5, wherein: The error correction code memory is a 64-bit south bridge two-way error correction code memory.

7. An electronic device comprising the error correction code memory according to claim 5 or 6.

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