A non-binary capacitor array successive approximation analog-to-digital converter circuit and operating method based on Padua sequence

Abstract

The present invention relates to a non-binary capacitor array successive approximation analog-to-digital converter circuit and operating method based on the Padua sequence, belonging to the field of integrated circuit technology. The circuit includes a comparator, a non-binary capacitor array, a logic control circuit, and a state switch array, wherein the top plate of the non-binary capacitor array is coupled to the first input terminal of the comparator, the second input terminal of the comparator is coupled to a zero potential, the logic control circuit is coupled to the output terminal of the comparator, and the state switch array is coupled to the bottom plate of the non-binary capacitor array and the logic control circuit; the state switches in the state switch array are used to represent the working phase of the non-binary capacitor array, with the state switches being closed for the sampling phase and open for the analog-to-digital conversion phase. The capacitor array of the present invention adopts a redundant design, and quantization errors generated during the quantization process of the analog-to-digital converter can be corrected through back-end correction technology.

Description

Technical Field

[0001] The present invention relates to a non-binary capacitor array successive approximation analog-to-digital converter circuit and a working method based on the Padua sequence, belonging to the technical field of integrated circuits. Background Art

[0002] Analog-to-digital converters (ADCs) are used in a variety of applications to periodically sample a continuous analog input signal and convert it into a discrete digital signal. A widely used type of ADC is the successive approximation register (SAR) ADC, which converts analog signals into digital signals using a successive approximation algorithm.

[0003] The capacitance DAC array of a traditional binary array-based SAR ADC has a capacitance value that is a power of 2. The capacitance value at the high bit is large and the capacitance mismatch is severe. This results in a low effective number of bits, large quantization error, and inability to correct it through back-end calibration technology.

[0004] During the quantization stage of a successive approximation analog-to-digital converter (A / D converter), which converts a continuous analog signal into a digital signal, nonlinearity inevitably occurs due to a series of non-ideal factors such as capacitor mismatch and component offset errors, leading to errors in the conversion result. Therefore, the quantization result needs to be corrected. The prerequisite for this correction is to incorporate redundant design into the circuit. Redundant design requires that the capacitance of each capacitor in each bit should be less than the sum of the capacitances of the capacitors below it. Furthermore, the logarithm of the total capacitance of the capacitor array divided by the capacitance of the lowest-bit capacitor (based on base 2) should be greater than or equal to the effective number of bits of the A / D converter. Traditional redundant design methods can result in non-binary capacitor arrays requiring individual design for each capacitor, making it impossible to replicate the capacitors using unit capacitance. This results in poor design flexibility, capacitor matching, and layout design.

[0005] A non-binary capacitor array SAR ADC design based on the Fibonacci sequence exists in the industry (see: Arafune T, Kobayashi Y, Shibuya S, et al. Fibonacci sequence weighted SAR ADC algorithm and its DAC topology [C] / / 2015 IEEE 11th International Conference on ASIC (ASICON). IEEE, 2015: 1-4.). The Fibonacci sequence is a series of numbers: 1, 1, 2, 3, 5, 8, 13, 21, ..., with each term, starting from the second term, equal to the sum of the previous two. Although the capacitance of each bit in the capacitor array is also an integer multiple of the unit capacitance, the SAR ADC based on the Fibonacci sequence non-binary capacitor array has more redundancy than the SAR ADC based on the Padua sequence non-binary capacitor array, even with the same number of capacitor array bits and effective number of bits, and can cope with larger mismatches. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention provides a non-binary capacitor array successive approximation analog-to-digital converter circuit and operating method based on the Padua sequence. The capacitor array employs a redundant design, and back-end correction techniques can be used to correct quantization errors generated during the quantization process of the analog-to-digital converter. The Padua sequence is a series of numbers: 1, 1, 1, 2, 2, 3, 4, 5, 7, 9, 12, 16, 21, ... Starting from the fourth term, each term in the series is the sum of the second and third terms preceding it.

[0007] The technical solutions of the present invention are as follows:

[0008] A non-binary capacitor array successive approximation analog-to-digital converter circuit based on the Padua sequence includes a comparator, a non-binary capacitor array, a logic control circuit, and a state switch array, wherein:

[0009] The top plate of the non-binary capacitor array is coupled to a first input terminal of the comparator, a second input terminal of the comparator is coupled to a zero potential, a logic control circuit is coupled to an output terminal of the comparator, and a state switch array is coupled to a bottom plate of the non-binary capacitor array and the logic control circuit;

[0010] The state switches in the state switch array are used to characterize the working phase of the non-binary capacitor array structure SAR ADC circuit. When the state switches are closed, it is a sampling phase, and when the state switches are open, it is an analog-to-digital conversion phase.

[0011] Preferably, the non-binary capacitor array includes at least a positive reference voltage terminal, a negative reference voltage terminal, an analog signal input terminal, three capacitors, and multiple redundant capacitors, wherein each of the three capacitors and the multiple redundant capacitors is arranged in parallel between the positive input terminal of the comparator and the positive reference voltage terminal, the negative reference voltage terminal, and the analog signal input terminal, and all the capacitors are labeled in order from the highest bit to the lowest bit or from the lowest bit to the highest bit, and the sum of the capacitances corresponding to the next lowest capacitor to any capacitor is greater than or equal to the sum of the capacitances corresponding to the capacitors adjacent to the capacitor at the next higher bit, and the ratio of the capacitance of each capacitor to the capacitance of the unit capacitor is set to conform to the Padua series, and the capacitance of each capacitor is a positive integer. For example, C0 is C, C1 is 2C, C2 is 2C, C3 is 3C, C4 is 4C, C5 is 5C, C6 is 7C, and C7 is 9C.

[0012] The operating method of the non-binary capacitor array successive approximation analog-to-digital converter circuit based on the Padua sequence is as follows:

[0013] (1) a state switch array couples an input signal, a positive reference voltage signal, and a negative reference voltage signal, and a logic control circuit selectively couples the positive reference voltage signal, the negative reference voltage signal, and the input signal to the bottom plate of the non-binary capacitor array by controlling the state switch array;

[0014] (2) During the sampling phase, the input signal is connected to the bottom plate of the non-binary capacitor array. When the sampling phase is completed, the bottom plate of the N-1 capacitor is switched to a positive reference voltage signal. The N-1 capacitor is the MSB capacitor, and the bottom plates of the remaining capacitors are switched to negative reference voltage signals. The three capacitors and multiple redundant capacitors are marked as C0-C N-1 ;

[0015] (3) In the conversion phase, the value of the MSB bit is determined by the comparison result obtained by the comparator. The logic control circuit controls the non-binary capacitor array to convert the MSB-1 bit according to the comparison result. If MSB=1, the logic control circuit switches the bottom plate of the N-1 capacitor in the non-binary capacitor array to the negative reference voltage signal, and switches the bottom plate of the N-2 capacitor to the positive reference voltage signal. The bottom plates of the remaining capacitors remain unchanged.

[0016] If MSB=0, the logic control circuit switches the bottom plate of the N-2-bit capacitor in the non-binary capacitor array to the positive reference voltage signal, and the bottom plates of the remaining bit capacitors remain unchanged;

[0017] According to the result of the comparator, the value of the MSB-1 bit is determined, and the conversion of the MSB-1 bit is completed. And so on, until the conversion of the remaining weight bits is completed, a non-binary successive approximation process is realized.

[0018] In step (1), the input signal is VIN, the positive reference voltage signal is VRP, the negative reference voltage signal is VRN, and the zero potential is ground GND.

[0019] Preferably, in step (2), after the sampling phase is completed, the input voltage of the first input terminal V1 of the comparator is

[0020]

[0021] Where C T Represents the sum of all capacitance values of the non-binary capacitor array, that is,

[0022] Preferably, in step (3), the way to determine the MSB bit value through the comparison result obtained by the comparator is that, since the second input terminal of the comparator is connected to the zero point, the result of the comparator represents the relationship between the voltage of the first input terminal of the comparator, that is, the voltage of the top plate of the non-binary capacitor array, and 0. If the voltage of the top plate of the non-binary capacitor array is greater than 0, the comparator output result is 1, and the logic control circuit reduces the voltage of the top plate of the non-binary capacitor array by controlling the state switch, thereby performing the next comparison; if the voltage of the top plate of the non-binary capacitor array is less than 0, the comparator output result is 0, and the logic control circuit increases the voltage of the top plate by controlling the state switch, thereby performing the next comparison, until the logic control circuit completes switching the state switch from the high position to the low position, then a quantization process is completed, and the quantized digital result is output.

[0023] Further preferably, in step (3), when MSB=1, the voltage at the first input terminal of the comparator is updated to:

[0024]

[0025] When MSB=0, the voltage at the first input of the comparator is updated to:

[0026]

[0027] In engineering practice, it is generally believed that the random errors of capacitors are independent of each other and obey the normal distribution N(0, σ 2 ). Based on the mathematical principles of normal distribution, redundancy design requires that the capacitance of each capacitor should be less than the sum of the capacitances of its lower-order capacitors, and that the logarithm of the total capacitance of the capacitor array with base 2 divided by the capacitance of the lowest-order capacitor should be greater than or equal to the effective number of bits of the analog-to-digital converter. From this, we can derive the inequality relationship between the effective number of bits of the analog-to-digital converter, the capacitor mismatch rate, the number of capacitor array bits, and the common ratio of the capacitor array weights, as shown below.

[0028]

[0029]

[0030] Where β represents the common ratio of the non-binary capacitor array, σ represents the capacitor mismatch ratio, ENOB represents the effective number of bits of the analog-to-digital converter, N represents the number of bits of the capacitor array, and X is the abscissa value of the standard normal distribution graph, which is obtained by looking up the confidence level and the standard normal distribution table. Confidence level refers to the yield rate that meets the design requirements.

[0031] The common ratio of the Padua sequence is approximately 1.324, and the common ratio of the Fibonacci sequence is approximately 1.618. Based on the above formula, it can be deduced that, when the number of effective bits and capacitor array bits are the same, a SAR ADC based on a Padua sequence non-binary capacitor array has more redundancy than a SAR ADC based on a Padua sequence non-binary capacitor array, and can cope with larger mismatches.

[0032] The beneficial effects of the present invention are:

[0033] 1. The capacitor array of the present invention adopts a redundant design, and the quantization error generated during the quantization process of the analog-to-digital converter can be corrected through the back-end correction technology.

[0034] 2. The capacitance value of each bit of the capacitor array of the present invention is a positive integer multiple of the unit capacitance, thereby reducing the difficulty of back-end layout design. The capacitor array can be obtained by unit replication, so that the mismatch between capacitors is smaller, the area is more fully utilized, and the capacitor array matching accuracy is higher.

[0035] 3. Compared with the SAR ADC based on the Fibonacci sequence non-binary capacitor array, the SAR ADC of the present invention has more redundancy when having the same number of redundant capacitor bits and effective number of bits, and can cope with larger mismatch. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a circuit principle diagram of the present invention;

[0037] Figure 2 This is the circuit schematic diagram of an 8-bit non-binary capacitor array successive approximation analog-to-digital converter based on the Padua sequence;

[0038] Figure 3 This is a graph showing the relationship between the maximum capacitance mismatch rate and the number of capacitor array bits for a non-binary capacitor array SAR ADC based on the Fibonacci sequence and a non-binary capacitor array SAR ADC based on the Padua sequence with 10 effective bits;

[0039] Wherein: 10, comparator; 20, logic control circuit; 30, state switch array. DETAILED DESCRIPTION

[0040] The present invention will be further described below with reference to embodiments and accompanying drawings, but is not limited thereto.

[0041] Example 1:

[0042] like Figure 2 As shown, this embodiment provides a non-binary capacitor array successive approximation analog-to-digital converter circuit based on the Padua sequence, including a comparator 10, a non-binary capacitor array, a logic control circuit 20 and a state switch array 30, wherein:

[0043] The top plate of the non-binary capacitor array is coupled to the first input terminal of the comparator, the second input terminal of the comparator is coupled to a zero potential, the logic control circuit is coupled to the output terminal of the comparator, the state switch array is coupled to the bottom plate of the non-binary capacitor array and the logic control circuit, and the state switch array is as follows Figure 2 As shown, it is composed of MOS tubes.

[0044] The state switches in the state switch array are used to characterize the working phase of the non-binary capacitor array structure SAR ADC circuit. When the state switches are closed, it is a sampling phase, and when the state switches are open, it is an analog-to-digital conversion phase.

[0045] The non-binary capacitor array includes a positive reference voltage terminal, a negative reference voltage terminal, an analog signal input terminal, three capacitors, and five redundant capacitors. Each of the three capacitors and the five redundant capacitors is arranged in parallel between the positive input terminal of the comparator and the positive reference voltage terminal, the negative reference voltage terminal, and the analog signal input terminal. All the capacitors are marked in sequence from the highest bit to the lowest bit or from the lowest bit to the highest bit, and the sum of the capacitances corresponding to the next lowest capacitor to any capacitor is greater than or equal to the sum of the capacitances corresponding to the capacitors in the next higher bit adjacent to any capacitor. The ratio of the capacitance of each capacitor to the capacitance of a unit capacitor is set to comply with the Padua sequence, and the capacitance of each capacitor is a positive integer.

[0046] Table 1 shows the capacitance weight d and the corresponding redundancy q of the non-binary capacitor array.

[0047] n Weight d Redundancy q / LSB 1 9 11 2 7 8 3 5 5 4 4 3 5 3 2 6 2 0 7 2 0 8 1 0

[0048] In Table 1, the capacitance weight d can be obtained according to the capacitance value of the capacitor array, and then the expression of the redundancy q is obtained:

[0049]

[0050] Wherein, N is the number of non-binary quantization times (ie, the number of non-binary code bits), and n is the quantization order.

[0051] The operating method of the non-binary capacitor array successive approximation analog-to-digital converter circuit based on the Padua sequence is as follows:

[0052] (1) a state switch array couples an input signal, a positive reference voltage signal, and a negative reference voltage signal, and a logic control circuit selectively couples the positive reference voltage signal, the negative reference voltage signal, and the input signal to the bottom plate of the non-binary capacitor array by controlling the state switch array;

[0053] (2) During the sampling phase, the input signal is connected to the bottom plate of the non-binary capacitor array. After the sampling phase is completed, the bottom plate of the N-1 capacitor is switched to the positive reference voltage signal. The N-1 capacitor is the MSB capacitor, and the bottom plates of the remaining capacitors are switched to the negative reference voltage signal. All capacitors are labeled C0-C7 in sequence.

[0054] (3) Conversion stage: The value of the MSB bit is determined by the comparison result obtained by the comparator. The logic control circuit controls the non-binary capacitor array to perform the MSB-1 bit conversion according to the comparison result. If MSB=1, the logic control circuit switches the bottom plate of the C7 capacitor in the non-binary capacitor array to the negative reference voltage signal, switches the bottom plate of the C6 capacitor to the positive reference voltage signal, and the bottom plates of the remaining capacitors remain unchanged.

[0055] If MSB=0, the logic control circuit switches the bottom plate of capacitor C6 in the non-binary capacitor array to the positive reference voltage signal, and the bottom plates of the other capacitors remain unchanged;

[0056] After the second conversion, the result of the comparator determines the value of the C6 bit, and so on, until the conversion of the remaining weight bits is completed, realizing a non-binary successive approximation process.

[0057] In engineering practice, it is generally believed that the random errors of capacitors are independent of each other and obey the normal distribution N(0, σ 2 ). Based on the mathematical principles of normal distribution, redundancy design requires that the capacitance of each capacitor should be less than the sum of the capacitances of its lower-order capacitors, and that the logarithm of the total capacitance of the capacitor array with base 2 divided by the capacitance of the lowest-order capacitor should be greater than or equal to the effective number of bits of the analog-to-digital converter. From this, we can derive the inequality relationship between the effective number of bits of the analog-to-digital converter, the capacitor mismatch rate, the number of capacitor array bits, and the common ratio of the capacitor array weights, as shown below.

[0058]

[0059]

[0060] Where β represents the common ratio of the non-binary capacitor array, σ represents the capacitor mismatch ratio, ENOB represents the effective number of bits of the analog-to-digital converter, N represents the number of bits of the capacitor array, and X is the abscissa value of the standard normal distribution graph, which is obtained by looking up the confidence level and the standard normal distribution table. Confidence level refers to the yield rate that meets the design requirements.

[0061] The common ratio of the Padua sequence is about 1.324, and the common ratio of the Fibonacci sequence is about 1.618. Taking the confidence level as 0.9974 (according to the standard normal distribution table shown in Table 2, the value of X is 2.8), and the ADC effective number of bits is 10. Substituting into the inequality, the relationship between the number of bits of the capacitor array and the capacitor mismatch rate is obtained (the capacitor mismatch rate is the maximum value of the range obtained by the inequality), as shown in the figure: Figure 3 As shown in the figure, when the number of capacitor array bits is 12, the maximum capacitor mismatch rate that the SAR ADC based on the Fibonacci sequence non-binary capacitor array can handle is 17.3%, while the maximum capacitor mismatch rate that the SAR ADC based on the Padua sequence non-binary capacitor array can handle is 47.16%. This shows that compared with the SAR ADC based on the Fibonacci sequence non-binary capacitor array and the SAR ADC based on the Padua sequence non-binary capacitor array, when the number of redundant capacitor bits and effective bits are the same, the SAR ADC based on the Padua sequence non-binary capacitor array has more redundancy and can handle larger mismatches.

[0062] Table 2: Standard normal distribution table

[0063]

[0064] Example 2:

[0065] A working method of a non-binary capacitor array successive approximation analog-to-digital converter circuit based on the Padua sequence as described in Example 1, except that:

[0066] In step (1), the input signal is VIN, the positive reference voltage signal is VRP, the negative reference voltage signal is VRN, and the zero potential is ground GND.

[0067] In step (2), after the sampling phase is completed, the input voltage of the first input terminal V1 of the comparator is

[0068]

[0069] Where C T Represents the sum of all capacitance values of the non-binary capacitor array, that is,

[0070] In step (3), the way to determine the MSB bit value through the comparison result obtained by the comparator is that, since the second input terminal of the comparator is connected to the zero point, the result of the comparator represents the relationship between the voltage of the first input terminal of the comparator, that is, the voltage of the top plate of the non-binary capacitor array, and 0. If the voltage of the top plate of the non-binary capacitor array is greater than 0, the comparator output result is 1, and the logic control circuit reduces the voltage of the top plate of the non-binary capacitor array by controlling the state switch, thereby performing the next comparison; if the voltage of the top plate of the non-binary capacitor array is less than 0, the comparator output result is 0, and the logic control circuit increases the voltage of the top plate by controlling the state switch, thereby performing the next comparison, until the logic control circuit completes switching the state switch from the high position to the low position, then a quantization process is completed, and the quantized digital result is output.

[0071] In step (3), when MSB=1, the voltage at the first input terminal of the comparator is updated to:

[0072]

[0073] When MSB=0, the voltage at the first input of the comparator is updated to:

[0074]

Claims

1. A non-binary capacitor array successive approximation analog-to-digital converter circuit based on the Padua sequence, characterized in that: It includes a comparator, a non-binary capacitor array, a logic control circuit and a state switch array, wherein: The top plate of the non-binary capacitor array is coupled to a first input terminal of the comparator, a second input terminal of the comparator is coupled to a zero potential, a logic control circuit is coupled to an output terminal of the comparator, and a state switch array is coupled to a bottom plate of the non-binary capacitor array and the logic control circuit; The state switches in the state switch array are used to represent the working phase of the non-binary capacitor array, the state switches are closed for the sampling phase, and the state switches are open for the analog-to-digital conversion phase; The non-binary capacitor array includes at least a positive reference voltage terminal, a negative reference voltage terminal, an analog signal input terminal, three capacitors, and multiple redundant capacitors. Each of the three capacitors and the multiple redundant capacitors is arranged in parallel between the positive input terminal of the comparator and the positive reference voltage terminal, the negative reference voltage terminal, and the analog signal input terminal. The three capacitors and the multiple redundant capacitors are marked in sequence from the highest bit to the lowest bit or from the lowest bit to the highest bit, and the sum of the capacitances corresponding to the second lowest capacitor to any capacitor is greater than or equal to the sum of the capacitances corresponding to the capacitors in the next higher bit adjacent to the capacitor. The ratio of the capacitance of each capacitor to the capacitance of the unit capacitor is set to comply with the Padua sequence, and the capacitance of each capacitor is a positive integer.

2. A method for operating a non-binary capacitor array successive approximation analog-to-digital converter circuit based on the Padua sequence according to claim 1, characterized in that: Here are the steps: (1) a state switch array couples an input signal, a positive reference voltage signal, and a negative reference voltage signal, and a logic control circuit selectively couples the positive reference voltage signal, the negative reference voltage signal, and the input signal to the bottom plate of the non-binary capacitor array by controlling the state switch array; (2) During the sampling phase, the input signal is connected to the bottom plate of the non-binary capacitor array. When the sampling phase is completed, the bottom plate of the N-1 capacitor is switched to a positive reference voltage signal. The N-1 capacitor is the MSB capacitor, and the bottom plates of the remaining capacitors are switched to negative reference voltage signals. The three capacitors and multiple redundant capacitors are marked as C0-C N-1 ; (3) In the conversion phase, the value of the MSB bit is determined by the comparison result obtained by the comparator. The logic control circuit controls the non-binary capacitor array to convert the MSB-1 bit according to the comparison result. If MSB=1, the logic control circuit switches the bottom plate of the N-1 capacitor in the non-binary capacitor array to the negative reference voltage signal, and switches the bottom plate of the N-2 capacitor to the positive reference voltage signal. The bottom plates of the remaining capacitors remain unchanged. If MSB=0, the logic control circuit switches the bottom plate of the N-2-bit capacitor in the non-binary capacitor array to the positive reference voltage signal, and the bottom plates of the remaining bit capacitors remain unchanged; According to the result of the comparator, the value of the MSB-1 bit is determined, and the conversion of the MSB-1 bit is completed. And so on, until the conversion of the remaining weight bits is completed, a non-binary successive approximation process is realized.

3. The operating method of the non-binary capacitor array successive approximation analog-to-digital converter circuit based on the Padua sequence according to claim 2, wherein: In step (2), after the sampling phase is completed, the input voltage of the first input terminal V1 of the comparator is Where C T Represents the sum of all capacitance values of the non-binary capacitor array, that is, 4. The operating method of the non-binary capacitor array successive approximation analog-to-digital converter circuit based on the Padua sequence according to claim 3, wherein: In step (3), the MSB bit value is determined by the comparison result obtained by the comparator in the following manner: the result of the comparator represents the relationship between the voltage of the first input terminal of the comparator, that is, the voltage of the top plate of the non-binary capacitor array, and 0; if the voltage of the top plate of the non-binary capacitor array is greater than 0, the comparator output result is 1, and the logic control circuit reduces the voltage of the top plate of the non-binary capacitor array by controlling the state switch, thereby performing the next comparison; if the voltage of the top plate of the non-binary capacitor array is less than 0, the comparator output result is 0, and the logic control circuit increases the voltage of the top plate by controlling the state switch, thereby performing the next comparison, until the logic control circuit completes switching the state switch from the high position to the low position, then a quantization process is completed, and the quantized digital result is output.

5. The operating method of the non-binary capacitor array successive approximation analog-to-digital converter circuit based on the Padua sequence according to claim 4, wherein: In step (3), when MSB=1, the voltage at the first input terminal of the comparator is updated to: When MSB=0, the voltage at the first input of the comparator is updated to:

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