Machine Learning Driven Prediction in Integrated Circuit Design

Abstract

Training data is collected for each training integrated circuit (IC) design in a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow; and extracting a first set of IC design labels in a second stage of the IC design flow, wherein the first stage of the IC design flow occurs earlier in the IC design flow than the second stage of the IC design flow. Next, a machine learning model is trained based on the training data.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Application Serial No. 62 / 898,086, filed September 10, 2019, the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] The present disclosure relates generally to integrated circuit (IC) design. More specifically, the present disclosure relates to machine learning driven prediction in IC design. Background Art

[0004] Advances in process technology and the growing demand for computing and storage have driven increases in the size and complexity of IC designs. This progress can be attributed to improvements in semiconductor design and manufacturing techniques, which have made it possible to integrate tens of millions of devices onto a single chip. Summary of the invention

[0005] Some embodiments described herein collect training data for each training IC design in a training IC design set in the following manner: in a first stage of an IC design process, extract a first set of IC design features; and in a second stage of the IC design process, extract a first set of IC design labels, wherein in the IC design process, the first stage of the IC design process occurs earlier than the second stage of the IC design process. Next, train a machine learning model so that the machine learning model uses the training data to predict a first set of IC design labels based on the first set of IC design features. Specifically, supervised learning techniques are used to train the machine learning model.

[0006] In some embodiments, the first phase may belong to the pre-routing portion of the IC design flow, which may end after global routing has been completed in the IC design flow. In some embodiments, the second phase may belong to the post-routing portion of the IC design flow, which may begin after track allocation and detailed routing have been completed in the IC design flow.

[0007] In some embodiments, the first stage may belong to a pre-clock network synthesis portion of an IC design flow, which may end after post-placement optimization has been completed in the IC design flow. In some embodiments, the second stage may belong to a post-clock network synthesis portion of an IC design flow, which may begin after clock network synthesis has been completed in the IC design flow.

[0008] In some embodiments, training a machine learning model to predict an IC design label based on IC design features includes reducing an error term, the error term representing an aggregate error between the predicted IC design label and the actual IC design label (the actual IC design label is extracted during the second stage of the IC design flow). In particular, reducing the error term may include iteratively modifying parameters of the machine learning model.

[0009] In some embodiments, IC design features include, but are not limited to: count of logic levels in a combinatorial logic cloud, average fan-out in a combinatorial logic cloud, count of inverters and buffers, count of cells with modification restrictions, count of transition violations, ratio between aggregate network delay and aggregate cell delay, location of cells, and size of cells.

[0010] In some embodiments, the IC design tags include but are not limited to: arrival time at a timing endpoint, required time at a timing endpoint, timing slack at a timing endpoint, transition at a timing endpoint, noise margin at a timing endpoint, arrival time at a terminal of a logic gate, required time at a terminal of a logic gate, timing slack at a terminal of a logic gate, transition at a terminal of a logic gate, and noise margin at a terminal of a logic gate.

[0011] Some embodiments use a trained model when processing a given IC design (which may not be in the set of training IC designs). Specifically, when the given IC design is processed by the first stage of the IC design flow, the embodiment extracts a second set of IC design features; uses the trained machine learning model to predict a second set of IC design labels based on the second set of IC design features; and performs operations on the given IC design based on the second set of IC design labels. In particular, the embodiment can select the type and / or degree of modification based on the second set of IC design labels, and apply the selected modification to the given IC design. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present disclosure can be understood based on the detailed description and drawings given below. The drawings are for illustration purposes only and do not limit the scope of the present disclosure. In addition, the drawings are not necessarily drawn to scale.

[0013] Figure 1 An IC design flow according to some embodiments described herein is illustrated.

[0014] Figure 2 Illustrated is a process for predicting IC design labels based on IC design features using machine learning according to some embodiments described herein.

[0015] Figure 3Illustrated is how IC design features and IC design labels may be used to train a machine learning model according to some embodiments described herein.

[0016] Figure 4 Illustrated is how a trained machine learning model may be used during an IC design flow according to some embodiments described herein.

[0017] Figure 5 Illustrated are examples of machine learning models according to some embodiments described herein.

[0018] Figure 6 An example flow for design, verification, and fabrication of an integrated circuit according to some embodiments described herein is illustrated.

[0019] Figure 7 An example machine of a computer system is illustrated within which a set of instructions may be executed, the instructions for causing the machine to perform any one or more of the methodologies discussed herein. DETAILED DESCRIPTION

[0020] In the present disclosure, the term "IC design flow" refers to a process for designing an IC. An IC design flow typically includes many stages (the terms "stage", "step" and "process" are used interchangeably in the present disclosure). For example, clock network synthesis is an example of a stage in an IC design flow, during which a clock network is constructed to distribute clock signals to sequential circuit elements in an IC design. Routing is an example of a stage that occurs near the end of an IC design flow. The routing process may take multiple inputs, including but not limited to a placed netlist, which includes cells with known positions (i.e., placed cells) but does not include wires that are routed to electrically interconnect the cells. The routing process determines wire routing to interconnect the placed cells to each other, and outputs a placed-routed netlist, which includes the placed cells and includes routing of wires that electrically interconnect the placed cells to each other. Many optimization criteria may be used during routing, including but not limited to reducing design rule violations, reducing the number of vias, reducing total wire length, reducing the likelihood of timing violations, and the like.

[0021] As the IC design progresses through the IC design flow, the accuracy of timing information (e.g., delays, slack, transitions, signal integrity, etc.) is improved. For example, after clock network synthesis, the effect of clock skew on timing information can be accurately calculated. Similarly, parasitic electrical characteristics of wires (e.g., parasitic resistance and parasitic capacitance) affect timing, but the parasitic electrical characteristics cannot be known with a high degree of accuracy until routing is completed. Therefore, after routing is completed on the IC design, the timing information of the IC design can be calculated using an accurate timing model, which uses actual wire routing in its calculations, and the accurately calculated timing information can be used to ensure that the IC design meets the timing constraint set.

[0022] As the IC design proceeds through the IC design flow, the set of constraints can be checked in the IC design. If the constraints are violated, the IC design may need to be sent back to the previous stage for additional design iterations, which may increase project costs and delays. For example, the back-end sign-off process can be used to check timing constraints using post-wiring timing information, which is calculated using a timing model that uses actual wire routing in the IC design. If the IC design satisfies the constraints checked during the back-end sign-off process, it can be determined that the IC design is ready for manufacturing. On the other hand, if a timing problem is found during the back-end sign-off process, the IC design may need to be sent back to the previous design stage for additional design iterations, which may significantly increase project costs and delays.

[0023] Some embodiments described in the present disclosure use machine learning to predict IC design tags that are expected to appear in later stages in the IC design flow. The predicted tags are used to perform IC design operations (e.g., placement and optimization operations) during the current stage in the IC design flow. Advantages of the embodiments disclosed herein include, but are not limited to, faster timing closure in the IC design flow, and better quality results produced by the IC design flow.

[0024] In this disclosure, the terms "IC design feature" and "IC design label" generally refer to any quantity in an IC design. Examples of IC design features or labels include, but are not limited to, delays, slack, transitions, noise margins, counts of logic levels in a combinatorial logic cloud, average fan-out in a combinatorial logic cloud, counts of inverters and buffers, counts of cells with modification restrictions, counts of transition violations, ratios between aggregate network delays and aggregate cell delays, locations of cells, sizes of cells, etc. In the field of machine learning, the term "feature" refers to a quantity that is provided as input to a machine learning model (i.e., a value on which a prediction is made), and the term "label" refers to a quantity that is produced as output by a machine learning model (i.e., a value predicted by the machine learning model).

[0025] Figure 1An IC design flow according to some embodiments described herein is illustrated.

[0026] During synthesis 102, the logic design is converted into a post-synthesis netlist containing cells. During post-synthesis optimization 104, the cells in the post-synthesis netlist are replaced by other functionally equivalent cells to optimize the timing, area and / or leakage power of the IC design. During placement 106, the cells in the post-synthesis netlist are assigned positions in the IC design layout area. During post-placement optimization 108, the cells in the post-synthesis netlist are moved and / or replaced by other functionally equivalent cells to optimize the timing, area and / or leakage power of the IC design. During clock network synthesis 110, the clock network is constructed to assign clock signals to the timing cells in the IC design. During post-clock network synthesis optimization 112, the clock network is modified (e.g., the clock network topology can be modified, the clock buffer can be added, removed or replaced, etc.) to optimize the timing, area and / or leakage power of the IC design.

[0027] After post-clock network synthesis optimization 112, wire routing is determined to electrically interconnect the units in the IC design. Routing can include three different stages: global routing, track allocation, and detailed routing. In some embodiments, track allocation and detailed routing operations can be combined into a single stage. Specifically, during global routing 114, the process can determine the approximate network topology and routing paths in the IC design layout to reduce overall routing congestion and wire length. The approximate network topology and routing paths can then be optimized during global routing optimization 116.

[0028] The Track Assignment and Detailed Routing 118 phase refines the global routing plan by assigning wires to tracks (tracks are closely spaced bundles of wires) in the Track Assignment step, and then determining the exact path and specific shape for each wire in the Detailed Routing step. Track Assignment and Detailed Routing 118 is typically the most time-consuming and computationally intensive operation in routing.

[0029] Next, the IC design flow may perform post-routing optimization 120 (and optionally other operations) to obtain a final IC design, which, if it satisfies a desired set of constraints that may be checked during a back-end sign-off process, may be taped out 122. Specifically, during post-routing optimization 120, nets that violate timing constraints, design rules, and / or signal integrity constraints may be rerouted.

[0030] In the present disclosure, the pre-clock network synthesis IC design flow includes: one or more IC design flow operations performed on the IC design before the clock network synthesis 110 stage on the IC design begins, and the post-clock network synthesis IC design flow includes: one or more IC design flow operations performed on the IC design after the clock network synthesis 112 on the IC design is completed.

[0031] Similarly, the pre-routing IC design flow includes: one or more IC design flow operations performed on the IC design before the track allocation and detailed routing 118 stage on the IC design begins, and the post-routing IC design flow includes: one or more IC design flow operations performed on the IC design after the track allocation and detailed routing 118 stage on the IC design is completed.

[0032] Figure 2 Illustrated is a process for predicting IC design labels based on IC design features using machine learning according to some embodiments described herein.

[0033] For each training IC design in the training IC design set, the process can extract a first set of IC design features from the training IC design in a first stage of the IC design flow, and can extract a first set of IC design labels from the training IC design in a second stage of the IC design flow, wherein the first stage of the IC design flow occurs earlier in the IC design flow than the second stage of the IC design flow (at 202).

[0034] In some embodiments, the first stage of the IC design flow belongs to the pre-routing portion of the IC design flow, and the second stage belongs to the post-routing portion of the IC design flow. In some embodiments, the first stage of the IC design flow belongs to the pre-clock tree synthesis portion of the IC design flow, and the second stage belongs to the post-clock tree synthesis portion of the IC design flow.

[0035] In the present disclosure, the term "clock group" refers to the timing paths in the same clock domain in an IC design, and the term "path group" generally refers to any set of timing paths that have been grouped into a specific group. Specifically, a given timing endpoint may have different required times for different path groups. In the present disclosure, the term "corner" refers to a specific set of manufacturing conditions (or process conditions) in which an IC design can be manufactured, and / or refers to a specific set of operating conditions in which an IC design can be operated. In the present disclosure, the term "mode" refers to a specific operating mode (e.g., standby mode, task mode, and test mode) in which an IC design can be operated. In the present disclosure, the term "multi-corner multi-mode (MCMM) scenario" refers to a combination of a specific corner and a specific mode. Note that the electrical characteristics of the cell and wire routing are different for each MCMM scenario, which makes the timing information different for each MCMM scenario.

[0036] Some embodiments collect ground truth (i.e., real labels) from any part of the IC design process. Examples of training data collected from the IC design process include, but are not limited to: IC design data from post-detailed wiring IC design, IC design data from the initial stage of post-wiring optimization, IC design data from any intermediate stage of post-wiring optimization, or IC design data from the end of post-wiring optimization. In particular, ground truth is collected for all restricted endpoints in each MCMM scenario and each clock and path group. In other words, the embodiments described herein are used together with any kind of IC design with any number of MCMM scenarios and path groups.

[0037] In some embodiments, the features and labels extracted from the IC design are not specific to any particular design style or technology. In particular, the extracted features and labels are generally applicable to all design styles across technology nodes. Examples of the extracted features and labels include, but are not limited to, counts of logic levels, required times at endpoints or at terminals of logic gates, arrival times at endpoints or at terminals of logic gates, counts of fan-outs, etc. The embodiments disclosed herein use a feature set that comprehensively explains the variations in fitting ground truth timing, which has been demonstrated by experimental results.

[0038] refer to Figure 2 , the process can train a machine learning model based on the first set of IC design features and the first set of IC design labels (at 204). Specifically, the machine learning model can be trained using supervised learning techniques so that the trained machine learning model accurately predicts (within a tolerance range) the first set of IC design labels based on the first set of IC design features.

[0039] In particular, predicting post-wiring timing based on pre-wiring features can be challenging because feature values ​​can change significantly between a pre-wiring IC design and a corresponding post-wiring IC design. Therefore, in some embodiments, a machine learning model that tolerates variations in the output (i.e., ground truth or post-wiring timing) is selected. Selecting a machine learning model that tolerates variations can be important for accurately predicting post-wiring timing based on pre-wiring IC design features (post-wiring timing can be affected by multiple high-level features and physical effects).

[0040] Some embodiments use tree-based machine learning models that are well suited for modeling large output variations because each subtree can model a subspace of variations in the output (relative to input features). In particular, random forest-based machine learning models can be well suited for this purpose because the model can allocate multiple trees to handle multiple variations in different subspaces of output relative to front-wired IC design features. Some embodiments use gradient boosted random forests because each boosted forest can incrementally fit tighter output variations that earlier forests in the chain could not accurately fit.

[0041] Some embodiments use neural networks (and variations thereof, such as deep neural networks, deep learning architectures, etc.), which can also be well suited to predicting post-routing timing based on pre-routing IC design features. In these embodiments, once the neural network has been adjusted for the number of layers and the number of hidden neurons in each layer, the neural network can accurately model output changes with a rich set of features. Note that neural networks are typically slower in inference speed than gradient boosted random forests. Therefore, gradient boosted random forest-based methods can be used in applications that require fast inference speeds, for example, in applications where trained machine learning models are reused to guide and / or perform incremental optimizations in IC design flows.

[0042] Figure 3 Illustrated is how IC design features and IC design labels may be used to train a machine learning model according to some embodiments described herein.

[0043] When processing IC design using IC design flow 124, the IC design may contain different contents at different stages, for example, the IC design at 302-1 to the IC design at 302-n may contain different contents, and in particular, the IC design at the later stage contains a more detailed or optimized layout than the IC design at the earlier stage. Figure 3Here, the letters k and m refer to numbers between 1 and n, i.e., 1 < k < m < n. Each stage in the IC design process 124 works on the IC design output by the previous stage. For example, stage 302-m works on the IC design output by stage 302-(m - 1). The extracted feature 306 can be extracted from IC design 302-k, which may correspond to the first stage of the IC design process, and the extracted label 308 can be extracted from IC design 302-m, which may correspond to the second stage of the IC design process. Next, the extracted feature 306 and the extracted label 308 can be used to train the machine learning model 310.

[0044] Typically, a machine learning model includes an error term that represents the aggregate error (e.g., root mean square error) between a predicted label (e.g., the timing slack at a timing endpoint predicted based on features extracted from the first stage) and an actual label (e.g., the actual slack at the timing endpoint extracted from the second stage). Training the machine learning model involves reducing the error term by iteratively modifying the parameters of the machine learning model. The parameter values of the machine learning model at the end of the training process represent the trained machine learning model 312.

[0045] Reference Figure 2 , the process can use the trained machine learning model during the IC design process. For example, when a given IC design is processed by the first stage of the IC design process, the process can use the trained machine learning model, and the given IC design may not be in the training IC design set. Specifically, the process can, in the first stage of the IC design process, extract a second set of IC design features from the given IC design; use the trained machine learning model to predict a second set of IC design labels based on the second set of IC design features; and perform an operation (at 206) on the given IC design based on the second set of IC design labels.

[0046] Figure 4 Illustrates how a trained machine learning model can be used during an IC design process according to some embodiments described herein.

[0047] The IC design tool suite 404 may be used during the IC design flow 124. The IC design tool suite 404 may transform the IC design as it progresses through the IC design flow 124, e.g., during the IC design flow 124, an IC design at stage 402-i may be transformed into a more detailed or optimized version of the IC design at stage 402-j. In particular, the IC design tool suite 404 may extract IC design features from the IC design during a first stage (e.g., stage 402-i) of the IC design flow 124, and provide the extracted IC design features to the trained machine learning model 312 as input. The trained machine learning model 312 may use the extracted IC design features to predict one or more IC design labels that are expected to appear at a later stage (e.g., stage 402-j) in the IC design flow 124 (e.g., the trained machine learning model 312 may predict post-routing timing information), and provide the predicted IC design labels to the IC design tool suite 404. The IC design tool suite 404 can then use the predicted IC design tags to select the type and extent of modifications to be made to the current IC design. Although some embodiments described herein use IC design features and tags extracted from the pre-routing IC design flow stage and the post-routing IC design flow stage, other embodiments can generally use IC design features and tags extracted from any two stages of the IC design flow.

[0048] As an example, a physical design flow can use a trained machine learning model so that the physical design flow can predict timing values ​​that the netlist will "see" early in the flow in an instantaneous manner. For example, a pre-routing optimization can use a trained machine learning model to accurately predict post-routing timing, which includes various changes to the netlist, physical context changes (routing, signal integrity, etc.), and timing characteristics changes (advanced timing models for detailed routing parasitics, timing calculators associated with signoff tools).

[0049] After the model has been trained, the pre-routing optimization flow can use the model in the following ways: (1) extract features, (2) pass the extracted features to the trained model to predict "look-ahead" timing (slack, arrival, delay, etc.), (3) adjust the timing of endpoints, stages, cells / nets based on the predictions of the trained model, and (4) perform one or more optimization steps using the adjusted timing values.

[0050] An example of applying a trained model in an optimization loop is as follows. Adjustments based on the trained model can be applied before datapath delay optimization. Next, after concurrent clock and data optimizations have been performed, a new feature set is extracted. Thereafter, the new adjustments can be calculated and applied after resuming optimization.

[0051] In a specific example, in the pre-routing step, assume that the critical path slack of the endpoint is +3ps in scenario s1, but its slack is -10ps after detailed routing. In addition, assume that the model has been trained in the pre-routing step to fit the endpoint slack after detailed routing in all scenarios.

[0052] Without using the model, in scenario SL, pre-routing delay optimization may not optimize any cells or nets in the critical path to the endpoint. Additionally, area, power recovery can optimize the cell and further reduce the slack to +0.5ps. However, after detailed routing, the path has -10ps slack. Therefore, the overall negative slack of the design is degraded after detailed routing.

[0053] Using this model, the critical path slack at the endpoint can be adjusted to -9.5ps (-0.5ps is the modeling error, and the adjustment factor is -12.5ps). Now, the pre-routing delay optimization can optimize this path and reduce the slack to -5ps. The recovery algorithm can protect the slack from further degradation, and after detailed routing, the slack may degrade by 5ps and degrade to -10ps. However, once we remove the -12.5ps adjustment factor, the slack of this path is now +2.5ps. Therefore, the total negative slack of the design has not been degraded when using this model.

[0054] In another specific example, assume that in the pre-routing step, the critical path slack of the endpoint is -5ps in scenario s1, but its slack is -10ps after detailed routing. Also assume that the model is trained at the pre-routing step to fit the endpoint slack of detailed routing in all scenarios.

[0055] Without using the model, pre-routing delay optimization can optimize this path to +0ps. After detailed routing, this path has -5ps of slack. Therefore, the overall negative slack of the design is degraded after detailed routing.

[0056] With this model, the critical path slack at the endpoint can be adjusted to -6ps (-1ps is the modeling error, and the adjustment factor is -1ps). Now, pre-routing delay optimization can optimize this path and reduce the slack to 0ps. After detailed routing, the slack may have degraded by 5ps and degraded to -5ps. However, once we remove the -6ps adjustment factor, the slack of this path is now +1ps. Therefore, the total negative slack of the design has not degraded, and in fact, the total negative slack of the design has improved from the case without the model.

[0057] Note that the embodiments described in this disclosure do not only predict the timing impact of wiring and the change of the accuracy of the timing model. On the contrary, the embodiments described herein also predict the impact of the netlist or placement changes that may occur during data and clock optimization. In addition, it is noted that the front wiring IC design features can be extracted from any front wiring IC design processed by the front wiring IC design step, and the front wiring IC design step may include but is not limited to synthesis, placement, clock tree synthesis and clock optimization. In other words, the embodiments described herein are not limited to using features extracted only from certain steps in the front wiring IC design flow. Therefore, the embodiments disclosed herein can be used to drive any front wiring engine, such as placement, physical synthesis, data, clock optimization, global wiring, etc. Specifically, when the front wiring engine must select a modification from a candidate modification set, the front wiring engine can use a trained machine learning model to predict the rear wiring timing information of each candidate modification in the candidate modification, and select the candidate modification based on the predicted rear wiring timing information.

[0058] Because the features extracted from the front-routing IC design and the back-routing IC design are not specific to any particular design style or technology and are generally applicable to all design styles across technology nodes, the machine learning model described in this article can be trained using IC designs that are implemented using different cell libraries, foundry technologies, and IC design flows. The trained machine learning model can then be used to predict back-routing timing information for IC designs implemented using different foundry technologies and / or cell libraries.

[0059] In some embodiments, the machine learning model includes two separate sub-models: a global timing model and a local timing model. Both models can be used in the applications described herein. The global timing model can be trained and used to predict timing endpoint relaxation, which can enable the optimization process to accurately select the timing critical path, resulting in faster timing convergence. The local timing model can be trained and used to predict delays and transitions in the logic level (for example, the logic level can refer to a driver gate and a set of load gates driven by the driver gate), which can enable the optimization process to accurately evaluate the impact of local optimization modifications on post-wiring timing, thereby preventing local optimization modifications from causing timing problems in the IC design process later.

[0060] Categories of features / labels that may be extracted by the embodiments described herein include, but are not limited to: (1) netlist and logic context, (2) physical context, (3) electrical, (4) constraints (MCMM, clocks, path groups, etc.), (5) timing paths, and (6) timing (slack, reach, transition, required, etc.).

[0061] Examples of features / labels that belong to the Netlist and Logic Context category include, but are not limited to: stage count in the critical path to the timing path endpoint, average fan-in and fan-out on the timing path, and maximum fan-in and fan-out on the timing path.

[0062] Examples of features / labels that fall into the physical context category include, but are not limited to: bounding boxes of pin locations in critical timing paths to timing endpoints.

[0063] Examples of features / labels that belong to the electrical category include, but are not limited to: maximum transition on a pin on a critical timing path, average transition on a pin on a critical timing path, maximum pin capacitance of cells in a critical timing path, average pin capacitance of cells in a critical timing path, pin capacitance of a clock pin at the start of timing, and pin capacitance of a clock pin at the end of timing.

[0064] Examples of features / labels belonging to the constraint category include, but are not limited to: maximum transition constraint, maximum capacitance constraint, required time of timing paths, and MCMM scenario.

[0065] Examples of features / labels that belong to the timing category include, but are not limited to: cell delay, network delay, pre-routing arrival time at timing endpoints and pre-routing transition time at timing endpoints, clock arrival time at timing start, and clock arrival time at timing end. In some embodiments, clock arrival features can be important for modeling skew effects for models fitted to post-detailed routing timing labels and for models fitted to post-clock network synthesis labels. Without these features, the model can be misleading when endpoints have the same label value (with or without skew).

[0066] Some embodiments rely on a sufficiently large feature space and ground truth (i.e., labels) during the training phase that can model changes while the core engine is running and / or when the netlist, physical context, constraints, flow, etc. are changed in an IC design that is not in the training IC design set. If there are large changes in any of these categories, the machine learning model can be retrained with the new data so that the new changes can be accurately modeled. Specifically, some embodiments described herein detect such large errors and prompt the user to retrain the model.

[0067] The embodiments described herein can predict the timing effects on IC designs due to routing and netlist changes. In addition, the embodiments described herein are used to predict timing parameters other than timing relaxation. For example, the embodiments described herein can predict post-routing waveform propagation, conversion changes, etc.

[0068] Figure 5Illustrated are examples of machine learning models according to some embodiments described herein. Figure 5 The machine learning models shown in are for illustrative purposes only and do not limit the scope of the embodiments to the disclosed form.

[0069] The machine learning model 500 may include regression trees T1, T2, and T3. Each non-leaf node of the regression tree may correspond to a condition, and each downward branch emanating from the non-leaf node may correspond to the result of evaluating the condition. For example, if the non-leaf node compares the value of a particular feature to a threshold, one branch may correspond to a feature having a value less than the threshold, and another branch may correspond to a feature having a value greater than or equal to the threshold. Each leaf node may correspond to a subset of the training data that satisfies the condition on the path from the root node to the leaf node.

[0070] The features 502 extracted from the first stage of the IC design process can be used to traverse each tree downward to reach the leaf nodes. For example, traversing trees T1, T2, and T3 based on the features 502 can cause leaf nodes 504-1, 504-2, and 504-3 to be selected. Then, a subset of the training data corresponding to leaf nodes 504-1, 504-2, and 504-3 can be used to calculate predicted labels 506 (labels 506 are expected to exist in the IC design of the second stage of the IC design process, where the second stage of the IC design is the stage where labels are extracted to train the machine learning model).

[0071] In some embodiments, the average of the labels in the subset of training data corresponding to leaf nodes 504-1, 504-2, and 504-3 can be used to calculate the predicted label. During training, the number of trees, the number of nodes in the tree, the topology of the tree, and the conditions associated with each node can be optimized to reduce the error between the predicted label and the actual label.

[0072] In some embodiments, the machine learning model may include a random forest with multiple tree sets. In some embodiments, each tree can be constructed by using a random split of the input features so that the information gain at each node of the tree is maximized. The selected features can be any k features (k≤N) among the N features. The depth of each tree can be controlled by using a maximum depth hyperparameter. When multiple trees are constructed, the output can be polled from all trees and averaged. The residuals can then be used to construct subsequent tree sets. The lifting part of the learning technique can iteratively minimize the residuals of the previous predictions from the tree. The maximum number of trees in the forest can be controlled using hyperparameters. The predicted label output by the model can be a weighted sum of the results from the tree set. During training, supervised learning techniques can learn weights based on the structure of the tree (i.e., the number of leaves, depth, etc.).

[0073] In some embodiments, and more specifically in embodiments that predict time series labels, the process can optimize (i.e., minimize) a particular error metric between the predicted labels and the actual labels. In particular, some embodiments use the root mean square error (RMSE), and minimize the RMSE metric during training. This metric determines the actual error, which after model tuning can affect the total negative slack metric of the design. In evaluating various error metrics (e.g., R 2 , mean square error, average absolute error, etc.), it was found that the RMSE metric is closely related to the design timing metric, and minimizing it can truly guide the physical design process optimization engine to achieve better and converged timing metrics.

[0074] Figure 6 An example flow 600 for design, verification, and fabrication of an integrated circuit according to some embodiments described herein is shown.

[0075] EDA processes 612 (the acronym "EDA" stands for "Electronic Design Automation") may be used to convert and verify design data and instructions representing an integrated circuit. Each of these processes may be structured and implemented as a plurality of modules or operations.

[0076] The process 600 may begin with creating a product concept 610 using information provided by a designer, which is transformed and verified using an EDA process 612. When the design is complete, the design is taped out 634, which refers to the artwork (e.g., geometric pattern) of the integrated circuit being sent to a manufacturing facility to make a mask set, which is then used to manufacture the integrated circuit. After the tape-out, the semiconductor die is manufactured 636, and packaging and assembly 638 are performed to produce a manufactured IC chip 640.

[0077] The specification of a circuit or electronic structure can be from low-level transistor material layout to a high-level description language. A high level of abstraction can be used to design circuits and systems using a hardware description language ("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be converted into a logic-level register transfer level ("RTL") description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of abstraction as a lower level of abstraction description adds more details to the design description. A lower level of abstraction as a less abstract description can be generated by a computer, derived from a design library, or created by another design automation process. An example of a specified language for specifying a more detailed description of a lower level of abstraction language is SPICE (which stands for "Simulation Program with an Emphasis on Integrated Circuits"). The description of each level of abstraction contains enough details to be used by the corresponding tools (e.g., formal verification tools) of that layer.

[0078] During system design 614, the functionality of the integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. Partitioning the design into different types of modules or components may occur at this stage.

[0079] During logic design and functional verification 616, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specification is checked. For example, components of a circuit can be verified to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components called "emulators" or "prototyping systems" are used to speed up functional verification.

[0080] During synthesis and design for testing 618, the HDL code is converted into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit operates according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the completed integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0081] During netlist verification 620, the netlist is checked for consistency with timing constraints and correspondence with HDL code. During design planning 622, the overall floorplan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0082] During layout or physical implementation 624, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connecting circuit components through multiple conductors) are performed, and selection of cells from a library can be performed to implement specific logic functions. As used herein, the term "cell" can specify a group of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are implemented as physical structures and implemented in simulation. Parameters, such as size, are specified for the selected cells (based on "standard cells"), and the parameters are made accessible in a database for use by EDA products.

[0083] During analysis and extraction 626, circuit functionality is verified at the layout level, which allows refinement of the layout design. During physical verification 628, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithography constraints, and that the circuit functionality matches the HDL design specifications. During resolution enhancement 630, the geometry of the layout is transformed to improve the way the circuit design is manufactured.

[0084] During tape-out, data is created for the production of lithographic masks (after applying lithographic enhancements where appropriate).During mask data preparation 632, the "tape-out" data is used to produce lithographic masks, which are used to produce finished integrated circuits.

[0085] Computer systems (such as Figure 7 The storage subsystem of the computer system 700) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as units for developing libraries and physical and logical design products that use the libraries.

[0086] Figure 7 Computer system 700 is shown as an example machine within which a set of instructions may be executed for causing the machine to perform any one or more of the methodologies discussed herein.

[0087] In some implementations, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0088] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Furthermore, while a single machine is shown, the term "machine" should also be construed to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0089] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 718, which communicate with each other via a bus 730.

[0090] The processing device 702 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 702 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 can be configured to execute instructions 726 for performing the operations and steps described herein.

[0091] The computer system 700 may also include a network interface device 708 to communicate over a network 720. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), a graphics processing unit 722, a signal generating device 716 (e.g., a speaker), a graphics processing unit 722, a video processing unit 728, and an audio processing unit 732.

[0092] The data storage device 718 may include a machine-readable storage medium 724 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media.

[0093] In some implementations, the instructions 726 include instructions for implementing functions corresponding to the present disclosure. Although the machine-readable storage medium 724 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine and processing device 702 to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0094] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. These operations are operations requiring physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0095] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise stated, as will be apparent from this disclosure, it should be understood that throughout the specification certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0096] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or the apparatus may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0097] The algorithm and display proposed herein are not intrinsically related to any particular computer or other device. Various other systems can be used together with the program according to the teachings herein, or it can be proved that it is convenient to construct a more specialized device to perform the method. In addition, the present disclosure is not described with reference to any specific programming language. It will be understood that various programming languages ​​can be used to implement the teachings of the present disclosure as described herein.

[0098] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0099] In the foregoing disclosure, the implementation of the present disclosure has been described with reference to its specific example implementation. It is obvious that various modifications can be made to these implementations without departing from the scope and broad spirit of the embodiments of the present disclosure as set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the accompanying drawings, and the same elements are marked with the same numerals. Therefore, the present disclosure and the accompanying drawings should be considered to be illustrative rather than restrictive.

Claims

1. A method comprising: In a first stage of the IC design flow, based on each training IC design in the training IC design set, a first set of IC design features is extracted, wherein the first set of IC design features includes a count of logic levels, a required time of a timing path, an arrival time of a timing path, a count of fan-outs, and a clock arrival time, and extracting, in a second phase of the IC design flow, a first set of IC design labels based on each training IC design in the set of training IC designs, wherein the first phase of the IC design flow occurs earlier in the IC design flow than the second phase of the IC design flow, and wherein the first set of IC design labels includes timing slacks at one or more timing endpoints; Training, by a processor, a machine learning model based on the first set of IC design features and the first set of IC design labels; as well as When the first IC design is in the first stage of the IC design flow, extracting a second set of IC design features from the first IC design, wherein the second set of IC design features includes a count of logic levels, a required time of a timing path, an arrival time of a timing path, a count of fan-outs, and a clock arrival time, using the trained machine learning model to predict timing slack at one or more timing endpoints in the first IC design based on a second set of IC design features, and An optimization is performed on the first IC design, the optimization using the predicted timing slacks at the one or more timing endpoints in the first IC design.

2. A method according to claim 1, wherein the first stage of the IC design process belongs to the front-routing part of the IC design process, and the front-routing part ends after the global routing has been completed in the IC design process, and wherein the second stage belongs to the post-routing part of the IC design process, and the post-routing part starts after the track allocation and detailed routing have been completed in the IC design process.

3. A method according to claim 1, wherein the first stage belongs to the pre-clock network synthesis part of the IC design process, and the pre-clock network synthesis part ends after the post-placement optimization has been completed in the IC design process, and wherein the second stage belongs to the post-clock network synthesis part of the IC design process, and the post-clock network synthesis part starts after the clock network synthesis has been completed in the IC design process.

4. The method of claim 1 , wherein using training data to train the machine learning model to predict the first set of IC design labels based on the first set of IC design features comprises: An error term representing an aggregate error between a predicted set of IC design labels and the first set of IC design labels is reduced.

5. The method of claim 4, wherein reducing the error term comprises: Iteratively modifying parameters of the machine learning model.

6. The method of claim 1 , wherein the count of logic levels comprises a count of logic levels in a combinatorial logic cloud, and each of the first set and the second set of IC design features further comprises at least one of: an average fan-out in the combinatorial logic cloud, a count of inverters and buffers, a count of cells with modification restrictions, a count of transition violations, a ratio between aggregate network delay and aggregate cell delay, a location of a cell, and a size of a cell.

7. The method of claim 6, wherein the first set of IC design tags further comprises at least one of: an arrival time at a timing endpoint, a required time at the timing endpoint, a transition at the timing endpoint, a noise margin at the timing endpoint, an arrival time at a terminal of a logic gate, a required time at the terminal of the logic gate, a timing slack at the terminal of the logic gate, a transition at the terminal of the logic gate, and a noise margin at the terminal of the logic gate.

8. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to: In a first stage of the IC design flow, a first set of IC design features is extracted from each training IC design in the set of training integrated circuit IC designs, wherein the first set of IC design features includes a count of logic levels, a required time of a timing path, an arrival time of a timing path, a count of fan-outs, and a clock arrival time; extracting, in a second phase of the IC design flow, a first set of IC design labels from each training IC design in the set of training IC designs, wherein the second phase of the IC design flow occurs later than the first phase of the IC design flow, and wherein the first set of IC design labels includes timing slacks at one or more timing endpoints; training a machine learning model based on the first set of IC design features and the first set of IC design labels; as well as When the first IC design is in the first stage of the IC design flow, extracting a second set of IC design features from the first IC design, wherein the second set of IC design features includes a count of logic levels, a required time of a timing path, an arrival time of a timing path, a count of fan-outs, and a clock arrival time, using the trained machine learning model to predict timing slack at one or more timing endpoints in the first IC design based on a second set of IC design features, and An optimization is performed on the first IC design, the optimization using the predicted timing slacks at the one or more timing endpoints in the first IC design.

9. A non-transitory computer-readable storage medium according to claim 8, wherein the first stage of the IC design process belongs to the front-routing part of the IC design process, and the front-routing part ends in the IC design process after global routing has been completed, and wherein the second stage belongs to the post-routing part of the IC design process, and the post-routing part starts in the IC design process after track allocation and detailed routing have been completed.

10. A non-transitory computer-readable storage medium according to claim 8, wherein the first stage belongs to the pre-clock network synthesis part of the IC design process, and the pre-clock network synthesis part ends after the post-placement optimization has been completed in the IC design process, and wherein the second stage belongs to the post-clock network synthesis part of the IC design process, and the post-clock network synthesis part starts after the clock network synthesis has been completed in the IC design process.

11. The non-transitory computer-readable storage medium of claim 8, wherein training the machine learning model to predict the first set of IC design labels based on the first set of IC design features comprises: An error term representing an aggregate error between a predicted set of IC design labels and the first set of IC design labels is reduced.

12. The non-transitory computer-readable storage medium of claim 11, wherein reducing the error term comprises: Iteratively modifying parameters of the machine learning model.

13. The non-transitory computer-readable storage medium of claim 8, wherein the count of logic levels comprises a count of logic levels in a combinatorial logic cloud, and each of the first set and the second set of IC design features further comprises at least one of: an average fan-out in the combinatorial logic cloud, a count of inverters and buffers, a count of cells with modification restrictions, a count of transition violations, a ratio between aggregate network delay and aggregate cell delay, a location of a cell, and a size of a cell.

14. The non-transitory computer-readable storage medium of claim 13, wherein the first set of IC design tags further comprises at least one of: an arrival time at a timing endpoint, a required time at the timing endpoint, a transition at the timing endpoint, a noise margin at the timing endpoint, an arrival time at a terminal of a logic gate, a required time at the terminal of the logic gate, a timing slack at the terminal of the logic gate, a transition at the terminal of the logic gate, and a noise margin at the terminal of the logic gate.

15. A device comprising: Memory, which stores instructions; as well as a processor coupled to the memory and executing the instructions, which when executed cause the processor to: For each training IC design in a set of training integrated circuit IC designs, collecting training data, wherein collecting the training data comprises: extracting a first set of IC design features from each training IC design in a first stage of an IC design flow, wherein the first set of IC design features comprises a count of logic levels, a required time of a timing path, an arrival time of a timing path, a count of fan-outs, and a clock arrival time; and extracting a first set of IC design labels from each training IC design in a second stage of the IC design flow, wherein the second stage of the IC design flow occurs later than the first stage of the IC design flow, and wherein the first set of IC design labels comprises timing slack at one or more timing endpoints; Using the training data to train a machine learning model; and When the first IC design is in the first stage of the IC design flow, extracting a second set of IC design features from the first IC design, wherein the second set of IC design features includes a count of logic levels, a required time of a timing path, an arrival time of a timing path, a count of fan-outs, and a clock arrival time, using the trained machine learning model to predict timing slack at one or more timing endpoints in the first IC design based on a second set of IC design features, and An optimization is performed on the first IC design, the optimization using the predicted timing slacks at the one or more timing endpoints in the first IC design.

16. A device according to claim 15, wherein the first stage of the IC design process belongs to the front-routing part of the IC design process, and the front-routing part ends in the IC design process after global routing has been completed, and wherein the second stage belongs to the post-routing part of the IC design process, and the post-routing part starts in the IC design process after track allocation and detailed routing have been completed.

17. A device according to claim 15, wherein the first stage belongs to the pre-clock network synthesis part of the IC design process, and the pre-clock network synthesis part ends after the post-placement optimization has been completed in the IC design process, and wherein the second stage belongs to the post-clock network synthesis part of the IC design process, and the post-clock network synthesis part starts after the clock network synthesis has been completed in the IC design process.

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