Read disturb scan merge

Abstract

A processing device in a memory system determines that data in a first block of a plurality of blocks in a memory component satisfies a first threshold criterion regarding the age of the data. In response to the data stored in the first block satisfying the first threshold criterion, the processing device maintains a first counter to track the number of read operations performed on the first block. The processing device further determines that the data stored in the first block does not satisfy the first threshold criterion, and in response, maintains a second counter to track the number of read operations performed on a superblock comprising the plurality of blocks.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to managing memory subsystems that include memory components with different characteristics. Background Technology

[0002] The memory subsystem can be a storage system, a memory module, or a hybrid of a storage device and a memory module. The memory subsystem may include one or more memory components for storing data. For example, the memory components may be non-volatile memory components and volatile memory components. Generally, a host system can utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0004] Figure 1 This describes an instance computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 This is a flowchart of an example method using a read counter with hierarchical granularity according to some embodiments of the present disclosure.

[0006] Figure 3 This is a block diagram illustrating read counters at the physical block level and superblock level granularity according to some embodiments of the present disclosure.

[0007] Figure 4 This is a flowchart of an example method for triggering a data integrity scan using a read counter at the physical block level, according to some embodiments of this disclosure.

[0008] Figure 5 This is a flowchart of an example method for triggering a data integrity scan using a read counter at the superblock level, according to some embodiments of this disclosure.

[0009] Figure 6 This is a flowchart of an example method for determining a read count scaling factor according to some embodiments of the present disclosure.

[0010] Figure 7 This is a block diagram illustrating a data structure for storing a read count scaling factor according to some embodiments of the present disclosure.

[0011] Figure 8 This is a flowchart of an example method of using a read count scaling factor when incrementing a read counter to trigger a data integrity scan, according to some embodiments of this disclosure.

[0012] Figure 9 This is a flowchart of an example method for applying hierarchical criteria to block refresh after a data integrity scan, according to some embodiments of this disclosure.

[0013] Figure 10 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0014] This disclosure relates to read interference scan merging across multiple planes of the memory component to minimize system bandwidth loss in a memory subsystem. The memory subsystem may be a memory device, a memory module, or a hybrid of a memory device and a memory module. The following is in conjunction with... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more memory components. The host system can provide data to be stored in the storage subsystem and can request data to be retrieved from the storage subsystem.

[0015] A memory component can be a memory device, such as a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. For some memory devices, a block is the smallest erasable area. Each block consists of a set of pages. Each page consists of a set of memory cells that store data bits. Memory cells may degrade as data is written to them for storage. Therefore, each memory cell of a memory component can handle a finite number of write operations performed before the memory cell can no longer reliably store data. Data stored in a memory cell of a memory component can be read from the memory component and transferred to the host system. When data is read from a memory cell of a memory component, nearby or adjacent memory cells may experience so-called read interference. Read interference is the result of continuous readings from a memory cell without inserting erase operations, which causes other nearby memory cells to change over time (e.g., become programmed). If too many read operations are performed on a memory cell, data stored in adjacent memory cells may become corrupted or incorrectly stored. This can lead to a higher data error rate at the memory cell. This increases the use of error detection and correction operations (e.g., error control operations) for subsequent operations performed on the memory cell (e.g., reads and / or writes). Increased use of error control operations can degrade the performance of the conventional memory subsystem. Furthermore, as the error rate of a memory cell or block continues to increase, it may even exceed the error correction capacity of the memory subsystem, resulting in irreparable data loss. Moreover, as more resources of the memory subsystem are used for error control operations, fewer resources are available for other read or write operations.

[0016] The error rate associated with the data stored at the block may increase due to read interference. Therefore, after performing a threshold number of read operations on the block, the memory subsystem may perform a data integrity check (also referred to herein as a "scan") to verify that the data stored at the block does not contain any errors. During the data integrity check, one or more reliability statistics are determined for the data stored at the block. One example of a reliability statistic is the Raw Bit Error Rate (RBER). RBER corresponds to the number of bit errors experienced by the data stored at the block per unit time.

[0017] Conventionally, if the reliability statistics of a block exceed a threshold (indicating a high error rate associated with the data stored at the block, at least in part attributable to read interference), the data stored at the block is relocated to a new block in the memory subsystem (also referred to herein as "folding"). Folding data stored at a block to another block may involve writing data to the other block to refresh the data stored by the memory subsystem. Doing so eliminates the effects of read interference associated with the data and erases the data at the block. However, as previously discussed, read interference can affect memory cells adjacent to the memory cells to which read operations are performed. Therefore, if a particular memory cell is read more frequently, read interference can cause uneven stress on the memory cells of the block. For example, memory cells in a block adjacent to frequently read memory cells may have a high error rate, while memory cells not adjacent to said memory cells may have a lower error rate due to the reduced impact of read interference on these memory cells.

[0018] Depending on the host system's data access activities for a particular memory subsystem, the effects of read interference can be concentrated on one or more specific memory pages within a block, or more evenly distributed across all memory pages of the block. For example, if read stress is concentrated on a single memory page, the block can be considered to be experiencing single-word-line (SWL) read interference (also known as "row hammer" read interference). SWL read interference can occur when the read frequency of a piece of data stored in the memory subsystem is significantly higher than that of the rest of the data in the same block. However, if the read stress is evenly distributed across multiple memory pages, the block can be considered to be experiencing uniform read interference (also known as "whole-block" read interference). Uniform read interference can occur when every piece of data in the block is read at approximately the same frequency.

[0019] Conventional memory subsystems use scan operations to perform data integrity checks at the block level. Because scan operations are performed at the block level, the memory subsystem monitors the number of read operations performed on a specific block and performs a scan operation when the read count (i.e., the number of read operations) meets or exceeds a certain read threshold. Depending on the implementation, the memory subsystem may maintain a read counter or multiple read counters to track the number of read operations performed on segments of different granularities. For example, some systems may maintain a separate read counter for each physical block, while others may maintain a read counter for a superblock (i.e., a collection of multiple physical blocks). In many cases, available memory space (e.g., RAM) is insufficient to support the use of read counters for each physical block. In these cases, the memory subsystem may use read counters at the superblock level. Controller firmware typically cannot distinguish between single-word-line read interference stress and uniform read interference stress, therefore it utilizes a conservative read threshold set based on single-word-line read interference stress. When a word line in a physical block experiences single-word-line read interference stress, the read count that triggers a scan may be 2 to 50 times lower than that of a word line in another physical block experiencing only uniform read interference stress. If two physical blocks are part of the same superblock, and the memory subsystem maintains a common read counter for the superblock, then the threshold number of read operations will be reached significantly faster than the actual number of reads seen by any of the individual physical blocks within the superblock. Therefore, while scanning one physical block may be appropriate, this scan operation may not be necessary for the remaining physical blocks in the superblock. Performing unnecessary scans in this way can cause the memory subsystem to perform excessive memory management operations. This can lead to degraded memory subsystem performance and increased power consumption. System bandwidth and other resources may also be occupied for extended periods, hindering their use for other functionalities.

[0020] This disclosure addresses the above and other shortcomings by using read counters with hierarchical granularity, where the granularity is based on whether the corresponding block stores recently written data. For blocks storing recently written data (i.e., open blocks), the memory subsystem can operate in a first operating mode and utilize read counters at the physical block level to individually track the number of read operations performed on each physical block. As the age of the data increases and the block no longer stores recently written data (i.e., closed blocks), for example if newer data has been written to other blocks on the memory component, the memory subsystem can switch to a second operating mode and utilize read counters at the superblock level to track the number of read operations performed together on all blocks in the superblock. By tracking read counts on closed blocks at the superblock level, the memory subsystem reduces the memory space overhead required to maintain the read counters and frees up the memory space for other data. By tracking read counts on open blocks at the physical block level, the memory subsystem reduces read count accumulation and decreases the frequency of performing data integrity scans, thereby improving performance, reducing power consumption, and freeing up system resources for other functionality. Therefore, when performing a read interference scan, the memory controller will be occupied for less time, thereby allowing the controller to have more time to handle other data access operations to the memory components.

[0021] Figure 1 This description describes an example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as memory components 112A to 112N. Memory components 112A to 112N may be volatile memory components, non-volatile memory components, or combinations thereof. The memory subsystem 110 may be a memory device, a memory module, or a hybrid of a memory device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. The host system 120, for example, uses the memory subsystem 110 to write data to and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, and includes, for example, electrical, optical, magnetic connections.

[0023] Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment, or networked business device), or a similar computing device containing memory and processing devices. Host system 120 may include or be coupled to memory subsystem 110 such that host system 120 can read data from or write data to memory subsystem 110. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. As used herein, “coupled to” generally refers to a connection between components, which may be a wired or wireless indirect communication connection or a direct communication connection (e.g., without intermediate components), including connections such as electrical, optical, magnetic, etc. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. The host system 120 may further utilize an NVM Fast (NVMe) interface to access memory components 112A to 112N when the memory subsystem 110 is coupled to the host system 120 via a PCIe interface. The physical host interface provides an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0024] Memory components 112A to 112N may comprise different types of non-volatile memory components and / or any combination of volatile memory components. Examples of non-volatile memory components include NAND flash memory. Each of memory components 112A to 112N may comprise one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., three-level cells (TLC) or four-level cells (QLC)). In some embodiments, a particular memory component may comprise both an SLC portion and an MLC portion of a memory cell. Each memory cell may store one or more data bits used by the host system 120. Although non-volatile memory components such as NAND flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112A to 112N may be (but are not limited to) random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase-change memory (PCM), magnetic random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. Additionally, the memory cells of memory components 112A to 112N may be grouped into memory pages or blocks, which may refer to units of the memory component used for storing data. The blocks can be further divided into one or more planes on each of the memory components 112A to 112N, wherein operations can be performed simultaneously on each of the planes. Corresponding blocks from different planes can be associated with each other in a single strip rather than across multiple planes.

[0025] Memory system controller 115 (hereinafter referred to as the "controller") can communicate with memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at memory components 112A to 112N, and other such operations. Controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. Controller 115 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. Controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of controller 115 includes embedded memory configured to store operations for performing various processes, operations, logical flows, and controlling the operation of memory subsystem 110, including handling communication between memory subsystem 110 and host system 120. In some embodiments, local memory 119 may include storage registers that store memory pointers, acquired data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure has been described as including controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0026] Generally, controller 115 can receive commands or operations from host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 112A to 112N. Controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical block addresses and physical block addresses associated with memory devices 112A to 112N. Controller 115 may further include host interface circuitry for communicating with host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 112A to 112N and translate responses associated with memory devices 112A to 112N into information for host system 120.

[0027] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) capable of receiving addresses from the controller 115 and decoding the addresses to access memory components 112A to 112N.

[0028] The memory subsystem 110 includes a scan determination component 113, which can be used to determine when to perform a scan or other data integrity check on blocks of memory components 112A through 112N. In one embodiment, the scan determination component 113 monitors the age of data stored in blocks of memory components 112A through 112N and implements a read counter with hierarchical granularity to track the number of read operations performed. The number of read operations performed is a metric that the scan determination component 113 can use to determine when to perform a data integrity scan. In one embodiment, the read counter is maintained in local memory 119. For blocks storing recently written data (i.e., open blocks), the scan determination component 113 can utilize a read counter at the physical block level to track the number of read operations performed on each physical block separately. In other embodiments, the scan determination component 113 can utilize the read counter and some other granularity, such as per word line, per word line group, or per other memory unit. When the read counter is maintained for smaller memory units, the accumulation rate is lower, and fewer word lines can be scanned during a data integrity scan. Therefore, when a read operation is performed on a physical block, the corresponding read counter for that physical block is incremented by a defined amount (e.g., 1). As the age of the data increases and the block no longer stores recently written data (i.e., a closed block), for example if newer data has been written to other blocks on the memory component, the scan determination component 113 can use read counters at the superblock level to track the number of read operations performed together on all blocks in the superblock. Therefore, when a read operation is performed on any block that is part of the superblock, the corresponding read counter for that superblock is incremented. If the scan determination component 113 determines that the read count (i.e., for an individual physical block or superblock) meets a first threshold criterion (e.g., exceeds a first read threshold), the scan determination component 113 can perform a data integrity scan to determine the error rate of all blocks in a physical block or superblock, as appropriate. After determining the corresponding error rate, the scan determination component 113 can determine whether any of the error rates exceeds an error threshold and can relocate the data from the block and reset the read count of the block. Further details regarding the operation of the scan determination component 113 are described below.

[0029] Figure 2 This is a flowchart illustrating an example method using a read counter with hierarchical granularity according to some embodiments of this disclosure. Method 200 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1The scanning and determination component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are feasible.

[0030] At operation 210, the processing device monitors the age of data stored in the various blocks on memory components 112A to 112N. In one embodiment, controller 115 maintains an index of all blocks stored on memory components 112A to 112N. For example, the index may contain a list of blocks and a sequential index number assigned to each of the blocks. When a new block is written to memory components 112A to 112N, controller 115 may add a corresponding entry to the index and assign an index number. Each time a new index number is assigned, the value of the index number may increment by one unit. Therefore, the value of the index number indicates the age of the data stored on the block, because the most recently written block may be assigned a higher index number than the previously written block. When a block is erased and / or overwritten with new data, controller 115 may assign a new index number to the block. In one embodiment, controller 115 maintains the index in local memory 119.

[0031] At operation 220, the processing device determines whether a particular block is storing recently written data. In one embodiment, the scan determination component 113 maintains a threshold criterion regarding the number of years the data has been stored, where the threshold criterion is used to determine whether the data was recently written. For example, the threshold criterion may include an index number representing a certain amount of recently written data. In one embodiment, the threshold criterion may be defined based on the number of blocks storing a certain amount of data (e.g., 1 gigabit) together. Therefore, the scan determination component 113 may determine the index number of a block, determine the difference between the index number and the highest index number in the index, and compare the difference with the threshold criterion. For example, if a block has an index number of 966, then the highest index number of 972 means a difference of 6, and if the threshold criterion is set to 24 blocks, the scan determination component 113 may determine that the data stored in the block meets the threshold criterion (i.e., is less than or equal to the threshold number of blocks). Conversely, if the difference is greater than the threshold number of blocks, then the data may be considered not to meet the threshold criterion.

[0032] If the block is storing recently written data, then in operation 230, the processing device maintains the first operating mode and uses a physical block-level read counter to track the number of read operations performed on the block. Figure 3This is a block diagram illustrating read counters at the physical block level according to some embodiments of the present disclosure. As illustrated, there are several logical superblocks S1, S2, S3, each comprising several physical blocks P0, P1 that span multiple logical unit numbers (LUNs) LUN1, LUN2, LUN3, LUN4. In one embodiment, a physical block is a portion of a strip of blocks spanning multiple LUNs (or planes) of a memory component. This strip may also be referred to as a superblock. In one embodiment, in a first operating mode, the scan determination component 113 maintains separate read counters C1 to C8 in local memory 119 for each physical block P0, P1 of each of the LUNs in superblock S1. If any of the blocks in a given superblock is storing recently written data, then the scan determination component 113 may use a separate physical block-level counter for each of the blocks in the superblock. Each time a read operation is performed on a block (e.g., P0 of LUN1), the scan determination component 113 may increment the corresponding physical block-level read counter (e.g., C1).

[0033] If the block is not storing recently written data, then in operation 240, the processing device switches to a second operating mode and uses a superblock-level read counter to track the number of read operations performed on the superblock. (As in...) Figure 3 As explained, if none of the blocks in a given superblock are storing recently written data, then the scan determination component 113 may use a single superblock-level counter (e.g., C9 or C10) for all blocks in the superblock (e.g., S2 or S3). Each time a read operation is performed on any of the blocks in the superblock, the scan determination component 113 may increment the corresponding superblock-level read counter (e.g., C9 or C10).

[0034] At operation 250, the processing device sets the value of the superblock-level read counter based on the highest value of any of the physical block-level read counters corresponding to physical blocks in the superblock. When transitioning from the first mode to the second mode, for example if data in the superblock has aged and is no longer eligible as recently written data, the scan determination component 113 can use the value of the physical block-level read counter to determine the value of the superblock-level read counter. For example, if it is determined that superblock S1 does not contain any recently written data at a certain point in time, the scan determination component 113 can identify the highest read count value from any of counters C1 to C8 and use that value as the new superblock-level read counter value for superblock S1.

[0035] Figure 4This is a flowchart of an example method for triggering a data integrity scan using a read counter at the physical block level, according to some embodiments of this disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The scanning and determination component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are feasible.

[0036] At operation 410, the processing device enters a first mode using a separate read counter for each physical block in the superblock. As described above, if any of the blocks in a given superblock S1 (e.g., P0 to P1 on LUN1 to LUN4) is storing recently written data, then the scan determination component 113 may use separate physical block-level counters C1 to C8 for each of the blocks in the superblock. At operation 420, the processing device increments the physical block-level read counter in response to receiving a read request directed to the corresponding block. For example, the controller 115 may receive a read request indicating a specific logical data address and may determine the corresponding physical block address of the data. The controller 115 may then perform a read operation on the block (e.g., P0 of LUN1 in superblock S1), and the scan determination component 113 may increment the corresponding physical block-level read counter (e.g., C1).

[0037] At operation 430, the processing device determines whether the value of the read counter C1 (i.e., the read count) meets a read threshold criterion (i.e., meets or exceeds a first read threshold). The read count represents the number of times the first block (e.g., P0 of LUN1) has been read since a previous scan operation or data integrity check was performed on the first block, at which point the read count is reset. In other embodiments, when a scan operation or data integrity check is performed, the read counter is not reset, but the read count threshold is incremented by a threshold amount. The first read threshold may represent the number of read operations performed on a given memory block before a scan or other data integrity check should be performed. In one embodiment, the scan determination component 113 compares the read count with the first read threshold to determine whether the read count meets or exceeds the first read threshold. If the read count does not meet or exceeds the first read threshold, the processing device returns to operation 410 and continues to monitor the read count values ​​of blocks on the memory component. In another embodiment, the first threshold criterion includes a read count below the first read threshold, such that if the read count does not meet the first threshold criterion, the processing device continues to operation 440.

[0038] If the read threshold criterion is met, then at operation 440, the processing device performs a data integrity scan to determine the error rate of the block. The error rate associated with the data stored at the block may increase due to read interference. Therefore, after performing a threshold number of read operations on the block, the memory subsystem 110 may perform a scan or other data integrity check to verify that the data stored at the block does not contain any errors, or that the number of errors is appropriately low. During the scan, the scan determination component 113 identifies one or more reliability statistics, such as the raw bit error rate (RBER), which represents the number of bit errors experienced by the data stored at the block per unit time. In one embodiment, during the scan, the scan determination component 113 reads a raw codeword (i.e., a fixed number of bits) from the block. The scan determination component 113 may apply the codeword to an error correction code (ECC) decoder to produce a decoded codeword and compare the decoded codeword with the raw codeword. The scan determination component 113 may count the number of flipped bits between the decoded codeword and the raw codeword, where the ratio of the number of flipped bits to the total number of bits in the codeword represents the RBER. The scan determination component 113 can repeat this process for additional codewords until the entire block has been scanned.

[0039] At operation 450, the processing device determines whether the error rate of the block meets an error threshold criterion (i.e., meets or exceeds an error threshold). In one embodiment, the scan determination component 113 compares the error rate with an error threshold representing the error correction capability of the memory component. If the error rate does not meet or exceeds the error threshold, the processing device returns to operation 410 and continues to monitor the read count value of the block on the memory component. In another embodiment, the error threshold criterion includes an error rate below an error threshold, such that if the error rate does not meet the error threshold criterion, the processing device continues to operation 460.

[0040] If the error threshold criterion is met, then in operation 460, the processing device relocates the data from the block to another block and resets the read count value of the read counter C1 (e.g., to 0 or some other initial value). In one embodiment, the scan determining component 113 reads the data stored in the corresponding block (i.e., the block whose error rate meets or exceeds the error threshold) and writes the data to another block. Once the data has been written to the other block, the data stored in the initial block is erased and the initial block can be programmed with the new data. Depending on the embodiment, the data may be relocated to another block on the same plane of the same memory component, another plane on the same memory component, or a different memory component of the memory subsystem 110.

[0041] Figure 5 This is a flowchart of an example method for triggering a data integrity scan using a read counter at the superblock level, according to some embodiments of this disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The scanning and determination component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are feasible.

[0042] In operation 510, the processing device enters a second mode using a single read counter for each superblock. As described above, if none of the blocks in a given superblock S2 (e.g., P0 to P1 on LUN1 to LUN4) are storing recently written data, then the scan determination component 113 may use a single superblock-level counter C9 for superblock S2. In operation 520, the processing device increments the superblock-level read counter C9 in response to receiving a read request directed to any block in superblock S2. For example, the controller 115 may receive a read request indicating a specific logical data address and may determine the corresponding physical block address of the data. The controller 115 may then perform a read operation on the block (e.g., P0 of LUN1 in superblock S2), and the scan determination component 113 may increment the corresponding superblock-level read counter (e.g., C9).

[0043] At operation 530, the processing device determines whether the value of the read counter C9 (i.e., the read count) meets a read threshold criterion (i.e., meets or exceeds a first read threshold). The read count represents the number of times any of the blocks in the corresponding superblock S2 has been read since a previous scan operation or data integrity check was performed on the block, at which point the read count is reset. The first read threshold may represent the number of read operations performed on a given memory block before a scan or other data integrity check should be performed. In one embodiment, the scan determination component 113 compares the read count with the first read threshold to determine whether the read count meets or exceeds the first read threshold. If the read count does not meet or exceeds the first read threshold, the processing device returns to operation 510 and continues to monitor the read count values ​​of blocks on the memory component. In another embodiment, the first threshold criterion includes a read count below the first read threshold, such that if the read count does not meet the first threshold criterion, the processing device continues to operation 540.

[0044] If the read threshold criterion is met, then at operation 540, the processing device performs a data integrity scan to determine the error rate for each physical block in superblock S2. During the scan, the scan determination component 113 identifies one or more reliability statistics, such as the raw bit error rate (RBER), which represents the number of bit errors experienced by the data stored at the block per unit time. In one embodiment, during the scan, the scan determination component 113 reads raw codewords (i.e., a fixed number of bits) from the block. The scan determination component 113 may apply the codewords to an error correction code (ECC) decoder to produce decoded codewords and compare the decoded codewords with the raw codewords. The scan determination component 113 may count the number of flipped bits between the decoded codewords and the raw codewords, where the ratio of the number of flipped bits to the total number of bits in the codewords represents the RBER. The scan determination component 113 may repeat this process for additional codewords until every block in the superblock has been scanned.

[0045] At operation 550, the processing device determines whether the error rate of any of the physical blocks meets an error threshold criterion (i.e., meets or exceeds an error threshold). In one embodiment, the scan determining component 113 compares the error rate of a block with an error threshold representing the error correction capability of the memory component. If the error rate of a particular block does not meet or exceeds the error threshold, the processing device returns to operation 510 and continues to monitor the read count values ​​of blocks on the memory component. In another embodiment, the error threshold criterion includes an error rate below an error threshold, such that if the error rate does not meet the error threshold criterion, the processing device proceeds to operation 560.

[0046] If the error threshold criterion is met, then in operation 560, the processing device relocates the data from the block to another block and resets the read count value of the read counter C9 (e.g., to 0 or some other initial value). In one embodiment, the scan determining component 113 reads the data stored in the corresponding block (i.e., the block whose error rate meets or exceeds the error threshold) and writes the data to another block. Once the data has been written to the other block, the data stored in the initial block is erased and the initial block can be programmed with the new data. Depending on the embodiment, the data may be relocated to another block on the same plane of the same memory component, another plane on the same memory component, or a different memory component of the memory subsystem 110.

[0047] Figure 6 This is a flowchart of an example method for determining a read count scaling factor according to some embodiments of the present disclosure. Method 600 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 600 is performed by… Figure 1 The scanning and determination component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are feasible.

[0048] At operation 610, the processing device performs a data integrity scan to identify one or more reliability statistics, such as RBER, associated with each word line in the block. In one embodiment, during the scan, the scan determination component 113 reads the original codeword (i.e., a fixed number of bits) from each word line, applies the codeword to the ECC decoder to produce a decoded codeword, and compares the decoded codeword with the original codeword. The scan determination component 113 may count the number of flipped bits between the decoded codeword and the original codeword, where the ratio of the number of flipped bits to the total number of bits in the codeword represents the RBER. The scan determination component 113 may repeat this process for additional codewords until every word line in the block has been scanned.

[0049] At operation 620, the processing device uses one or more single-word lines from the determined error rate identification block to read interference-affected areas. The single-word line read interference-affected areas may have significantly higher error rates than other word line areas. In one embodiment, the scan determination component 113 may compare the determined error rates of each word line with each other and identify the highest error rate. For example, the scan determination component may identify word lines with determined error rates exceeding a certain threshold amount (the average of all word line error rates) as constituting single-word line read interference-affected areas. In one embodiment, word lines with error rates higher than a first threshold may be considered part of a single-word line read interference-affected area, and word lines with error rates lower than a second threshold may be considered part of another word line area.

[0050] At operation 630, the processing device determines the read interference capability of one or more single-word-line read interference victim areas and other word-line areas unaffected by single-word-line read interference. In one embodiment, the scan determination component 113 compares the determined error rate for each of the word lines with an error threshold for the block to normalize the result. The scan determination component 113 may determine that the determined error rate represents a percentage of the error threshold for the corresponding word line. For example, if the error threshold is 200 and the determined error rate for the word line is 20, then the resulting percentage is 10%. The remaining percentage (i.e., 90%) represents the read interference capability of the word line. In one embodiment, the scan determination component 113 makes a similar determination for each of one or more single-word-line read interference victim areas and other word-line areas. For example, a word line from a single-word-line read interference victim area has an error rate of 180, giving a 90% percentage indicates a read interference capability of 10%. In one embodiment, a word line with read interference capability below a first threshold can be considered part of a single word line read interference victim area, and a word line with read interference capability above a second threshold can be considered part of another word line area.

[0051] At block 640, the processing device determines a read count scaling factor based on the ratio of read interference capability of other word line regions to read interference capability of one or more single-word line read interference victim regions. In one embodiment, scan determination component 113 determines a first average read interference capability of all word lines in the portion identified as other word line regions and a second average read interference capability of all word lines in the portion identified as one or more single-word line read interference victim regions. In another embodiment, scan determination component 113 determines a first maximum read interference capability of all word lines in the portion identified as other word line regions and a second maximum read interference capability of all word lines in the portion identified as one or more single-word line read interference victim regions. Scan determination component 113 may determine a ratio of the first maximum value to the second maximum value, wherein the determined ratio may be used as a read count scaling factor. For example, if the first maximum value is 90% and the second maximum value is 10%, then the determined read count scaling factor is 9. In one embodiment, scan determination component 113 may store an indication of the read count scaling factor in data structure 700, such as in Figure 7 The explanation is as follows. Figure 7 This is a block diagram illustrating a data structure 700 for storing read count scaling factors according to some embodiments of the present disclosure. In one embodiment, the data structure includes entries corresponding to each segment (e.g., block) on a memory component and may be stored, for example, in local memory 119. As illustrated, each entry may include an identifier of the corresponding segment, the current read count of the segment, a defined scan threshold for the segment, an indication of one or more single-word line read interference victim areas in the segment, and a determined scaling factor for the segment.

[0052] Refer again Figure 6 At block 650, the processing device serves the read counters of one or more single-word-line read interference victim areas and other word-line areas based on a read count scaling factor. In one embodiment, for each read operation directed to a word line in one or more single-word-line read interference victim areas, scan determination component 113 may increment the read counter of the block by a default amount (e.g., 1), and for each read operation directed to a word line in other word-line areas, scan determination component 113 may increment the read counter of the block by a scaling amount (e.g., 1 / 9). The following is in conjunction with... Figure 8 Additional details regarding the use of this read count scaling factor are described below.

[0053] Figure 8This is a flowchart of an example method using a read count scaling factor when incrementing a read counter to trigger a data integrity scan, according to some embodiments of this disclosure. Method 800 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 800 is performed by… Figure 1 The scanning and determination component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are feasible.

[0054] At operation 810, the processing device receives a read request from the host system 120 or from another component of the memory subsystem 110. At operation 820, the processing device determines whether the read request is directed to data stored in a single-word-line read interference victim area. In one embodiment, the controller 115 may receive a read request indicating a specific logical data address and may determine the corresponding physical block address of the data. As described above, the data structure 700 may include indications of one or more single-word-line read interference victim areas within the segment. Therefore, if the physical address is part of an address range identified in the data structure 700, then the controller 115 may determine that the data identified in the read request is stored in a single-word-line read interference victim area. Otherwise, the controller 115 considers the read request to be directed to another word-line area of ​​the block.

[0055] If a read request is directed to data stored in a single-word read interference victim area, then in operation 830, the processing device increments the read counter for the block by a default amount. In one embodiment, the scan determining component increments the read counter in the data structure 700 corresponding to the identified block by a default amount (e.g., 1). The default amount is a configurable parameter and may have other values ​​in other embodiments.

[0056] If a read request is not directed to data stored in the single-word read interference victim area, then at operation 840, the processing device increments the read counter for the block by a scaling amount. In one embodiment, the scaling amount includes a value representing the reciprocal of the scaling factor. For example, if the determined scaling factor is 9, then the scaling amount could be 1 / 9.

[0057] At operation 850, the processing device determines whether the value of the read counter (i.e., the read count) meets a read threshold criterion (i.e., meets or exceeds a first read threshold). The read count represents the number of times the block has been read since a previous scan operation or data integrity check was performed on the block, at which point the read count is reset. The first read threshold may represent the number of read operations performed on a given memory block before a scan or other data integrity check should be performed. In one embodiment, the scan determination component 113 compares the read count with the first read threshold to determine whether the read count meets or exceeds the first read threshold. If the read count does not meet or exceeds the first read threshold, the processing device returns to operation 810 and waits to receive another read request from the host system 120.

[0058] If the read threshold criterion is met, then at operation 860, the processing device performs a data integrity scan to determine the error rate for the block. The error rate associated with the data stored at the block may increase due to read interference. Therefore, after performing a threshold number of read operations on the block, the memory subsystem 110 may perform a scan or other data integrity check to verify that the data stored at the block does not contain any errors, or that the number of errors is appropriately low. During the scan, the scan determination component 113 identifies one or more reliability statistics, such as the RBER representing the number of bit errors experienced per unit time by the data stored at the block. In one embodiment, during the scan, the scan determination component 113 reads the original codeword (i.e., a fixed number of bits) from the block. The scan determination component 113 may apply the codeword to an ECC decoder to produce a decoded codeword and compare the decoded codeword with the original codeword. The scan determination component 113 may count the number of flipped bits between the decoded codeword and the original codeword, where the ratio of the number of flipped bits to the total number of bits in the codeword represents the RBER. The scan determination component 113 may repeat this process for additional codewords until the entire block has been scanned.

[0059] At operation 870, the processing device determines whether the block's error rate meets an error threshold criterion (i.e., meets or exceeds an error threshold). In one embodiment, the scan determination component 113 compares the error rate with an error threshold representing the error correction capability of the memory component. If the error rate does not meet or exceeds the error threshold, the processing device returns to operation 810 and waits to receive another read request from the host system 120.

[0060] If the error threshold criterion is met, then in operation 880, the processing device relocates the data from the block to another block and resets the read count value of the read counter (e.g., to 0 or some other initial value). In one embodiment, the scan determining component 113 reads the data stored in the block and writes the data to another block. Once the data has been written to the other block, the data stored in the initial block is erased and the initial block can be programmed with the new data. Depending on the embodiment, the data may be relocated to another block on the same plane of the same memory component, another plane on the same memory component, or a different memory component of the memory subsystem 110.

[0061] Figure 9 This is a flowchart of an example method for applying hierarchical criteria to block refresh after a data integrity scan, according to some embodiments of this disclosure. Method 900 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 900 is performed by… Figure 1 The scanning and determination component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are feasible.

[0062] At operation 910, the processing device performs a data integrity scan to determine the error rate for each word line on the block. The error rate associated with the data stored in the block may increase due to read interference. Therefore, after performing a threshold number of read operations on the block, the memory subsystem 110 may perform a scan or other data integrity check to verify that the data stored in the block does not contain any errors, or that the number of errors is appropriately low. During the scan, the scan determination component 113 identifies one or more reliability statistics, such as the RBER representing the number of bit errors experienced per unit time by the data stored in the block. In one embodiment, during the scan, the scan determination component 113 reads the original codeword (i.e., a fixed number of bits) from the block. The scan determination component 113 may apply the codeword to an ECC decoder to produce a decoded codeword and compare the decoded codeword with the original codeword. The scan determination component 113 may count the number of flipped bits between the decoded codeword and the original codeword, where the ratio of the number of flipped bits to the total number of bits in the codeword represents the RBER. The scan determination component 113 may repeat this process for additional codewords until every word line in the block has been scanned.

[0063] At operation 920, the processing device determines whether the highest error rate of a specific word line in the block meets an error threshold criterion (i.e., meets or exceeds an error threshold). In one embodiment, the scan determination component 113 compares the highest error rate of a given word line in the block with an error threshold representing the error correction capability of the memory component. If the highest error rate does not meet or exceeds the error threshold, the processing device returns to operation 810 and waits to receive another read request from the host system 120.

[0064] If the highest error rate of a block meets the error threshold criterion, then in operation 930, the processing device determines how many word lines have an error rate that meets the error threshold criterion and whether the number of word lines meets the folding threshold criterion. Generally, the error threshold criterion is based on the hard decoding threshold of the ECC decoder to minimize the error handling trigger rate. However, in practice, there can be significant read interference margins for read retry and soft decoding capabilities. The word line with the highest error rate in a block may be affected by local read stress (e.g., single-word-line read interference stress) or inherently weaker than other word lines. Therefore, it may not be necessary to refresh the entire block based on this single word line. Therefore, the scan determination component 113 can determine whether a threshold number of word lines have an error rate exceeding the error threshold before deciding to refresh the block. If the number of word lines with high error rates does not meet the folding threshold criterion, then the scan determination component can rely on the error handling process built into the memory subsystem 110 to handle those errors.

[0065] However, if the number of word lines with a high error rate does indeed meet the folding threshold criterion, then in operation 940, the processing device relocates the data from the block to another block and resets the read count value of the read counter (e.g., to 0 or some other initial value). In one embodiment, the scan determining component 113 reads the data stored in the block and writes the data to another block. Once the data has been written to the other block, the data stored in the initial block is erased and the initial block can be programmed with the new data. Depending on the embodiment, the data may be relocated to another block on the same plane of the same memory component, another plane on the same memory component, or a different memory component of the memory subsystem 110.

[0066] Figure 10 An example machine illustrating computer system 1000 is described, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 1000 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (The operation of the scanning determination component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The computer may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0067] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0068] The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1018, which communicate with each other via a bus 1030.

[0069] Processing device 1002 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 1002 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 1002 is configured to execute instructions 1026 for performing the operations and steps discussed herein. Computer system 1000 may further include a network interface device 1008 for communication via network 1020.

[0070] Data storage system 1018 may include machine-readable storage medium 1024 (also referred to as computer-readable medium) on which one or more sets of instructions 1026 or software embodying any or more of the methods or functions described herein are stored. During execution of instructions 1026 by computer system 1000, the instructions may also reside wholly or at least partially in main memory 1004 and / or processing device 1002, which also constitute machine-readable storage medium. Machine-readable storage medium 1024, data storage system 1018, and / or main memory 1004 may correspond to... Figure 1 The memory subsystem 110.

[0071] In one embodiment, instruction 1026 includes instructions for implementing the corresponding Figure 1 The scanning determines the functional instructions of component 113. Although machine-readable storage medium 1024 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0072] Certain portions of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of operations that leads to a desired result. These operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, or similar terms, primarily for general reasons.

[0073] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) numbers in the registers and memories of the computer system into physical quantities similarly represented as those in the computer system's memory or registers or other such information storage systems.

[0074] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically configured for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0075] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will appear as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0076] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0077] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than limiting.

Claims

1. A storage subsystem comprising: A memory component comprising multiple blocks; and A processing device operatively coupled to the memory assembly to perform the following operations: The data in the first block of the plurality of blocks stored in the memory component is determined to satisfy a first threshold criterion regarding the number of years of the data; In response to the data stored in the first block satisfying the first threshold criterion, a first counter is maintained to track the number of read operations performed on the first block; It is determined that the data stored in the first block does not meet the first threshold criterion; and In response to the data stored in the first block not meeting the first threshold criterion, a second counter is maintained to track the number of read operations performed on the superblock that includes the plurality of blocks.

2. The storage subsystem according to claim 1, wherein the processing device further performs the following operations: In response to the data stored in the first block satisfying the first threshold criterion, a plurality of counters are maintained to track the number of read operations performed on each of the plurality of blocks.

3. The storage subsystem according to claim 2, wherein the processing device further performs the following operations: Set the value of the second counter to be equal to the highest value of any of the plurality of counters; and Discard the aforementioned counters.

4. The storage subsystem of claim 1, wherein the plurality of blocks in the superblock are arranged in stripes across a plurality of planes of the memory assembly.

5. The storage subsystem according to claim 1, wherein the processing device further performs the following operations: Determine that the value of the first counter satisfies a second threshold criterion regarding the number of read operations performed on the first block; and In response to the value of the first counter satisfying the second threshold criterion, a data integrity scan is performed to determine the first error rate of the first block.

6. The storage subsystem of claim 5, wherein, in order to perform the data integrity scan, the processing device performs the following operations: Determine whether the first error rate meets the error threshold criterion; and In response to the first error rate satisfying the error threshold criterion: The data stored in the first block is relocated to another block on the memory component; and Reset the value of the first counter to its initial value.

7. The storage subsystem of claim 1, wherein the processing device further performs the following operations: Determine that the value of the second counter satisfies a third threshold criterion regarding the number of read operations performed on the superblock; and In response to the value of the second counter satisfying the third threshold criterion, a data integrity scan is performed to determine the error rate of each of the plurality of blocks in the superblock.

8. The storage subsystem of claim 7, wherein, in order to perform the data integrity scan, the processing device performs the following operations: Determine whether at least one of the error rates of at least one of the plurality of blocks satisfies an error threshold criterion; and In response to at least one of the error rates satisfying the error threshold criterion: The data stored in at least one of the plurality of blocks is relocated to another block on the memory component; and Reset the value of the second counter to its initial value.

9. The storage subsystem of claim 7, wherein, in order to perform the data integrity scan, the processing device performs the following operations: Determine whether the highest error rate among the corresponding blocks in the plurality of blocks satisfies the error threshold criterion; In response to the highest of the error rates satisfying the error threshold criterion, it is determined whether the number of error rates of the corresponding blocks among the plurality of blocks that satisfy the error threshold criterion satisfies the folding threshold criterion; and In response to the number satisfying the folding threshold criterion: The data stored in the corresponding of the plurality of blocks is relocated to other blocks on the memory component; and Reset the value of the second counter to its initial value.

10. A method of operating a memory subsystem, comprising: The data in the first block of a plurality of blocks stored in a memory component is determined to satisfy a first threshold criterion regarding the number of years of the data; In response to the data stored in the first block satisfying the first threshold criterion, the memory subsystem maintains a first operating mode, wherein in the first operating mode, read counts for the first block are tracked at the physical block level; It is determined that the data stored in the first block does not meet the first threshold criterion; and In response to the data stored in the first block not satisfying the first threshold criterion, a second operating mode of the memory subsystem is initiated, wherein in the second operating mode, the read count is tracked at the superblock level, wherein the superblock includes the plurality of blocks.

11. The method of claim 10, further comprising: In the first operating mode, the read count is determined to satisfy a second threshold criterion regarding the number of read operations performed on the first block; and In response to the read count satisfying the second threshold criterion, a data integrity scan is performed to determine the first error rate of the first block.

12. The method of claim 11, wherein performing the data integrity scan comprises: Determine whether the first error rate meets the error threshold criterion; and In response to the first error rate satisfying the error threshold criterion: The data stored in the first block is relocated to another block on the memory component; and Reset the read count of the first block to its initial value.

13. The method of claim 10, further comprising: In the second operating mode, it is determined that the read count satisfies a third threshold criterion regarding the number of read operations performed on the superblock; and In response to the read count satisfying the third threshold criterion, a data integrity scan is performed to determine the error rate of each of the plurality of blocks in the superblock.

14. The method of claim 13, wherein performing the data integrity scan comprises: Determine whether at least one of the error rates of at least one of the plurality of blocks satisfies an error threshold criterion; and In response to at least one of the error rates satisfying the error threshold criterion: The data stored in at least one of the plurality of blocks is relocated to another block on the memory component; and The read count for the superblock is reset to its initial value.

15. A non-transitory computer-readable storage medium comprising instructions, when executed by a processing means, causing the processing means to perform the following operations: The data in the first block of a plurality of blocks stored in a memory component is determined to satisfy a first threshold criterion regarding the number of years of the data; In response to the data stored in the first block satisfying the first threshold criterion, a first counter is maintained to track the number of read operations performed on the first block; It is determined that the data stored in the first block does not meet the first threshold criterion; and In response to the data stored in the first block not meeting the first threshold criterion, a second counter is maintained to track the number of read operations performed on the superblock that includes the plurality of blocks.

16. The non-transitory computer-readable storage medium of claim 15, wherein the instructions further cause the processing apparatus to perform the following operations: In response to the data stored in the first block satisfying the first threshold criterion, a plurality of counters are maintained to track the number of read operations performed on each of the plurality of blocks.

17. The non-transitory computer-readable storage medium of claim 16, wherein the instructions further cause the processing apparatus to perform the following operations: Set the value of the second counter to be equal to the highest value of any of the plurality of counters; and Discard the aforementioned counters.

18. The non-transitory computer-readable storage medium of claim 15, wherein the instructions further cause the processing apparatus to perform the following operations: Determine that the value of the first counter satisfies a second threshold criterion regarding the number of read operations performed on the first block; and In response to the value of the first counter satisfying the second threshold criterion, a data integrity scan is performed to determine a first error rate of the first block, wherein, in order to perform the data integrity scan, the processing device performs the following operations: Determine whether the first error rate meets the error threshold criterion; and In response to the first error rate satisfying the error threshold criterion: The data stored in the first block is relocated to another block on the memory component; and Reset the value of the first counter to its initial value.

19. The non-transitory computer-readable storage medium of claim 15, wherein the instructions further cause the processing apparatus to perform the following operations: Determine that the value of the second counter satisfies a third threshold criterion regarding the number of read operations performed on the superblock; and In response to the value of the second counter satisfying the third threshold criterion, a data integrity scan is performed to determine the error rate of each of the plurality of blocks in the superblock, wherein, in order to perform the data integrity scan, the processing device performs the following operations: Determine whether at least one of the error rates of at least one of the plurality of blocks satisfies an error threshold criterion; and In response to at least one of the error rates satisfying the error threshold criterion: The data stored in at least one of the plurality of blocks is relocated to another block on the memory component; and Reset the value of the second counter to its initial value.

20. The non-transitory computer-readable storage medium of claim 19, wherein, in order to perform the data integrity scan, the instructions further cause the processing device to perform the following operations: Determine whether the highest error rate among the corresponding blocks in the plurality of blocks satisfies the error threshold criterion; The highest of the error rates satisfies the error threshold criterion; Determine whether the number of error rates of the corresponding entities among the plurality of blocks that satisfy the error threshold criterion satisfies the folding threshold criterion; and In response to the number satisfying the folding threshold criterion: The data stored in the corresponding of the plurality of blocks is relocated to other blocks on the memory component; and Reset the value of the second counter to its initial value.

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