Solid-state imaging device having shared circuit elements and imaging device

Abstract

An imaging device includes a plurality of unit pixels arranged as pixel groups separated from each other by a separation structure. The unit pixels within each pixel group are separated from each other by the separation structure and share a circuit element. The separation structure between the pixel groups is a full-thickness separation structure. At least a portion of the separation structure between the unit pixels within a pixel group is a deep trench separation structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an imaging device having a dynamic vision sensor capability. BACKGROUND

[0002] In the related art, a synchronous type solid-state imaging device that acquires image data in synchronization with a synchronization signal such as a vertical synchronization signal has been used in imaging devices and the like. In a typical synchronous type solid-state imaging device, since it is difficult to acquire image data at every cycle (for example, every 1 / 60 second) of the synchronization signal, it is difficult to cope with cases requiring relatively high-speed processing, for example, in fields requiring high-speed (for example, real-time) processing, such as autonomous vehicles and robots, and the like. In this regard, a non-synchronous type solid-state imaging device in which a detection circuit is provided for each pixel for detecting a case where the amount of light reception exceeds a threshold value as an address event in real time has been proposed. The non-synchronous type solid-state imaging device that detects an address event for each pixel is also referred to as a dynamic vision sensor (DVS). SUMMARY

[0003] [PROBLEMS]

[0004] However, in the DVS system, in addition to the circuit configuration for reading out a pixel signal having a voltage value corresponding to the amount of light reception, a circuit configuration for detecting an address event must also be provided, and thus the occupancy ratio of the light receiving elements on the light receiving surface decreases. By utilizing a shared transistor, embodiments of the present disclosure can provide a high-resolution imaging device having sufficient sensitivity. In addition, in order to reduce crosstalk, the different pixels or photodetectors within the DVS system must be separated. For example, in previous DVS systems, RFTI (full-thickness dielectric trench) separation was employed. However, the adoption of the RFTI separation structure in the previous DVS systems makes it impossible or difficult to share transistors or other circuit elements between the photodetectors. As a result, the quantum efficiency (hereinafter referred to as "light receiving efficiency") of the incident light of the DVS system has been relatively poor.

[0005] Therefore, the present disclosure provides a solid-state imaging device and an imaging device capable of improving the light receiving efficiency.

[0006] [TECHNICAL SOLUTION]

[0007] According to embodiments and aspects of the present disclosure, a camera device is provided that includes a plurality of photoelectric conversion regions or a plurality of pixels arranged in an array. Groups of the plurality of photoelectric conversion regions or the plurality of pixels that share at least some circuit elements, including but not limited to transistors, are formed within the array. A full-thickness rear deep trench isolation (RFTI) structure is provided between the groups of the plurality of photoelectric conversion regions. A rear deep trench isolation (RDTI) is provided along at least a portion of a boundary between adjacent photoelectric conversion regions within each group of the plurality of photoelectric conversion regions.

[0008] Further, according to embodiments and aspects of the present disclosure, some or all of the photoelectric conversion regions are operatively connected to first and second readout circuits. Further, the circuit elements shared between the photoelectric conversion regions within the group of photoelectric conversion regions can include at least some elements of the first and second readout circuits shared between the photoelectric conversion regions within any group of photoelectric conversion regions. The shared elements can include, but are not limited to, transistors, floating diffusion, and signal lines.

[0009] Further, according to embodiments and aspects of the present disclosure, at least a portion of the one or more shared elements can be formed below the RDTI isolation structure, i.e., between the end of the RDTI structure that terminates within the substrate and the non-light-incident surface of the substrate. The present disclosure provides a solid-state camera device and camera device with dynamic vision sensing and camera capabilities that can improve light reception efficiency. More particularly, embodiments of the present disclosure provide a camera device with improved aperture ratio. BRIEF DESCRIPTION OF DRAWINGS

[0010] [ Figure 1 ] Figure 1 is a block diagram illustrating a schematic configuration example of a solid-state camera device according to an embodiment of the present disclosure.

[0011] [ Figure 2 ] Figure 2 is a diagram illustrating a layer stack structure example of a solid-state camera device according to an embodiment of the present disclosure.

[0012] [ Figure 3 ] Figure 3 is a block diagram illustrating a functional configuration example of a solid-state camera device according to an embodiment of the present disclosure.

[0013] [ Figure 4 ] Figure 4 is a diagram illustrating an array example of unit pixels according to an embodiment of the present disclosure when a Bayer array is employed in a color filter array.

[0014] [ Figure 5 ] Figure 5 is a circuit diagram showing a schematic configuration example of a unit pixel according to an embodiment of the present disclosure.

[0015] [ Figure 6 ] Figure 6 is a block diagram showing a schematic configuration example of an address event detection unit according to an embodiment of the present disclosure.

[0016] [ Figure 7 ] Figure 7 is a circuit diagram showing a schematic configuration example of a subtracter and a quantizer according to an embodiment of the present disclosure.

[0017] [ Figure 8 ] Figure 8 is a block diagram showing a schematic configuration example of a column ADC according to an embodiment of the present disclosure.

[0018] [ Figure 9 ] Figure 9 is a timing chart showing an example of operation of a solid-state imaging device according to an embodiment of the present disclosure.

[0019] [ Figure 10 ] Figure 10 is a flowchart showing an example of operation of a solid-state imaging device according to an embodiment of the present disclosure.

[0020] [ Figure 11 ] Figure 11 is a circuit diagram showing a schematic configuration example of a unit pixel group according to at least some embodiments of the present disclosure.

[0021] [ Figure 12A ] Figure 12A is a plan view of a pixel configuration according to a first exemplary embodiment of the present disclosure.

[0022] [ Figure 12B ] Figure 12B is a cross section of a portion of the first exemplary embodiment.

[0023] [ Figure 13A ] Figure 13A is a plan view of a pixel configuration according to a second exemplary embodiment of the present disclosure.

[0024] [ Figure 13B ] Figure 13B is a cross section of a portion of the second exemplary embodiment.

[0025] [ Figure 13C ] Figure 13C is a cross section of another portion of the second exemplary embodiment.

[0026] [Figure 14A ] Figure 14A is a plan view of a pixel configuration according to a third exemplary embodiment of the present disclosure.

[0027] [ Figure 14B ] Figure 14B is a cross section of a portion of the third exemplary embodiment.

[0028] [ Figure 14C ] Figure 14C is a cross section of another portion of the third exemplary embodiment.

[0029] [ Figure 15A ] Figure 15A is a plan view of a pixel configuration according to a fourth exemplary embodiment of the present disclosure.

[0030] [ Figure 15B ] Figure 15B is a cross section of a portion of the fourth exemplary embodiment.

[0031] [ Figure 15C ] Figure 15C is a cross section of another portion of the fourth exemplary embodiment.

[0032] [ Figure 16A ] Figure 16A is a plan view of a pixel configuration according to a fifth exemplary embodiment of the present disclosure.

[0033] [ Figure 16B ] Figure 16B is a cross section of a portion of the fifth exemplary embodiment.

[0034] [ Figure 16C ] Figure 16C is a cross section of another portion of the fifth exemplary embodiment.

[0035] [ Figure 17A ] Figure 17A is a plan view of a pixel configuration according to a sixth exemplary embodiment of the present disclosure.

[0036] [ Figure 17B ] Figure 17B is a cross section of a portion of the sixth exemplary embodiment.

[0037] [ Figure 18A ] Figure 18A is a plan view of a pixel configuration according to a seventh exemplary embodiment of the present disclosure.

[0038] [ Figure 18B ] Figure 18B is a cross section of a portion of the seventh exemplary embodiment.

[0039] [ Figure 18C ] Figure 18Cis a cross-section of a portion of the seventh exemplary embodiment.

[0040] [ Figure 19A ] Figure 19A is a plan view of a pixel configuration according to an eighth exemplary embodiment of the present disclosure.

[0041] [ Figure 19B ] Figure 19B is a cross-section of a portion of the eighth exemplary embodiment.

[0042] [ Figure 20A ] Figure 20A is a plan view of a pixel configuration according to a ninth exemplary embodiment of the present disclosure.

[0043] [ Figure 20B ] Figure 20B is a cross-section of a portion of the ninth exemplary embodiment.

[0044] [ Figure 21A ] Figure 21A is a plan view of a pixel configuration according to a tenth exemplary embodiment of the present disclosure.

[0045] [ Figure 21B ] Figure 21B is a cross-section of a portion of the tenth exemplary embodiment.

[0046] [ Figure 22A ] Figure 22A is a plan view of a pixel configuration according to an eleventh exemplary embodiment of the present disclosure.

[0047] [ Figure 22B ] Figure 22B is a cross-section of a portion of the eleventh exemplary embodiment.

[0048] [ Figure 23 ] Figure 23 is a circuit diagram showing a schematic configuration example of a unit pixel according to at least some embodiments of the present disclosure.

[0049] [ Figure 5 ] Figure 11 is a plan view of a pixel configuration according to a twelfth exemplary embodiment of the present disclosure.

[0050] [ Figure 11 ] Figure 23 is a cross-section of a portion of the twelfth exemplary embodiment.

[0051] [ Figure 24A ] Figure 24B is a plan view of a pixel configuration according to a thirteenth exemplary embodiment of the present disclosure.

[0052] [ Figure 24A ] Figure 12Ais a cross section of a portion of the thirteenth example embodiment.

[0053] [ Figure 24B ] Figure 24A is a cross section of another portion of the thirteenth example embodiment.

[0054] [ Figure 24B ] Figure 23 is a plan view of a pixel configuration according to a fourteenth example embodiment of the present disclosure.

[0055] [ Figure 24A ] Figure 25A is a cross section of a portion of the fourteenth example embodiment.

[0056] [ Figure 25B ] Figure 25A is a plan view of a pixel configuration according to a fifteenth example embodiment of the present disclosure.

[0057] [ Figure 25C ] Figure 25A is a cross section of a portion of the fifteenth example embodiment.

[0058] [ Figure 25A ] Figure 23 is a cross section of another portion of the fifteenth example embodiment.

[0059] [ Figure 25A ] Figure 25B is a plan view of a pixel configuration according to a sixteenth example embodiment of the present disclosure.

[0060] [ Figure 25C ] Figure 25B is a cross section of a portion of the sixteenth example embodiment.

[0061] [ Figure 25C ] Figure 26A is a cross section of another portion of the sixteenth example embodiment.

[0062] [ Figure 26B ] Figure 26A is a plan view of a pixel configuration of a related art.

[0063] [ Figure 26A ] Figure 26B is a cross section of a portion of a related art configuration.

[0064] [ Figure 27A ] Figure 27B is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0065] [ Figure 27A ] Figure 27C is a diagram showing an example of mounting positions of an outside-vehicle information detecting unit and an imaging unit. DETAILED DESCRIPTION

[0066] Hereinafter, embodiments of the present disclosure will be described in detail based on the drawings. Further, in the following embodiments, the same parts are denoted by the same reference numerals, and thus a repeated explanation will be omitted.

[0067] A typical dynamic vision sensor (DVS) adopts a so-called event-driven driving method in which the presence or absence of an address event trigger is detected for each unit pixel, and a pixel signal is read out from a unit pixel in which the address event trigger is detected.

[0068] Further, the unit pixel in this specification indicates the minimum unit of a pixel including one photoelectric conversion element (also referred to as a "light receiving element"), and can correspond to, for example, each dot in image data read out from an image sensor. In addition, the address event indicates an event that occurs for each address respectively assigned to a plurality of unit pixels arranged in a two-dimensional lattice shape. The event detection sensor responds asynchronously to intensity changes. The intensity change is related to a change in photo current, and if such a change exceeds a constant threshold, it will be detected as an event.

[0069] Figure 27A is a block diagram illustrating a schematic configuration example of an imaging device according to at least some embodiments of the present disclosure. As shown, for example, the imaging device 100 includes an imaging lens 110, a solid-state imaging device 200, a recording unit 120, and a control unit 130. The imaging device 100 can be provided, for example, as a camera or a part of a camera mounted in an industrial robot, a vehicle-mounted camera, or the like. Figure 12A

[0070] The imaging lens 110 can include an optical system that guides (for example, converges) incident light and images an image of the incident light on a light-receiving surface of the solid-state imaging device 200. The light-receiving surface is a surface in the solid-state imaging device 200 on which a photoelectric conversion element is arranged. The solid-state imaging device 200 photoelectrically converts the incident light and generates image data. In addition, the solid-state imaging device 200 can perform predetermined signal processing such as noise removal and white balance adjustment on the generated image data. The result of the signal processing and a detection signal indicating the presence or absence of an address event trigger are output to the recording unit 120 through a signal line 209. Further, a method of generating the detection signal indicating the presence or absence of an address event trigger will be described later.

[0071] The recording unit 120 is constituted by, for example, a flash memory, a dynamic random access memory (DRAM), or a static random access memory (SRAM), or the like, and records data input from the solid-state imaging device 200.

[0072] ​The control unit 130 is configured of, for example, a central processing unit (CPU) or the like, and outputs various instructions through a signal line 139 to control each unit such as the solid-state imaging device 200 in the imaging device 100.

[0073] Next, a configuration example of the solid-state imaging device 200 will be described in detail with reference to the drawings.

[0074] Figure 27B is a diagram illustrating a layer stack structure example of a solid-state imaging device according to at least some embodiments of the present disclosure. As Figure 28A indicated, the solid-state imaging device 200 can have a structure in which the light-receiving chip 201 and the logic chip 202 are stacked one on top of the other. In the joining of the light-receiving chip 201 and the logic chip 202, for example, a so-called direct joining in which the joining surfaces of the chips are planarized and the chips are stacked together with intermolecular forces can be used. However, this is not limited thereto, and for example, a so-called Cu-Cu joining in which copper (Cu) electrode pads formed on the joining surfaces are bonded and bump joining or the like can be used.

[0075] In addition, the light-receiving chip 201 and the logic chip 202 are electrically connected to each other, for example, through a connection portion such as a through silicon via (TSV) that penetrates the semiconductor substrate. In the connection using the TSV, for example, the following methods or the like can be employed: a so-called double TSV method in which two TSVs including a TSV formed in the light-receiving chip 201 and a TSV formed from the light-receiving chip 201 to the logic chip 202 are connected to each other on the outer surfaces of the chips; and a so-called shared TSV method in which the light-receiving chip 201 and the logic chip 202 are connected through a TSV that penetrates both chips.

[0076] However, if the Cu-Cu joining or the bump joining is used in the joining of the light-receiving chip 201 and the logic chip 202, both the light-receiving chip 201 and the logic chip 202 are electrically connected to each other through Cu-Cu joints or bump joints.

[0077] Figure 28B is a block diagram illustrating a functional configuration example of a solid-state imaging device according to at least some embodiments of the present disclosure. As Figure 28C indicated, the solid-state imaging device 200 includes a drive circuit 211, a signal processing unit 212, an arbiter 213, a column ADC 220, and a pixel array unit 300.

[0078] A plurality of unit pixels 310 is arranged in a two-dimensional lattice in the pixel array unit 300. The unit pixel 310 will be described later in detail. For example, each unit pixel 310 includes a photoelectric conversion element such as a photodiode and a circuit (hereinafter referred to as a pixel circuit or a pixel imaging signal generation readout circuit) that generates a pixel signal having a voltage value corresponding to the amount of charge generated in the photoelectric conversion element. Here, the pixel circuit can be shared by a plurality of photoelectric conversion elements. In this case, the unit pixel 310 includes one photoelectric conversion element and the shared pixel circuit, respectively.

[0079] A plurality of unit pixels 310 is arranged in a two-dimensional lattice in the pixel array unit 300. The plurality of unit pixels 310 can be grouped into a plurality of pixel blocks each including a predetermined number of unit pixels. Hereinafter, a set of unit pixels arranged in a horizontal direction is referred to as a "row", and a set of unit pixels arranged in a direction orthogonal to the row is referred to as a "column".

[0080] Each unit pixel 310 generates a charge corresponding to the amount of light received at each photoelectric conversion element. In addition, the unit pixel 310 is capable of being operated individually or in combination with one or more other unit pixels 310 in the same group to detect the presence or absence of an address event trigger based on whether the value of a current (hereinafter referred to as a photocurrent) generated from the charge generated in the photoelectric conversion element or the amount of change thereof exceeds a predetermined threshold. In addition, when the address event is triggered, a request for reading out a pixel signal having a voltage value corresponding to the amount of light reception of the photoelectric conversion element is output to the arbitrator 213.

[0081] The drive circuit 211 drives each unit pixel 310 and enables each unit pixel 310 to output a pixel signal to the column ADC 220.

[0082] The arbitrator 213 arbitrates the requests from the unit pixels and transmits a predetermined response to the unit pixel 310 that made the request based on the result of the arbitration. The unit pixel 310 that received the response provides a detection signal (hereinafter simply referred to as an "address event detection signal") indicating the presence or absence of an address event trigger to the drive circuit 211 and the signal processing unit 212.

[0083] The column ADC 220 converts an analog pixel signal from a column into a digital signal for each unit pixel 310 column. In addition, the column ADC 220 provides the digital signal generated by the conversion to the signal processing unit 212.

[0084] The signal processing unit 212 performs predetermined signal processing such as correlated double sampling (CDS) processing (noise removal) and white balance adjustment on the digital signal transmitted from the column ADC 220. In addition, the signal processing unit 212 supplies the signal processing result and the address event detection signal to the recording unit 120 through the signal line 209.

[0085] The unit pixels 310 within the pixel array unit 300 can be arranged in pixel groups 314. In the illustrated configuration, for example, the pixel array unit 300 is composed of pixel groups 314 including a set of unit pixels 310 that receive wavelength components necessary for reconstructing a color. For example, in the case of reconstructing a color based on RGB three primary colors, in the pixel array unit 300, unit pixels 310 that receive red (R) light, unit pixels 310 that receive green (G) light, and unit pixels 310 that receive blue (B) light are arranged in the group 314a according to a predetermined color filter array. Figure 12A

[0086] Examples of the color filter array configuration include various arrays such as a 2x2 pixel Bayer array, a 3x3 pixel color filter array (hereinafter also referred to as an "X-Trans (registered trademark) type array") employed in an X-Trans (registered trademark) CMOS sensor, a 4x4 pixel Quad Bayer array (also referred to as a "Quadra array"), and a 4x4 pixel color filter that combines a white color RGB color filter to a Bayer array (hereinafter also referred to as a "white RGB array"). Here, in the following description, a case in which a Bayer array is employed as the color filter array will be exemplified.

[0087] Figure 27A is a schematic diagram illustrating an array example of the unit pixel 310 in a case in which the pixel group 314 employing an arrangement of the unit pixel 310 and its associated color filter is employed in the color filter array for forming a plurality of Bayer arrays 310A. As illustrated in Figure 28A As illustrated, in a case in which a Bayer array is employed as the color filter array configuration, in the pixel array unit 300, a basic pattern 310A including a total of four unit pixels of 2x2 pixels is repeatedly arranged in the column direction and the row direction. For example, the basic pattern 310A is composed of a unit pixel 310R including a red (R) filter, a unit pixel 310Gr including a green (Gr) filter, a unit pixel 310Gb including a green (Gb) filter, and a unit pixel 310B including a blue (B) filter.

[0088] Next, a configuration example of the unit pixel 310 will be described. Figure 28B is a circuit diagram illustrating a schematic configuration example of the unit pixel 310 according to at least some embodiments of the present disclosure. As illustrated in​​ As shown, the unit pixel 310 includes, for example, a pixel imaging signal generation unit (or readout circuit) 320, a light-receiving unit 330, and an address event detection unit (or readout circuit) 400. According to at least one example embodiment, the readout circuit 400 is configured to control the readout circuit 320 based on charges generated by one or more photoelectric conversion elements (or photoelectric conversion regions) 333. Each photoelectric conversion element 333 can be associated with a unit pixel transistor 334. Further, ​ The logic circuit 210 in the image pickup device 200 is, for example, composed of ​ The logic circuit in the image pickup device 200 is, for example, composed of a drive circuit 211, a signal processing unit 212, and an arbiter 213.

[0089] The light-receiving unit 330 includes, for example, a transfer transistor (first transistor) 331, an overflow gate (OFG) transistor (fifth transistor) 332, and a photoelectric conversion element 333. A transfer signal TRG transferred from the drive circuit 211 is supplied to the gate of the pixel group transfer transistor 331 of the light-receiving unit 330, and a control signal OFG transferred from the drive circuit 211 is supplied to the gate of the OFG transistor 332. The output through the pixel group transfer transistor 331 of the light-receiving unit 330 is connected to the pixel imaging signal generation unit 320, and the output through the OFG transistor 332 is connected to the address event detection unit 400.

[0090] The pixel imaging signal generation unit 320 includes, for example, a reset transistor (second transistor) 321, an amplification transistor (third transistor) 322, a selection transistor (fourth transistor) 323, and a floating diffusion layer (FD) 324.

[0091] The pixel group transfer transistor 331 and the OFG transistor 332 of the light-receiving unit 330 are configured by using, for example, an N-type MOS (metal-oxide-semiconductor) transistor (hereinafter referred to as an “NMOS transistor”). Similarly, the reset transistor 321, the amplification transistor 322, and the selection transistor 323 of the pixel imaging signal generation unit 320 are configured by using, for example, an NMOS transistor, respectively.

[0092] The address event detection unit 400 includes, for example, a current-voltage conversion unit 410 and a subtracter 430. However, the address event detection unit 400 is also provided with a buffer, a quantizer, and a transfer unit. In the following description, the address event detection unit 400 will be described in detail by using, for example, an ADIBO (ADvanced Image Based on Object) model. ​ The address event detection unit 400 includes, for example, a current-voltage conversion unit 410 and a subtracter 430. However, the address event detection unit 400 is also provided with a buffer, a quantizer, and a transfer unit. In the following description, the address event detection unit 400 will be described in detail by using, for example, an ADIBO (ADvanced Image Based on Object) model.

[0093] In the illustrated configuration, the photoelectric conversion element 333 of the light-receiving unit 330 photoelectrically converts incident light and generates electric charges. The pixel group transfer transistor 331 transfers the electric charges generated in the photoelectric conversion element 333 to the floating diffusion layer 324 in accordance with a transfer signal TRG. The OFG transistor 332 supplies an electric signal (photo current) based on the electric charges generated in the photoelectric conversion element 333 to the address event detection unit 400 in accordance with a control signal OFG.

[0094] The floating diffusion layer 324 accumulates the electric charges transferred from the photoelectric conversion element 333 through the pixel group transfer transistor 331. The reset transistor 321 discharges (initializes) the electric charges accumulated in the floating diffusion layer 324 in accordance with a reset signal transferred from the drive circuit 211. The amplification transistor 322 enables a pixel signal having a voltage value corresponding to the amount of electric charges of the electric charges accumulated in the floating diffusion layer 324 to appear in the vertical signal line VSL. The selection transistor 323 switches the connection between the amplification transistor 322 and the vertical signal line VSL in accordance with a selection signal SEL transferred from the drive circuit 211. Further, the analog pixel signal appearing in the vertical signal line VSL is read out by the column ADC 220 and converted into a digital pixel signal.

[0095] When the control unit 130 gives an instruction to start address event detection, the drive circuit 211 in the logic circuit 210 outputs a control signal OFG for setting the OFG transistor 332 of the light-receiving unit 330 in the pixel array unit 300 to an on state. With this arrangement, the photo current generated in the photoelectric conversion element 333 of the light-receiving unit 330 is supplied to the address event detection unit 400 of each unit pixel 310 through the OFG transistor 332.

[0096] When an address event trigger is detected based on the photo current from the light-receiving unit 330, the address event detection unit 400 of each unit pixel 310 outputs a request to the arbitrator 213. In response to this, the arbitrator 213 arbitrates the requests sent from each unit pixel 310 and sends a predetermined response to the unit pixel 310 that made the request based on the arbitration result. The unit pixel 310 that received the response supplies a detection signal (hereinafter referred to as an “address event detection signal”) indicating the presence or absence of an address event trigger to the drive circuit 211 and the signal processing unit 212 in the logic circuit 210.

[0097] The drive circuit 211 sets the OFG transistor 332 in the unit pixel 310 that is the supply source of the address event detection signal to an off state. With this arrangement, the supply of the photo current from the light-receiving unit 330 in the unit pixel 310 to the address event detection unit 400 stops.

[0098] Next, the drive circuit 211 sets the pixel group transfer transistor 331 in the light-receiving unit 330 of the unit pixel 310 to an on state by the transfer signal TRG. With this arrangement, the electric charge generated in the photoelectric conversion element 333 of the light-receiving unit 330 is transferred to the floating diffusion layer 324 through the pixel group transfer transistor 331. In addition, a pixel signal having a voltage value corresponding to the amount of electric charge accumulated in the floating diffusion layer 324 appears in the vertical signal line VSL connected to the selection transistor 323 of the pixel imaging signal generation unit 320.

[0099] As described above, in the solid-state imaging device 200, the unit pixel 310 triggered from detection of an address event outputs a pixel signal SIG to the column ADC 220.

[0100] Further, for example, the two logarithmic (LG) transistors (sixth and seventh transistors) 411 and 414 and the two amplification transistors (eighth and ninth transistors) 412 and 413 in the current-voltage conversion unit 410 of the address event detection unit 400, the pixel imaging signal generation unit 320, and the light-receiving unit 330 are provided in, for example, the light-receiving chip 201, while the other components can be provided in, for example, the logic chip 202 bonded with the light-receiving chip 201 by Cu-Cu bonding. Therefore, in the following description, in the unit pixel 310, the configuration provided in the light-receiving chip 201 is referred to as an “upper layer circuit”. ​

[0101] ​ is a block diagram illustrating a schematic configuration example of an address event detection unit according to at least some embodiments of the present disclosure. As ​ indicated, the address event detection unit 400 includes a current-voltage conversion unit 410, a buffer 420, a subtracter 430, a quantizer 440, and a transfer unit 450.

[0102] The current-voltage conversion unit 410 converts the photocurrent from the light-receiving unit 330 into a voltage signal of a logarithm thereof, and supplies the voltage signal generated by the conversion to the buffer 420.

[0103] The buffer 420 corrects the voltage signal transferred from the current-voltage conversion unit 410, and outputs the corrected voltage signal to the subtracter 430.

[0104] The subtracter 430 lowers the voltage level of the voltage signal transferred from the buffer 420 in accordance with the row drive signal transferred from the drive circuit 211, and supplies the lowered voltage signal to the quantizer 440.

[0105] ​The quantizer 440 quantizes the voltage signal transmitted from the subtracter 430 into a digital signal, and outputs the digital signal generated by the quantization as a detection signal to the transmission unit 450.

[0106] The transmission unit 450 transmits the detection signal transmitted from the quantizer 440 to the signal processing unit 212 and the like. For example, when an address event trigger is detected, the transmission unit 450 provides the transmission request of the address event detection signal from the transmission unit 450 to the driving circuit 211 and the signal processing unit 212 to the arbiter 213. In addition, when a response with respect to the request is received from the arbiter 213, the transmission unit 450 provides the detection signal to the driving circuit 211 and the signal processing unit 212.

[0107] For example, ​ The current-voltage conversion unit 410 in the illustrated configuration includes, for example, two LG transistors 411 and 414, two amplification transistors 412 and 413, and a constant current circuit 415. ​ The two LG transistors 411 and 414, the two amplification transistors 412 and 413, and the constant current circuit 415 are connected as illustrated.

[0108] For example, the source of the LG transistor 411 and the gate of the amplification transistor 413 are connected to the drain of the OFG transistor 332 of the light receiving unit 330. In addition, for example, the drain of the LG transistor 411 is connected to the source of the LG transistor 414 and the gate of the amplification transistor 412. For example, the drain of the LG transistor 414 is connected to the power supply terminal VDD.

[0109] In addition, for example, the source of the amplification transistor 413 is grounded, and the drain thereof is connected to the gate of the LG transistor 411 and the source of the amplification transistor 412. For example, the drain of the amplification transistor 412 is connected to the power supply terminal VDD through the constant current circuit 415. For example, the constant current circuit 415 is constituted by a load MOS transistor such as a p-type MOS transistor.

[0110] In this connection relationship, a ring source follower circuit is constructed. By this arrangement, the photo current from the light receiving unit 330 is converted into a voltage signal having a logarithmic value corresponding to the charge amount thereof. Furthermore, the LG transistors 411 and 414 and the amplification transistors 412 and 413 can be constituted by, for example, NMOS transistors, respectively.

[0111] ​ is a circuit diagram illustrating a schematic configuration example of a subtracter and a quantizer according to at least some embodiments of the present disclosure. As ​ As illustrated, the subtracter 430 includes capacitors 431 and 433, an inverter 432, and a switch 434. In addition, the quantizer 440 includes a comparator 441.

[0112] One end of the capacitor 431 is connected to the output terminal of the buffer 420, and the other end is connected to the input terminal of the inverter 432. The capacitor 433 is connected in parallel to the inverter 432. The switch 434 opens or closes a path connecting both ends of the capacitor 433, in accordance with a row drive signal.

[0113] The inverter 432 inverts the voltage signal input through the capacitor 431. The inverter 432 outputs the inverted signal to the non-inverting input terminal (+) of the comparator 441.

[0114] When the switch 434 is closed, the voltage signal Vinit is input to the buffer 420 side of the capacitor 431. In addition, the opposite side becomes a virtual ground terminal. For convenience, the potential of the virtual ground terminal is set to zero. At this time, when the capacitance of the capacitor 431 is set to C1, the electric potential Qinit accumulated in the capacitor 431 is represented by the following expression (1). On the other hand, since both ends of the capacitor 433 are short-circuited, the electric charge accumulated therein becomes zero.

[0115] Qinit = C1 x Vinit (1)

[0116] Next, when considering a case where the switch 434 is opened and the voltage of the capacitor 431 on the buffer 420 side changes and reaches Vafter, the electric charge Qafter accumulated in the capacitor 431 is represented by the following expression (2).

[0117] Qafter = C1 x Vafter (2)

[0118] On the other hand, when the output voltage is set to Vout, the electric charge Q2 accumulated in the capacitor 433 is represented by the following expression (3).

[0119] Q2 = -C2 x Vout (3)

[0120] At this time, since the total amount of electric charge of the capacitors 431 and 433 does not change, the following expression (4) holds.

[0121] Qinit = Qafter + Q2 (4)

[0122] When expression (1) to expression (3) are substituted into expression (4), the following expression (5) is obtained.

[0123] Vout = -(C1 / C2) x (Vafter - Vinit) (5)

[0124] Expression (5) represents a subtraction operation of the voltage signals, and the gain of the subtraction result becomes C1 / C2. Generally, it is desirable to maximize (or alternatively, increase) the gain, and thus it is preferable to design so that C1 becomes large and C2 becomes small. On the other hand, when C2 is too small, kTC noise increases, and thus there is a concern that the noise characteristic deteriorates. Therefore, the reduction of the C2 capacitance is limited within a range that can allow noise. In addition, since the address event detection unit 400 including the subtracter 430 is mounted for each unit pixel 310, there is an area restriction on the capacitances C1 and C2. The values of the capacitances C1 and C2 are determined in consideration of the restriction.

[0125] The comparator 441 compares the voltage signal transmitted from the subtracter 430 with a predetermined threshold voltage Vth applied to the inverting input terminal (-). The comparator 441 outputs a signal representing the comparison result as a detection signal to the transmission unit 450.

[0126] In addition, when the conversion gain of the current-voltage conversion unit 410 is set to CGlog and the gain of the buffer 420 is set to "1", the gain A of the address event detection unit 400 as a whole is represented by the following expression (6).

[0127] [Mathematical Expression 1]

[0128]

[0129] In expression (6), i photo _n represents the photoelectric current of the nth unit pixel 310, and the unit is, for example, ampere (A). N represents the number of unit pixels 310 in the pixel block, and is "1" in this embodiment.

[0130] ​ is a block diagram showing a schematic configuration example of a column ADC according to at least some embodiments of the present disclosure. The column ADC 220 includes a plurality of ADCs 230 provided for each unit pixel 310 column.

[0131] Each ADC 230 converts an analog pixel signal appearing in the vertical signal line VSL into a digital signal. For example, the pixel signal is converted into a digital signal having a bit length larger than that of the detection signal. For example, when the detection signal is set to two bits, the pixel signal is converted into a digital signal of three or more bits (16 bits or the like). The ADC 230 supplies the generated digital signal to the signal processing unit 212.

[0132] Next, the operation of the solid-state imaging device 200 according to at least some embodiments of the present disclosure will be explained in detail with reference to the drawings.

[0133] First, an example of the operation of the solid-state imaging device 200 will be described using a timing chart. ​ is a timing chart showing an example of the operation of the solid-state imaging device according to the first embodiment.

[0134] As shown in ​ at time T0, when the control unit 130 gives an instruction to start address event detection, the drive circuit 211 raises the control signal OFG applied to the gates of the OFG transistors 332 of all the light-receiving units 330 in the pixel array unit 300 to the high level. With this arrangement, the plurality of OFG transistors 332 of all the light-receiving units 330 enter the on state, and the photoelectric current based on the electric charge generated in the photoelectric conversion element 333 of each light-receiving unit 330 is supplied from the light-receiving unit 330 to the plurality of address event detection units 400, respectively.

[0135] In addition, the transfer signal TRG applied to the gates of the pixel group transfer transistors 331 in each light-receiving unit 330 all remain at the low level during the period in which the control signal OFG is at the high level. Therefore, the plurality of transfer transistors 331 in all the light-receiving units 330 are in the off state during this period.

[0136] Next, it will be assumed that the address event detection unit 400 of an arbitrary unit pixel 310 detects an address event trigger during the period in which the control signal OFG is at the high level. In this case, the address event detection unit 400 that detected the address event trigger sends a request to the arbiter 213. In response to this, the arbiter 213 arbitrates the request, and returns a response to the request to the address event detection unit 400 that sent the request.

[0137] For example, during the period from time T1 to time T2, the address event detection unit 400 that received the response raises the detection signal input to the drive circuit 211 and the signal processing unit 212 to the high level. In addition, in this description, it will be assumed that the detection signal is a one-bit signal.

[0138] At subsequent time T2, the drive circuit 211 that input the high-level detection signal from the address event detection unit 400 at time T1 lowers all the control signals OFG to the low level. With this arrangement, the supply of the photoelectric current from all the light-receiving units 330 of the pixel array unit 300 to the address event detection units 400 stops.

[0139] In addition, at time T2, the drive circuit 211 raises the selection signal SEL applied to the gate of the selection transistor 323 in the pixel imaging signal generation unit 320 of the unit pixel 310 that detects the address event trigger (hereinafter referred to as "readout target unit pixel") to the high level, and, for a constant pulse period, the drive circuit 211 raises the reset signal RST applied to the gate of the reset transistor 321 of the same pixel imaging signal generation unit 320 to the high level, thereby discharging (initializing) the charge accumulated in the floating diffusion layer 324 of the pixel imaging signal generation unit 320. In this way, the voltage appearing in the vertical signal line VSL in a state where the floating diffusion layer 324 is initialized is read out as a reset level pixel signal (hereinafter simply referred to as "reset level") by the ADC 230 connected to the vertical signal line VSL in the column ADC 220, and is converted into a digital signal.

[0140] Next, at time T3 after the reset level is read out, the drive circuit 211 applies the transfer signal TRG of the constant pulse period to the gate of the pixel group transfer transistor 331 of the light-receiving unit 330 in the readout target unit pixel 310. With this arrangement, the charge generated in the photoelectric conversion element 333 of the light-receiving unit 330 is transferred to the floating diffusion layer 324 in the pixel imaging signal generation unit 320, and a voltage corresponding to the charge accumulated in the floating diffusion layer 324 appears in the vertical signal line VSL. In this way, the voltage appearing in the vertical signal line VSL is read out as a signal level pixel signal (hereinafter simply referred to as "signal level") of the light-receiving unit 330 by the ADC 230 connected to the vertical signal line VSL in the column ADC 220, and is converted into a digital value.

[0141] The signal processing unit 212 performs CDS processing in which the difference between the reset level and the signal level read out as described above is obtained as a net pixel signal corresponding to the amount of light reception of the photoelectric conversion element 333.

[0142] Next, at time T4, the drive circuit 211 lowers the selection signal SEL applied to the gate of the selection transistor 323 in the pixel imaging signal generation unit 320 of the readout target unit pixel 310 to the low level, and raises the control signal OFG applied to the gates of the OFG transistors 332 of all the light-receiving units 330 in the pixel array unit 300 to the high level. With this arrangement, the address event trigger detection of all the light-receiving units 330 in the pixel array unit 300 will restart.

[0143] Next, an example of the operation of the solid-state imaging device 200 will be described using a flowchart. ​is a flowchart showing an example of operation of a solid-state imaging device according to at least some embodiments of the present disclosure. For example, the operation is initiated when a predetermined application program for detecting an address event is executed.

[0144] As shown in ​ In this operation, first, each unit pixel 310 in the pixel array unit 300 detects the presence or absence of an address event trigger (step S901). In addition, the drive circuit 211 determines whether an address event trigger is detected in any one of the unit pixels 310 (step S902).

[0145] In a case where an address event trigger is not detected (NO in step S902), the operation proceeds to step S904. On the other hand, in a case where an address event trigger is detected (YES in step S902), the drive circuit 211 reads out the pixel signal of the unit pixel 310 in which the address event trigger is detected (step S903), and then proceeds to step S904.

[0146] In step S904, it is determined whether to terminate the operation. In a case where the operation is not terminated (NO in step S904), the operation returns to step S901, and the subsequent operation is repeated. On the other hand, in a case where the operation is terminated (YES in step S904), the operation is terminated.

[0147] ​ is a circuit diagram showing an example of the schematic configuration of a pixel group circuit 1100 of a group 314 of unit pixels 310 according to at least some embodiments of the present disclosure. More particularly, ​ A pixel group circuit 1100 is shown in which the opto-electric conversion units 333 of all the unit pixels 310 included in the group 314 of unit pixels 310 share elements of the circuit 1100. In this example, the unit pixels 310 are part of a pixel group 314 including a basic Bayer array pattern 310A in which a first unit pixel 310R is associated with a red color filter, a second unit pixel 310Gb is associated with a green color filter, a third unit pixel 310Gr is associated with a green color filter, and a fourth unit pixel 310B is associated with a blue color filter. Thus, this example includes a group 314 of four unit pixels 310. However, other arrangements and configurations can also be employed.

[0148] The pixel group circuit 1100 generally includes a light receiving unit 330 having a plurality of photoelectric conversion units 333. The photoelectric conversion units 333 can for example but not limited to include photodiodes. While other configurations can also be employed, in this example, each unit pixel 310 includes one photoelectric conversion unit 333. Further, in this circuit 1100 in which multiple unit pixels 310 share at least some elements, the light receiving unit 330 includes a plurality of unit pixel transistors 334, and the photoelectric conversion unit 333 of each unit pixel 310 is selectively connected to the pixel group transfer transistor 331 and the pixel group overflow gate transistor 332 through the unit pixel transfer transistor 334 of each unit pixel. The pixel group circuit 1100 also includes a pixel imaging signal generation readout circuit 320 and an address event detection readout circuit 400. The pixel imaging signal generation readout circuit 320 and the address event detection readout circuit 400 can be configured in the same or similar manner as the readout circuits 320 and 400 of ​ The address event detection readout circuit 400 can also be formed of two transistors, depending on the required sensitivity and pixel size.

[0149] As noted above, each photoelectric conversion unit 333 is selectively connected to other circuit elements through the unit pixel transfer transistor 334. Further, one or more photoelectric conversion units 333 can be simultaneously connected to other circuit elements through operation of the unit pixel transfer transistors 334. For example, in an imaging mode, the unit pixel transfer transistors 334 associated with the selected photoelectric conversion unit 333 and the pixel group transfer transistor 331 are in an on state so as to operatively connect the selected photoelectric conversion unit 333 to the pixel imaging signal generation readout circuit 320. In an event detection or dynamic vision sensor (DVS) mode, the unit pixel transfer transistors 334 associated with the selected photoelectric conversion unit 333 and the pixel group overflow gate transistor 332 are in an on state so as to operatively connect the selected photoelectric conversion unit 333 to the address event detection readout circuit 400. Under typical operating conditions, in the imaging mode, a single photoelectric conversion unit 333 can be operated at any time to provide a signal to the pixel imaging signal generation readout circuit 320, while in the DVS mode, one, some, or all of the photoelectric conversion units 333 can be operated at any time to provide a signal to the address event detection readout circuit 400.

[0150] The connection between any one photoelectric conversion unit 333 and the pixel imaging signal generation readout circuit 320 is established by operation of the unit pixel transfer transistors 334a-d and the pixel group transfer transistor 331 to enable transfer of charge from the selected photoelectric conversion unit 333a-d to the FD 324 of the pixel imaging signal generation readout circuit 320. Then, for example as in connection with the pixel imaging signal generation readout circuit 320 of FIG. 3, the charge is transferred to the FD 324, and the voltage on the FD 324 is converted to a pixel imaging signal by the pixel imaging signal generation readout circuit 320. ​As explained, charge can be read out from the FD 324. While in a typical imaging operation charge from a single photoelectric conversion cell 333 is transferred to the pixel imaging signal generation readout circuit 320, other modes can also be employed in which signals from multiple photoelectric conversion cells 333 corresponding to multiple unit pixels 310 are transferred to the pixel imaging signal generation readout circuit 320. As will be appreciated by those skilled in the art in light of this disclosure, the pixel group overflow gate transistor 332 remains off during imaging operations. As will also be appreciated by those skilled in the art in light of this disclosure, for the pixel group 314, operation of the pixel image signal generation circuit 320 can be triggered by event detection by the address event detection readout circuit 400.

[0151] Connection between any one or more photoelectric conversion cells 333 and the address event detection readout circuit 400 is established by operation of the unit pixel transfer transistor 334 and the pixel group overflow gate transistor 332 of the selected photoelectric conversion cell 333 to enable transfer of charge from the selected photoelectric conversion cell 333 to the address event detection readout circuit 400. In accordance with at least some embodiments of this disclosure, when operating the pixel group circuit 1100 in the address event detection mode, all of the unit pixel transfer transistors 334 and the pixel group overflow gate transistors 332 are operated to simultaneously connect all of the photoelectric conversion cells 333 within the pixel group 314 to the address event detection readout circuit 400 for that pixel group 314. As will be appreciated by those skilled in the art in light of this disclosure, the pixel group transfer transistor 331 remains off during event detection operations.

[0152] Thus, ​ The circuit configuration of the pixel group circuit 1100 is an example of an arrangement in which multiple unit pixels 310 of the image pickup device 100 are capable of performing both event detection and imaging operations, and the photoelectric conversion cell 333 of each unit pixel 310 shares elements of the event detection circuit 400 and the pixel imaging signal generation readout circuit 320.

[0153] ​ is a plan view of the pixel array unit 300, ​ is a plan view of the pixel array unit 300, ​The cross-section taken by line A-A' shows the configuration 1204 of pixel group 314 according to a first exemplary embodiment of the present disclosure. In this example, groups 314 of unit pixels 310 are defined, and groups 314 of unit pixels 310 are separated from each other by full-thickness dielectric trench isolation or simple full-thickness trench isolation (RFTI) structure 1208. Within each pixel group 314, unit pixels 310 are separated from each other by inter-group separation structure 1210 in the form of deep trench isolation (RDTI) structure 1212. The inter-group separation structure 1210 within pixel group 314 can include a horizontal portion 1210a extending between unit pixels 310 in adjacent rows and a vertical portion 1210b extending between unit pixels 310 in adjacent columns. More specifically, pixel configuration 1204 is characterized by an RDTI structure 1212 along the entire boundary between adjacent unit pixels 310 within each pixel group 314, wherein a first RDTI structure 1212a extends between adjacent rows of unit pixels 310 within each pixel group 314, and a second RDTI structure 1212b extends between adjacent columns of unit pixels 310 within each pixel group 314. Although this example shows four pixel groups 314 of a 2×2 array (where each pixel group 314 includes four unit pixels 310 of a 2×2 subarray or group array pattern), other configurations may also be employed.

[0154] According to embodiments of this disclosure, such as ​ As shown, the RFTI structure 1208 extends through the entire thickness of the substrate 1216, in which a photodiode 333 of a unit pixel 314 is formed. That is, the RFTI structure 1208 extends from at least a first light-incident surface 1220 of the substrate 1216 to a second non-light-incident surface 1224. The RDTI structure 1212 extends from a first end 1228 at the first surface 1220 or above the first surface 1220 to a second end 1232 formed toward the second surface 1224 of the substrate 1216. Specifically, since the distance the RDTI structure 1212 extends is less than the thickness of the substrate 1216, the RDTI structure 1212 does not reach the second surface 1224. Therefore, material of the substrate 1216 remains between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. Both the RFTI structure 1208 and the RDTI structure 1212 can be formed with a dielectric core 1213. The dielectric core 1213 can be formed, for example, but not limited to, silicon dioxide.

[0155] Similarly, ​As shown, each unit pixel 310 may include an insulating layer or planarization layer 1236 formed on the first surface 1220 of the substrate 1216. Additionally, a color filter 1240 may be provided for each unit pixel 310. In this example, a green color filter 1240Gb is provided as part of the first of the illustrated unit pixels 310Gb, and a blue color filter 1240B is provided as part of the second of the illustrated unit pixels 310B. Each unit pixel 310 may also be provided with an on-chip lens 1244. According to another embodiment, a light-shielding element or structure 1248 may be formed on or above the RFTI 1208 and / or RDTI 1212 structures on or above the first surface 1220 of the substrate 1216.

[0156] and ​ and ​ The circuit elements associated with each pixel group 314 in the example pixel group construction 1204 can be connected with ​ The circuit elements shown in the pixel group circuit 1100 are the same or similar. According to embodiments of this disclosure, one or more circuit elements, such as transistors, conductors, or other elements of the pixel group circuit 1100, are at least partially formed or located between the second end 1232 of one or more RDTI structures 1212 and the second surface 1224 of the substrate 1216 within the pixel group 314 region. For example, in ​ and ​ In one example, at least a portion of the logarithmic transistor 414 of the address event detection readout circuit 400 for the pixel group circuit 1100 can be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. As another example, at least a portion of the drain / source regions of the amplifying transistors 412 and 413 can be formed in the region between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. As yet another example, at least a portion of the node 1236 connecting the unit pixel transistor 334 to the pixel group transfer transistor 331 and the pixel group overflow gate transistor 332 can be formed between the second ends 1232 of the two intersecting RDTI structures 1212 and the second surface 1224 of the substrate 1216.

[0157] Accordingly, embodiments of the present disclosure are able to provide suitable separation between pixel groups 314 using RFTI structures 1208 and between unit pixels 310 within pixel groups 314 using RDTI structures 1212, while providing a more favorable ratio of total pixel group 314 area to area of the photoelectric conversion unit 333 of the unit pixels 310 within the pixel group 314 by facilitating sharing of pixel group circuit 1100 elements and by forming at least a portion of the elements of the pixel group circuit 1100 in the area between the end of the RDTI structure 1212 and the surface of the substrate 1216. Further, by increasing the area of the photoelectric conversion unit 333 relative to the total pixel group 314 area, performance of the unit pixels 310 within the pixel group 314 can be improved, for example, by improving the saturated signal and sensitivity of the unit pixels 310 in the group 314, as compared to alternative constructions without the RDTI 1212 or other partial thickness structure 1208.

[0158] The advantages of embodiments of the present disclosure can be further understood by comparing the construction 1204 of the pixel group 314 according to embodiments of the present disclosure to the construction 2904 of a background pixel group shown in FIG. 29. ​ and ​ In this background example, RFTI structures 2908 are used to define boundaries between unit pixels 2910 within the pixel group 2914 and between pixel groups 2914. In particular, in this example background construction, sharing of transistors or other circuit elements between unit pixels 2910 is not provided. Further, it is not possible to include circuit elements in the area also occupied by the RFTI structures 2908. As a result, in this prior art example, the circuit element portion 2901 is large relative to the area of the photoelectric conversion unit portion 2933 of the unit pixels 2910. In other words, the area of the photoelectric conversion unit portion 2933 of this prior art example is a relatively small proportion of the total unit pixel 310 area.

[0159] ​ is a plan view of a construction 1304 of a pixel group 314 according to a second exemplary embodiment of the present disclosure, ​ is a cross-section of a portion of the second exemplary embodiment taken along line A-A’ of ​ is a cross-section of a portion of the second exemplary embodiment taken along line B-B’ of ​ is a cross-section of a portion of the second exemplary embodiment taken along line C-C’ of ​cross-section of another portion of the second exemplary embodiment taken along line B-B'. In this example, groups 314 of unit pixels 310 are defined and the groups 314 of unit pixels 310 are separated from one another by RFTI structures 1208. In addition, inter-pixel group separation structures 1210 including RFTI 1208 and RDTI 1212 structures are provided. More particularly, the RFTI structures 1208 form part of the boundaries between unit pixels 310 within different columns of unit pixels 310 in the same pixel group 314, and the RDTI structures 1212 form the remainder of the boundaries between unit pixels 310 within different columns of unit pixels 310 in the same pixel group 314. The RDTI structures 1212 form boundaries between unit pixels 310 within different rows of unit pixels 310 in the same pixel group 314. Although four pixel groups 314 in a 2x2 array are shown in this example (where each pixel group 314 includes four unit pixels 310 in a 2x2 sub-array or group array pattern), other configurations can also be employed.

[0160] As shown in ​ and ​ , at least a portion of various circuit elements can be formed between the second ends 1232 of the RDTI structures 1212 and the second surface 1224 of the substrate 1216. For example, as shown in ​ , at least a portion of an amplification transistor 413 and at least a portion of a pixel group overflow gate transistor 332 can be formed between the second ends 1232 of the RDTI structures 1212 extending between different rows of unit pixels 310 within a pixel group 314 and the second surface 1224 of the substrate 1216. As another example, as shown in ​ , at least a portion of a reset transistor 321 and at least a portion of an amplification transistor 322 can be formed between the ends 1232 of the RDTI structures 1212 and the second surface 1224 of the substrate 1216.

[0161] Referring again to ​ , the portion of the inter-pixel group separation structure 1210b between adjacent columns of unit pixels 310 within a pixel group 314 has a single RDTI structure 1212 portion that intersects with the portion of the inter-pixel group separation structure 1210a that is formed entirely by RDTI structures 1212. Thus, at least a portion of the node 1236 to which the pixel group transfer transistor 331 and the pixel group overflow gate transistor 332 are connected can be formed in the area where the two RDTI structures 1212 intersect within a pixel group 314.

[0162] ​ is a plan view of a configuration 1404 of a pixel group 314 according to a third exemplary embodiment of the present disclosure, ​ is a cross-section along ​a cross-section of a portion of the third exemplary embodiment taken along line A-A’, ​ is a cross-section of another portion of the third exemplary embodiment taken along line B-B’. ​ In this example, groups 314 of unit pixels 310 are defined, and the groups 314 of unit pixels 310 are separated from one another by RFTI structures 1208. In addition, pixel-to-pixel separation structures 1210 including RFTI 1208 and RDTI 1212 structures are provided. More particularly, the pixel-to-pixel separation structures 1210 within a pixel group 314 can include horizontal portions 1210a extending between unit pixels 310 in adjacent rows and including RFTI 1208 and RDTI 1212 structures, and vertical portions 1210b extending between unit pixels 310 in adjacent columns and being composed of RDTI structures 1212. Although a 2x2 array of four pixel groups 314 is shown in this example (where each pixel group 314 includes a 2x2 subarray or group array pattern of four unit pixels 310), other configurations can be employed.

[0163] As shown in ​ and ​ , at least a portion of various circuit elements can be formed between the second ends 1232 of the RDTI structures 1212 and the second surface 1224 of the substrate 1216. For example, as shown in ​ , at least a portion of an amplification transistor 413 and at least a portion of a pixel group overflow gate transistor 332 can be formed between the second ends 1232 of the RDTI structures 1212 extending between different columns of unit pixels 310 within a pixel group 314 and the second surface 1224 of the substrate 1216. As another example, as shown in ​ , at least a portion of a reset transistor 321 and at least a portion of an amplification transistor 322 can be formed between the ends 1232 of the RDTI structures 1212 and the second surface 1224 of the substrate 1216.

[0164] Referring again to ​ , portions of the pixel-to-pixel separation structures 1210a between adjacent rows of unit pixels 310 within a pixel group 314 have a single RDTI structure 1212 portion that intersects with portions of the pixel-to-pixel separation structures 1210b that are all formed by RDTI structures 1212. Thus, at least a portion of the node 1236 to which the pixel group transfer transistor 331 and the pixel group overflow gate transistor 332 are connected can be formed in the area where the two RDTI structures 1212 intersect within a pixel group 314.

[0165] ​ is a plan view of a configuration of a pixel group 314 according to a fourth exemplary embodiment of the present disclosure, ​It is along ​ A cross-section of a portion of the fourth exemplary embodiment, taken by line A-A'. ​ It is along ​ The cross-section of another portion of the fourth exemplary embodiment is taken by line B-B'. In this example, a group 314 of unit pixels 310 is defined, and the group 314 of unit pixels 310 is separated from each other by RFTI structure 1208. In addition, a pixel group separation structure 1210 including RFTI 1208 and RDTI 1212 structures is provided. More specifically, the pixel group separation structure 1210 within a pixel group can include a horizontal portion 1210a extending between unit pixels 310 in adjacent rows and including RFTI 1208 and RDTI 1212 structures, and a vertical portion 1210b extending between unit pixels 310 in adjacent columns and including RFTI 1208 and RDTI 1212 structures. ​ In the example, two segments of the RFTI structure 1208 extend horizontally from between pixel groups 314 located in different columns of pixel groups 314. One segment of the RFTI structure 1208 extends vertically from the RFTI structure 1208 positioned along the lower boundary of pixel group 314. One segment of the RDTI structure 1212 extends vertically from the RFTI structure 1208 positioned along the upper boundary of pixel group 314. Additionally, a segment of the horizontal RDTI structure 1212 is located between the two horizontal RFTI structures 1208.

[0166] like ​ and ​ As shown, at least a portion of various circuit elements can be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. For example, such as ​ As shown, at least a portion of the drain / source region between the pixel group transfer transistor 331 and the pixel group overflow gate transistor 332, a portion of the pixel group transfer transistor 331, and / or a portion of the pixel group overflow gate transistor 332 can be formed between the second end 1232 of the RDTI structure 1212 extending between different columns of unit pixels 310 within the pixel group 314 and the second surface 1224 of the substrate 1216. Additionally, at least a portion of the boundary between adjacent unit pixels 310 can be separated from each other by a portion of the RFTI structure 1208. Therefore, embodiments of this disclosure enable unit pixels 310 within the same pixel group to share elements of the pixel group circuitry 1100, while also enabling these unit pixels 310 to be separated.

[0167] ​A construction example of the pixel group 314 is also shown, in which the shared transistors are located in a single row of unit pixels 310 within each pixel group 314. For example, the select transistor 323, the amplification transistor 322, the reset transistor 321, the pixel group transfer transistor 331, the OFG transistor 332, the first and second logarithmic transistors 411 and 414, and the amplification transistors 412 and 413 can all be formed in one of the two rows of unit pixels 310. In addition, the transistors can all be formed in a row of unit pixels 310 within which the division between adjacent unit pixels 310 of any pixel group is formed entirely by the RDTI structure 1212.

[0168] ​ is a plan view of a pixel construction according to a fifth example embodiment of the disclosure, ​ is a cross-section of a portion of the fifth example embodiment taken along line A-A' of ​ ​ is a cross-section of another portion of the fifth example embodiment taken along line B-B' of ​ In this example, groups 314 of unit pixels 310 are defined, and the groups 314 of unit pixels 310 are separated from one another by the RFTI structure 1208. In addition, a pixel group separation structure 1210 including RFTI 1208 and RDTI 1212 structures is provided. More particularly, the pixel group separation structure 1210 within a pixel group 314 can include a horizontal portion 1210a extending between unit pixels 310 in adjacent rows and including RFTI 1208 and RDTI 1212 structures, and a vertical portion 1210b extending between unit pixels 310 in adjacent columns and including RFTI 1208 and RDTI 1212 structures. In ​ In the example of

[0169] As in ​ and ​ ​As shown, separation between adjacent unit pixels 310 is provided while also enabling at least a portion of various circuit elements to be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. For example, as shown in FIG. 12B, at least a portion of the log transistors 411 can be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216 extending between different columns of unit pixels 310 within the pixel group 314. Thus, embodiments of the present disclosure enable unit pixels 310 within the same pixel group to share elements of the pixel group circuit 1100 while also enabling the unit pixels 310 to be separated. ​ As shown, the RFTI structure 1208 extends between at least some shared boundaries between adjacent unit pixels 314. As shown in FIG. 12B, at least a portion of the log transistors 411 can be formed between the second end 1232 of the RFTI structure 1208 and the second surface 1224 of the substrate 1216 extending between different columns of unit pixels 310 within the pixel group 314. Thus, embodiments of the present disclosure enable unit pixels 310 within the same pixel group to share elements of the pixel group circuit 1100 while also enabling the unit pixels 310 to be separated. ​ As shown, at least a portion of the log transistors 411 can be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216 extending between different columns of unit pixels 310 within the pixel group 314. Thus, embodiments of the present disclosure enable unit pixels 310 within the same pixel group to share elements of the pixel group circuit 1100 while also enabling the unit pixels 310 to be separated.

[0170] ​ is a plan view of a pixel configuration according to a sixth exemplary embodiment of the present disclosure, ​ is a cross-section of a portion of the sixth exemplary embodiment taken along line A-A’ of ​ In this example, groups 314 of unit pixels 310 are defined and the groups 314 of unit pixels 310 are separated from one another by the RFTI structure 1208. In addition, a pixel group separation structure 1210 including RFTI 1208 and RDTI 1212 structures is provided. More particularly, the pixel group separation structure 1210 within the pixel group 314 can include horizontal portions 1210a extending between unit pixels 310 in adjacent rows and including RFTI 1208 and RDTI 1212 structures and vertical portions 1210b extending between unit pixels 310 in adjacent columns and including RFTI 1208 and RDTI 1212 structures. In ​ In the example of FIG. 12B, two segments of the RFTI structure 1208 extend horizontally from the RFTI structure 1208 between pixel groups 314 in different columns of pixel groups 314 and one segment of the RDTI structure 1212 extends horizontally between the two horizontal segments of the RFTI structure 1208. In addition, two segments of the RFTI structure 1208 extend vertically from the RFTI structure 1208 at the top and bottom of the pixel group 314 and one vertical segment of the RDTI structure 1212 extends vertically between the two segments of the RFTI structure 1208. The vertical segment of the RDTI structure 1212 also intersects the horizontal segment of the RDTI structure 1212 in the middle region of the pixel group.

[0171] As shown in FIG. 12B, at least a portion of the log transistors 411 can be formed between the second end 1232 of the RFTI structure 1208 and the second surface 1224 of the substrate 1216 extending between different columns of unit pixels 310 within the pixel group 314. Thus, embodiments of the present disclosure enable unit pixels 310 within the same pixel group to share elements of the pixel group circuit 1100 while also enabling the unit pixels 310 to be separated. ​ and ​As shown, separation between adjacent unit pixels 310 is provided. In particular, RFTI structures 1208 extend between at least some shared boundaries between adjacent unit pixels 310. Separation between adjacent unit pixels 310 in the central region of a pixel group 314 is provided by RDTI structures 1212, enabling unit pixel transistors 334 to be formed in regions within the pixel group 314 where two RDTI structures 1212 intersect at least a portion of the node 1236 to which the pixel group transfer transistor 331 and the pixel group overflow gate transistor 332 are connected. Thus, embodiments of the disclosure enable unit pixels 310 within the same pixel group to share elements of the pixel group circuit 1100, while also enabling these unit pixels 310 to be separated.

[0172] ​ is a plan view of a pixel configuration according to a seventh exemplary embodiment of the disclosure, ​ is a cross-section of a portion of the seventh exemplary embodiment taken along line A-A' of ​ ​ is a cross-section of a portion of the seventh exemplary embodiment taken along line B-B' of ​ In this embodiment, each pixel group 314 includes eight unit pixels 310, with the unit pixels 310 arranged in four rows of two columns. In addition, the eight unit pixels 310 within a pixel group 314 share at least some circuit elements. A mix of separation structures 1210 is applied to provide separation between adjacent unit pixels 310. In particular, separation between the first and second rows of unit pixels 310 and separation between the third and fourth rows of unit pixels 310 is provided by two horizontal RFTI structures 1208 extending from the vertical separation structures 1208 on either side of the pixel group 314, with a horizontal RDTI structure 1212 extending between the two horizontal RFTI structures 1208 in each case. Separation between the second and third rows of unit pixels 310 is provided entirely by RDTI structures 1212. Separation between the first and second columns of unit pixels 310 is provided entirely by RDTI structures 1212.

[0173] As ​ , ​ and ​ ​As shown, the separation between adjacent unit pixels 310 within a pixel group 314 is provided by a hybrid of RFTI 1208 and RDTI 1212 structures. In addition, unit pixels share circuit elements, and at least a portion of the various circuit elements can be formed in a region of the substrate 1216 that is at least partially between the end 1228 of the RDTI structure 1212 and the surface 1224 of the substrate 1216. For example, at least a portion of both of the logarithmic transistors 411 and 414 can be formed between the end of the RDTI structure 1212 and the second surface 1224 of the substrate 1216, and at least a portion of the reset transistor 321 can be formed between the end of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. Thus, separation is provided while the photoelectric conversion element 333 can use more area compared to prior constructions.

[0174] ​ is a plan view of a pixel construction according to an eighth example embodiment of the present disclosure, ​ is a cross-section of a portion of the eighth example embodiment taken along the line A-A’ of ​ In this embodiment, each pixel group 314 includes eight unit pixels 310, with the unit pixels 310 arranged in four rows of two columns. In addition, the eight unit pixels 310 within a pixel group 314 share at least some circuit elements. A hybrid of RFTI 1208 separation structures and RDTI 1212 separation structures is applied to provide separation between adjacent unit pixels 310. In particular, the separation between the first and second rows of unit pixels 310 and the separation between the third and fourth rows of unit pixels 310 are provided by two horizontal RFTI structures 1208 extending from the vertical separation structures 1208 on either side of the pixel group 314, with a horizontal RDTI structure 1212 extending between the two horizontal RFTI structures 1208 in each case. The separation between the second and third rows of unit pixels 310 is provided entirely by RDTI structures 1212. The separation between the first and second columns of unit pixels 310 is provided entirely by RDTI structures 1212. Thus, the arrangement of separation structures is similar to that of the seventh embodiment. However, there is a difference in the location of the shared elements of circuitry between the seventh example embodiment and the eighth example embodiment.

[0175] As ​ and ​As shown, the separation between adjacent unit pixels 310 within a pixel group 314 is provided by a mix of RFTI 1208 structures and RDTI 1212 structures. In addition, unit pixels share circuit elements, and at least a portion of the various circuit elements can be formed in a region of the substrate 1216 that is at least partially between the end 1228 of the RDTI structure 1212 and the surface 1224 of the substrate 1216. For example, at least a portion of the pixel group overflow gate transistor 332 can be at least partially formed in the region between the second end 1228 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. Thus, separation is provided while the photoelectric conversion element 333 can use more area compared to prior constructions.

[0176] ​ is a plan view of a pixel construction according to a ninth example embodiment of the present disclosure, ​ is a cross-section of a portion of the ninth example embodiment taken along the line A-A’ of ​ In this embodiment, each pixel group 314 includes eight unit pixels 310, with the unit pixels 310 arranged in four rows of two columns. In addition, the eight unit pixels 310 within a pixel group 314 share at least some circuit elements. A mix of RFTI 1208 separation structures and RDTI 1212 separation structures are applied to provide separation between adjacent unit pixels 310. In particular, the separation between the first and second rows of unit pixels 310 and the separation between the third and fourth rows of unit pixels 310 are provided by two horizontal RFTI structures 1208 extending from the vertical separation structures 1208 on either side of the pixel group 314, with a horizontal RDTI structure 1212 extending between the two horizontal RFTI structures 1208 in each case. The separation between the second and third rows of unit pixels 310 is provided entirely by the RDTI structure 1212. The separation between the first and second columns of unit pixels 310 is provided by two vertical RFTI structures extending from the horizontal separation structures 1208 at the top and bottom boundaries of the pixel group 314 a distance less than the entire vertical extent of the top and bottom rows of unit pixels 310, respectively, and a RDTI structure 1212 extending vertically between the two vertical RFTI structures 1208. Thus, the arrangement of separation structures is similar to that of the seventh and eighth embodiments. However, this ninth example embodiment differs from the seventh and eighth example embodiments in the location of the shared elements of circuitry.

[0177] As ​ and ​As shown, the separation between adjacent unit pixels 310 within a pixel group 314 is provided by a mix of RFTI 1208 structures and RDTI 1212 structures. In addition, unit pixels share circuit elements, and at least a portion of the various circuit elements can be formed in a region of the substrate 1216 that is at least partially between the end 1232 of the RDTI structure 1212 and the surface 1224 of the substrate 1216. For example, at least a portion of some or all of the select transistor 323, the amplification transistor 322, the reset transistor 321, the transfer transistor 331, the overflow gate transistor 332, the first and second logarithmic transistors 411 and 414, and the first and second amplification transistors 412 and 413 can be formed at least partially in a region between the second end 1228 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. Thus, separation is provided while the photoelectric conversion element 333 can use more area compared to existing configurations.

[0178] ​ is a plan view of a portion of the pixel array unit 300, ​ is a cross-section taken along the line A-A’ of ​ the pixel group 314 according to the tenth example embodiment of the present disclosure. This embodiment is similar to the first example embodiment, except that each pixel group 314 includes pixels 310 that are sensitive to the same color. As in the first example and as can be applied to other embodiments of the present disclosure, groups 314 of unit pixels 310 are defined, and the groups 314 of unit pixels 310 are separated from one another by a full-thickness dielectric trench isolation (RFTI) structure 1208. Within each pixel group 314, the unit pixels 310 are separated from one another by a pixel group-to-pixel group separation structure 1210 in the form of a deep trench isolation (RDTI) structure 1212. The pixel group-to-pixel group separation structure 1210 within a pixel group 314 can include horizontal portions 1210a that extend between unit pixels 310 in adjacent rows and vertical portions 1210b that extend between unit pixels 310 in adjacent columns. More particularly, the pixel configuration 1204 is characterized by RDTI structures 1212 along the entire boundary between adjacent unit pixels 310 within each pixel group 314, with first RDTI structures 1212a extending between adjacent rows of unit pixels 310 within each pixel group 314 and second RDTI structures 1212b extending between adjacent columns of unit pixels 310 within each pixel group 314.

[0179] As shown, each unit pixel 310 within the same pixel group 314 includes a color filter 1240 of the same color. In addition, as ​ shown, the separation between adjacent unit pixels 310 within a pixel group 314 is provided by a mix of RFTI 1208 structures and RDTI 1212 structures. In addition, unit pixels share circuit elements, and at least a portion of the various circuit elements can be formed in a region of the substrate 1216 that is at least partially between the end 1232 of the RDTI structure 1212 and the surface 1224 of the substrate 1216. For example, at least a portion of some or all of the select transistor 323, the amplification transistor 322, the reset transistor 321, the transfer transistor 331, the overflow gate transistor 332, the first and second logarithmic transistors 411 and 414, and the first and second amplification transistors 412 and 413 can be formed at least partially in a region between the second end 1228 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. Thus, separation is provided while the photoelectric conversion element 333 can use more area compared to existing configurations. ​As shown, the pixel group 314 can be arranged in such a way that the pixel array unit 300 is constructed as a Bayer array or other camera sensor pattern, with the pixel group 314 as the unit, rather than with each individual pixel 310 as the unit.

[0180] like ​ and ​ As shown, the separation between adjacent unit pixels 310 within pixel group 314 is provided by the RDTI 1212 structure. Furthermore, unit pixels share circuit elements, and at least a portion of various circuit elements can be formed in the region of substrate 1216 at least partially located between the end 1228 of the RDTI structure 1212 and the surface 1224 of substrate 1216. For example, at least a portion of the logarithmic transistor 414 of the address event detection readout circuit 400 for pixel group circuit 1100 can be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of substrate 1216. As another example, at least a portion of the drain / source regions of amplifying transistors 412 and 413 can be formed in the region between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of substrate 1216. As another example, at least a portion of the node 1236 connecting the unit pixel transistor 334 with the pixel group transfer transistor 331 and the pixel group overflow gate transistor 332 can be formed between the second end 1232 of the two intersecting RDTI structures 1212 and the second surface 1224 of the substrate 1216.

[0181] ​ It is a planar view constructed from pixels according to the eleventh exemplary embodiment of this disclosure. ​ This is a cross-section of a portion of the eleventh exemplary embodiment taken along line A-A'. This embodiment is similar to the fifth exemplary embodiment, except that each pixel group 314 includes pixels 310 sensitive to the same color. Therefore, in this example, groups 314 of unit pixels 310 are defined, and groups 314 of unit pixels 310 are separated from each other by RFTI structure 1208. Additionally, an inter-pixel group separation structure 1210 including RFTI 1208 and RDTI 1212 structures is provided. More specifically, the inter-pixel group separation structure 1210 within the pixel group 314 can include a horizontal portion 1210a extending between unit pixels 310 in adjacent rows and including RFTI 1208 and RDTI 1212 structures, and a vertical portion 1210b extending between unit pixels 310 in adjacent columns and including RFTI 1208 and RDTI 1212 structures. ​In the example, two segments of RFTI structure 1208 extend horizontally from between pixel groups 314 located in different columns of pixel group 314, and one segment of RDTI structure 1212 extends horizontally between the two horizontal segments of RFTI structure 1208. Two segments of RDTI structure 1212 extend vertically from the top and bottom of RFTI structure 1208 in pixel group 314, with one vertical segment of RFTI structure 1208 extending from the vertical RDTI structure 1212. Each vertical segment of RFTI structure 1208 within pixel group 314 is separated from each other by the vertical segment of RDTI structure 1212 in the middle region of pixel group 314. The vertical segment of RDTI structure 1212 also intersects with the horizontal segment of RDTI structure 1212 in the middle region of the pixel group.

[0182] like ​ and ​ As shown, this provides isolation between adjacent unit pixels 310, while also allowing at least a portion of various circuit elements to be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. For example, as ​ As shown, at least a portion of the logarithmic transistor 411 can be formed between the second end 1232 of the RDTI structure 1212 extending between unit pixels 310 in different columns within the pixel group 314 and the second surface 1224 of the substrate 1216. Therefore, embodiments of this disclosure allow unit pixels 310 within the same pixel group to share elements of the pixel group circuitry 1100, while also allowing these unit pixels 310 to be separated.

[0183] ​ This is a circuit diagram illustrating a schematic construction example of a pixel group circuit 2300 for a group 314 of a unit pixel 310 according to at least some embodiments of the present disclosure. More specifically, ​ A pixel group circuit 2300 is shown, wherein the photoelectric conversion units 333 of all unit pixels 310 included in a group 314 of unit pixels 310 share elements of the circuit 2300. In this example, the unit pixel 310 is part of a pixel group 314 including a basic Bayer array pattern 310A, wherein a first unit pixel 310R is associated with a red filter, a second unit pixel 310Gb is associated with a green filter, a third unit pixel 310Gr is associated with a green filter, and a fourth unit pixel 310B is associated with a blue filter. Thus, this example includes a group 314 of four unit pixels 310. However, other arrangements and configurations are also possible.

[0184] The pixel group circuit 2300 generally includes a light receiving unit 2330 having a plurality of photoelectric conversion units 333. The photoelectric conversion units 333 can for example but not limited to include photodiodes. While other configurations can also be employed, in this example, each unit pixel 310 includes one photoelectric conversion unit 333. The pixel group circuit 2300 also includes a pixel imaging signal generation readout circuit 320 and an address event detection readout circuit 400. The pixel imaging signal generation readout circuit 320 and the address event detection readout circuit 400 can be configured in the same or similar manner as the readout circuits 320 and 400 of ​ and ​ .

[0185] The pixel group circuit 2300 differs from the pixel group circuit 1100 of ​ in that the pixel group circuit 2300 omits the pixel group transfer transistor 331 and the pixel group overflow gate transistor 332. Instead, the pixel group circuit 2300 includes the light receiving unit 2330 having a unit pixel transfer transistor 2331 and a unit pixel overflow gate transistor 2332 for each photoelectric conversion unit 333 of each unit pixel 310 within the pixel group 314. According to this arrangement, each photoelectric conversion unit 333 of each unit pixel 310 can be selectively connected to the imaging signal generation readout circuit 320 by operation of the unit pixel transfer transistor 2331 of the selected pixel and can be selectively connected to the address event detection readout circuit 400 by operation of the unit pixel overflow gate transistor 2332 of the selected pixel.

[0186] In the imaging mode, the unit pixel transfer transistor 2331 associated with each selected photoelectric conversion unit 333 is in an on state so as to operably connect the selected photoelectric conversion unit 333 to the floating diffusion 324 of the pixel imaging signal generation readout circuit 320. In the event detection mode or dynamic vision sensor (DVS) mode, the unit pixel overflow gate transistor 2332 associated with each selected photoelectric conversion unit 333 is in an on state so as to operably connect the selected photoelectric conversion unit 333 to the address event detection readout circuit 400. Under typical operating conditions, in the imaging mode, a single photoelectric conversion unit 333 can be operated at any time to provide a signal to the pixel imaging signal generation readout circuit 320, while in the DVS mode, one, some or all of the photoelectric conversion units 333 can be operated at any time to provide a signal to the address event detection readout circuit 400.

[0187] Although in a typical imaging operation the charge from a single photoelectric conversion unit 333 is transferred to the pixel imaging signal generation readout circuit 320, other modes in which signals from multiple photoelectric conversion units 333 corresponding to multiple unit pixels 310 are transferred to the pixel imaging signal generation readout circuit 320 can also be employed. Those skilled in the art will understand upon considering the present disclosure that the unit pixel overflow gate transistor 332 remains closed during imaging operations, and that the unit pixel transfer transistor 2331 remains closed during event detection mode. Those skilled in the art will further understand upon considering the present disclosure that operation of the pixel image signal generation circuit 320 can be triggered by detection of an event by the address event detection readout circuit 400 for the pixel group 314.

[0188] Thus, ​ The circuit configuration 2300 is an example in which the plurality of unit pixels 310 of the image pickup device 100 are able to perform both event detection and imaging operations, and the photoelectric conversion unit 333 of each unit pixel 310 shares elements of the event detection circuit 400 and the pixel imaging signal generation readout circuit 320.

[0189] ​ is a plan view of a pixel configuration 2404 according to a twelfth example embodiment of the present disclosure, ​ is a cross section of a portion of the twelfth example embodiment taken along line A-A’ in ​ The pixel configuration 2404 is similar to the pixel configuration 2300 of the eleventh example embodiment, except that the pixel configuration 2404 includes a pixel group 2402 in which the photoelectric conversion unit 333 of each unit pixel 310 shares elements of the event detection circuit 400 and the pixel imaging signal generation readout circuit 320. ​Similar to the pixel structure 1204, the difference lies in that the photoelectric conversion unit 333 of each unit pixel 310 includes a unit pixel transfer transistor 2331 and a unit pixel overflow gate transistor 2332, but does not include a pixel group transfer transistor 331 and a pixel group overflow gate transistor 332. Therefore, in this example, a group 314 of unit pixels 310 is defined, which is separated from each other by a full-thickness dielectric trench isolation (RFTI) structure 1208. Within each pixel group 314, the unit pixels 310 are separated from each other by an inter-group separation structure 1210 in the form of a deep trench isolation (RDTI) structure 1212. The inter-group separation structure 1210 within the pixel group 314 can include a horizontal portion 1210a extending between unit pixels 310 in adjacent rows and a vertical portion 1210b extending between unit pixels 310 in adjacent columns. More specifically, pixel configuration 1204 is characterized by an RDTI structure 1212 along the entire boundary between adjacent unit pixels 310 within each pixel group 314, wherein a first RDTI structure 1212a extends between adjacent rows of unit pixels 310 within each pixel group 314, and a second RDTI structure 1212b extends between adjacent columns of unit pixels 310 within each pixel group 314. Although this example shows four pixel groups 314 of a 2×2 array (where each pixel group 314 includes four unit pixels 310 of a 2×2 subarray or group array pattern), other configurations may also be employed.

[0190] According to embodiments of this disclosure, such as ​ As shown, the RFTI structure 1208 extends through the entire thickness of the substrate 1216, in which a photodiode 333 of a unit pixel 314 is formed. That is, the RFTI structure 1208 extends from at least a first light-incident surface 1220 of the substrate 1216 to a second non-light-incident surface 1224. The RDTI structure 1212 extends from a first end 1228 at the first surface 1220 or above the first surface 1220 to a second end 1232 formed toward the second surface 1224 of the substrate 1216. Specifically, since the distance the RDTI structure 1212 extends is less than the thickness of the substrate 1216, the RDTI structure 1212 does not reach the second surface 1224. Therefore, material of the substrate 1216 remains between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216.

[0191] exist ​ and ​ In the example pixel group construction 2404, the circuit elements associated with each pixel group 314 can be... ​The circuit elements of pixel group circuit 2300 are the same as or similar to those of pixel group circuit 1100. According to embodiments of the present disclosure, one or more circuit elements of pixel group circuit 2300, such as transistors, conductors, or other elements, are formed at least partially between the second end 1232 of one or more RDTI structures 1212 and the second surface 1224 of the substrate 1216 within the pixel group 314 area or are located between the second end 1232 of one or more RDTI structures 1212 and the second surface 1224 of the substrate 1216 within the pixel group 314 area. For example, in the example of FIG. 24A, at least a portion of the address event detection readout circuit 400 for pixel group circuit 1100, such as the logarithmic transistor 411 and / or the amplification transistor 412, can be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. As another example, at least a portion of the node 2436 and 2437 at which the unit pixel transistor 334 is connected to the pixel imaging signal generation readout circuit 320 and the address event detection readout circuit 400, respectively, can be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224. As yet another example, at least a portion of at least one of the nodes 2436 or 2437 can be formed between the second end 1232 of two intersecting RDTI structures 1212 and the second surface 1224 of the substrate 1216. ​ In the example of FIG. 24B, at least a portion of the address event detection readout circuit 400 for pixel group circuit 1100, such as the logarithmic transistor 411 and / or the amplification transistor 412, can be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. As another example, at least a portion of the node 2436 and 2437 at which the unit pixel transistor 334 is connected to the pixel imaging signal generation readout circuit 320 and the address event detection readout circuit 400, respectively, can be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224. As yet another example, at least a portion of at least one of the nodes 2436 or 2437 can be formed between the second end 1232 of two intersecting RDTI structures 1212 and the second surface 1224 of the substrate 1216.

[0192] Accordingly, embodiments of the present disclosure can provide suitable separation between pixel groups 314 using RFTI structures 1208 and between unit pixels 310 within a pixel group 314 using RDTI structures 1212, while providing a more favorable ratio of the total area of the pixel group 314 to the area of the opto-electric conversion unit 333 of the unit pixel 310 within the pixel group 314 by facilitating sharing of pixel group circuit 1100 elements and by forming at least a portion of the elements of the pixel group circuit 1100 in the area between the end of the RDTI structure 1212 and the surface of the substrate 1216.

[0193] ​ is a plan view of a pixel configuration according to a thirteenth example embodiment of the present disclosure, ​ is a cross-section of a portion of the thirteenth example embodiment taken along line A-A’ in ​ is a cross-section of a portion of the thirteenth example embodiment taken along line A-A’ in ​ is a cross-section of a portion of the thirteenth example embodiment taken along line A-A’ in ​cross-section of another portion of the thirteenth example embodiment taken along line B-B' in FIG. 12A. In this example, groups 314 of unit pixels 310 are defined and the groups 314 of unit pixels 310 are separated from one another by RFTI structures 1208. In addition, inter-pixel group separation structures 1210 including RFTI 1208 and RDTI 1212 structures are provided. More particularly, the inter-pixel group separation structures 1210 within the pixel groups 314 can include horizontal portions 1210a extending between unit pixels 310 in adjacent rows and including RFTI 1208 and RDTI 1212 structures and vertical portions 1210b extending between unit pixels 310 in adjacent columns and including RFTI 1208 and RDTI 1212 structures. In ​ this example, two segments of RFTI structures 1208 extend horizontally from the RFTI structures 1208 between the pixel groups 314 in different columns of pixel groups 314 and one segment of RDTI structures 1212 extends horizontally between the two horizontal segments of RFTI structures 1208. Two segments of RDTI structures 1212 extend vertically from the RFTI structures 1208 at the top and bottom of the pixel groups 314, with one vertical segment of RFTI structures 1208 extending from the vertical RDTI structures 1212. Each vertical segment of RFTI structures 1208 within the pixel groups 314 is separated from one another by a vertical segment of RDTI structures 1212 in the middle region of the pixel groups 314. The vertical segment of RDTI structures 1212 also intersects the horizontal segments of RDTI structures 1212 in the middle region of the pixel groups.

[0194] This example embodiment can include pixel group circuitry constructed the same as or similar to the pixel group circuitry 2300 of ​ FIG. 23. As shown in ​ , ​ and ​ adjacent unit pixels 310 are provided while also enabling at least a portion of various circuit elements to be formed between the second end 1232 of the RDTI structures 1212 and the second surface 1224 of the substrate 1216. For example, as shown in ​ the RFTI structures 1208 extend between at least some shared boundaries between adjacent unit pixels 314. As shown in ​As shown, the region between the second end 1232 of the RDTI structure 1212 extending between different columns of unit pixels 310 within pixel group 314 and the second surface 1224 of the substrate 1216 is available. Additionally, at least a portion of the amplifying transistor 412 can be formed between the second end 1232 of the RDTI structure 1212 and the second surface 1224 of the substrate 1216. Therefore, embodiments of this disclosure allow unit pixels 310 within the same pixel group to share elements of the pixel group circuitry 1100, while also allowing these unit pixels 310 to be separated.

[0195] ​ It is a planar view constructed from pixels according to the fourteenth exemplary embodiment of this disclosure. ​ It is along ​ The image shows a cross-section of a portion of the fourteenth exemplary embodiment, taken along line A-A'. In this embodiment, each pixel group 314 includes eight unit pixels 310, arranged in four rows and two columns. Additionally, the eight unit pixels 310 within the pixel group 314 share at least some circuit elements. Furthermore, each photoelectric conversion element 333 of each unit pixel 310 is connected to a unit pixel transfer transistor 2331 and a unit pixel overflow gate transistor 2332. A mixture of separation structures is applied to provide separation between adjacent unit pixels 310. Specifically, the separation between the first and second rows of unit pixels 310, and the separation between the third and fourth rows of unit pixels 310, is provided by two horizontal RFTI structures 1208 extending from a vertical separation structure 1208 on either side of the pixel group 314, wherein in each case, a horizontal RDTI structure 1212 extends between the two horizontal RFTI structures 1208. The separation between the second and third rows of unit pixels 310 is entirely provided by the RDTI structure 1212. The separation between the first and second columns of unit pixel 310 is entirely provided by RDTI structure 1212.

[0196] like ​ and ​ As shown, the separation between adjacent unit pixels 310 within pixel group 314 is provided by a hybrid structure of RFTI 1208 and RDTI 1212. Furthermore, unit pixels share circuit elements, and at least a portion of various circuit elements can be formed in the region of substrate 1216 at least partially located between the end 1228 of RDTI structure 1212 and the surface 1224 of substrate 1216. For example, at least a portion of amplifying transistor 413 and / or at least a portion of reset transistor 321 can be formed between the end of RDTI structure 1212 and the second surface 1224 of substrate 1216. Therefore, separation is provided, while the photoelectric conversion element 333 can utilize more area compared to existing configurations.

[0197] ​ is a plan view of a pixel configuration according to a fifteenth example embodiment of the present disclosure, ​ is a cross-section of a portion of the fifteenth example embodiment taken from ​ region A, ​ is a cross-section of another portion of the fifteenth example embodiment taken from ​ region B. The arrangement of pixel groups 314 and the arrangement of unit pixels 310 within each pixel group 314 can be the same or similar to that shown in ​ Thus, groups 314 of unit pixels 310 are defined, and the groups 314 of unit pixels 310 are separated from one another by RFTI structures 1208. Within each pixel group 314, the unit pixels 310 are separated from one another by inter-pixel group separation structures 1210 in the form of RDTI structures 1212. The inter-pixel group separation structures 1210 within a pixel group 314 can include horizontal portions 1210a extending between unit pixels 310 in adjacent rows and vertical portions 1210b extending between unit pixels 310 in adjacent columns. More particularly, the pixel configuration 1204 is characterized by RDTI structures 1212 along the entire boundary between adjacent unit pixels 310 within each pixel group 314, with first RDTI structures 1212a extending between adjacent rows of unit pixels 310 within each pixel group 314 and second RDTI structures 1212b extending between adjacent columns of unit pixels 310 within each pixel group 314. Although a 2x2 array of four pixel groups 314 is shown in this example (with each pixel group 314 including four unit pixels 310 in a 2x2 subarray or group array pattern), other configurations can also be employed.

[0198] According to embodiments of the present disclosure, as ​ shown, the RFTI structures 1208 extend through the entire thickness of the substrate 1216, and the RDTI structures 1212 extend from a first end 1228 at or above the first surface 1220 to a second end 1232 formed toward the second surface 1224 of the substrate 1216. In the embodiment shown, the RFTI 1208 and RDTI 1212 structures have a polysilicon core 2750 separated from the substrate 1216 by a dielectric 2754. The dielectric 2754 may, for example but without limitation, be in the form of an oxide or nitride material. Further, the use of separation structures 1208 and 1212 having a polysilicon core 2750 as disclosed herein can be applied to any other pixel group 314 configuration and circuit configuration of embodiments of the present disclosure.

[0199] ​ is a plan view of a pixel configuration according to a sixteenth example embodiment of the present disclosure, ​ is a cross-section of a portion of the sixteenth example embodiment, ​ is a cross-section of another portion of the sixteenth example embodiment. The arrangement of the pixel groups 314 and the arrangement of the unit pixels 310 within each pixel group 314 can be the same or similar to that shown in ​ and ​ However, in this sixteenth example embodiment, as shown in ​ and ​ the RFTI 1208 and RDTI structure 1212 include a tungsten core 2870 within a dielectric inner layer 2854, which in turn is separated from the substrate 1216 by a passivation layer 2874. The use of the split structures 1208 and 1212 with tungsten cores 2870 as disclosed herein can be applied to any other pixel group 314 configuration and circuit configuration of embodiments of the present disclosure. Further, different split structure 1208 and 1212 materials can be used within a single pixel array unit 300. For example, some split structures 1208 and 1212 can include a dielectric core, some split structures 1208 and 1212 can include a polysilicon core, and some split structures can include a tungsten core.

[0200] Figure 30 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a mobile body control system to which the technology according to the present disclosure is applicable.

[0201] The vehicle control system 12000 includes a plurality of electronic control units connected to each other through a communication network 12001. In the example shown in Figure 30 the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound image output unit 12052, and a vehicle-mounted network interface (I / F) 12053 are shown in the drawing.

[0202] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle in accordance with various programs. For example, the drive system control unit 12010 functions as a control device for devices such as a drive force generation device such as an internal combustion engine and a drive motor for generating the drive force of the vehicle, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating the braking force of the vehicle.

[0203] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, an intelligent key system, a power window device, and various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps. In this case, an electric wave transmitted from a portable device that substitutes for a key or a signal of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives the input of the electric wave or the signal, and controls a door lock device, a power window device, lamps, and the like of the vehicle.

[0204] The outside -vehicle information detecting unit 12030 detects information about the outside of the vehicle on which the vehicle control system 12000 is mounted. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging unit 12031. The outside-vehicle information detecting unit 12030 enables the imaging unit 12031 to capture an image of the outside of the vehicle, and receives the captured image. Based on the received image, the outside-vehicle information detecting unit 12030 can perform object detection processing or distance detection processing on a pedestrian, a vehicle, an obstacle, a sign, or a letter on a road surface.

[0205] The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal corresponding to the amount of received light. The imaging unit 12031 can output the electric signal as an image, or can output the electric signal as ranging information. In addition, the light received by the imaging unit 12031 can be visible light or non-visible light such as infrared rays.

[0206] The in-vehicle information detecting unit 12040 detects information of the inside of the vehicle. For example, the in-vehicle information detecting unit 12040 is connected with a driver state detecting unit 12041 that detects the state of the driver. For example, the driver state detecting unit 12041 includes a camera that images the driver, and based on detection information input from the driver state detecting unit 12041, the in-vehicle information detecting unit 12040 can calculate the degree of fatigue or the degree of concentration of the driver, or can determine whether the driver is drowsy.

[0207] Based on information about the outside or inside of the vehicle acquired by the outside information detecting unit 12030 or the inside information detecting unit 12040, the microcomputer 12051 calculates control target values of the driving force generating device, the steering mechanism, or the braking device, and is able to output a control command to the drive system control unit 12010. For example, the microcomputer 12051 is able to perform cooperative control for realizing an advanced driver assistance system (ADAS: advanced driver assistance system) function including collision avoidance or impact mitigation of the vehicle, follow-up running based on an inter-vehicle distance, vehicle speed maintenance running, vehicle collision warning, and lane departure warning of the vehicle, and the like.

[0208] In addition, the microcomputer 12051 is able to control the driving force generating device, the steering mechanism, and the braking device, and the like, based on information about the vicinity of the vehicle acquired by the outside information detecting unit 12030 or the inside information detecting unit 12040, thereby performing cooperative control for realizing autonomous driving of the vehicle independently of the operation of the driver, and the like.

[0209] In addition, based on information about the outside of the vehicle acquired by the outside information detecting unit 12030, the microcomputer 12051 is able to output a control command to the body system control unit 12020. For example, the microcomputer 12051 is able to control a headlamp in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside information detecting unit 12030, thereby performing cooperative control for realizing glare protection, such as switching a high beam to a low beam.

[0210] The sound image output unit 12052 transmits an output signal of at least one of a sound and an image to an output device that is able to visually or aurally notify a passenger on the vehicle or outside of the vehicle of information. In Figure 30 Examples of the output device are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 can include at least one of a vehicle-mounted display or a head-up display, for example.

[0211] Figure 31 FIG. 12 is a diagram showing an example of a mounting position of the imaging unit 12031.

[0212] In Figure 31 , as the imaging unit 12031, an imaging unit 12101, 12102, 12103, 12104, and 12105 are provided.

[0213] For example, the imaging units 12101, 12102, 12103, 12104, and 12105 are installed at positions such as the front nose, the side mirrors, the rear bumper, the rear door, and the upper portion of the windshield of the vehicle 12100. The imaging unit 12101 provided to the front nose and the imaging unit 12105 provided to the upper portion of the windshield in the vehicle interior mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided to the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided to the rear bumper or the rear door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided to the upper portion of the windshield in the vehicle interior can be mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, and the like.

[0214] Further, Figure 31 Examples of the imaging ranges of the imaging units 12101 to 12104 are shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided to the front nose, the imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided to the side mirrors, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided to the rear bumper or the rear door. For example, when a plurality of pieces of image data imaged by the imaging units 12101 to 12104 are superimposed, an overhead image when the vehicle 12100 is viewed from above can be obtained.

[0215] At least one of the imaging units 12101 to 12104 can have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 can be a stereo camera including a plurality of imaging elements, or can be an imaging element including pixels for phase difference detection.

[0216] For example, the microcomputer 12051 can obtain distances to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in the distances over time (relative speeds with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging units 12101 to 12104, and thereby extract, as a preceding vehicle, a three-dimensional object that is closest to the vehicle 12100 on a travel road and travels at a predetermined speed (for example, greater than or equal to 0 km / h) in almost the same direction as the vehicle 12100. Further, the microcomputer 12051 can pre-set a vehicle-to-vehicle distance to be maintained in front of the preceding vehicle, and perform automatic brake control (also including follow-up stop control) and automatic acceleration control (also including follow-up acceleration control), and the like. As described above, cooperative control for realizing automatic driving in which the vehicle autonomously travels without depending on the operation of the driver, or the like, can be performed.

[0217] For example, the microcomputer 12051 is able to classify pieces of three-dimensional object data related to three-dimensional objects into data of two-wheeled vehicles, data of standard vehicles, data of large vehicles, data of pedestrians, and data of other three-dimensional objects such as utility poles, on the basis of distance information obtained from the imaging units 12101 to 12104, thereby extract the three-dimensional object data, and is able to use the three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be visually recognized by a driver of the vehicle 12100 and obstacles that are difficult to visually recognize. In addition, the microcomputer 12051 determines a collision risk that indicates a degree of danger of collision with each obstacle. In a case where the collision risk is equal to or greater than a set value and a collision is likely to occur, the microcomputer 12051 is able to output a warning to the driver through the audio speaker 12061 or the display unit 12062, or perform forced deceleration or evasive steering through the drive system control unit 12010, thereby assisting driving to avoid a collision.

[0218] At least one of the imaging units 12101 to 12104 can be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 is able to recognize a pedestrian by determining whether the pedestrian is present in an image captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting a specific point in an image captured by the imaging units 12101 to 12104 that are infrared cameras, and determining whether an object represented by a series of specific points that are contour lines is a pedestrian by pattern matching processing. When the microcomputer 12051 determines that a pedestrian is present in an image captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the sound image output unit 12052 controls the display unit 12062 so that a rectangular contour line for emphasis is superimposed and displayed on the recognized pedestrian. In addition, the sound image output unit 12052 can also control the display unit 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0219] In the foregoing, an explanation has been given of an example of a vehicle control system to which the technology according to the present disclosure is applicable. The technology according to the present disclosure is applicable to the imaging unit 12031 and the driver state detection unit 12041 and the like in the above-described configuration.

[0220] In the foregoing, while an embodiment of the present disclosure has been explained, the technical scope of the present disclosure is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present disclosure. In addition, the configuration elements in other embodiments and modified examples can also be appropriately combined.

[0221] In addition, the effects in the embodiments described in this specification are merely exemplary and there can be additional effects without being limited.

[0222] Further, the present technology can adopt the following configuration. (1)

[0224] An imaging device comprising:

[0225] a pixel array unit, wherein the pixel array unit includes a plurality of pixel groups, wherein each pixel group includes:

[0226] a plurality of unit pixels, wherein the plurality of unit pixels includes at least a first unit pixel and a second unit pixel;

[0227] a plurality of photoelectric conversion regions, wherein each unit pixel includes at least one of the photoelectric conversion regions;

[0228] a first readout circuit selectively connected to the plurality of photoelectric conversion regions;

[0229] a second readout circuit selectively connected to the plurality of photoelectric conversion regions; and

[0230] a separation structure, wherein the separation structure separates the first unit pixel from the second unit pixel. (2)

[0232] The imaging device according to (1), wherein the separation structure includes a deep trench separation structure portion. (3)

[0234] The imaging device according to (1) or (2), wherein the separation structure includes a full-thickness trench separation structure portion. (4)

[0236] The imaging device according to (1), wherein the separation structure is entirely a deep trench separation structure. (5)

[0238] The imaging device according to any one of (1) to (4), wherein the second readout circuit is an address event detection readout circuit. (6)

[0240] The imaging device according to any one of (1) to (5), wherein the first readout circuit is an imaging signal generation circuit. (7)

[0242] The imaging device according to any one of (1) to (6), further comprising:

[0243] A substrate, wherein the photoelectric conversion element is formed in the substrate, wherein a first surface of the substrate is a light incident surface, wherein a second surface of the substrate is a non-light incident surface, and wherein at least a portion of elements of at least one of the first readout circuit and the second readout circuit is formed between an end of the deep trench isolation structure and the second surface of the substrate. (8)

[0245] The imaging device according to any one of (1) to (7), wherein the photoelectric conversion region of the first unit pixel is selectively connected to the imaging signal generation circuit through a first unit pixel transfer transistor and a pixel group transfer transistor, and wherein the photoelectric conversion region of the second unit pixel is selectively connected to the imaging signal generation circuit through a second unit pixel transfer transistor and the pixel group transfer transistor. (9)

[0247] The imaging device according to (8), wherein the photoelectric conversion region of the first unit pixel is selectively connected to the address event detection readout circuit through the first unit pixel transfer transistor and a pixel group overflow gate transistor, and wherein the photoelectric conversion region of the second unit pixel is selectively connected to the address event detection readout circuit through the second unit pixel transfer transistor and the pixel group overflow gate transistor. (10)

[0249] The imaging device according to any one of (1) to (7), wherein the photoelectric conversion region of the first unit pixel is selectively connected to the imaging signal generation circuit through a first unit pixel transfer transistor, and wherein the photoelectric conversion region of the second unit pixel is selectively connected to the imaging signal generation circuit through a second unit pixel transfer transistor. (11)

[0251] The imaging device according to (10), wherein the photoelectric conversion region of the first unit pixel is selectively connected to the address event detection readout circuit through a first unit pixel overflow gate transistor, and wherein the photoelectric conversion region of the second unit pixel is selectively connected to the address event detection readout circuit through a second unit pixel overflow gate transistor. (12)

[0253] The imaging device according to any one of (1) to (11), wherein each pixel group further includes a third unit pixel and a fourth unit pixel, and wherein the first unit pixel, the second unit pixel, and the third unit pixel are arranged in a 2x2 array. (13)

[0255] The imaging device of (12), wherein each group of pixels is separated from an adjacent group of pixels by a full-thickness trench separation structure. (14)

[0257] The imaging device of (12) or (13), wherein the separation structure separating the first unit pixel from the second unit pixel is a first separation structure, wherein the first separation structure separates the third unit pixel from the fourth unit pixel, wherein a second separation structure separates the first unit pixel from the third unit pixel, wherein the second separation structure separates the second unit pixel from the fourth unit pixel, and wherein the second separation structure intersects the first separation structure. (15)

[0259] The imaging device of (14), wherein the first separation structure is entirely a deep trench separation structure, and wherein the second separation structure is entirely a deep trench separation structure. (16)

[0261] The imaging device of (14), wherein the first separation structure is entirely a deep trench separation structure, wherein at least a first portion of the second separation structure is a deep trench separation structure, and wherein at least a second portion of the second separation structure is a full-thickness separation structure. (17)

[0263] The imaging device of (14), wherein at least a first portion of the first separation structure is a deep trench separation structure, wherein at least a second portion of the first separation structure is a full-thickness separation structure, and wherein the second separation structure is entirely a deep trench separation structure. (18)

[0265] The imaging device of (14), wherein at least a first portion of the first separation structure is a deep trench separation structure, wherein at least a second portion of the first separation structure is a full-thickness separation structure, wherein at least a first portion of the second separation structure is a deep trench separation structure, and wherein at least a second portion of the second separation structure is a full-thickness separation structure. (19)

[0267] An electronic device comprising:

[0268] an imaging lens; and

[0269] a solid-state imaging device comprising:

[0270] a pixel array unit, wherein the imaging lens lets incident light pass through the pixel array unit, wherein the pixel array unit includes a plurality of pixel groups, wherein each pixel group includes:

[0271] a plurality of unit pixels, wherein the plurality of unit pixels includes at least a first unit pixel and a second unit pixel;

[0272] a plurality of photoelectric conversion regions, wherein each unit pixel includes at least one of the photoelectric conversion regions;

[0273] a first readout circuit selectively connected to the plurality of photoelectric conversion regions;

[0274] a second readout circuit selectively connected to the plurality of photoelectric conversion regions; and

[0275] a separation structure, wherein the separation structure separates the first unit pixel from the second unit pixel.

[0276] Those skilled in the art will understand that various modifications, combinations, sub-combinations, and changes can be made to the embodiments without departing from the scope of the appended claims or their equivalents.

Claims

1. An imaging device comprising: a pixel array unit, wherein the pixel array unit comprises a plurality of pixel groups, wherein each pixel group comprises: a plurality of unit pixels, wherein the plurality of unit pixels comprises at least a first unit pixel and a second unit pixel; a plurality of photoelectric conversion regions, wherein each unit pixel comprises at least one of the photoelectric conversion regions; a first readout circuit that is an imaging signal generation circuit and is selectively connected to the plurality of photoelectric conversion regions; a second readout circuit that is an address event detection readout circuit and is selectively connected to the plurality of photoelectric conversion regions; a separation structure, wherein the separation structure separates the first unit pixel from the second unit pixel and comprises a deep trench separation structure portion; and a substrate, wherein the photoelectric conversion regions are formed in the substrate, wherein a first surface of the substrate is a light incident surface, wherein a second surface of the substrate is a non-light incident surface, the deep trench separation structure portion extends from a first end at or above the first surface to a second end formed toward the second surface, and wherein at least a portion of elements of at least one of the first readout circuit and the second readout circuit are formed between the second end of the separation structure and the second surface of the substrate.

2. The camera according to claim 1, wherein The separation structure further comprises a full-thickness trench separation structure portion.

3. The camera of claim 1, wherein The photoelectric conversion regions of the first unit pixel are selectively connected to the imaging signal generation circuit through a first unit pixel transfer transistor and a pixel group transfer transistor, and wherein the photoelectric conversion regions of the second unit pixel are selectively connected to the imaging signal generation circuit through a second unit pixel transfer transistor and the pixel group transfer transistor.

4. The camera of claim 3, wherein, The photoelectric conversion regions of the first unit pixel are selectively connected to the address event detection readout circuit through the first unit pixel transfer transistor and a pixel group overflow gate transistor, and wherein the photoelectric conversion regions of the second unit pixel are selectively connected to the address event detection readout circuit through the second unit pixel transfer transistor and the pixel group overflow gate transistor.

5. The camera of claim 1, wherein The photoelectric conversion regions of the first unit pixel are selectively connected to the imaging signal generation circuit through a first unit pixel transfer transistor, and wherein the photoelectric conversion regions of the second unit pixel are selectively connected to the imaging signal generation circuit through a second unit pixel transfer transistor.

6. The camera of claim 5, wherein, The photoelectric conversion regions of the first unit pixel are selectively connected to the address event detection readout circuit through a first unit pixel overflow gate transistor, and wherein the photoelectric conversion regions of the second unit pixel are selectively connected to the address event detection readout circuit through a second unit pixel overflow gate transistor.

7. The image pickup device according to any one of claims 1 to 5, wherein Each pixel group further comprises a third unit pixel and a fourth unit pixel, and wherein the first unit pixel, the second unit pixel, the third unit pixel, and the fourth unit pixel are arranged in a 2x2 array.

8. The camera of claim 7, wherein, Each pixel group is separated from an adjacent pixel group by a full-thickness trench separation structure.

9. The camera of claim 8, wherein, The separation structure separating the first unit pixel from the second unit pixel is a first separation structure, wherein the first separation structure separates the third unit pixel from the fourth unit pixel, wherein a second separation structure separates the first unit pixel from the third unit pixel, wherein the second separation structure separates the second unit pixel from the fourth unit pixel, and wherein the second separation structure intersects the first separation structure.

10. The camera of claim 9, wherein, The first separation structure is entirely a deep trench separation structure, and wherein the second separation structure is entirely a deep trench separation structure.

11. The camera of claim 9, wherein, The first separation structure is entirely a deep trench separation structure, wherein at least a first portion of the second separation structure is a deep trench separation structure, and wherein at least a second portion of the second separation structure is a full thickness separation structure.

12. The camera of claim 9, wherein, At least a portion of the first separation structure is a deep trench separation structure, wherein at least a second portion of the first separation structure is a full thickness separation structure, and wherein the second separation structure is entirely a deep trench separation structure.

13. The camera of claim 9, wherein, At least a portion of the first separation structure is a deep trench separation structure, wherein at least a second portion of the first separation structure is a full thickness separation structure, wherein at least a first portion of the second separation structure is a deep trench separation structure, and wherein at least a second portion of the second separation structure is a full thickness separation structure.

14. An electronic device comprising: an imaging lens; and a solid-state image pickup device according to any one of claims 1 to 13, wherein the imaging lens passes incident light through the pixel array unit.

Images