Asymmetric pipeline fifo process based on elastic buffers

Abstract

The invention is entitled "Asymmetric Pipeline FIFO Process Based on Elastic Buffering." The present disclosure relates generally to efficient management of elastic buffers. Efficient management can be achieved through the use of an asymmetric asynchronous first-in-first-out (FIFO) method based on write pointer and read pointer normalization. Normalization is done according to FIFO depth while maintaining a single bit change method. To achieve a parts-per-million (PPM) compensated asymmetric dynamic capability, multiple sub-FIFOs are used for relative side pointer synchronization. Combining these features allows for the creation of an asynchronous asymmetric FIFO with pipeline characteristics.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 085035, filed on September 29, 2020, which is incorporated herein by reference. Background Technology Technical Field

[0003] The implementation scheme disclosed herein relates to effective management of resilient buffers.

[0004] Description of the Related Art

[0005] High-speed interfaces are now commonly used in any solid-state drive (SSD) product; typical protocols include SATA, PCIe, and SAS. Each high-speed protocol transmits data in serial differential signaling. Clock data recovery (CDR) circuitry is responsible for deriving the serial data and clock from the data stream. Both the transmitting and receiving ends use independent reference clock sources. Frequency differences may occur due to the difference between the recovered frequency and the local frequency. To ensure the correctness of the received data and timing synchronization between the recovered clock and the local clock, a resilient buffer is used to compensate for the clock difference between the transmitting and receiving points. The resilient buffer is used to absorb latency and latency variations caused by software parsing or other types of transmission over the physical medium in a manner acceptable to the protocol specification.

[0006] There are two main elastic buffer operating modes: nominally empty and half-full. Nominally empty removes all available specific predefined (SKP) symbols and continuously strives to empty. Half-full is designed to operate in the middle of the dynamic memory range to ensure that positive or negative biases are absorbed without compromising the continuity of the data stream, such as... Figure 1 As shown.

[0007] In PCIe, clock compensation targets are achieved by adding or removing SKP symbols as part of an ordered set of SKP symbols, where each set comprises one to five SKP symbols. Depending on memory fill, elastic buffer logic removes or adds SKP symbols to approximate the average value as closely as possible.

[0008] As mentioned above, the clock recovered by the CDR and the local clock are asynchronous. To ensure the quality of the received data stream, a synchronization method is used between the independent clock domains. Typically, an asynchronous first-in-first-out (FIFO) method with Gray code conversion mode is used for single-bit switching to reduce the impact of mean bit failure time (MTBF).

[0009] Two factors are required for proper use of Gray coding. The first factor is that the storage depth must be aligned to a power of two (i.e., 2, 4, 8, 16, 32, etc.), which is negligible for low depth FIFOs, but can have a significant hardware (HW) consumption impact in the case of FIFOs with large depth. For example, a FIFO with a depth of 129 entries must be scaled up to 256 entries. The second factor is that each write operation (sometimes referred to as a "push" operation) is only allowed a single entry. The number of dynamic values of entries at a single "push" is not allowed.

[0010] The elastic buffer must be able to absorb the parts per million (PPM) variations caused by the spread spectrum clock (SSC) mechanism. In other words, the dynamic range of the elastic buffer memory must be wide enough for effective compensation, and the memory needs to be rounded to a power of two, which in most cases will make the situation worse from a HW consumption perspective.

[0011] Due to the symbol-based data resolution, the elastic buffer must efficiently and reliably add and drop SKP symbols, as shown in Figure 2 Due to the Gray code limitation, the dynamic increase of the write pointer and the read pointer is not allowed, which requires the use of handshake FIFOs or FIFO chaining, which in turn causes an increase in the addition of HW resources and data path latency.

[0012] Therefore, there is a need in the art for a more efficient method for elastic buffer memory management. SUMMARY

[0013] The present disclosure generally relates to efficient management of elastic buffers. Efficient management can be achieved by using an asymmetric asynchronous first-in-first-out (FIFO) method based on write pointer and read pointer normalization. Normalization is done according to FIFO depth while maintaining a single bit change method. To achieve the asymmetric dynamic capability of parts per million (PPM) compensation, multiple sub-FIFOs are used for relative side pointer synchronization. Combining these features allows the creation of an asynchronous asymmetric FIFO with pipeline characteristics.

[0014] In one embodiment, a data storage device includes one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to transfer data to a host device according to an asynchronous asymmetric first-in-first-out (FIFO) process.

[0015] In another embodiment, a data storage device includes one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller includes a main first-in-first-out (FIFO) chip; a write FIFO chip coupled to the main FIFO chip; a readout FIFO chip coupled to the main FIFO chip; an array of write sub-FIFO chips, wherein the array of write sub-FIFO chips is coupled to the write FIFO chip and the readout FIFO chip; and an array of readout sub-FIFO chips, wherein the array of readout sub-FIFO chips is coupled to the write FIFO chip and the readout FIFO chip.

[0016] In another embodiment, a data storage device includes means for storing data; and a controller coupled to the means for storing data, wherein the controller is configured to: calculate a minimum index value; calculate a maximum index value; and synchronize indices of a read pointer and a write pointer based on the calculated minimum index value and maximum index value. BRIEF DESCRIPTION OF DRAWINGS

[0017] So that the manner in which the above recited features of the present disclosure are attained and understood can be readily understood, a more detailed description of the present disclosure can be had by reference to the embodiments thereof that are illustrated in the attached drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure can admit to other equally effective embodiments.

[0018] Figure 1 is a schematic diagram of the operating principle of a resilient buffer operating in half-full mode according to the disclosed embodiments.

[0019] Figure 2 is a schematic diagram of asymmetric entries for a write pointer and a read pointer in a resilient buffer according to the disclosed embodiments.

[0020] Figure 3 is a schematic diagram of a storage system according to the disclosed embodiments.

[0021] Figure 4 shows a comparison between unnormalized Gray-coded values and normalized Gray-coded values of the disclosed embodiments.

[0022] Figure 5 shows an example of multiple entries for a push operation and a pop operation according to the disclosed embodiments.

[0023] Figure 6is a schematic diagram of logic for a sub-FIFO method based on an asynchronous FIFO according to the disclosed embodiments.

[0024] Figure 7 is a schematic diagram of the elastic buffer behavior based on a FIFO with sub-FIFO synchronization for out-of-stack operations and in-of-stack operations according to the disclosed embodiments.

[0025] To facilitate an understanding of this description, like reference characters are used to identify like elements throughout the service drawings. It is contemplated that elements disclosed in one embodiment can be advantageous ly used in other embodiments without specific recitation. DETAILED DESCRIPTION

[0026] In the following, reference is made to the embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. Rather, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the present disclosure. Additionally, although the embodiments of the present disclosure can achieve advantages over other possible solutions and / or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not a limitation of the present disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims, unless specifically recited therein. Likewise, reference to "the disclosure" should not be interpreted as an identification of any specific invention, nor should the description be interpreted as an entire explanation of any invention subject matter disclosed herein, unless specifically recited in the claims.

[0027] The present disclosure generally relates to the efficient management of elastic buffers. Efficient management can be achieved through the use of an asymmetric asynchronous first-in-first-out (FIFO) method based on write pointer and read pointer normalization. Normalization is done according to FIFO depth while maintaining a single bit change method. To achieve a millionth of a percent (PPM) compensated asymmetric dynamic capability, multiple sub-FIFOs are used for relative side pointer synchronization. Combining these features allows for the creation of an asynchronous asymmetric FIFO with pipe characteristics.

[0028] Figure 1 is a schematic diagram of the operating principle of an elastic buffer operating in a half-full mode according to the disclosed embodiments. The elastic buffer operating in a half-full mode is intended to work in the middle of the dynamic memory range in order to ensure the absorption of any positive or negative deviation does not impede the continuity of the data flow. In other words, the elastic buffer operating in a half-full mode attempts to maintain any generated latency, such as those generated between a positive latency range and a negative latency range by transmission over a physical medium, software parsing, etc. It should be understood that other elastic buffer operating modes are contemplated, such as nominal empty, and can be applicable to the embodiments described herein.

[0029] In Figure 1 In some cases, the time delay can be negligible. However, in other cases, the time delay can be large enough to cause non-optimal effects, such as causing a bottleneck.

[0030] The time delay between the positive time delay range and the negative time delay range is considered the average time delay and is shown by the dashed line. The generated time delay is shown by the transmission time delay curve 102. To achieve the time delay around the average time delay dashed line, a compensation time delay shown by the compensation time delay curve 104 is added or removed in response to the generated time delay. The resulting curve is the average time delay curve 106. The average time delay curve 106 (i.e., the clock compensation target) can be achieved by adding or removing specific pre-defined (SKP) symbols that are part of a SKP ordered set. In some embodiments, each set of SKP ordered sets includes from about one to about five SKP symbols.

[0031] For example, at time "A", the transmission time delay curve 102 has a negative time delay. To compensate for the negative time delay and return the average time delay curve 106 to the average time delay dashed line, SKP symbols can be added to the recovered clock (i.e., the clock associated with the compensation time delay curve 104), thereby adding positive time delay to the compensation time delay curve 104. At time "B", the transmission time delay curve 102 becomes more positive, and SKP symbols can be removed so that the change in the compensation time delay curve 104 matches the change in the transmission time delay curve 102.

[0032] Similarly, at time "C", the transmission time delay curve 102 has a positive time delay, such that the compensation time delay should be a negative time delay to maintain the average time delay. Accordingly, SKP symbols are removed from the recovered clock to generate a negative compensation time delay, as shown by the compensation time delay curve 104. At time "D", the average time delay curve 106 is slightly offset from the average time delay dashed line. However, due to the addition and removal of SKP symbols from the recovered clock, the magnitude of the offset is minimized. Times "E", "F", and "G" show the more robust addition and removal of SKP symbols from the recovered clock in response to changes in the transmission time delay as shown by the transmission time delay curve 102, as shown by the compensation time delay curve 104.

[0033] Figure 2 is a schematic diagram of asymmetric entries for a write pointer and a read pointer in a resilient buffer according to the disclosed embodiments. The resilient buffer, such as the resilient buffer 100, can include a write pointer 202 and a read pointer 204. The write pointer 202 and the read pointer 204 can be implemented as a single pointer, such as the write pointer 202 and the read pointer 204 shown in FIG. 2. In some embodiments, the write pointer 202 and the read pointer 204 can be implemented as separate pointers. Figure 1Elastic buffers operating in semi-full mode (e.g., elastic buffers for a USB 3.0 device) can need to be able to absorb parts-per-million (PPM) variations due to spread spectrum clock (SSC) mechanisms. SSC mechanisms are used to reduce radiated emissions of digital clock signals by changing the frequency of the clock signal in a controlled manner. In other words, the dynamic range of the elastic buffer memory can need to be large enough to account for the dynamic changes of the SSC mechanisms.

[0034] To reduce mean time between failures (MTBF) impact, an asynchronous first-in-first-out (FIFO) approach can be utilized in conjunction with a Gray code transition mode. In the FIFO approach, a first element received (such as a first data) is the first element sent. Likewise, a second element received is the second element sent. However, the asynchronous FIFO approach in conjunction with the Gray code transition mode can only receive a single data variation, such as a single SKP symbol or an increase or decrease in data. Receiving more than a single data variation (such as multiple SKP symbols) can cause the Gray code transition mode to have reduced performance.

[0035] In Figure 2 , asymmetric entries for a write pointer and a read pointer in an elastic buffer are shown. The write pointer is indicated by a plurality of push operations 202, 204, 206, 208 and the read pointer is indicated by a plurality of pop operations 210, 212, 214, 216. Each of the plurality of push operations 202, 204, 206, 208 and each of the plurality of pop operations 210, 212, 214, 216 has eight possible entries that can be filled by data or an SKP symbol. The number of possible entries listed is not intended to be limiting, but to provide an example of possible implementations. The maximum number of possible entries is defined by the memory depth, where the memory depth is aligned to a "power of two." For example, the maximum number of possible entries can be any number that satisfies the following equation: maximum number of possible entries = 2 x where "x" refers to any appropriate integer value. For example, in Figure 2 the implementation shown, when x = 3, the maximum number of possible entries is equal to 8 because 2 3 = 8 or 2*2*2 = 8, where the number of entries is equal to or less than 8.

[0036] The first push operation 202 includes 6 elements (NoEs), where 4 of the 6 NoEs are associated with data (1-4) and the remaining 2 of the 6 NoEs are associated with SKP symbols. The second push operation 204 includes 4 NoEs, where all 4 NoEs are associated with data (5-8). The third push operation 206 includes 5 NoEs, where 4 of the 5 NoEs are associated with data (9-12) and the remaining 1 of the 5 NoEs is associated with an SKP symbol. The fourth push operation 208 includes 1 NoE, where the 1 NoE is associated with data (13).

[0037] During the third push operation 206, a first pop operation 210 occurs, where the first pop operation 210 includes 4 NoEs. The 4 NoEs of the first pop operation 210 are associated with data (1-4). Similarly, during the fourth push operation 208, a second pop operation 212 occurs, where the second pop operation 212 includes 4 NoEs. 2 of the 4 NoEs of the second pop operation 212 are associated with SKP symbols and the remaining 2 of the 4 NoEs of the second pop operation are associated with data (5-6). A third pop operation 214 includes 2 NoEs, where the 2 NoEs are associated with data (7-8). A fourth pop operation 216 includes 6 NoEs, where 5 of the 6 NoEs are associated with data (9-13) and the remaining 1 of the 6 NoEs is associated with an SKP symbol. Because the NoEs can increase by more than 1 when moving from a push operation to a push operation, such as between the first push operation 202 and the second operation 204, or from a pop operation to a pop operation, such as between the third pop operation 214 and the fourth pop operation 216, the Gray coding pattern can be inefficient in handling the dynamic increase of the read and / or write pointers from a push operation to a push operation or from a pop operation to a pop operation.

[0038] Figure 3 is a schematic block diagram illustrating a storage system 300 in accordance with the disclosed embodiments, where a data storage device 304 can be used as a storage device for a host device 302. For example, the host device 302 can utilize a non-volatile memory (NVM) 314 included in the data storage device 304 to store and retrieve data. The host device 302 can include host DRAM to temporarily store data to be sent to the data storage device 304. In some examples, the storage system 300 can include multiple storage devices, such as the data storage device 304, which can work as a storage array. For example, the storage system 300 can include multiple data storage devices 304 configured as a redundant array of inexpensive / independent disks (RAID) working together as a mass storage device for the host device 302.

[0039] Host device 302 can store data to and / or retrieve data from one or more storage devices (such as data storage device 304). Figure 3 As shown, host device 302 can communicate with data storage device 304 via interface (I / F) 306. Host device 302 can include any of a variety of devices, including computer servers, network attached storage (NAS) units, desktop computers, laptops, tablets, set-top boxes, mobile phones such as so-called "smart" phones, so-called "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending or receiving data from the data storage device.

[0040] Data storage device 304 includes a controller 308, an NVM 314, volatile memory 310, an interface 306, and a buffer 312. In some examples, for clarity, data storage device 304 may include... Figure 3 Additional components not shown. For example, data storage device 304 may include a printed circuit board (PCB) to which components of data storage device 304 are mechanically attached, and the PCB includes conductive traces for electrically interconnecting components of data storage device 304, etc. In some examples, the physical dimensions and connector configuration of data storage device 304 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 3.5” data storage devices (e.g., HDDs or SSDs), 2.5” data storage devices, 1.8” data storage devices, peripheral component interconnects (PCI), PCI expansion (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini cards, MiniPCI, etc.). In some examples, data storage device 304 may be directly coupled (e.g., directly soldered) to the motherboard of host device 302.

[0041] The interface 306 of the data storage device 304 can include one or both of a data bus for exchanging data with the host device 302 and a control bus for exchanging commands with the host device 302. The interface 306 can operate according to any suitable protocol. For example, the interface 306 can operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. Electrical connections of the interface 306 (e.g., the data bus, the control bus, or both) are electrically connected to the controller 308, providing electrical connections between the host device 302 and the controller 308, allowing data to be exchanged between the host device 302 and the controller 308. In some examples, the electrical connections of the interface 306 can also allow the data storage device 304 to receive power from the host device 302.

[0042] The NVM 314 can include a plurality of memory devices or storage units. The NVM 314 can be configured to store and / or retrieve data. For example, a storage unit of the NVM 314 can receive data and receive a message from the controller 308 instructing the storage unit to store the data. Similarly, a storage unit of the NVM 314 can receive a message from the controller 308 instructing the storage unit to retrieve data. In some examples, each of the storage units can be referred to as a die. In some examples, a single physical chip can include multiple dies (i.e., multiple storage units). In some examples, each storage unit can be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0043] In some examples, each storage unit of the NVM 314 can include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0044] The NVM 314 can include a plurality of flash memory devices or storage units. The NVM flash memory devices can include NAND or NOR based flash memory devices and can store data based on electric charges contained in a floating gate of a transistor for each flash memory unit. In NVM flash memory devices, a flash memory device can be divided into a plurality of dies, where each of the plurality of dies includes a plurality of blocks that can be further divided into a plurality of pages. Each of the plurality of blocks within a particular memory device can include a plurality of NVM cells. Rows of NVM cells can be electrically connected using word lines to define a page of the plurality of pages. Respective cells in each of the plurality of pages can be electrically connected to a respective bit line. Further, the NVM flash memory devices can be 2D or 3D devices and can be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller 108 can write data to and read data from the NVM flash memory devices at a page level and erase data from the NVM flash memory devices at a block level of data.

[0045] The data storage device 304 also includes a volatile memory 310 that can be used by the controller 308 to store information. The volatile memory 310 can include one or more volatile memory devices. In some examples, the controller 308 can use the volatile memory 310 as a cache. For example, the controller 308 can store cached information in the volatile memory 310 until the cached information is written to the non-volatile memory 314. Examples of volatile memory 310 include, without limitation, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.).

[0046] Data storage device 304 includes a controller 308 that can manage one or more operations of data storage device 304. For example, controller 308 can manage reading data from NVM 314 and / or writing data to NVM 314. In some embodiments, when data storage device 304 receives a write command from host device 302, controller 308 can initiate a data storage command to store data to NVM 314 and monitor the progress of the data storage command. Controller 308 can determine at least one operational characteristic of storage system 300 and store at least one operational characteristic to NVM 314. In some embodiments, when data storage device 304 receives a write command from host device 302, controller 308 temporarily stores data associated with the write command in internal memory or buffer 312 before sending the data to NVM 314. In other embodiments, controller 308 may be configured to transfer data to host device 302 according to an asynchronous asymmetric FIFO process.

[0047] Figure 4 A comparison is shown between the unnormalized Gray code value 400 and the normalized Gray code value 450 according to the disclosed embodiment. Unnormalized Gray code values ​​are "powers of 2" numbers, such as... Figure 2 The "power of 2" numbers mentioned above. For low-depth FIFO depths, rounding to the nearest power of 2 value is negligible. For example, when the required depth is 7, the nearest power of 2 value is 8, where rounding the required depth to the next nearest power of 2 value increases the required depth by a minimum, or in this example, by 1. However, for high-depth FIFO depths, rounding to the nearest power of 2 value can lead to a large hardware utilization impact. For example, when the required depth is 224, the nearest power of 2 value is 256 (224 is 7 / 8 of 256). The required depth increases by 32.

[0048] In Gray coding mode, a single bit can change each time NoE increments. For example, in the unnormalized Gray code value 400, as N=0 increments to N=1, the Gray code value changes from 0000 to 0001, indicating a single bit change. When the index counter is 14 (N=0), reading the fifteenth value causes the index counter to return from N=13 to N=0 because the required rounding depth is rounded to the next nearest power of 2 (which is 16). When N=13, the Gray code value is 1011. When returning to N=0, the Gray code value is 0000. Therefore, Gray coding mode can have reduced reliability or reduced performance because it may not be able to handle more than a single bit change.

[0049] However, by normalizing the FIFO depth of both the read and write pointers, an asynchronous asymmetric FIFO with pipelined characteristics can be generated by the controller of the data storage device. Controllers (such as...) Figure 3 The controller 308 can transmit data to the host device (such as...) according to the asynchronous asymmetric FIFO. Figure 3 The host device 302) of the asynchronous asymmetric FIFO has a pipelined process that satisfies the requirement of a Gray coding pattern that changes only a single bit for each increment. The asynchronous asymmetric FIFO process includes a minimum index value and a maximum index value. The minimum index value and the maximum index value are the lower and upper limits, respectively, of an intermediate range that can cover a depth of "power of 2".

[0050] In one example, the minimum index value is calculated using the formula: ((required depth raised to the power of 2) / 2) - (required depth / 2), where the required depth is twice the number of index entries to account for both full and empty states, and the power of 2 is an even number in a geometric series starting at 2 with a common ratio of 2. For example, when the required depth is 7, twice the required depth raised to the power of 2 is 16. Substituting the value into the formula results in (16 / 2) - (14 / 2), or a minimum index value of 1.

[0051] The maximum index value is calculated using the following formula: ((required depth raised to the power of 2) / 2) + (required depth / 2) - 1, where the required depth is twice the number of index entries to account for both full and empty states, and the power of 2 is an even number in a geometric series starting from 2 with a common ratio of 2. For example, when the required depth is 7, twice the required depth raised to the power of 2 is 16. Substituting the value into the formula results in (16 / 2) + (14 / 2) - 1, or a maximum index value of 14.

[0052] As shown in the normalized Gray code value 450, when N = 14 (maximum index value), the Gray code value is 1001. When the depth increases by 1, the value of N equals 1 (minimum index value) and the resulting Gray code value is 0001, which satisfies the maximum value requirement for single-bit variation.

[0053] In another example, when the required depth is 6, the minimum index value is 2 and the maximum index value is 13, indicating the upper and lower limits of the "power of 2" depth. As shown in the normalized Gray code value 450, when N = 13 (maximum index value), the Gray code value is 1011. When the depth increases by 1, the value of N equals 2 (minimum index value) and the resulting Gray code value is 0011, which satisfies the maximum value required for a single bit change.

[0054] In yet another example, when the required depth is 5, then the minimum index value is 3 and the maximum index value is 12, indicating the upper and lower bounds of the "power of 2" depth. As shown by the normalized Gray-coded value 450, when N = 12 (the maximum index value), the Gray-coded value is 1010. When the depth is increased by 1, the N value equals 3 (the minimum index value) and the resulting Gray-coded value is 0010, which satisfies the maximum value of the single bit change requirement.

[0055] Figure 5 Examples of a number of entries for a push operation 500 and a pop operation 550 are shown in accordance with the disclosed embodiments. To ensure the reliability and quality of data during cross-domain crossing (CDC), the index of the read pointer should be synchronized with the write pointer on the opposite side for empty or full state detection. Further, the CDC can be able to handle a dynamic number of entries during the push or pop operation. In some embodiments, the push operation clock period and the pop operation clock period can be offset.

[0056] For example, in the first clock cycle of the push operation 500, 3 of the 8 available entries are pushed. Since 3 entries are pushed, the number of push slots decreases from 8 to 5 and the push write index increases to 3. After the push operation is completed, as shown, the pop read index increases from 0 to 2 when the push empty slots increase from 5 to 7.

[0057] Likewise, during the pop operation 550, 2 of the 8 entries are popped at a second clock cycle, where the second clock cycle is different from the first clock cycle, and 1 of the 8 entries is popped at a third clock cycle, where the third clock cycle occurs after the second cycle. Because the push operation 500 includes 3 push entries, the pop busy slots are 3. However, when 2 of the 8 entries are popped, the push read index is 2. After 2 of the 8 pop entries are completed, the pop busy slots decrease to 1 due to the 1 remaining pop entry to be completed. When the remaining 1 pop entry is completed, the push read index increases to 3.

[0058] Figure 6 A schematic diagram of logic 600 for a sub-FIFO method based on an asynchronous FIFO in accordance with the disclosed embodiments. A controller (such as a processor) 610 is coupled to a memory 620. The memory 620 includes a sub-FIFO 630 and a sub-FIFO 640. The sub-FIFO 630 includes a push operation 650 and a pop operation 660. The sub-FIFO 640 includes a push operation 670 and a pop operation 680. Figure 3The controller 308) can include logic 600. The controller includes: a master FIFO chip 602; a write FIFO chip 604 coupled to the master FIFO chip 602; a read FIFO chip 606 coupled to the master FIFO chip 602; a write sub-FIFO array 608 coupled to both the write FIFO chip 604 and the read FIFO chip 606; and a read sub-FIFO array 610 coupled to both the write FIFO chip 604 and the read FIFO chip 606. In some embodiments, the master FIFO chip 602 is a dual port random access memory (RAM). The write sub-FIFO array 608 and the read sub-FIFO array 610 each include a plurality of sub-FIFO chips, where the number of sub-FIFO chips of the write sub-FIFO array 608 is equal to the number of sub-FIFO chips of the read sub-FIFO array 610.

[0059] The master FIFO chip can be configured to calculate Figure 4 The minimum index value and the maximum index value described in the logic 600 are performed for an asynchronous FIFO-based sub-FIFO method. When a write data signal (wdata) is received by the master FIFO chip 602, the write FIFO chip 604 sends a write address (waddr) to the master FIFO chip 602 and simultaneously sends a write pointer (wptr) to the read sub-FIFO array 610. Likewise, when a read data signal (rdata) is received by the master FIFO chip 602, the read FIFO chip 604 sends a read address (raddr) to the master FIFO chip 602 and simultaneously sends a read pointer (rptr) to the write sub-FIFO array 608. In addition, the master FIFO chip 602 can be configured to receive a write clock enable signal (wclken).

[0060] When the read sub-FIFO array 610 receives the write pointer (wptr), the read sub-FIFO array 610 generates and sends a write double clocked read pointer (wq2_rptr) to the write FIFO chip 604. Likewise, when the write sub-FIFO array 608 receives the read pointer (rptr), the write sub-FIFO array 608 generates and sends a read double clocked write pointer (rq2_wptr) to the read FIFO chip 606. The operation of sending the write double clocked read pointer (wq2_rptr) and the read double clocked write pointer (rq2_wptr) to the opposite read FIFO chip 606 or write FIFO chip 604 allows for data synchronization from the write side to the read side, and vice versa. The read sub-FIFO array 610 and the write sub-FIFO array 608 can be configured to increment an index counter by a value of 1, such that a Gray coding pattern requirement is met and such that multiple entry data of the same clock time can be stacked or de-stacked simultaneously.

[0061] The write sub-FIFO array 608 and the write FIFO chip 604 can receive a write clock signal (wclk). Likewise, the read sub-FIFO array 610 and the read FIFO chip 606 can receive a read clock signal (rclk). Further, the write FIFO chip 604 and the write sub-FIFO array 608 can be configured to receive a negative write to a read signal (wrst_n), and the read FIFO chip 606 and the read sub-FIFO array 608 can be configured to receive a negative write to a write signal (rrst_n).

[0062] Figure 7 is a schematic diagram of the behavior of a flexible buffer based on a FIFO with sub-FIFO synchronization for a de-queue operation 700 and an enqueue operation 750 according to the disclosed embodiments. The de-queue operation 700 illustrates the change in the enqueue empty slot as the de-queue busy slot changes. Likewise, the enqueue operation 750 illustrates the change in the de-queue busy slot as the enqueue empty slot changes.

[0063] Initially, the flexible buffer is empty (i.e., the enqueue empty slot level and the de-queue busy slot level are between the empty limit and the full limit). Movement away from the intermediate memory value (i.e., the expected average value) indicates a de-queue and / or an enqueue operation. The flexible buffer absorbs latency such that the values of the enqueue empty level and the de-queue busy level do not reach the empty boundary or the full boundary. SKP symbols can be added or removed in order to remain within the dynamic range available for latency fixing. For example, in the de-queue operation 700, as the de-queue busy slot level becomes more empty, the enqueue empty slot level becomes more empty. Likewise, in the enqueue operation 750, as the de-queue busy slot level becomes more full, the enqueue empty slot level becomes more full. After a certain amount of operations or a certain amount of time, the controller and / or processor is configured to add / remove SKP symbols to return the enqueue empty slot level and the de-queue busy slot level to the expected average value of the empty / busy slot levels. As a result of the method based on asynchronous asymmetric FIFOs described in the logic 600 and Figure 4 the method based on asynchronous asymmetric FIFOs, it is possible to remove or add SKP symbols in any number such that latency can be dynamically adjusted.

[0064] By utilizing the method based on asynchronous asymmetric FIFOs, it is possible to optimize the storage depth of the flexible buffer. Additionally, the variation of data corruption when passing between independent clock domains in the flexible buffer is minimized. Finally, by not using handshaking FIFOs and / or FIFO chaining, the data path latency is reduced through the PHY which increases the throughput performance due to the pipelining characteristics.

[0065] In one embodiment, a data storage device includes one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to transfer data to a host device according to an asynchronous asymmetric first-in-first-out (FIFO) process. The asynchronous asymmetric FIFO process includes calculating a minimum index value and a maximum index value. The minimum index value is calculated according to the following formula: ((round up to a power of 2 of a required depth) / 2) - ((the required depth) / 2), where the required depth is a number of index entries multiplied by 2 to account for full and empty states, and round up to a power of 2 is an even number of a geometric sequence starting with 2 and having a common ratio of 2. The maximum index value is calculated according to the following formula: ((round up to a power of 2 of a required depth) / 2) + ((the required depth) / 2) - 1.

[0066] In another embodiment, a data storage device comprises: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller comprises: a main first-in-first-out (FIFO) chip; a write FIFO chip coupled to the main FIFO chip; a readout FIFO chip coupled to the main FIFO chip; an array of write sub-FIFO chips, wherein the array of write sub-FIFO chips is coupled to the write FIFO chip and the readout FIFO chip; and an array of readout sub-FIFO chips, wherein the array of readout sub-FIFO chips is coupled to the write FIFO chip and the readout FIFO chip. The array of write sub-FIFO chips comprises a first plurality of sub-FIFO chips, wherein the array of readout sub-FIFO chips comprises a second plurality of sub-FIFO chips, and wherein the first plurality is equal to the second plurality. The readout FIFO chip is configured to send a readout address to the main FIFO chip, wherein the readout FIFO chip is configured to send a read pointer to the array of write sub-FIFO chips. The array of write sub-FIFO chips is configured to transfer a write double clocked read pointer to the write FIFO chip. The write FIFO chip is configured to send a write address to the main FIFO chip, wherein the write FIFO chip is configured to send a write pointer to the array of readout sub-FIFO chips. The array of readout sub-FIFO chips is configured to transfer a readout double clocked write pointer to the readout FIFO chip. The array of write sub-FIFO chips is configured to receive a write clock signal and a write-to-read, the write-to-read being a negative signal. The array of readout sub-FIFO chips is configured to receive a readout clock signal and a read-to-write, the read-to-write being a negative signal. The write FIFO chip is configured to receive the write clock signal, and wherein the readout FIFO chip is configured to receive the readout clock signal. The write FIFO chip is configured to receive the write-to-read, the write-to-read being a negative signal, and wherein the readout FIFO chip is configured to receive the read-to-write, the read-to-write being a negative signal. The main FIFO chip is configured to receive a write clock enable signal. The main FIFO chip is configured to receive a write data signal, and wherein the main FIFO chip is configured to send a readout data signal. The main FIFO chip is a dual port random access memory (RAM).

[0067] In another embodiment, a data storage device includes means for storing data and a controller coupled to the means for storing data, wherein the controller is configured to: calculate a minimum index value; calculate a maximum index value; and synchronize indices of a read pointer and a write pointer based on the calculated minimum index value and maximum index value. The data storage device further includes means for receiving a write pointer signal, a read out clock signal, and a read-write, the read-write being a negative signal. The data storage device further includes means for receiving a read pointer signal, a write in clock signal, and a write-read, the write-read being a negative signal.

[0068] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure can be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the claims that follow.

Claims

1. A data storage device, the data storage device comprising: one or more memory devices; and a controller coupled to the one or more memory devices, wherein: the controller is configured to transfer data to a host device according to an asynchronous non-symmetric first-in-first-out process (asynchronous non-symmetric FIFO process); the asynchronous non-symmetric FIFO process includes calculating a minimum index value and a maximum index value; and the minimum index value indicates a lower bound of a range of memory depths and the maximum index value indicates an upper bound of the range of memory depths.

2. A data storage device, the data storage device comprising: one or more memory devices; and a controller coupled to the one or more memory devices, wherein: the controller is configured to transfer data to a host device according to an asynchronous non-symmetric first-in-first-out process (asynchronous non-symmetric FIFO process); the asynchronous non-symmetric FIFO process includes calculating a minimum index value and a maximum index value; the minimum index value is calculated according to the following formula: ((Rounded to power of 2 of requested depth) / 2) - ((requested depth) / 2) where requested depth is the number of index entries multiplied by 2 to account for both full and empty states, and where rounded to power of 2 is an even number of a geometric series starting at 2 with a common ratio of 2.

3. The data storage device of claim 2, wherein the maximum index value is calculated according to the following formula: ((Rounded to power of 2 of requested depth) / 2) + ((requested depth) / 2) - 1.

4. A data storage device, the data storage device comprising: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller includes: a master first-in-first-out chip (master FIFO chip); a write FIFO chip coupled to the master FIFO chip; a readout FIFO chip coupled to the master FIFO chip; an array of write sub-FIFO chips, wherein the array of write sub-FIFO chips is coupled to the write FIFO chip and the readout FIFO chip; and an array of readout sub-FIFO chips, wherein the array of readout sub-FIFO chips is coupled to the write FIFO chip and the readout FIFO chip, wherein: the readout FIFO chip is configured to send a readout address to the master FIFO chip, the readout FIFO chip is configured to send a read pointer to the array of write sub-FIFO chips, and the array of write sub-FIFO chips is configured to transfer a write double clocked read pointer to the write FIFO chip.

5. The data storage device of claim 4, wherein the array of write sub-FIFO chips includes a first plurality of sub-FIFO chips, wherein the array of readout sub-FIFO chips includes a second plurality of sub-FIFO chips, and wherein the first plurality is equal to the second plurality. ​ ​ ​ 6. The data storage device of claim 4, wherein the write FIFO chip is configured to send a write address to the master FIFO chip, wherein the write FIFO chip is configured to send a write pointer to the readout sub-FIFO chip array.

7. The data storage device of claim 6, wherein the readout sub-FIFO chip array is configured to transfer a readout double clock write pointer to the readout FIFO chip.

8. The data storage device of claim 4, wherein the write sub-FIFO chip array is configured to receive a write clock signal and a write-read, the write-read being a negative signal.

9. The data storage device of claim 8, wherein the readout sub-FIFO chip array is configured to receive a readout clock signal and a read-write, the read-write being a negative signal.

10. The data storage device of claim 9, wherein the write FIFO chip is configured to receive the write clock signal, and wherein the readout FIFO chip is configured to receive the readout clock signal.

11. The data storage device of claim 10, wherein the write FIFO chip is configured to receive the write-read, the write-read being a negative signal, and wherein the readout FIFO chip is configured to receive the read-write, the read-write being a negative signal.

12. The data storage device of claim 4, wherein the master FIFO chip is configured to receive a write clock enable signal.

13. The data storage device of claim 12, wherein the master FIFO chip is configured to receive a write data signal, and wherein the master FIFO chip is configured to send a readout data signal.

14. The data storage device of claim 4, wherein the master FIFO chip is a dual port random access memory (RAM).

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