Memory acceleration verification method and device, electronic equipment and storage medium

By simulating the handling logic of cache hit failure in memory acceleration cards and using the access information table to verify the consistency between response data and written data, the lack of verification in memory acceleration cards is solved, achieving efficient detection and debugging and ensuring the normal operation of memory acceleration functions.

CN114327847BActive Publication Date: 2026-06-09LOONGSON TECH CORP
View PDF 4 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
LOONGSON TECH CORP
Filing Date
2020-09-30
Publication Date
2026-06-09

AI Technical Summary

Technical Problem

The lack of effective verification methods for the processing logic of memory acceleration cards in the existing technology leads to the inability to ensure the normal operation of memory acceleration functions and low detection efficiency.

Method used

By simulating the processing logic of a memory acceleration card when a cache hit fails, the number of accesses is recorded using an access information table. When the maximum number of accesses is reached, the consistency between the response data and the pre-recorded write data is verified. Otherwise, the access request is resent and the number of accesses is recorded, thus realizing the detection and debugging of the memory acceleration function.

Benefits of technology

It improves the detection and debugging efficiency of memory acceleration functions, ensures the normal operation of memory acceleration cards, and improves the accuracy and efficiency of detection.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN114327847B_ABST
    Figure CN114327847B_ABST
Patent Text Reader

Abstract

Embodiments of the present application provide a memory acceleration verification method and device, electronic equipment and storage medium, and belong to the technical field of computers. The method comprises: obtaining an access request, the access request comprising a memory address; when the number of accesses of the memory address in an access information table is greater than or equal to a maximum number of accesses, returning data indicated by the memory address as response data to control the verification of the response data by pre-recorded write data; otherwise, controlling the retransmission of the access request and recording the current access of the memory address by the number of accesses in the access information table. By simulating the processing logic of the memory acceleration card when the cache hit fails, and verifying the returned response data, it can be determined whether the memory acceleration function is normal, facilitating the detection and debugging of the memory acceleration function by the staff, and the detection and debugging efficiency can be improved.
Need to check novelty before this filing date? Find Prior Art