An I2C debugging method, system and device of a BMC and a computer readable storage medium

Abstract

The application discloses an I2C debugging method, system and device of a BMC and a computer readable storage medium, comprising: acquiring an I2C topology of a BMC to be simulated; according to the I2C topology and pre-stored hardware characteristic information of an I2C device, a virtual I2C link corresponding to the I2C topology is virtually output by using a HW interface of QEMU; and the simulated hardware information is transmitted to the BMC through the virtual I2C link, and the BMC is monitored and debugged. The application virtually outputs the I2C topology of the BMC by using QEMU, simulates the hardware information output of a motherboard, and tests the I2C function of the BMC in advance before the motherboard is completed, so that the BMC testing and the motherboard research and development are carried out in parallel, and the research and development efficiency of the server is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a BMC I2C debugging method, system and device and computer readable storage medium. BACKGROUND

[0002] With the rapid development of the Internet industry, the demand for servers in various industries is increasing, which also accelerates the update of servers. Therefore, providing the latest servers faster helps enterprises seize market opportunities.

[0003] In the existing server, there is a small system independent of the CPU, that is, BMC (Baseboard Management Controller), which provides monitoring and management for the server. In the development process of the server, the motherboard of the server needs to go through the process of hardware design, board making and verification, which takes 3 months to 1 year. The BMC development process is relatively fast, usually earlier than the motherboard development completion. After the completion of BMC, the motherboard needs to be returned to the board to start verification. Before the motherboard is developed, BMC cannot be tested, which is a blocking point in the server development process and affects the server development efficiency.

[0004] Therefore, a BMC I2C (Inter-Integrated Circuit) debugging method is needed to improve the server development efficiency. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a BMC I2C debugging method, system and device and computer readable storage medium, which can improve the server development efficiency. The specific scheme is as follows:

[0006] A BMC I2C debugging method, comprising:

[0007] Obtain the I2C topology of the BMC to be simulated;

[0008] According to the I2C topology and the pre-stored hardware characteristic information of the I2C device, a virtual I2C link corresponding to the I2C topology is virtually output by using the HW interface of QEMU.

[0009] The virtual I2C link is used to transmit simulated hardware information to the BMC, and the BMC is monitored and debugged.

[0010] Optionally, the process of transmitting simulated hardware information to the BMC through the virtual I2C link comprises:

[0011] According to the virtual I2C link, a pull-up and pull-down signal during data transmission in the I2C link is simulated in a manner of using a software delay according to a communication frequency, and the simulated hardware information is transmitted to the BMC.

[0012] Optionally, the process of virtually outputting the virtual I2C link corresponding to the I2C topology by using the HW interface of QEMU according to the I2C topology and the hardware characteristic information of the I2C device pre-stored comprises:

[0013] According to the I2C topology, an extension chip used in each level of the I2C link is acquired;

[0014] According to the hardware characteristic information, channel information of each extension chip is acquired;

[0015] According to the I2C topology, the extension chip and the channel information of the extension chip, the virtual I2C link corresponding to the I2C topology is virtually outputted by using the HW interface of QEMU.

[0016] Optionally, the process of virtually outputting the virtual I2C link corresponding to the I2C topology by using the HW interface of QEMU according to the I2C topology, the extension chip and the channel information of the extension chip comprises:

[0017] According to the I2C topology, an I2C communication pin used for I2C communication in the BMC is confirmed;

[0018] According to the extension chip and the channel information of the extension chip, the number of I2C channels of each extension chip is confirmed;

[0019] According to the I2C topology, the I2C communication pin of the BMC is connected with the extension chip of each level and the channel of the extension chip, so as to obtain an I2C circuit diagram;

[0020] The I2C circuit diagram is virtually outputted by using the HW interface of QEMU.

[0021] The application further discloses an I2C debugging system of a BMC, which comprises:

[0022] a topology acquisition module, configured to acquire an I2C topology of a BMC to be simulated;

[0023] a link virtualization module, configured to virtually output a virtual I2C link corresponding to the I2C topology by using the HW interface of QEMU according to the I2C topology and hardware characteristic information of an I2C device pre-stored;

[0024] a debugging module, configured to transmit simulated hardware information to the BMC through the virtual I2C link, and monitor and debug the BMC.

[0025] Optionally, the debugging module is specifically configured to simulate a pull-up and pull-down signal during data transmission in the I2C link by using a software delay according to a communication frequency, and transmit the simulated hardware information to the BMC.

[0026] Optionally, the link virtualization module comprises:

[0027] a chip confirmation sub-module configured to acquire an expansion chip used in each level of the I2C link according to the I2C topology;

[0028] a channel confirmation sub-module configured to acquire channel information of each expansion chip by using the hardware characteristic information;

[0029] a link virtualization sub-module configured to virtually output a virtual I2C link corresponding to the I2C topology by using a HW interface of QEMU according to the I2C topology, the expansion chip and the channel information of the expansion chip.

[0030] Optionally, the link virtualization sub-module comprises:

[0031] a pin confirmation unit configured to confirm an I2C communication pin used for I2C communication in the BMC according to the I2C topology;

[0032] a channel confirmation unit configured to confirm an I2C channel number of each expansion chip according to the expansion chip and the channel information of the expansion chip;

[0033] a line virtualization unit configured to connect the I2C communication pin of the BMC with the expansion chip in each level and the channel of the expansion chip according to the I2C topology, and obtain an I2C line diagram;

[0034] a link virtualization unit configured to virtually output the virtual I2C link by virtually outputting the I2C line diagram by using the HW interface of QEMU.

[0035] The application further discloses an I2C debugging device of a BMC, comprising:

[0036] a memory configured to store a computer program;

[0037] a processor configured to execute the computer program to realize the I2C debugging method of the BMC.

[0038] The application further discloses a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the I2C debugging method of the BMC.

[0039] The I2C debugging method of the BMC provided in the present application comprises the following steps: obtaining the I2C topology of the BMC to be simulated; according to the I2C topology and the pre-stored hardware characteristic information of the I2C device, a virtual I2C link corresponding to the I2C topology is virtually output by using the HW interface of QEMU; and the simulated hardware information is transmitted to the BMC through the virtual I2C link, so as to monitor and debug the BMC.

[0040] The present application utilizes the I2C topology of the BMC virtually output by QEMU to simulate the hardware information of the motherboard, so that the I2C function of the BMC can be tested in advance before the motherboard is completed, and the BMC testing and the motherboard development are carried out in parallel, thereby improving the development efficiency of the server. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute a part of the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on the provided drawings.

[0042] Figure 1 A flowchart of the I2C debugging method of the BMC disclosed in the embodiments of the present application is shown in the figure.

[0043] Figure 2 A flowchart of another I2C debugging method of the BMC disclosed in the embodiments of the present application is shown in the figure.

[0044] Figure 3 A structure diagram of the I2C debugging system of the BMC disclosed in the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments only constitute a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0046] The embodiments of the present application disclose an I2C debugging method of a BMC, as shown in the figure. Figure 1 The method comprises the following steps:

[0047] S11: obtaining the I2C topology of the BMC to be simulated.

[0048] Specifically, before the server mainboard corresponding to the virtual simulation BMC is manufactured, the design scheme of the server mainboard is known, therefore, the I2C topology between the BMC and the server mainboard in the future is known, therefore, if the simulation I2C test of the BMC is to be carried out in advance, the I2C topology of the BMC needs to be acquired.

[0049] In the I2C topology, it is recorded that the BMC needs to use which pins and how many pins for I2C communication, and the required extension chip model is also recorded, and the connection relationship between the I2C pins of the BMC and the extension chip and the pins of the extension chip, that is, the I2C circuit diagram of each level.

[0050] S12: According to the I2C topology and the pre-stored hardware characteristic information of the I2C device, a virtual I2C link corresponding to the I2C topology is virtually output by using the HW interface of QEMU.

[0051] Specifically, although the model of the extension chip is recorded in the I2C topology, the specific pin condition of the extension chip is not recorded, therefore, the pre-stored hardware characteristic information of the I2C device is still needed to determine the pin condition of the extension chip, and then the I2C link is virtually output in combination with the I2C topology, the virtual I2C link corresponding to the I2C topology can be virtually output by using the HW interface of QEMU (Quick EMUlator, virtual operating system simulator), and the virtual I2C link can accurately simulate the transmission condition of the signal between each level, thereby giving the possibility of virtual test.

[0052] S13: The simulated hardware information is transmitted to the BMC through the virtual I2C link, and the BMC is monitored and debugged.

[0053] Specifically, the design of the server mainboard is known, therefore, it can be predicted that the BMC uses the I2C link to monitor which hardware devices, therefore, the hardware information of each hardware on the server is virtually output by using QEMU, and the simulated hardware information is transmitted to the BMC through the virtual I2C link which has been virtually output, the BMC is debugged by judging whether the BMC can accurately monitor, record and display the input hardware information, and finally it is ensured that the BMC can effectively monitor and complete the debugging.

[0054] It can be seen that, by using QEMU to virtually output the I2C topology of the BMC, the hardware information of the mainboard is simulated, the I2C function of the BMC is tested in advance before the mainboard is manufactured, the BMC test and the mainboard research and development are carried out in parallel, and the research and development efficiency of the server is improved.

[0055] The embodiment of the application discloses a specific I2C debugging method of BMC, and further describes and optimizes the technical scheme relative to the previous embodiment. Referring to Figure 2 Specifically,

[0056] S21: Obtain the I2C topology of the BMC to be simulated.

[0057] S22: Obtain the extension chips used in each level of the I2C link according to the I2C topology.

[0058] Specifically, the extension chips used in each level of the I2C link are determined according to the markers in the I2C topology. It can be understood that, in order to extend the I2C link of the BMC, a multi-level extension chip is used for extension, for example, as shown in Table 1. The first level is the I2C0 pin of the BMC, the second level is extended through a 9548 chip, the third level is extended by using a 9555 extension chip, and the fourth level is directly connected with a hardware device, so that the third level extension chip obtains the hardware information of the memory in the fourth level and feeds back to the BMC level by level. Of course, the BMC can use more than one I2C pin to construct an I2C communication link, and each pin can also form a multi-level extension as shown in Table 1.

[0059] Table 1

[0060]

[0061]

[0062] S23: Obtain the channel information of each extension chip by using the hardware characteristic information.

[0063] Specifically, the hardware characteristic information records the specific pin data and other information of each extension chip, for example, based on Table 1, the 9548 extension chip can extend 8 channels, each channel can connect a 9555 extension chip, and the 9555 extension chip can be connected with 6 IO channels of a hardware device, for example, a memory. As shown in Table 1, one BMC pin can be connected with one 9548 extension chip, one 9548 extension chip can be connected with 8 9555 extension chips, and a total of 48 channels can be extended to be connected with the hardware device. Of course, the specific extension condition can be set according to actual application requirements, which is not limited here.

[0064] S24: Virtually output a virtual I2C link corresponding to the I2C topology by using the HW interface of QEMU according to the I2C topology, the extension chip and the channel information of the extension chip.

[0065] Specifically, after confirming the I2C topology, the expansion chip and the channel information of the expansion chip, the above information can be integrated to virtually output a virtual I2C link corresponding to the I2C topology by using the HW interface of QEMU.

[0066] The further specific virtual process can further include S241 to S244; wherein,

[0067] S241: According to the I2C topology, confirming the I2C communication pins in the BMC for I2C communication.

[0068] Specifically, since the BMC includes multiple pins, first, it is necessary to confirm how many of those pins are used for I2C communication, so as to draw the wiring diagram later.

[0069] S242: According to the expansion chip and the channel information of the expansion chip, confirming the number of I2C channels of each expansion chip.

[0070] S243: According to the I2C topology, connecting the I2C communication pins of the BMC with the expansion chips at each level and the channels of the expansion chips to obtain an I2C wiring diagram.

[0071] Specifically, after obtaining the I2C communication pins of the BMC and the expansion chips at each level and the channels of the expansion chips, a simple I2C wiring diagram can be drawn according to the I2C topology, and the wiring diagram only shows the connection relationship between the chips and the pins, and does not have the function of simulating data transmission.

[0072] S244: Virtually outputting a virtual I2C link by using the HW interface of QEMU to virtually output the I2C wiring diagram.

[0073] Specifically, after obtaining the I2C wiring diagram, the content drawn in the I2C wiring diagram can be loaded with actual running data to be virtualized by using the HW interface of QEMU, so as to obtain a virtual I2C link that can simulate signal transmission.

[0074] Specifically, the hardware characteristic information can also be integrated into the I2C topology diagram, so that the I2C topology diagram includes complete I2C link information, and at that time, the virtualization can be performed according to the I2C topology diagram. In addition, the hardware characteristic information can be updated to ensure that all devices required for simulation can be covered. It can be understood that the hardware on the simulation motherboard finally connected to the I2C link can also be stored in a separate file, which can be input by the user, and the hardware information required for this simulation can be obtained by reading. Of course, the hardware information required for simulation and the connection relationship with the I2C link can also be integrated into the I2C topology, and the hardware required for simulation and the connection relationship with the I2C link can be obtained by reading the I2C topology.

[0075] S25: transmitting the simulated hardware information to the BMC by simulating the pull-up and pull-down signals during data transmission in the I2C link according to a communication frequency using a software delay method through the virtual I2C link.

[0076] Specifically, the pull-up and pull-down of the I2C can be simulated according to the communication frequency using the software delay method, for example, using a frequency of 100 MHz, 1 or 0 is returned at a delay of 1 / 100 MHz when the virtual I2C setting is called, which is used to simulate the pull-up and pull-down.

[0077] Correspondingly, the embodiment of the application further discloses an I2C debugging system of a BMC, referring to Figure 3 As shown in the figure, the system comprises:

[0078] The topology acquisition module 11 is configured to acquire the I2C topology of the BMC to be simulated.

[0079] The link virtualization module 12 is configured to virtually output the virtual I2C link corresponding to the I2C topology by using the HW interface of QEMU according to the I2C topology and the pre-stored hardware characteristic information of the I2C device.

[0080] The debugging module 13 is configured to transmit the simulated hardware information to the BMC through the virtual I2C link, and monitor and debug the BMC.

[0081] It can be seen that the embodiment of the application virtually outputs the hardware information of the motherboard by using the QEMU to virtually simulate the I2C topology of the BMC, so that the I2C function of the BMC can be tested in advance before the motherboard is completed, the BMC testing and the motherboard development are carried out in parallel, and the development efficiency of the server is improved.

[0082] Specifically, the debugging module 13 is specifically configured to simulate the pull-up and pull-down signals during data transmission in the I2C link according to a communication frequency using a software delay method through the virtual I2C link, and transmit the simulated hardware information to the BMC.

[0083] Specifically, the link virtualization module 12 can comprise a chip confirmation sub-module, a channel confirmation sub-module, a channel confirmation sub-module and a link virtualization sub-module, wherein,

[0084] The chip confirmation sub-module is configured to acquire the expansion chip used in each level in the I2C link according to the I2C topology.

[0085] The channel confirmation sub-module is configured to acquire the channel information of each expansion chip by using the hardware characteristic information.

[0086] The link virtualization sub-module is configured to virtually output the virtual I2C link corresponding to the I2C topology by using the HW interface of QEMU according to the I2C topology, the expansion chip and the channel information of the expansion chip.

[0087] Specifically, the link virtual sub-module can include: a pin confirmation unit, a channel confirmation unit, a line virtual unit and a link virtual unit; wherein,

[0088] The pin confirmation unit is configured to confirm, according to the I2C topology, an I2C communication pin in the BMC for I2C communication.

[0089] The channel confirmation unit is configured to confirm, according to the expansion chip and the channel information of the expansion chip, the number of I2C channels of each expansion chip.

[0090] The line virtual unit is configured to connect, according to the I2C topology, the I2C communication pin of the BMC with the expansion chips at each level and the channels of the expansion chips, to obtain an I2C line diagram.

[0091] The link virtual unit is configured to virtually output a virtual I2C link by using a HW interface of the QEMU to virtually output the I2C line diagram.

[0092] In addition, the embodiment of the present application further discloses an I2C debugging device of a BMC, which comprises:

[0093] The memory is configured to store the computer program.

[0094] The processor is configured to execute the computer program to implement the I2C debugging method of the BMC as described above.

[0095] In addition, the embodiment of the present application further discloses a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the I2C debugging method of the BMC as described above.

[0096] Finally, it should be noted that, in this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0097] Those skilled in the art will further realize that the mere conception of the examples described herein is sufficient to enable practitioners to practice the examples as changed or modified for specific applications, and that various other modifications or changes in addition to those suggested can be resorted to without departing from the spirit and scope of the disclosure. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature and not as restrictive.

[0098] The above has carried on the detailed introduction to the technical content provided by the present application, the principle and implementation mode of the present application are set forth by applying the specific examples in this paper, the above example explanation is only for helping to understand the method and core idea of the present application; At the same time, for the general technical personnel in the art, according to the idea of the present application, the specific implementation mode and application range will have the change; The above is described, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A method for I2C debugging of a BMC, the method comprising: The method comprises the following steps: acquiring an I2C topology of a BMC to be simulated; virtually outputting a virtual I2C link corresponding to the I2C topology by using a HW interface of QEMU according to the I2C topology and pre-stored hardware characteristic information of an I2C device; transmitting simulated hardware information to the BMC through the virtual I2C link, and monitoring and debugging the BMC; wherein the step of virtually outputting the virtual I2C link corresponding to the I2C topology by using the HW interface of QEMU comprises: acquiring extension chips used by each level of the I2C link according to the I2C topology, and confirming I2C communication pins used for I2C communication in the BMC, confirming the number of I2C channels of each extension chip according to the extension chips and channel information of the extension chips, connecting the I2C communication pins of the BMC with the extension chips of each level and the channels of the extension chips according to the I2C topology, and obtaining an I2C circuit diagram, and virtually outputting the virtual I2C link by using the HW interface of QEMU, wherein the hardware characteristic information records pin data information of each extension chip.

2. The BMC's I2C debugging method of claim 1, wherein, The step of transmitting the simulated hardware information to the BMC through the virtual I2C link comprises: transmitting the simulated hardware information to the BMC by simulating pull-up and pull-down signals during data transmission in the I2C link by using software delay according to a communication frequency through the virtual I2C link.

3. The method of claim 1 or 2, wherein, The step of virtually outputting the virtual I2C link corresponding to the I2C topology by using the HW interface of QEMU according to the I2C topology and the pre-stored hardware characteristic information of the I2C device comprises: acquiring extension chips used by each level of the I2C link according to the I2C topology; acquiring channel information of each extension chip by using the hardware characteristic information; virtually outputting the virtual I2C link corresponding to the I2C topology by using the HW interface of QEMU according to the I2C topology, the extension chips and the channel information of the extension chips.

4. An I2C debugging system for a BMC, the system comprising: The method comprises the following steps: a topology acquisition module, configured to acquire an I2C topology of a BMC to be simulated; a link virtualization module, configured to virtually output a virtual I2C link corresponding to the I2C topology by using a HW interface of QEMU according to the I2C topology and pre-stored hardware characteristic information of an I2C device; a debugging module, configured to transmit simulated hardware information to the BMC through the virtual I2C link, and monitor and debug the BMC; wherein the link virtualization module comprises a link virtualization submodule, and the link virtualization submodule comprises: a pin confirmation unit, configured to acquire extension chips used by each level of the I2C link according to the I2C topology, and confirm I2C communication pins used for I2C communication in the BMC; a channel confirmation unit, configured to confirm the number of I2C channels of each extension chip according to the extension chips and channel information of the extension chips, wherein the hardware characteristic information records pin data information of each extension chip. A line virtual unit is configured to connect I2C communication pins of the BMC with extension chips of each level and channels of the extension chips according to the I2C topology, so as to obtain an I2C line graph; A link virtual unit is configured to virtualize the I2C line graph by using a HW interface of QEMU, so as to virtualize the virtual I2C link.

5. The I2C debugging system of BMC according to claim 4, wherein, The debugging module is specifically configured to simulate pull-up and pull-down signals in data transmission in the I2C link by using a software delay mode according to a communication frequency, and transmit simulated hardware information to the BMC through the virtual I2C link.

6. The I2C debugging system of a BMC according to claim 4 or 5, characterized in that, The link virtual module comprises: A chip confirmation sub-module is configured to acquire extension chips used in each level in the I2C link according to the I2C topology; A channel confirmation sub-module is configured to acquire channel information of each extension chip by using the hardware characteristic information; A link virtual sub-module is configured to virtualize a virtual I2C link corresponding to the I2C topology by using a HW interface of QEMU according to the I2C topology, the extension chips and the channel information of the extension chips.

7. An I2C debugging apparatus of a BMC, characterized by, comprise: A memory is configured to store a computer program; A processor is configured to execute the computer program to implement the I2C debugging method of the BMC according to any one of claims 1 to 3.

8. A computer-readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium, and when executed by the processor, the computer program implements the I2C debugging method of the BMC according to any one of claims 1 to 3.

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