Logical architecture system, establishment and verification method, device, equipment and storage medium

Abstract

The present disclosure provides a logic architecture system, establishment and verification method, device, electronic device and storage medium, the logic architecture system includes: a logic unit establishment module, used to establish at least two basic logic units, the basic logic units include at least one of a data verification type logic unit, a data processing type logic unit and a compound logic unit, the compound logic unit has both data verification and data processing functions; a connection unit establishment module, used to establish at least one connection unit, the connection unit is used to connect any two basic logic units of the at least two basic logic units to obtain a connected logic unit. The system provided by the embodiment of the present application can be applied to various data verification requirements, thereby ensuring the correct operation of the machine learning system.

Description

Technical Field

[0001] The present disclosure relates to the field of machine learning technology, and in particular to a logical architecture system, a method for establishing a logical architecture system, a data verification method, a data verification device, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the development of computer technology, machine learning technology has been gradually applied to various fields (such as face recognition, machine translation, etc.). There are usually a lot of complex data control logic (such as experimental configuration files) in machine learning systems. For example, the data control logic includes various algorithms, hyperparameters, training framework code control logic, computing resource scheduling and allocation rules, etc. When the complexity of the system increases, the verification of these data in the entire training process becomes very complicated, and the current verification tools can only perform relatively simple checks on some basic types, which in turn affects the correct operation of the machine learning system. Summary of the invention

[0003] The embodiments of the present disclosure at least provide a logical architecture system, a method for establishing a logical architecture system, a data verification method, a data verification device, an electronic device, and a computer-readable storage medium.

[0004] In a first aspect, an embodiment of the present disclosure provides a logical architecture system, including:

[0005] A logic unit establishment module, used to establish at least two basic logic units, wherein the basic logic units include at least one of a data verification logic unit, a data processing logic unit and a composite logic unit, wherein the composite logic unit has both data verification and data processing functions;

[0006] A connection unit establishment module is used to establish at least one connection unit, and the connection unit is used to connect any two basic logical units among the at least two basic logical units to obtain a connected logical unit; the basic logical units and the at least one connection unit are used to construct a data verification system, and the data verification is used to verify and / or process the data to be verified.

[0007] In the disclosed embodiment, since the logic architecture system can establish various basic logic units and connection units, and since the basic logic units have the function of verifying and / or processing basic data, a data verification system that meets various requirements can be built based on various basic logic units and connection units, thereby ensuring the correct operation of the machine learning system. In addition, since each basic logic unit can be reused, the ease of use and reliability of programming can be improved.

[0008] According to the first aspect, in a possible implementation, the connection unit includes at least one of a connection unit, a connection unit and a pipeline connection unit, the pipeline connection unit is used to connect two basic logic units in series, and the basic logic unit located after the pipeline connection unit receives the processing result of the basic logic unit located before the pipeline connection unit.

[0009] According to the first aspect, in a possible implementation, the data verification logic unit is used to verify the authenticity of the data, and when the data verification is true, returns the value of the input data, and when the data verification is false, throws an exception; the data processing logic unit is used to process the data and return the processing result.

[0010] According to the first aspect, in a possible implementation manner, the priority of the pipeline connection unit is higher than that of the and connection unit, and the and connection unit has a higher priority than that of the or connection unit.

[0011] According to the first aspect, in a possible implementation, the types of the basic logic units include at least one of a numerical logic unit, a character logic unit, a type logic unit, a structure logic unit, and a tool logic unit.

[0012] According to the first aspect, in a possible implementation manner, the system further includes:

[0013] A unit conversion module is used to convert the basic logic unit and / or the connected logic unit into a corresponding calculation unit; wherein the calculation unit supports the operation of at least one operator.

[0014] According to the first aspect, in a possible implementation, the unit conversion module is further used to convert the established computing unit into a corresponding basic logic unit or a corresponding connected logic unit.

[0015] According to the first aspect, in a possible implementation manner, the logic unit establishment module is further used to construct a functional logic unit based on a preset function.

[0016] In a second aspect, an embodiment of the present disclosure provides a method for establishing a logical architecture system, including:

[0017] Establish at least two basic logic units, wherein the basic logic unit includes at least one of a data verification logic unit, a data processing logic unit and a composite logic unit, wherein the composite logic unit has both data verification and data processing functions;

[0018] Establish at least one connection unit, wherein the connection unit is used to connect any two basic logic units among the at least two basic logic units to obtain a connected logic unit; the basic logic units and the at least one connection unit are used to construct a data verification system, wherein the data verification is used to verify and / or process the data to be verified.

[0019] In a third aspect, an embodiment of the present disclosure provides a data verification method, including:

[0020] Based on the target requirements and the logical architecture system described in any one of the embodiments of the first aspect, a target data verification system is constructed;

[0021] The data to be verified is input into the target data verification system to verify and / or process the data to be verified.

[0022] In a fourth aspect, an embodiment of the present disclosure provides a data verification device, including:

[0023] The system construction module is used to construct a target data verification system based on target requirements and the logical architecture system described in any of the aforementioned embodiments.

[0024] The data verification module is used to input the data to be verified into the target data verification system to verify and / or process the data to be verified.

[0025] In a fifth aspect, an embodiment of the present disclosure provides an electronic device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the method for establishing a logical architecture system as described in the second aspect, or the data verification method as described in the third aspect is performed.

[0026] In a sixth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for establishing a logical architecture system as described in the second aspect, or the data verification method as described in the third aspect, is executed.

[0027] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0029] Figure 1 A functional module diagram of a logical architecture system provided by an embodiment of the present disclosure is shown;

[0030] Figure 2 A functional module diagram of another logical architecture system provided by an embodiment of the present disclosure is shown;

[0031] Figure 3 A flowchart of a method for establishing a logical architecture system provided by an embodiment of the present disclosure is shown;

[0032] Figure 4 A flow chart of a data verification method provided by an embodiment of the present disclosure is shown;

[0033] Figure 5 A schematic diagram of the structure of a data verification device provided by an embodiment of the present disclosure is shown;

[0034] Figure 6 A schematic structural diagram of an electronic device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0036] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0037] The term "and / or" herein only describes an association relationship, indicating that three relationships may exist. For example, A and / or B may represent the following three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set consisting of A, B, and C.

[0038] With the development of computer technology, machine learning and artificial intelligence related technologies have made great progress in recent years, reaching a certain level in face recognition, machine translation, content understanding and generation, game strategy, etc. Based on the progress of the algorithm itself, a series of machine learning algorithm frameworks and platforms have gradually emerged, becoming the core force to promote algorithm progress and application.

[0039] There are usually a lot of complex data control logic (such as experimental configuration files) in machine learning systems. For example, the data control logic includes various algorithms, hyperparameters, training framework code control logic, computing resource scheduling and allocation rules, etc. As the complexity of the system increases, the verification of this data in the entire training process becomes very complicated, and the existing similar tools can only perform relatively simple checks on some basic types, which in turn affects the correct operation of the machine learning system.

[0040] Based on the above research, the present disclosure provides a logic architecture system, including a logic unit establishment module and a connection unit establishment module. The logic unit establishment module is used to establish at least two basic logic units, the basic logic units include at least one of a data verification type logic unit, a data processing type logic unit and a compound logic unit, and the compound logic unit has both data verification and data processing functions; the connection unit establishment module is used to establish at least one connection unit, and the connection unit is used to connect any two basic logic units of the at least two basic logic units to obtain a connected logic unit; the basic logic unit and the at least one connection unit are used to build a data verification system.

[0041] In the disclosed embodiment, since the logic architecture system can establish various basic logic units and connection units, and since the basic logic units have the function of verifying and / or processing basic data, a data verification system that meets various requirements can be built based on various basic logic units and connection units, thereby ensuring the correct operation of the machine learning system. In addition, the ease of use and reliability of programming can also be improved.

[0042] The following is an introduction and explanation of the relevant terms involved in the embodiments of the present application:

[0043] Artificial Intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that machines have the functions of perception, reasoning and decision-making.

[0044] Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level and software-level technologies. The basic technologies of artificial intelligence generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, operation / interaction systems, mechatronics and other technologies. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0045] Machine Learning (ML) is a multi-disciplinary subject that involves probability theory, statistics, approximation theory, convex analysis, algorithm complexity theory and other disciplines. It specializes in studying how computers simulate or implement human learning behavior to acquire new knowledge or skills and reorganize existing knowledge structures to continuously improve their performance. Machine learning is the core of artificial intelligence and the fundamental way to make computers intelligent. Its applications are spread across all areas of artificial intelligence. Machine learning and deep learning usually include artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning and other technologies.

[0046] Decision intelligence, including fully tuned training configuration, efficient algorithm implementation and pre-trained model library, can help researchers and engineers quickly start learning, verify ideas and produce business baseline models for reinforcement learning. For example, in this public security embodiment, a data verification system can be built based on the logical architecture system and combined with decision intelligence to achieve efficient data verification.

[0047] See also Figure 1 As shown in FIG. 1 , a functional module diagram of a logical architecture system provided by an embodiment of the present disclosure is shown. Figure 1As shown, the logic architecture system 100 includes a logic unit establishment module 10 and a connection unit establishment module 20. The logic unit establishment module 10 is used to establish at least two basic logic units, wherein the basic logic units include at least one of a data verification logic unit, a data processing logic unit, and a compound logic unit, wherein the compound logic unit has both data verification and data processing functions.

[0048] Specifically, the data verification logic unit is used to verify the authenticity of data, and if the data verification is true, returns the value of the input data, and if the data verification is false, throws an exception.

[0049] For example, a data verification logic unit refers to the type of verification, such as is_type(int) and interval(1,10). If the verification is false (failed), an exception will be thrown. Therefore, for a data verification logic unit, the truth or falsehood of data verification is determined by whether an exception is thrown (false if an exception is thrown, true if no exception is thrown), and the result of data processing is the original value passed in.

[0050] The data processing logic unit is used to process data and return the processing result. Exemplarily, the data processing logic unit refers to the type of conversion, such as to_type(int) and plus(233). There is no concept of failure, and only the processed value is returned. For the data processing logic unit, the result of data processing is based on the return value, and the data verification result is always true.

[0051] The compound logic unit will process the data and may find that the data is illegal during the processing and throw an exception. Therefore, for the compound logic unit, there is both the truth or falsehood of the data verification and the result of the data processing.

[0052] The connection unit establishment module 20 is used to establish at least one connection unit, and the connection unit is used to connect any two basic logical units of the at least two basic logical units to obtain a connected logical unit. The connection unit includes at least one of an AND connection unit (&), an OR connection unit (|), and a pipe connection unit (>>).

[0053] The meaning of each connection unit is introduced in detail below.

[0054] (I) AND connection (&) unit: The AND connection unit is used to connect two basic logic units in an "AND" relationship to form a connected logic unit, that is, a new logic unit.

[0055] For example, there are logic units a and b, and the meanings of a&b are as follows:

[0056] If a is verified to be true, and b is verified to be true, then the value processed by b is returned, and a&b is verified to be true;

[0057] If a verifies as true and b verifies as false, then the exception thrown by b is thrown, and a&b verifies as false;

[0058] If a is verified to be false, the exception thrown by a is thrown. If a&b are verified to be false, b will be skipped (II) or the connection (|) unit: The or connection unit is used to connect two basic logical units in an "or" relationship to form a connected logical unit, that is, to form a new logical unit.

[0059] For example, there are basic logic units c and d, and the meaning of c|d is as follows:

[0060] If c is verified to be true, the processed value of c is returned, d is skipped, and c|d is verified to be true;

[0061] If c is verified to be false and d is verified to be true, then the processed value of d is returned, and c|d is verified to be true;

[0062] If c verifies as false and d verifies as false, then throw the exception thrown by d, and c|d verifies as false.

[0063] (III) Pipeline connection (>>) unit: The pipeline connection unit is used to connect two basic logic units in series, and the basic logic unit located after the pipeline connection unit receives the processing result of the basic logic unit located before the pipeline connection unit, that is, the latter will receive the processing result of the former.

[0064] For example, there are logic units e and f, then the meaning of e>>f is as follows:

[0065] If e verifies to be true, then f will receive the processed return value of e as input;

[0066] If f is verified to be true, the value processed by f is returned, and e>>f is verified to be true;

[0067] If f verifies as false, throw the exception thrown by f, e>>f verifies as false;

[0068] If e verifies as false, then the exception thrown by e is thrown, and e>>f verifies as false.

[0069] In addition, it should be noted that, when a new connected logical unit includes two or more connection units, the priority of the pipe connection unit is higher than the AND connection unit, and the AND connection unit has a higher priority than the OR connection unit.

[0070] After establishing various basic logic units and at least one connection unit in the above logic architecture system 100, the target logic unit can be determined from at least two basic logic units and the target connection unit can be determined from at least one connection unit according to different requirements, and a data verification system can be built based on the determined target logic unit and the target connection unit. That is, based on the basic logic units defined above and the three connection units, a complex and reusable high-order logic unit can be built.

[0071] For example, for the concatenated logical unit is_type(str)>>rematch("[0-9]+")>>to_type(int)|is_type(int):

[0072] When the string 12345 is input, it satisfies is_type(str) and rematch("[0-9]+"), so to_type(int) is executed at last, and the integer number 12345 is obtained, which is verified to be true;

[0073] When the integer number 12345 is input, is_type(int) is satisfied, so the integer number 12345 is finally obtained, and the verification is true;

[0074] When the floating point number 12345.12 is input, it cannot satisfy is_type(str) or is_type(int), so an is_type(int) exception is thrown and the verification is false;

[0075] When the string abcde is input, it satisfies is_type(str), but does not satisfy rematch("[0-9]+") and cannot satisfy is_type(int), so an is_type(int) exception is thrown and the verification is false.

[0076] In the disclosed embodiment, since the selected target logic unit and target connection unit are different, the verification logic of the data verification system built each time and the verification function realized by the verification are different. Therefore, based on the logic architecture system provided in the disclosed embodiment, various data verification systems can be built in combination with different requirements, so as to realize the verification of data of different types and different complexities, so as to ensure the correct operation of the machine learning system. In addition, since the functions of each basic logic unit have been set in the process of building the data verification system using the logic architecture system, there is no need to reprogram, which can improve the ease of use and reliability of programming. For example, local data with similar data logic can reuse the same basic logic unit.

[0077] In some implementations, the types of the basic logic units may include at least one of a numerical logic unit, a character logic unit, a type logic unit, a structure logic unit, and a tool logic unit. Each type of the basic logic unit is described in detail below.

[0078] (1) Numerical logic units, which represent the processing and verification of numerical values, as follows:

[0079] plus(addend), a data processing logic unit, indicates adding data. For example, for a data processing logic unit plus(2), after inputting 1, 3 is returned.

[0080] minus(subtrahend), a data processing logic unit, indicates subtraction of data. For example, for the processing unit minus(2), after 1 is passed in, -1 is returned.

[0081] minus_with(minuend), a processing unit, indicates subtraction of data. For example, for the processing unit minus_with(2), after 1 is passed in, 1 is returned.

[0082] multi(multiplier), a data processing logic unit, indicates multiplication of data. For example, for the data processing logic unit multi(2), after 1 is passed in, 2 is returned.

[0083] divide(divisor), a data processing logic unit, means dividing data. For example, for the data processing logic unit divide(2), after 6 is passed in, 3 is returned.

[0084] divide_with(dividend), a data processing logic unit, indicates dividing data. For example, for the data processing logic unit divide_with(6), after 2 is passed in, 3 is returned.

[0085] is_positive(), a data verification logic unit, verifies whether the data is a positive number. For example, for the data verification logic unit is_positive(), if 6 is passed in, it will be verified as true and 6 will be returned; if -1 is passed in, it will be verified as false and an exception will be thrown.

[0086] non_positive(), a data verification logic unit, verifies whether the data is a non-positive number. For example, for the data verification logic unit non_positive(), if 6 is passed in, it will be verified as false and an exception will be thrown; if -1 is passed in, it will be verified as true and -1 will be returned.

[0087] interval(lower,upper), a data verification logic unit, verifies whether the data is in the interval [lower,upper]. For example, for the verification unit interval(1,5), if 0 is passed in, the verification is false and an exception is thrown; if 3 is passed in, the verification is true and 3 is returned; if 6 is passed in, the verification is false and an exception is thrown.

[0088] numeric(), a compound logic unit, processing type converts various types of data into numeric types. For example, for the compound logic unit numeric(), if 1 is passed in, 1 is returned; if the string + inf is passed in, the number math.inf is returned (this is a legal number in Python); if the string abcdefgh is passed in, an exception will be thrown because the data is illegal.

[0089] (2) Character class units, as follows:

[0090] upper(), a data processing logic unit, converts string data to uppercase. For example, for the data processing logic unit upper(), if the string abc is passed in, ABC will be returned.

[0091] enum(items), a data validation logic unit, verifies whether the string data is any item in the enumeration. For example, for the data validation logic unit enum(["NORTH","EAST","WEST","SOUTH"]), if the string NORTH is passed in, it is verified to be true and the string NORTH is returned; if the string UPPER is passed in, it is verified to be false and an exception is thrown.

[0092] rematch(regexp), a data validation logic unit, verifies whether the string data satisfies a given regular expression. For example, for the data validation logic unit rematch("^[a-zA-Z0-9_]+$"), if the string abc_123 is passed in, the verification is true and the string abc_123 is returned; if the string *$#@% is passed in, the verification is false and an exception is thrown.

[0093] refind(regexp), a compound logic unit, extracts a substring that matches the specified regular expression from the given string data, and throws an exception if no match is found. For example, for the compound logic unit refind("[a-zA-Z0-9_]+@[a-zA-Z0-9\.]+"), the string email:mymail@gmail.com is passed in, and mymail@gmail.com is returned; the string email is bullshit is passed in, and no match is found, and an exception is thrown.

[0094] (3) Type class unit, as follows:

[0095] to_type(type), a data processing logic unit, converts the given data to the specified type and returns it. For example, for the data processing logic unit to_type(int), if a string + 345 is passed in, the integer number 345 is returned; if a floating point number 345.123 is passed in, the rounded number 345 is returned.

[0096] is_type(type), a data validation logic unit, verifies whether the data is of a specified type. For example, for the data validation logic unit is_type(int), if the integer 345 is passed in, the verification is true and 345 is returned; if the string + 345 is passed in, the verification is false and an exception is thrown.

[0097] (4) Structural units, as follows:

[0098] mapping(mps), a compound logic unit, determines whether the given data is of a mapping type and attempts to perform various processing. For example, for the compound logic unit mapping({'a':is_type(int),'b':refind('[az]+')}), if the dictionary type data {'a':233,'b':'abcde345'} is passed in, the dictionary type data {'a':233,'b':'abcde'} will be returned; if the dictionary type data {'a':233.45,'b':'abcde'} is passed in, the verification in the is_type(int) child logic unit is false, so the verification is false and an exception is thrown; if the string type data abcde is passed in, the format is wrong and an exception is thrown.

[0099] list(lst), compound logic unit, determines whether the given data is a list type, and attempts to perform various processing. For example, for the compound logic unit list(refind("[a-zA-Z0-9_]+@[a-zA-Z0-9\.]+")), the input list type ['abc@126.comxxx','bt@gmail.com...'], the return list type ['abc@126.com','bt@gmail.com']; the input list type ['abcde','bt@gmail.com...'], the first item is verified to be false, so the verification is false and an exception is thrown; the input string type data abcde, the format is wrong, and an exception is thrown.

[0100] (5) Tool units, as follows:

[0101] true(), data processing logic unit, always true. For example, for the data processing logic unit true(), no matter what value is passed in, it will be verified as true and return the passed in value. Therefore, to a certain extent, it is reasonable to regard true as a processing or even composite unit.

[0102] value(v), a data processing logic unit, will return v regardless of any value passed in.

[0103] check_only(p), a data verification logic unit, performs all the verification and processing done by p, but ultimately only returns the original value passed in. For example, check_only(refind("[a-zA-Z0-9_]+@[a-zA-Z0-9\.]+")), passes in the string abc@126.com xxx, refind's verification is true, and returns abc@126.com, but when it returns to the check_only layer, it still returns the original value passed in, that is, abc@126.com xxx; passes in the string abcde, refind throws an exception, so check_only will also throw an exception.

[0104] It is understandable that although the above-mentioned logical architecture system can realize the construction of data verification systems with various functions, it does not support some complex mathematics and object operations well enough. It requires a large number of basic logic units such as plus(x) and minus(x) to build. When the mathematics and object expressions become complex, they look unintuitive and difficult to maintain.

[0105] Thus, in some embodiments, see Figure 2 As shown, the logic architecture system 100 further includes a unit conversion module 30. The unit conversion module 30 can convert the above basic logic units and / or the connected logic units into corresponding computing units; wherein the computing units support the operation of at least one operator.

[0106] Exemplarily, the logic architecture system 100 can establish a computing system (i.e., a unit conversion module), which can be constructed based on the operator overloading operation of Python and can be converted to and from the aforementioned logic units. In this embodiment, the supported operator overloading operations include: addition, added, subtraction, subtracted, multiplication, multiplied, division, divided, remainder, remainder, exponentiation, exponentiation, get item (i.e., __getitem__), get attribute (i.e., __getattr__), and run (i.e., __call__).

[0107] In addition, the unit conversion module 30 can also convert the established computing unit into a corresponding basic logic unit or a corresponding connected logic unit. For example, if the designed computing unit is x, then in the program, x+1 represents the action of x+1, and converting x+1 back to a basic logic unit is equivalent to plus(1); 3**((x+1)*2) back to a connected logic unit is equivalent to plus(1)>>multi(2)>>power_with(3); other operations and calculations are similar and will not be repeated here.

[0108] It can be understood that in actual applications, some existing processing or verification logic may still be presented in the form of functions. Therefore, in some embodiments, the logic unit establishment module 10 can also construct a functional logic unit based on a preset function, so that it can be compatible with existing function-based logic methods.

[0109] For example, the Decorator Pattern can be used to decorate an existing function (preset function) to form a functional logic unit, where the Decorator Pattern allows adding new functions to an existing object without changing its structure. This type of design pattern belongs to the structural pattern, which is a wrapper for an existing class. For example, for the following code:

[0110]

[0111] After decoration

[0112]

[0113] Then the logical unit add(plus(1),minus(2)) can be formed

[0114] Specifically, when the value 1 is passed in, plus(1) gets the result 2, and minus gets the result -1. In add(2,-1), an exception is thrown because b<0, and the verification is false.

[0115] When the input value is 2, plus(1) gets the result 3, minus gets the result 0, and add(3,0) gets the result 3, which is verified to be true.

[0116] Therefore, in the embodiment of the present disclosure, the existing verification logic written based on functions can be effectively utilized in the data verification processing link, thereby improving the user experience of the logic architecture system 100.

[0117] Based on the same technical concept, the embodiments of the present disclosure also provide a method for establishing a logical architecture system corresponding to the logical architecture system. Since the principle of solving the problem by the method in the embodiments of the present disclosure is similar to the above-mentioned logical architecture system in the embodiments of the present disclosure, the implementation of the method can refer to the implementation of the system, and the repeated parts will not be repeated.

[0118] See also Figure 3 As shown, it is a flowchart of a method for establishing a logical architecture system provided in an embodiment of the present disclosure. The method for establishing a logical architecture system includes the following S101 to S102:

[0119] S101, establishing at least two basic logic units, wherein the basic logic units include at least one of a data verification logic unit, a data processing logic unit and a compound logic unit, and the compound logic unit has both data verification and data processing functions.

[0120] S102, establishing at least one connection unit, wherein the connection unit is used to connect any two basic logic units among the at least two basic logic units to obtain a connected logic unit; the basic logic units and the at least one connection unit are used to construct a data verification system, wherein the data verification is used to verify and / or process the data to be verified.

[0121] See also Figure 4 FIG. 2 is a flow chart of a data verification method provided by an embodiment of the present disclosure, and the data verification method includes the following S201 to S202:

[0122] S201, constructing a target data verification system based on target requirements and the logical architecture system described in any of the aforementioned embodiments.

[0123] S202: input the data to be verified into the target data verification system to verify and / or process the data to be verified.

[0124] Exemplarily, a target data verification system can be constructed based on the logic architecture system 100 and target requirements described in any of the aforementioned embodiments. Specifically, a target logical unit can be determined from at least two basic logical units and a target connection unit can be determined from at least one connection unit according to the target requirements, and a target data verification system can be constructed based on the determined target logical unit and target connection unit. Then, the data to be verified is input into the target data verification system to verify and / or process the data to be verified to obtain a verification result or a processing result.

[0125] It should be noted that, in some implementations, the data verification process includes, but is not limited to, verifying whether the data itself is correct, verifying whether the data logic is correct, etc., and also includes various operations on the data.

[0126] The target requirements are set according to the actual situation. For example, the target requirements can be determined according to the complexity of the data to be verified. The data to be verified can be data under any data control logic in the machine learning system. For example, it can be the verification of the system's hyperparameters under the model training task, the verification of the training framework code control logic, the verification of the computing resource scheduling and allocation rules, etc., without specific limitation. The fields involved in machine learning include but are not limited to face recognition, machine translation, game decision-making, etc.

[0127] Exemplarily, the target requirement may be determined in response to target parameter information input by a user, or may be determined based on task information sent upstream by an application service, or may be obtained by parsing some task configuration files, and the specific implementation method is not limited.

[0128] In addition, the execution subject of the method for establishing the logical architecture system and the data verification method provided in the embodiments of the present disclosure is generally a computer device with certain computing capabilities, and the computer device includes, for example: a terminal device or a server or other processing device, and the terminal device can be a mobile device, a user terminal, a handheld device, etc. The server can be an independent physical server, or a server cluster or a distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. In some possible implementations, the data verification method can be implemented by a processor calling computer-readable instructions stored in a memory.

[0129] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0130] Based on the same technical concept, a data verification device corresponding to the data verification method is also provided in the embodiment of the present disclosure. Since the principle of solving the problem by the device in the embodiment of the present disclosure is similar to the above-mentioned data verification method in the embodiment of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0131] See also Figure 5 FIG. 5 is a schematic diagram of a data verification device 500 provided in an embodiment of the present disclosure, and the data verification device 500 includes:

[0132] The system construction module 501 is used to construct a target data verification system based on target requirements and the logical architecture system described in any of the aforementioned embodiments.

[0133] The data verification module 502 is used to input the data to be verified into the target data verification system to verify and / or process the data to be verified.

[0134] Based on the same technical concept, the embodiment of the present disclosure also provides an electronic device. Figure 6 , which is a schematic diagram of the structure of an electronic device 700 provided in an embodiment of the present disclosure, including a processor 701, a memory 702, and a bus 703. The memory 702 is used to store execution instructions, including a memory 7021 and an external memory 7022; the memory 7021 is also called an internal memory, which is used to temporarily store the operation data in the processor 701 and the data exchanged with the external memory 7022 such as a hard disk. The processor 701 exchanges data with the external memory 7022 through the memory 7021.

[0135] In the embodiment of the present application, the memory 702 is specifically used to store the application code for executing the solution of the present application, and the execution is controlled by the processor 701. That is, when the electronic device 700 is running, the processor 701 communicates with the memory 702 through the bus 703, so that the processor 701 executes the application code stored in the memory 702, and then executes the method described in any of the above embodiments.

[0136] Among them, the memory 702 can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0137] The processor 701 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present invention may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0138] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 700. In other embodiments of the present application, the electronic device 700 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0139] The present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for establishing a logical architecture system or the method for verifying data in the above method embodiment are executed. The storage medium may be a volatile or non-volatile computer-readable storage medium.

[0140] The embodiments of the present disclosure also provide a computer program product, which carries a program code. The instructions included in the program code can be used to execute the steps of the method for establishing a logical architecture system or the method for data verification in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0141] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is implemented as a computer storage medium. In another optional embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0142] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0143] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0144] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0145] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

[0146] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A logical architecture system, characterized in that: include: A logic unit establishment module, used to establish at least two basic logic units, wherein the basic logic units include at least one of a data verification logic unit, a data processing logic unit and a composite logic unit, wherein the composite logic unit has both data verification and data processing functions; A connection unit establishment module is used to establish at least one connection unit, and the connection unit is used to connect any two basic logical units among the at least two basic logical units to obtain a connected logical unit; the basic logical units and the at least one connection unit are used to construct a data verification system, and the data verification is used to verify and / or process the data to be verified.

2. The system according to claim 1, characterized in that in, The connection unit includes at least one of a connection unit, a connection unit and a pipeline connection unit. The pipeline connection unit is used to connect two basic logic units in series, and the basic logic unit located after the pipeline connection unit receives the processing result of the basic logic unit located before the pipeline connection unit.

3. The system according to claim 1, characterized in that The data verification logic unit is used to verify the authenticity of the data, and if the data verification is true, returns the value of the input data, and if the data verification is false, throws an exception; the data processing logic unit is used to process the data and return the processing result.

4. The system according to claim 2, characterized in that The priority of the pipeline connection unit is higher than that of the and connection unit, and the and connection unit has a higher priority than that of the or connection unit.

5. The system according to claim 1, characterized in that The types of the basic logic units include at least one of a numerical logic unit, a character logic unit, a type logic unit, a structure logic unit and a tool logic unit.

6. The system according to claim 1, characterized in that The system further comprises: A unit conversion module is used to convert the basic logic unit and / or the connected logic unit into a corresponding calculation unit; wherein the calculation unit supports the operation of at least one operator.

7. The system according to claim 6, characterized in that The unit conversion module is also used to convert the established computing unit into a corresponding basic logic unit or a corresponding connected logic unit.

8. The system according to claim 1, characterized in that The logic unit building module is also used to build a function logic unit based on a preset function.

9. A method for establishing a logical architecture system, characterized in that: include: Establish at least two basic logic units, wherein the basic logic unit includes at least one of a data verification logic unit, a data processing logic unit and a composite logic unit, wherein the composite logic unit has both data verification and data processing functions; Establish at least one connection unit, wherein the connection unit is used to connect any two basic logic units among the at least two basic logic units to obtain a connected logic unit; the basic logic units and the at least one connection unit are used to construct a data verification system, wherein the data verification is used to verify and / or process the data to be verified.

10. A data verification method, characterized in that: include: Based on the target requirements and the logical architecture system as described in any one of claims 1 to 8, a target data verification system is constructed; The data to be verified is input into the target data verification system to verify and / or process the data to be verified.

11. A data verification device, characterized in that: include: A system building module, used to build a target data verification system based on target requirements and the logical architecture system as described in any one of claims 1 to 8; The data verification module is used to input the data to be verified into the target data verification system to verify and / or process the data to be verified.

12. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate via the bus. When the machine-readable instructions are executed by the processor, the method for establishing a logic architecture system as described in claim 9 is performed, or the data verification method as described in claim 10 is performed.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed by a processor, executes the method for establishing a logical architecture system as claimed in claim 9, or the data verification method as claimed in claim 10.

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