Packaging structure, device, board and method for layout of integrated circuit

Abstract

This disclosure provides a package structure, an integrated circuit device, a board, and a method for placing integrated circuits on a wafer in the package structure. A system-on-chip (SoC) is die-mounted in the system area of ​​the wafer; a memory is die-mounted in the storage area of ​​the wafer; and multiple capacitors are die-mounted in the capacitor area of ​​the wafer. The capacitor area is the outlier region outside the system area and the storage area.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductors and, more particularly, to a package structure, an integrated circuit device, a board, and a method for placing an integrated circuit on a wafer in a package structure. Background Art

[0002] CoWoS (chip on wafer on substrate) is an integrated manufacturing technology that first connects the chip to the silicon wafer through the CoW (chip on wafer) packaging process, and then connects the CoW chip to the substrate to form the CoWoS. This technology allows multiple chips to be packaged together, with the bare chips on the plane interconnected via a silicon interposer, achieving the technical benefits of a small package size, low power consumption, and a small number of pins. CoWoS is powered by capacitors.

[0003] A common application is to package multiple chips with different functions using CoWoS. However, configuring multiple capacitors often increases chip area, leading to higher costs. Therefore, a solution that saves area to accommodate capacitors is urgently needed. Summary of the Invention

[0004] In order to at least partially solve the technical problems mentioned in the background technology, the solution disclosed herein provides a packaging structure, an integrated circuit device, a board, and a method for layout of integrated circuits on a wafer of the packaging structure.

[0005] In one aspect, the present disclosure discloses a method for layout of integrated circuits on a wafer in a packaged structure, comprising: die-attaching a system-on-chip (SoC) in a system area on the wafer; die-attaching a memory in a storage area on the wafer; and die-attaching a plurality of capacitors in a capacitor area on the wafer. The capacitor area is an outlier region outside the system area and the storage area.

[0006] In another aspect, the present disclosure discloses a package structure comprising a system-on-chip (SoC), memory, and multiple capacitors. The SoC is disposed in a system region on a wafer; the memory is disposed in a storage region on the wafer; and multiple capacitors are disposed in a capacitor region on the wafer. The capacitor region is an out-of-range region outside the system region and the storage region.

[0007] In another aspect, the present disclosure discloses an integrated circuit device including the aforementioned package structure; and also discloses a board including the aforementioned integrated circuit device.

[0008] In order to fully utilize the area of ​​the chip, the solution disclosed herein appropriately plans the layout of the capacitor to save area, which not only improves the capacitance value but also saves manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts.

[0010] Figure 1 is a structural diagram showing a board according to an embodiment of the present disclosure;

[0011] Figure 2 is a structural diagram showing an integrated circuit device according to an embodiment of the present disclosure;

[0012] Figure 3 is a schematic diagram showing the internal structure of a computing device according to an embodiment of the present disclosure;

[0013] Figure 4 is a schematic diagram showing the internal structure of a processor core according to an embodiment of the present disclosure;

[0014] Figure 5 is a schematic diagram showing a layout of a packaging structure according to an embodiment of the present disclosure;

[0015] Figure 6 is a schematic diagram showing the layout of another packaging structure according to an embodiment of the present disclosure;

[0016] Figure 7 is a schematic diagram showing the layout of another packaging structure according to an embodiment of the present disclosure;

[0017] Figure 8 is a schematic diagram showing the layout of another packaging structure according to an embodiment of the present disclosure;

[0018] Figure 9 1 is a diagram showing various spacing limitations associated with capacitors in the disclosed embodiment;

[0019] Figure 10 is a flow chart illustrating the layout of integrated circuits on a wafer according to another embodiment of the present disclosure;

[0020] Figure 11 2 is a cross-sectional view showing the structure of the CoW packaging process according to an embodiment of the present disclosure;

[0021] Figure 12 1 is a cross-sectional view showing the structure of the CoWoS packaging process according to an embodiment of the present disclosure;

[0022] Figure 13is a flow chart showing another embodiment of the present disclosure for fabricating a CoWoS structure on a wafer;

[0023] Figure 14A is a cross-sectional view of a packaging structure corresponding to each step of another embodiment of the present disclosure;

[0024] Figure 14B is a cross-sectional view of a packaging structure corresponding to each step of another embodiment of the present disclosure;

[0025] Figure 15A is a cross-sectional view of a packaging structure corresponding to each step of another embodiment of the present disclosure;

[0026] Figure 15B is a cross-sectional view of a packaging structure corresponding to each step of another embodiment of the present disclosure; and

[0027] Figure 15C 1 is a cross-sectional view of a packaging structure corresponding to each step of another embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The following will clearly and completely describe the technical solutions in the embodiments of this disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this disclosure, not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this disclosure.

[0029] It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, specification, and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0030] It should also be understood that the terminology used in this disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the term "and / or" as used in this disclosure and the claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0031] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context.

[0032] The specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0033] Today's semiconductor manufacturing process begins with a complete wafer, a thin, circular sheet of pure silicon, typically available in sizes ranging from 6 inches, 8 inches, and 12 inches. The wafer is then cut into small pieces, called dies. Each die is mounted with a chip and wired to achieve a specific electrical function. The die is then packaged into a single unit to house, secure, seal, and protect the chip, while enhancing its electrical and thermal performance. Wires are then used to connect the chip's contacts to the pins of the package housing, completing the chip package.

[0034] One embodiment of the present disclosure is a CoWoS packaging structure formed on a wafer. In this embodiment, the chip mainly includes memory and a system-on-chip, but the present disclosure is not limited to packaging only the aforementioned components.

[0035] The memory is used to temporarily store computational data required by the system-on-chip (SoC) and to exchange data with external memory. In this embodiment, the memory may be high-bandwidth memory (HBM), a high-performance DRAM fabricated using a 3D stacking process. It is suitable for applications requiring high memory bandwidth, such as graphics processors and network switching and forwarding equipment (e.g., routers and switches).

[0036] System on a chip (SoC) refers to a technology that integrates a complete system on a single chip, packaging all or part of the necessary electronic circuits. In this embodiment, the system on a chip is assembled on a board. Figure 1 FIG. 1 is a schematic diagram showing the structure of a board 10 according to an embodiment of the present disclosure. Figure 1 As shown, board 10 includes a combined processing device 101, which is an artificial intelligence computing unit that supports various deep learning and machine learning algorithms, meeting the intelligent processing needs in complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. Deep learning technology is particularly widely used in the field of cloud intelligence. A notable feature of cloud-based intelligent applications is the large amount of input data, which places high demands on the platform's storage and computing capabilities. Board 10 of this embodiment is suitable for cloud-based intelligent applications and has extensive off-chip storage, on-chip storage, and substantial computing power.

[0037] The combined processing device 101 is connected to an external device 103 via an external interface device 102. External device 103 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Data to be processed can be transmitted from the external device 103 to the combined processing device 101 via the external interface device 102. The calculation results of the combined processing device 101 can be transmitted back to the external device 103 via the external interface device 102. Depending on the application scenario, the external interface device 102 may have different interface formats, such as a PCIe interface.

[0038] Board 10 also includes an external memory 104 for storing data, which includes one or more storage units 105. External memory 104 is connected to a control device 106 and combined processing device 101 via a bus for data transmission. Control device 106 in board 10 is configured to control the state of combined processing device 101. To this end, in one application scenario, control device 106 may include a microcontroller (MCU).

[0039] Figure 2 1 is a schematic diagram showing the combination processing device 101 of this embodiment. Figure 2 As shown in FIG, combined processing device 101 includes computing device 201, interface device 202, processing device 203, and DRAM 204. In one application scenario, computing device 201, interface device 202, and processing device 203 are integrated into the aforementioned system-on-chip. In another application scenario, computing device 201 itself is the aforementioned system-on-chip.

[0040] The computing device 201 is configured to perform user-specified operations and is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 203 through the interface device 202 to jointly complete the user-specified operations.

[0041] Interface device 202 is used to transmit data and control instructions between computing device 201 and processing device 203. For example, computing device 201 can obtain input data from processing device 203 via interface device 202 and write it to a storage device on-chip of computing device 201. Furthermore, computing device 201 can obtain control instructions from processing device 203 via interface device 202 and write them to a control cache on-chip of computing device 201. Alternatively or optionally, interface device 202 can also read data from the storage device of computing device 201 and transmit it to processing device 203.

[0042] The processing device 203 is a general processing device that performs basic controls including but not limited to data handling, starting and / or stopping the computing device 201, etc. Depending on the implementation method, the processing device 203 can be one or more types of processors in a central processing unit, a graphics processing unit or other general and / or special processors, these processors include but are not limited to a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, only with respect to the computing device 201 disclosed in the present invention, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 201 and the processing device 203 are integrated and considered together, the two are regarded as forming a heterogeneous multi-core structure.

[0043] The DRAM 204 is the aforementioned high-bandwidth memory, which is used to store data to be processed. The size is usually 16G or larger, and is used to save data of the computing device 201 and / or the processing device 203.

[0044] Figure 3 The figure shows a schematic diagram of the internal structure of a computing device 201. The computing device 201 is used to process input data for computer vision, speech, natural language processing, data mining, and other applications. The computing device 201 in the figure adopts a multi-core layered structure design, which includes an external storage controller 301, a peripheral communication module 302, an on-chip interconnect module 303, a synchronization module 304, and multiple clusters 305.

[0045] There can be multiple external storage controllers 301, and two are shown in the figure as an example. They are used to respond to access requests issued by the processor core and access external storage devices, such as Figure 2DRAM204 in the chip, thereby reading data from outside the chip or writing data. The peripheral communication module 302 is used to receive control signals from the processing device 203 through the interface device 202, and start the computing device 201 to perform tasks. The on-chip interconnect module 303 connects the external storage controller 301, the peripheral communication module 302 and multiple clusters 305 to transmit data and control signals between each module. The synchronization module 304 is a global synchronization barrier controller (GBC) used to coordinate the work progress of each cluster and ensure information synchronization. Multiple clusters 305 are the computing cores of the computing device 201. Four are shown as an example in the figure. With the development of hardware, the computing device 201 disclosed in this disclosure can also include 8, 16, 64, or even more clusters 305. Clusters 305 are used to efficiently execute deep learning algorithms.

[0046] Each cluster 305 includes multiple processor cores (IPU cores) 306 and a memory core (MEM core) 307 .

[0047] The figure shows four processor cores 306 as an example, but the present disclosure does not limit the number of processor cores 306. Figure 4 Each processor core 306 includes three modules: a control module 41 , a calculation module 42 and a storage module 43 .

[0048] The control module 41 coordinates and controls the operations of the computing module 42 and the storage module 43 to complete deep learning tasks. It includes an instruction fetch unit (IFU) 411 and an instruction decode unit (IDU) 412. The instruction fetch unit 411 retrieves instructions from the processing device 203, while the instruction decode unit 412 decodes the retrieved instructions and sends the decoded results as control information to the computing module 42 and the storage module 43.

[0049] The operation module 42 includes a vector operation unit 421 and a matrix operation unit 422. The vector operation unit 421 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformation. The matrix operation unit 422 is responsible for the core calculations of the deep learning algorithm, namely matrix multiplication and convolution.

[0050] The memory module 43 is used to store or transfer relevant data and includes a neuron RAM (NRAM) 431, a weight RAM (WRAM) 432, an input / output direct memory access module (IODMA) 433, and a move direct memory access module (MVDMA) 434. NRAM 431 is used to store input and output data and intermediate results for calculations by the processor core 306; WRAM 432 is used to store the weights of the deep learning network; IODMA 433 controls memory access between NRAM 431 / WRAM 432 and DRAM 204 via the broadcast bus 309; and MVDMA 434 controls memory access between NRAM 431 / WRAM 432 and SRAM 308.

[0051] Back to Figure 3 The storage core 307 is primarily used for storage and communication, namely, storing shared data or intermediate results between the processor cores 306, and performing communication between the cluster 305 and the DRAM 204, between the clusters 305, and between the processor cores 306. In other embodiments, the storage core 307 has scalar operation capabilities and is used to perform scalar operations.

[0052] The storage core 307 includes a shared memory unit (SRAM) 308, a broadcast bus 309, a cluster direct memory access module (CDMA) 310, and a global direct memory access module (GDMA) 311. The SRAM 308 acts as a high-performance data transfer station. Data reused between different processor cores 306 within the same cluster 305 does not need to be obtained from the DRAM 204 by each processor core 306. Instead, it is transferred between the processor cores 306 via the SRAM 308. The storage core 307 only needs to quickly distribute the reused data from the SRAM 308 to multiple processor cores 306, thereby improving inter-core communication efficiency and significantly reducing on-chip and off-chip input / output access.

[0053] The broadcast bus 309, CDMA 310, and GDMA 311 are used for communication between the processor cores 306, communication between the clusters 305, and data transmission between the clusters 305 and the DRAM 204, respectively. Each of these will be described below.

[0054] The broadcast bus 309 facilitates high-speed communication between the processor cores 306 within the cluster 305. In this embodiment, the broadcast bus 309 supports inter-core communication methods including unicast, multicast, and broadcast. Unicast refers to point-to-point data transmission (i.e., from one processor core to another), multicast transfers a copy of data from the SRAM 308 to a specific number of processor cores 306, and broadcast transfers a copy of data from the SRAM 308 to all processor cores 306, a special case of multicast.

[0055] CDMA 310 controls memory access to SRAM 308 between different clusters 305 within the same computing device 201. GDMA 311 cooperates with external memory controller 301 to control memory access from SRAM 308 of cluster 305 to DRAM 204, or reads data from DRAM 204 to SRAM 308.

[0056] Figure 5 A schematic diagram illustrating the layout of a package structure according to this embodiment is shown. This package structure is located in a molding compound region 50 of a wafer. The molding compound region 50 includes a system area 51 and two memory areas 52. The system area 51 is located in the center of the molding compound region 50, and the memory areas 52 are located on either side of the system area 51. The chip in the package structure includes a system-on-chip 501 and multiple memories 502. The system-on-chip 501 is the aforementioned system-on-chip and may include only the computing device 201 or the computing device 201, the interface device 202, and the processing device 203. The system-on-chip 501 is located in the system area 51, and the memories 502 are DRAMs 204. In this embodiment, there are six DRAMs 204, which are evenly distributed in the memory area 52, with three memories 502 located in each side of the memory area 52.

[0057] Due to the size of the system on chip 501 and the memory 502, there will be zero-zero areas when laying out these chips. The zero-zero areas refer to the idle areas outside the system area 51 and the memory area 52 in the molding compound area 50. In this embodiment, the capacitors required for the CoWoS structure are laid out in these zero-zero areas. Figure 5 As shown, this chip layout creates out-of-range regions on the top and bottom sides of the system area 51, and capacitors are placed in these out-of-range regions. More specifically, the chip in the package structure also includes multiple capacitors 503. The molding compound area 50 includes two capacitor regions 53, one located in the out-of-range region of the molding compound area 50, namely, the top and bottom sides of the system area 51. These capacitors 503 are evenly distributed in the capacitor regions 53 to fully utilize the area of ​​the molding compound area 50.

[0058] If the capacitor area 53 is not large enough to accommodate all the capacitors required for the CoWoS structure, this embodiment can place the remaining capacitors outside the molding compound area 50. Figure 5 As shown, the chip also includes non-molding compound areas 54 located on the top and bottom sides of the molding compound area 50 to accommodate more capacitors. This embodiment does not limit the location of non-molding compound areas 54; essentially, any area around the molding compound area 50 can serve as non-molding compound areas 54, with their size determined by the number and size of the capacitors. In this embodiment, capacitors are preferably placed in the non-molding compound areas within the molding compound area 50. If space is insufficient, capacitors can be placed in the non-molding compound areas 54.

[0059] This embodiment does not limit the specifications of the capacitor. According to the specific requirements of the chip, any suitable capacitor on the market can be used, such as but not limited to the capacitor model GRM2165C1H333GA01 produced by Murata.

[0060] Apart from Figure 5 Chip layout, Figure 6 A schematic diagram shows the layout of another package structure of this embodiment. Unlike the previous layout, the zero-shaped regions appear at the four corners of the molding compound area 50, and the capacitors are arranged in these zero-shaped regions. More specifically, the molding compound area 50 includes four capacitor regions 53, located at the four corners of the molding compound area 50. The capacitors 503 are evenly distributed within these capacitor regions 53 to fully utilize the area of ​​the molding compound area 50.

[0061] Figure 7 A schematic diagram shows the layout of another package structure of this embodiment. Unlike the previous layout, four memory cells 502 are located at the four corners of the molded material area 50, and the mismatched region appears between the two memory regions 52 on either side of the system area 51. Therefore, the molded material area 50 includes two capacitor regions 53, located between the two memory regions 52 on either side of the system area 51. These capacitors 503 are evenly distributed within the capacitor regions 53 to fully utilize the area of ​​the molded material area 50.

[0062] Figure 8 Schematic diagram of another packaging structure layout of this embodiment is shown. The difference from the above layout is that the system area 51 is provided with two on-chip systems 501. Figure 5 The layout of FIG5 is similar in that the zero regions appear on the top and bottom sides of the system region 51 , so the capacitor 503 is arranged in these zero regions.

[0063] Figures 5 to 8The several chip layouts shown are merely examples of possible locations for the zero region, i.e., the capacitor region. Generally speaking, the capacitor region is located in the zero region of the molding compound area 50 , which can be between the system region 51 and the chip edge, between the system region 51 and the memory region 52 , between the memory region 52 and the chip edge, or between memory regions 52 and other memory regions 52 .

[0064] Due to the engineering limitations of semiconductor manufacturing processes, the distance between chips and capacitors is restricted to ensure that all components can operate normally without generating electrical interference. Figure 9 1 shows various spacing limitations associated with the capacitors in this embodiment. Distance d1 between capacitor 503 and system area 51 must be greater than 0.5 mm, distance d2 between capacitor 503 and storage area 52 must be greater than 1 mm, distance d3 between capacitor 503 and the wafer edge (boundary 901 of molding compound region 50) must be greater than 0.5 mm, and distance d4 between capacitors 503 must be greater than 0.5 mm.

[0065] Although Figures 6 to 8 The non-molding material area 54 is not shown in the chip layout of FIG. 1 , which does not mean that these chip layouts do not need the non-molding material area 54 to accommodate more capacitors. Figure 5 It is easy to understand from the above description that various chip layouts can configure the non-molding material area 54 around the molding material area 50 to accommodate capacitors, so it is not described in detail.

[0066] In addition to the system on chip 501 and the memory 502, the chip disclosed herein may also include various integrated circuits, such as various passive and active microelectronic devices, such as resistors, other types of capacitors (such as MIMCAPs), inductors, diodes, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal oxide semiconductor (LDMOS) transistors, high-power metal oxide semiconductor transistors, or other types of transistors.

[0067] This embodiment uses the zero-area outside the system area and storage area as a capacitor area to layout the capacitors required by the chip, thereby reducing the area of ​​the chip. Under the premise that the wafer size remains unchanged, the reduced chip volume means that a single wafer can accommodate more chips, thereby achieving the technical effect of reducing manufacturing costs.

[0068] Another embodiment of the present disclosure is a method for placing integrated circuits on a wafer, the flow chart of which is as follows: Figure 10 shown.

[0069] In step 1001, a system-on-chip (SoC) is die-attached in the system area of ​​a wafer. As previously described, the chip layout is located in the molding compound area of ​​the wafer, which includes the system area and the memory area. The chip in the package structure includes the SoC and the memory. This embodiment utilizes die-attach technology to place the SoC in the system area.

[0070] An exemplary die attach technology is controlled collapse chip connection (C4). Controlled collapse chip connection uses high-temperature solder, flux, or solder paste applied to tinned electrodes on a substrate or transferred to the solder balls of a chip. The chip is then placed on the substrate and heated during attachment to reflow the connection or batch reflow in a standard reflow oven.

[0071] In step 1002, a memory is mounted on a chip in the storage area of ​​the wafer. There can be multiple memories, depending on actual needs. The memory of this embodiment can be a high-bandwidth memory, which is a multi-layer DRAM stacked on top of each other and finally mounted in the storage area. High-bandwidth memory creates a high-bit-width, low-frequency video memory, so that it does not require such a high frequency while providing a relatively large video memory bit width. Under the same 4GB capacity, the video memory bit width that high-bandwidth memory can provide is 4096 bits, which is several times higher than GDDR5. The emergence of high-bandwidth memory expands the chip layout from 2D to 3D, which helps to reduce the area of ​​the chip.

[0072] In step 1003, multiple capacitors are chip-mounted on the capacitor area on the chip. As mentioned above, the capacitor area of ​​this embodiment is the odd-numbered area outside the system area and the storage area. This embodiment arranges the capacitors required for the CoWoS structure in these odd-numbered areas to fully utilize the area of ​​the molding compound area 50, thereby reducing the chip area. The capacitor area of ​​this embodiment can be located between the system area and the edge of the chip, between the system area and the storage area, between the storage area and the edge of the chip, and between the storage area and the storage area. The spacing restrictions related to the capacitors are as follows: Figure 9 As shown, no further details are given.

[0073] Figure 11A cross-sectional view of the packaging process structure of the CoW of the aforementioned embodiment is shown. The structure first generates multiple through silicon vias (TSVs) 1102 on the wafer 1101. The through silicon via technology is a high-density packaging technology that replaces the wire bonding technology. It uses conductive materials such as copper, tungsten, and polysilicon to achieve vertical electrical interconnection of the through silicon vias. This technology reduces the interconnection length through vertical interconnection, reduces signal delay and unnecessary capacitance / inductance, and achieves low power consumption, high-speed communication between chips, increases bandwidth, and realizes miniaturization of device integration. Then, microbump preparation technology is used to form microbumps 1103 to bond the chip 1104, capacitor 1105, and wafer 1101 together. The chip 1104 in the figure exemplarily includes the aforementioned system on chip and multiple memories.

[0074] CoWoS is Figure 11 It is based on the CoW process and then connected to the substrate. Figure 12 The CoWoS packaging process structure is shown. First, the chip 1104 is filled with underfill, then solder balls 1201 are applied and bonded to a substrate (such as a printed circuit board) 1202. Finally, the package 1203 is added to complete the process.

[0075] In the disclosed embodiments, multiple capacitors are formed on wafer 1101 to provide power to the chip. The larger the capacitance, the more stable the power supply. For deep learning chips with high power consumption, large capacitance is crucial. This disclosure proposes a method for providing high capacitance by placing capacitors in the zero-out region of the CoWoS process.

[0076] Another embodiment of the present disclosure is a method for forming a CoWoS structure on a wafer, that is, first forming Figure 11 The CoW structure shown is then made Figure 12 The CoWoS structure shown in FIG. Figure 13 14 and 15 show cross-sectional views of the packaging structures corresponding to the steps of this embodiment.

[0077] First, this embodiment uses silicon through vias to form multiple redistribution layers on the first side of the chip. More specifically, in step 1301, a plurality of silicon through via layers are formed on the first side of the chip 1401 (ie, the chip 1101) using a mask. Figure 14Aillustratively shows first TSV layer 1402 and second TSV layer 1403. In this embodiment, if the thickness of wafer 1401 is 775 microns, the TSV layer depth is 107 microns. In step 1302, a thermal wet oxidation process is used on the first side surface to generate water vapor, which chemically reacts with the silicon material of the wafer to form a first dielectric layer 1404 on the first side surface. First dielectric layer 1404 is composed of silicon nitride. After this step is completed, structure 141 is formed on the first side of wafer 1401.

[0078] In step 1303 , a conductive layer 1409 is electroplated. The conductive layer 1409 is made of copper. After this step, a structure 142 is formed on the first side of the wafer 1401 .

[0079] In step 1304, multiple redistribution layers 1405 are deposited. Chemical mechanical polishing (CMP) is first used to smooth the surface of the first side, and the conductive layer 1409 on the first side is removed, leaving only the conductive layer 1409 within the TSV layer. The function of the redistribution layers 1405 is to electrically connect the TSV layer to the chip contacts. Based on the actual chip contact requirements, these redistribution layers 1405 must be specifically designed to ensure that the contacts are properly electrically connected to the appropriate TSV layer. Figure 14A Only two layers of redistribution layers 1405 are shown as examples, with dielectric deposited between them. After this step is completed, a structure 143 is formed on the first side of the wafer 1401.

[0080] In step 1305, a second dielectric layer 1406 is deposited. Using a mask layout, masking is performed above the exits of each TSV layer, leaving the redistribution layer 1405 above the exits of each TSV layer exposed and unobstructed by the second dielectric layer 1406. After this step is completed, structure 144 is formed on the first side of wafer 1401.

[0081] In step 1306, a plurality of first wafer bumps are formed on the plurality of redistribution layers 1405. More specifically, a first wafer bump is formed on each through-silicon via (TSV) layer using a C4 process, such that the first wafer bump is electrically connected to the TSV layer through the redistribution layer 1405. After this step is completed, structure 145 is formed on the first side of wafer 1401. The drawing exemplarily shows two first wafer bumps: first wafer bump 1407 and first wafer bump 1408. First wafer bump 1407 is electrically connected to the first TSV layer 1402 through the redistribution layer 1405, and first wafer bump 1408 is electrically connected to the second TSV layer 1403 through the redistribution layer 1405. The spacing D1 between the two first wafer bumps is 60 microns, and the center-to-center distance D2 is 130, 150, or 180 microns.

[0082] Then, step 1307 is performed to bond a plurality of first wafer bumps to the system on chip and the memory. After this step is completed, the first side of the wafer 1401 is formed as shown in FIG. Figure 15A In the structure 151 shown, the chip 1501 includes the aforementioned system on chip and memory.

[0083] In step 1308, the system area and storage area are filled with underfill. The material of the underfill can improve the protection against humidity, thermal shock and various mechanical shocks, and its function is to provide higher reliability and longer life cycle. After this step is completed, the first side of the wafer 1401 is formed as shown in FIG. Figure 15A In the structure 152 shown, the bottom filler 1502 protects the contacts and the first wafer bumps of the chip 1501.

[0084] In step 1309, a plurality of first wafer bumps and capacitors are bonded. After this step is completed, the first side of the wafer 1401 is formed as shown in FIG. Figure 15A The structure 153 shown exemplarily shows two capacitors 1503 bonded on a plurality of first wafer bumps. These capacitors 1503 are arranged in a capacitor area, that is, a zero-area outside the system area and the storage area.

[0085] In step 1310, the system on chip, memory and multiple capacitors are encapsulated to form a CoW structure. That is, the chip 1501 and the capacitor 1503 are packaged, and a CoW structure is formed on the first side of the wafer 1401. Figure 15B The structure 154 shown, wherein the encapsulating plastic 1504 covers the chip 1501 and the capacitor 1503, plays the role of placing, fixing, sealing, protecting and enhancing the electrical and thermal performance. Figure 11 CoW structure.

[0086] In step 1311, the CoW structure is glass bonded. First, the entire CoW structure is flipped over so that the first side faces downward. Then, the encapsulating plastic 1504 and the glass 1505 are bonded mechanically or chemically to form a laminate. Common bonding methods include anodic bonding, adhesive interlayer bonding, silicon (or glass) surface coating bonding, etc. After this step is completed, the first side of the wafer 1401 is formed as shown in FIG. Figure 15B Structure 155 is shown.

[0087] In step 1312, the wafer is polished so that the surface on the other side of the through silicon via is flush with the surface on the second side of the wafer. Figure 15BAs shown in structure 156, this embodiment uses chemical mechanical polishing to smooth the surface of the second side of the chip 1401 and make the surfaces of all silicon vias 1506 flush with the second side surface, that is, the surfaces of the silicon vias 1506 are exposed on the second side.

[0088] In step 1313, a plurality of second wafer bumps are formed on the second side to connect the other side of the through silicon via. Figure 15C As shown in the structure 157 , a second wafer bump 1507 is formed at the opening of each through silicon via 1506 on the second side using a C4 process.

[0089] In step 1314, the second wafer bump is soldered to the substrate. Figure 15C As shown in the structure 158, first remove the glass 1505, then flip the chip 1401 over so that the packaging plastic 1504 faces upward, first polish the packaging plastic 1504 so that the surface of the chip 1501 is exposed to the air to help dissipate heat, and then solder the second wafer bumps 1507 to the substrate 1508. The spacing between the two second wafer bumps 1507 is 60 microns, and the center distance is 130, 150, or 180 microns. This is now complete. Figure 12 CoWoS packaging structure.

[0090] If capacitor region 53 is not large enough to accommodate all the capacitors required for the CoWoS structure, this embodiment can also place the remaining capacitors outside of the molding compound region 50. In this case, this embodiment then solders the capacitors to the substrate in step 1315. As shown in structure 159 of Figure 15 , additional capacitors 1509 are soldered to substrate 1508. The combination of capacitors 1503 and 1509 increases the overall capacitance, significantly improving power supply stability.

[0091] This disclosure uses the zero-shaped area of ​​the molding compound area as a capacitor area to layout the capacitors required for the chip, so as to reduce the area of ​​the chip. Under the premise that the wafer size remains unchanged, the reduction in the volume of the chip means that a single wafer can accommodate more chips, thereby achieving the technical effect of reducing manufacturing costs.

[0092] The foregoing content can be better understood in accordance with the following terms:

[0093] Item A1. A method for laying out integrated circuits on a chip with a packaged structure, comprising: chip-mounting a system-on-chip in a system area on the chip; chip-mounting a memory in a storage area on the chip; and chip-mounting a plurality of capacitors in a capacitor area on the chip; wherein the capacitor area is an out-of-range area outside the system area and the storage area.

[0094] Item A2. The method of Item A1, wherein the capacitor region is located between the system region and the edge of the wafer.

[0095] Item A3. The method of Item A1, wherein the capacitor region is located between the system region and the storage region.

[0096] Item A4. The method of Item A1, wherein the capacitor region is located between the storage region and the edge of the wafer.

[0097] Item A5. The method of Item A1, wherein the capacitor region is located between a plurality of the storage regions.

[0098] Clause A6. The method of clause A1, wherein the plurality of capacitors are located more than 0.5 mm from the system area.

[0099] Item A7. The method of Item A1, wherein the plurality of capacitors are located more than 1 mm from the storage area.

[0100] Item A8. The method of Item A1, wherein the plurality of capacitors are located more than 0.5 mm from an edge of the wafer.

[0101] Item A9. The method of Item A1, wherein the distance between the plurality of capacitors is greater than 0.5 mm.

[0102] Item A10. The method according to any one of Items A1 to 9 further includes: forming a plurality of redistribution layers on the first side of the chip using through silicon vias; forming a plurality of first wafer bumps on the plurality of redistribution layers; and bonding the plurality of first wafer bumps to the system on chip, the memory, and the plurality of capacitors.

[0103] Item A11. The method according to Item A10 further includes: filling the system area and the storage area with bottom filling glue.

[0104] Item A12. The method according to Item A11 further includes: plastic-encapsulating the system-on-chip, the memory, and the plurality of capacitors to form a CoW structure.

[0105] Item A13. The method of Item A12, further comprising: glass bonding the CoW structure; and polishing the wafer so that a surface on the other side of the through-silicon via is flush with a surface on the second side of the wafer.

[0106] Item A14. The method according to Item A13, further comprising: forming a plurality of second wafer bumps on the second side to connect the other side of the through silicon via; and soldering the plurality of second wafer bumps to a substrate.

[0107] Item A15. The method according to Item A14, wherein the steps of forming a plurality of first wafer bumps and the steps of forming a plurality of second wafer bumps adopt a C4 process.

[0108] Item A16. The method of Item A14, wherein a pitch between the plurality of first wafer bumps and the plurality of second wafer bumps is 60 microns.

[0109] Item A17. The method of Item A10, wherein a center-to-center distance between the plurality of first wafer bumps and the plurality of second wafer bumps is 150 microns.

[0110] Item A18. The method of Item A1, wherein the memory is a high bandwidth memory.

[0111] Item A19. The method of Item A1, wherein the package structure is a CoWoS package structure.

[0112] Item A20, a packaging structure, comprising: a system on chip, arranged in a system area on a chip; a memory, arranged in a storage area on the chip; and a plurality of capacitors, arranged in a capacitor area on the chip; wherein the capacitor area is an erroneous area outside the system area and the storage area.

[0113] Item A21. The package structure of Item A20, wherein the capacitor region is located between the system region and the edge of the die.

[0114] Item A22. The package structure of Item A20, wherein the capacitor region is located between the system region and the storage region.

[0115] Item A23. A package structure according to Item A20, wherein the capacitor region is located between the storage region and the edge of the chip.

[0116] Item A24. The package structure of Item A20, wherein the capacitor region is located between the plurality of storage regions.

[0117] Clause A25. The package structure of any one of clauses A20 to A24, wherein the plurality of capacitors are located at a distance greater than 0.5 mm from the system area.

[0118] Clause A26. The package structure of any one of clauses A20 to A24, wherein the plurality of capacitors are located at a distance greater than 1 mm from the storage area.

[0119] Item A27. The package structure of any one of Items A20 to A24, wherein the plurality of capacitors are located more than 0.5 mm from the edge of the die.

[0120] Item A28. The package structure of any one of items A20 to A24, wherein a distance between the plurality of capacitors is greater than 0.5 mm.

[0121] Item A29. The package structure of Item A1, wherein the memory is a high-bandwidth memory.

[0122] Item A30. The package structure of Item A1, wherein the package structure is a CoWoS package structure.

[0123] Item A31. An integrated circuit device comprising the package structure of any one of items A20-30.

[0124] Item A32. A board comprising the integrated circuit device of Item A31.

[0125] The above is a detailed introduction to the embodiments of the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and core ideas of the present disclosure. At the same time, for those skilled in the art, based on the ideas of the present disclosure, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A method for laying out integrated circuits on a wafer in a package structure, comprising: die attaching a system-on-chip in a system area on the wafer; chip-mount memory in a storage area on said wafer; as well as chip-mounting a plurality of capacitors in a capacitor region on the wafer; The capacitor area is an odd-numbered area outside the system area and the storage area; the odd-numbered area is an idle area outside the system area and the storage area in the molding material area; The method further comprises: forming a plurality of redistribution layers on a first side of the wafer using through silicon vias; forming a plurality of first wafer bumps on the plurality of redistribution layers; and The plurality of first wafer bumps are bonded to the system on chip, the memory, and the plurality of capacitors. 2 . The method of claim 1 , wherein the capacitor region is located between the system region and the edge of the wafer. 3 . The method according to claim 1 , wherein the capacitor area is located between the system area and the storage area.

4. The method of claim 1, wherein the capacitor region is located between the storage region and the edge of the wafer. The method according to claim 1 , wherein the capacitor region is located between a plurality of the storage regions. The method according to claim 1 , wherein the plurality of capacitors are located at a distance greater than 0.5 mm from the system area. The method of claim 1 , wherein the plurality of capacitors are located at a distance greater than 1 mm from the storage area.

8. The method of claim 1, wherein the plurality of capacitors are located more than 0.5 mm from an edge of the wafer.

9. The method of claim 1, wherein a distance between the plurality of capacitors is greater than 0.5 mm.

10. The method according to any one of claims 1 to 9, further comprising: Fill the system area and the storage area with bottom filling glue.

11. The method according to claim 10, further comprising: The system on chip, the memory and the plurality of capacitors are plastic-encapsulated to form a CoW structure.

12. The method according to claim 11, further comprising: glass bonding the CoW structure; as well as The wafer is polished so that the surface of the other side of the through silicon via is flush with the surface of the second side of the wafer.

13. The method according to claim 12, further comprising: forming a plurality of second wafer bumps on the second side to connect the other side of the through silicon via; as well as The plurality of second wafer bumps are welded to the substrate. 14 . The method according to claim 13 , wherein the steps of forming a plurality of first wafer bumps and the steps of forming a plurality of second wafer bumps are performed using a C4 process. 15 . The method according to claim 13 , wherein a pitch between the plurality of first wafer bumps and the plurality of second wafer bumps is 60 μm. 16 . The method according to claim 13 , wherein a center-to-center distance between the plurality of first wafer bumps and the plurality of second wafer bumps is 150 μm. The method of claim 1 , wherein the memory is a high bandwidth memory. The method according to claim 1 , wherein the packaging structure is a CoWoS packaging structure.

19. A packaging structure comprising: System on chip, a system area located on a chip; Memory, a storage area provided on the chip; as well as a plurality of capacitors disposed in a capacitance region on the wafer; The capacitor area is an odd-numbered area outside the system area and the storage area; the odd-numbered area is an idle area outside the system area and the storage area in the molding material area; A plurality of redistribution layers are formed on the first side of the wafer using through silicon vias; a plurality of first wafer bumps are formed on the plurality of redistribution layers; and the plurality of first wafer bumps are bonded to the system on chip, the memory and the plurality of capacitors. 20 . The package structure according to claim 19 , wherein the capacitor region is located between the system region and the edge of the chip. 21 . The package structure according to claim 19 , wherein the capacitor region is located between the system region and the storage region. 22 . The package structure according to claim 19 , wherein the capacitor region is located between the storage region and the edge of the chip. 23 . The package structure according to claim 19 , wherein the capacitor region is located between the plurality of storage regions. 24 . The package structure according to claim 19 , wherein the distance between the plurality of capacitors and the system area is greater than 0.5 mm. 25 . The package structure according to claim 19 , wherein the distance between the plurality of capacitors and the storage area is greater than 1 mm. 26 . The package structure according to claim 19 , wherein the distance between the plurality of capacitors and the edge of the wafer is greater than 0.5 mm. 27 . The package structure according to claim 19 , wherein a distance between the plurality of capacitors is greater than 0.5 mm. The package structure according to claim 19 , wherein the memory is a high bandwidth memory. The packaging structure according to claim 19 , wherein the packaging structure is a CoWoS packaging structure.

30. An integrated circuit device comprising the package structure according to any one of claims 19-29.

31. A board comprising the integrated circuit device according to claim 30.

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