Electronic device and interface device comprising the same

Abstract

An electronic device and an interface device including the same are provided. The interface device further includes an input device for communicating with the electronic device, wherein the electronic device includes a display layer, a sensor layer disposed on the display layer and sensing a first input through the input device, a display driving unit for generating a vertical synchronization signal for driving the display layer, and a control unit for controlling the sensor layer, wherein the control unit outputs a first uplink signal to the sensor layer in synchronization with a first uplink vertical synchronization signal among the vertical synchronization signals, and outputs a second uplink signal to the sensor layer in synchronization with a second uplink vertical synchronization signal among the vertical synchronization signals, the second uplink signal having a phase different from a phase of the first uplink signal.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0126052, filed on September 28, 2020, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0002] The embodiments / implementations of the invention generally relate to an electronic device with improved image quality and an interface device including the electronic device. Background Technology

[0003] Electronic devices can detect external inputs applied from outside the device. External inputs can be user inputs. User inputs can include various types of external inputs such as a part of the user's body, light, heat, a pen, and pressure. In cases where the external input is via a pen, the electronic device can determine the pen's coordinates using either electromagnetic resonance (EMR) or active electrostatics (AES) methods.

[0004] The information disclosed in this background section is only for understanding the background art of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] The apparatus / method constructed according to the embodiments / examples of the invention can reduce or eliminate any flicker caused by conflicting signals by generating uplink signals with different phases to cancel out any flicker occurring on the display of the electronic device. This is achieved by generating an optical illusion effect, wherein a first flicker caused by a data signal and a first noise from the first uplink signal during a first uplink frame period and a second flicker caused by a data signal and a second noise from the second uplink signal during a second uplink frame period that occurs after the first uplink frame period effectively cancel each other out, thereby improving the image quality on the display of the electronic device by greatly reducing or eliminating flicker occurring on the display.

[0006] Thus, this disclosure provides an electronic device with improved image quality and an interface device including the electronic device.

[0007] Embodiments of the inventive concept provide an electronic device comprising: a display layer configured to display an image for a plurality of frame periods; a sensor layer disposed on the display layer and configured to operate in a first mode in which a first input via an input device is sensed and in a second mode in which a second input via touch is sensed; and a control unit configured to control the sensor layer, wherein the control unit outputs a first uplink signal to the sensor layer during a first uplink frame period in the plurality of frame periods in the first mode, and outputs a second uplink signal having a phase different from the first uplink signal to the sensor layer during a second uplink frame period in the plurality of frame periods in the first mode.

[0008] In an embodiment, the first uplink signal and the second uplink signal may each include different synchronization data.

[0009] In the embodiments, the first mode and the second mode can each be provided as a plurality of first modes and a plurality of second modes, and can repeat each other. The control unit can output a first uplink signal to the sensor layer in the 2n-1 first mode (n is a positive integer), and can output a second uplink signal to the sensor layer in the 2n first mode.

[0010] In an embodiment, the first uplink signal and the second uplink signal may each be provided as a plurality of first uplink signals and a plurality of second uplink signals, and the output timing of the first uplink signal in the (n+2)th frame period may be delayed by a first time compared with the output timing of the first uplink signal in the nth frame period (n is a positive integer).

[0011] In an embodiment, the output timing of the second uplink signal in the (n+3)th frame period can be delayed by a second time compared to the output timing of the second uplink signal in the (n+1)th frame period.

[0012] In the embodiment, the first uplink signal and the second uplink signal can each be provided as a plurality of first uplink signals and a plurality of second uplink signals, and the control unit can continuously output the first uplink signal to the sensor layer for m frame periods (m is an integer greater than 1), and can continuously output the second uplink signal to the sensor layer for k frame periods (k is an integer greater than 1).

[0013] In an embodiment, the output timing of the first uplink signal in the (n+1)th frame period may be delayed by a first time compared to the output timing of the first uplink signal in the nth frame period (n is a positive integer), and the output timing of the second uplink signal in the (i+1)th frame period may be delayed by a second time compared to the output timing of the second uplink signal in the ith frame period (i is a positive integer).

[0014] In an embodiment, the first period of the plurality of frame periods may be different from the second period of the first uplink signal.

[0015] In an embodiment, when an image of one frame period is displayed on the display layer, the control unit can operate sequentially in a first mode and a second mode.

[0016] In an embodiment, the first mode may include a first time period and a second time period, in which a first uplink signal or a second uplink signal is transmitted to the input device, and in the second time period, a first input is sensed based on a downlink signal provided from the input device, wherein the second time period occurs after the first time period.

[0017] In an embodiment, the electronic device may further include a display driving unit configured to generate a vertical synchronization signal for driving the display layer, wherein the control unit outputs a first uplink signal or a second uplink signal to the sensor layer in synchronization with the vertical synchronization signal.

[0018] In an embodiment of the inventive concept, an interface device includes an electronic device and an input device configured to communicate with the electronic device, wherein the electronic device includes: a display layer; a sensor layer disposed on the display layer and configured to sense a first input through the input device; a display driving unit configured to generate a vertical synchronization signal for driving the display layer; and a control unit configured to control the sensor layer, wherein the control unit outputs a first uplink signal to the sensor layer in sync with a first uplink synchronization signal in the vertical synchronization signal, and outputs a second uplink signal having a phase different from the first uplink signal to the sensor layer in sync with a second uplink synchronization signal in the vertical synchronization signal.

[0019] In an embodiment, the first uplink signal may include first synchronization data, the second uplink signal may include second synchronization data, and based on the first synchronization data and the second synchronization data, the input device can distinguish between the first uplink signal and the second uplink signal.

[0020] In this embodiment, the input device can receive a first uplink signal and a second uplink signal, output a first downlink signal based on the first uplink signal, and output a second downlink signal based on the second uplink signal.

[0021] In this embodiment, the input device can receive a first uplink signal and a second uplink signal, and can output a downlink signal based solely on the first uplink signal.

[0022] In this embodiment, the synchronization signal is a vertical synchronization signal, wherein the vertical synchronization signal can be provided as multiple vertical synchronization signals, and the control unit can output the first uplink signal to the sensor layer in synchronization with the (2n-1)th vertical synchronization signal (n is a positive integer), and can output the second uplink signal to the sensor layer in synchronization with the 2nth vertical synchronization signal.

[0023] In an embodiment, the first uplink signal, the second uplink signal, and the vertical synchronization signal can each be provided as a plurality of first uplink signals, a plurality of second uplink signals, and a plurality of vertical synchronization signals, and when compared with the output timing of the first uplink signal synchronized to the nth vertical synchronization signal (n is a positive integer) output to the sensor layer, the output timing of the first uplink signal synchronized to the (n+2)th vertical synchronization signal output to the sensor layer can be delayed by a first time.

[0024] In an embodiment, the output timing of the second uplink signal, which is synchronized with the (n+3)th vertical synchronization signal, can be delayed by a second time compared to the output timing of the second uplink signal synchronized with the (n+1)th vertical synchronization signal output to the sensor layer.

[0025] In the embodiment, the first uplink signal, the second uplink signal, and the vertical synchronization signal can each be provided as multiple first uplink signals, multiple second uplink signals, and multiple vertical synchronization signals, respectively. The control unit can continuously output the first uplink signal to the sensor layer for m frame periods (m is an integer greater than 1), and can continuously output the second uplink signal to the sensor layer for k frame periods (k is an integer greater than 1).

[0026] In an embodiment, compared with the output timing of the first uplink signal output to the sensor layer synchronized with the n+1th vertical synchronization signal (n is a positive integer), the output timing of the first uplink signal output to the sensor layer synchronized with the nth vertical synchronization signal (n is a positive integer) can be delayed by a first time, and compared with the output timing of the second uplink signal output to the sensor layer synchronized with the i-th vertical synchronization signal (i is a positive integer), the output timing of the second uplink signal output to the sensor layer synchronized with the i+1th vertical synchronization signal can be delayed by a second time.

[0027] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description or may be learned by practice of the inventive concept.

[0028] It will be understood that the foregoing general description and the following detailed description are illustrative and explanatory, and are intended to provide further explanation of the invention as claimed. Attached Figure Description

[0029] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the inventive concept.

[0030] Figure 1A This is a perspective view showing an interface device constructed according to an embodiment based on the principles of the invention.

[0031] Figure 1B This is a perspective view showing an interface device according to an embodiment.

[0032] Figure 2 This is a block diagram schematically illustrating an electronic device and an input device according to an embodiment.

[0033] Figure 3A This is a cross-sectional view of an electronic device according to an embodiment.

[0034] Figure 3B This is a cross-sectional view of an electronic device according to an embodiment.

[0035] Figure 4 This is a cross-sectional view of an electronic device according to an embodiment.

[0036] Figure 5 This is a block diagram of the display layer and display driving unit according to an embodiment.

[0037] Figure 6 This is a block diagram of the sensor layer and control unit according to an embodiment.

[0038] Figure 7A A portion of the sensor layer operating in a first mode according to an embodiment is shown.

[0039] Figure 7B A portion of the sensor layer operating in a first mode according to an embodiment is shown.

[0040] Figure 8 A portion of the sensor layer operating in a second mode according to an embodiment is shown.

[0041] Figure 9 This is a conceptual diagram used to describe the operation of the display layer and sensor layer according to an embodiment.

[0042] Figure 10 The waveforms of each of the first uplink signal and the second uplink signal according to an embodiment are shown.

[0043] Figure 11 The data of each of the first uplink signal and the second uplink signal according to an embodiment are schematically shown.

[0044] Figure 12 This is a conceptual diagram used to describe the operation of the display layer and sensor layer according to an embodiment.

[0045] Figure 13 This is a conceptual diagram used to describe the operation of the display layer and sensor layer according to an embodiment.

[0046] Figure 14 This is a conceptual diagram used to describe the operation of the display layer and sensor layer according to an embodiment. Detailed Implementation

[0047] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable terms as non-limiting examples of apparatuses or methods employing one or more inventive concepts disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but are not necessarily exclusive. For example, a particular shape, configuration, and characteristic of an embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0048] Unless otherwise stated, the illustrated embodiments are to be understood as providing features of different details that provide some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0049] Crosshairs and / or shading are typically used in accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scale, commonalities between illustrated elements, and / or any other characteristics, properties, etc., of the elements. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, a particular process sequence may be performed in a sequence different from that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0050] When a component or layer is referred to as being "on," "connected to," or "bonded to" another component or layer, the component or layer may be directly on, directly connected to, or directly bonded to the other component or layer, or there may be intermediate components or layers present. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another component or layer, there are no intermediate components or layers present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without intermediate components. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system (such as the x, y, and z axes) but can be interpreted in a broader sense. For example, the D1, D2, and D3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as XYZ, XYY, YZ, and ZZ). As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0051] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0052] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element and another (other) element as shown in the accompanying drawings. Spatial relative terms are intended to include different orientations of the device in use, operation, and / or manufacture, in addition to those depicted in the drawings. For example, if the device in the drawings is flipped, an element described as “below” or “under” another element or feature would subsequently be positioned “above” said other element or feature. Thus, the term “below” can include both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0053] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. Furthermore, the terms “comprising,” “having,” “including,” and / or variations thereof, when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “basically,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are thus used to interpret inherent deviations in measured, calculated, and / or provided values ​​that will be recognized by those skilled in the art.

[0054] Various embodiments are described herein with reference to sectional views and / or exploded views that are schematic diagrams of idealized embodiments and / or intermediate structures. Thus, variations in the illustrated shapes are contemplated, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the areas, but will include deviations in shape due to, for example, manufacturing processes. In this way, the areas shown in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device and are not necessarily intended to be limiting.

[0055] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of implementing blocks, units, and / or modules by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, blocks, units, and / or modules of some embodiments can be physically combined into more complex blocks, units, and / or modules.

[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense, unless expressly defined herein.

[0057] The invention will be explained in detail below with reference to the accompanying drawings.

[0058] Figure 1A This is a perspective view showing an interface device constructed according to an embodiment based on the principles of the invention.

[0059] Reference Figure 1A The interface device 10000 may include an electronic device 1000 and an input device 2000. The electronic device 1000 can detect a first input through the input device 2000. The interface device 10000 may also be referred to as a digitizer.

[0060] The electronic device 1000 can be a device activated by an electrical signal. For example, the electronic device 1000 can be a mobile phone, tablet computer, car navigation device, game console, or wearable device, but is not limited thereto. Figure 1A Electronic device 1000 is exemplarily shown as a mobile phone.

[0061] An effective region 1000A and a peripheral region 1000NA may be defined within an electronic device 1000. The electronic device 1000 may display an image through the effective region 1000A. The effective region 1000A may include a surface defined by a first direction DR1 and a second direction DR2 orthogonal to the first direction DR1 (i.e., the x-axis and y-axis in the xyz coordinate system). The peripheral region 1000NA may surround the effective region 1000A.

[0062] The thickness direction of the electronic device 1000 can be parallel to a third direction DR3, which is orthogonal to both the first direction DR1 and the second direction DR2 (i.e., the third direction DR3 corresponds to the z-axis in the xyz coordinate system). Therefore, the front surface (or top surface) and rear surface (or bottom surface) of each component constituting the electronic device 1000 can be defined based on the third direction DR3.

[0063] The electronic device 1000 can detect external inputs applied from outside the electronic device 1000. External inputs can include various types of external inputs such as a part of the user's body, light, heat, and pressure. Each type of external input can be referred to as a secondary input.

[0064] Figure 1A The electronic device 1000 shown can detect input via a user's touch and input via an input device 2000. The input device 2000 can refer to a device other than the user's body. Input via the input device 2000 can be referred to as the first input. For example, the input device 2000 can be an active pen, a stylus, a touch pen, or an electronic pen. In the following description, by way of example, the input device 2000 will be described as an active pen.

[0065] Electronic device 1000 and input device 2000 can perform bidirectional communication with each other. Electronic device 1000 can provide uplink signals to input device 2000. For example, uplink signals may include synchronization data or information about electronic device 1000, but are not particularly limited thereto. Input device 2000 can provide downlink signals to electronic device 1000. Downlink signals may include synchronization signals or status information of input device 2000. For example, downlink signals may include coordinate information of input device 2000, battery information of input device 2000, tilt information of input device 2000, and / or various pieces of information stored in input device 2000, but downlink signals are not particularly limited thereto. Uplink signals and downlink signals may each be provided as multiple uplink signals and multiple downlink signals. Uplink signals and downlink signals will be described later.

[0066] Figure 1B This is a perspective view showing an interface device according to an embodiment. When giving about Figure 1BWhen describing, refer to Figure 1A The components described are indicated by the same reference numerals, and for the sake of illustration, their descriptions will not be given.

[0067] Reference Figure 1B The interface device 10000-1 may include an electronic device 1000-1 and an input device 2000. Figure 1B The diagram shows the electronic device 1000-1 folded at a predetermined angle. When the electronic device 1000-1 is unfolded, the effective area 1000A-1 may include a plane defined by a first direction DR1 and a second direction DR2 orthogonal to the first direction DR1.

[0068] The effective region 1000A-1 may include a first region 1000A1, a second region 1000A2, and a third region 1000A3. The first region 1000A1, the second region 1000A2, and the third region 1000A3 may be sequentially defined along a first direction DR1. The second region 1000A2 may be bent about a folding axis 1000FX extending in a second direction DR2. Therefore, the first region 1000A1 and the third region 1000A3 may be referred to as non-folded regions, and the second region 1000A2 may be referred to as a folded region.

[0069] When the electronic device 1000-1 is folded, the first region 1000A1 and the third region 1000A3 can face each other. Therefore, in the fully folded state, the effective region 1000A-1 may not be exposed to the outside, which can be referred to as an inward fold. However, this is illustrative, and the operation of the electronic device 1000-1 is not limited to this.

[0070] For example, when the electronic device 1000-1 according to the embodiment is folded, the first region 1000A1 and the third region 1000A3 can face away from each other. Therefore, in the folded state, the effective region 1000A-1 can be exposed to the outside, which can be referred to as outward folding.

[0071] Electronic device 1000-1 can perform only one of the inward folding operation and the outward folding operation. Alternatively, electronic device 1000-1 can perform both the inward folding operation and the outward folding operation. In this case, the same area of ​​electronic device 1000-1 (e.g., the second area 1000A2) can be folded both inward and outward.

[0072] Despite Figure 1B The example shows one folded region and two non-folded regions, but the number of each of the folded and non-folded regions is not limited thereto. For example, electronic device 1000-1 may include more than two non-folded regions and multiple folded regions respectively disposed between adjacent non-folded regions.

[0073] although Figure 1B The folding shaft 1000FX is shown extending in the second direction DR2, but the embodiment is not limited thereto. For example, the folding shaft 1000FX may extend in a direction parallel to the first direction DR1. In this case, the first region 1000A1, the second region 1000A2, and the third region 1000A3 may be arranged sequentially along the second direction DR2.

[0074] Electronic device 1000-1 and input device 2000 can perform bidirectional communication with each other. Electronic device 1000-1 can provide each uplink signal to input device 2000. Input device 2000 can provide each downlink signal to electronic device 1000-1. Electronic device 1000-1 can detect the coordinates or tilt of input device 2000 by using the signals provided from input device 2000.

[0075] Figure 2 This is a block diagram schematically illustrating an electronic device and an input device according to an embodiment.

[0076] Reference Figure 2 The electronic device 1000 may include a display layer 100, a sensor layer 200, a display driving unit 100C, a control unit 200C, and a main control unit 1000C.

[0077] Display layer 100 can be a component that substantially generates an image. Display layer 100 can be a light-emitting display layer, and can be, for example, an organic light-emitting display layer, a quantum dot display layer, a micro-LED display layer, or a nano-LED display layer.

[0078] Sensor layer 200 may be disposed on display layer 100. Sensor layer 200 can sense external input applied from the outside. Sensor layer 200 can sense a first input through input device 2000 and a second input through user's body 3000.

[0079] The main control unit 1000C can control the overall operation of the electronic device 1000. For example, the main control unit 1000C can control the operation of the display driving unit 100C and the control unit 200C. The main control unit 1000C may include at least one microprocessor and may be referred to as the host.

[0080] The display driving unit 100C can control the display layer 100. The main control unit 1000C may also include a graphics controller. The display driving unit 100C can receive image data RGB and control signals D-CS from the main control unit 1000C. The control signals D-CS may include various signals. For example, the control signals D-CS may include an input vertical synchronization signal, an input horizontal synchronization signal, a master clock, a data enable signal, etc. Based on the control signals D-CS, the display driving unit 100C can generate vertical synchronization signals and horizontal synchronization signals for controlling the timing of signals provided to the display layer 100.

[0081] Control unit 200C can control sensor layer 200. Control unit 200C can receive control signal I-CS from main control unit 1000C. Control signal I-CS may include a mode determination signal and a clock signal for determining the drive mode of control unit 200C. Based on control signal I-CS, control unit 200C can operate in a first mode in which a first input through input device 2000 is detected, or in a second mode in which a second input through user's body 3000 is detected. Based on the mode determination signal, control unit 200C can perform control such that sensor layer 200 operates in either the first or second mode.

[0082] The control unit 200C can calculate the coordinate information of the first or second input based on the signal received from the sensor layer 200, and can provide the main control unit 1000C with a coordinate signal I-SS containing the coordinate information. The main control unit 1000C can allow the execution of an operation corresponding to the user's input based on the coordinate signal I-SS. For example, based on the coordinate signal I-SS, the main control unit 1000C can operate the display driving unit 100C to display a new application image on the display layer 100.

[0083] The input device 2000 may include a housing 2100, a power supply 2200, a controller 2300, a communication module 2400, and pen electrodes 2500. However, the components constituting the input device 2000 are not limited to those listed above. For example, the input device 2000 may also include an electrode switch for switching between a signal transmission mode and a signal reception mode, a pressure sensor for sensing pressure, a memory for storing predetermined information, or a rotation sensor for sensing rotation, etc.

[0084] The housing 2100 may be pen-shaped and may have an internal receiving space. The power supply 2200, controller 2300, communication module 2400 and pen electrodes 2500 may be housed in the receiving space defined inside the housing 2100.

[0085] Inside the input device 2000, the power supply 2200 can supply power to the controller 2300, communication module 2400, etc. The power supply 2200 may include a battery or a high-capacity capacitor.

[0086] The controller 2300 can control the operation of the input device 2000. The controller 2300 can be an application-specific integrated circuit (ASIC). The controller 2300 can be configured to operate according to a designed program.

[0087] The communication module 2400 may include a transmitting circuit 2410 and a receiving circuit 2420. The transmitting circuit 2410 may output each downlink signal DLS to the sensor layer 200. The receiving circuit 2420 may receive each uplink signal ULS provided from the sensor layer 200. The uplink signal ULS may have a frequency of approximately 500 kHz (kilohertz). The uplink signal ULS may include a first uplink signal ULS1 (see...). Figure 9 ) and the second uplink signal ULS2 (see Figure 9 The first uplink signal ULS1 (see...) Figure 9 ) and the second uplink signal ULS2 (see Figure 9 These can each be provided as multiple first uplink signals and multiple second uplink signals. The first uplink signal ULS1 will be described later (see...). Figure 9 ) and the second uplink signal ULS2 (see Figure 9 The transmitting circuit 2410 can receive signals provided by the controller 2300 and modulate the signals into signals that can be sensed by the sensor layer 200, and the receiving circuit 2420 can modulate the signals provided by the sensor layer 200 into signals that can be processed by the controller 2300.

[0088] The pen electrode 2500 can be electrically connected to the communication module 2400. A portion of the pen electrode 2500 can protrude from the housing 2100. Additionally, the input device 2000 may include a cover housing for covering the pen electrode 2500 exposed from the housing 2100. Optionally, the pen electrode 2500 can be embedded inside the housing 2100.

[0089] Figure 3A This is a cross-sectional view of an electronic device according to an embodiment.

[0090] Reference Figure 3A The electronic device 1000 may include a display layer 100 and a sensor layer 200. The display layer 100 may include a substrate layer 110, a circuit layer 120, a light-emitting element layer 130, and an encapsulation layer 140.

[0091] The substrate layer 110 may be a component for providing a substrate surface on which the circuit layer 120 is disposed. The substrate layer 110 may be a glass substrate, a metal substrate, or a polymer substrate. However, the embodiments are not limited thereto, and the substrate layer 110 may be an inorganic layer, an organic layer, or a composite material layer.

[0092] The substrate layer 110 may have a multilayer structure. For example, the substrate layer 110 may include a first synthetic resin layer and silicon dioxide (SiO2) disposed on the first synthetic resin layer. x The system comprises a silicon oxide layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second synthetic resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer can be referred to as substrate barrier layers.

[0093] Each of the first and second synthetic resin layers may include a polyimide resin. Furthermore, each of the first and second synthetic resin layers may include at least one selected from acrylate resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. Additionally, in this specification, "~~" indicates that the resin includes the functional group "~~".

[0094] Circuit layer 120 may be disposed on substrate layer 110. Circuit layer 120 may include insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. Insulating layers, semiconductor layers, and conductive layers may be formed on substrate layer 110 by methods such as coating and deposition, and then the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by multiple photolithography processes. Subsequently, semiconductor patterns, conductive patterns, and signal lines included in circuit layer 120 may be formed.

[0095] The light-emitting element layer 130 may be disposed on the circuit layer 120. The light-emitting element layer 130 may include a light-emitting element. For example, the light-emitting element layer 130 may include organic light-emitting materials, quantum dots, quantum rods, micro LEDs, or nano LEDs.

[0096] An encapsulation layer 140 may be disposed on the light-emitting element layer 130. The encapsulation layer 140 can protect the light-emitting element layer 130 from foreign substances such as moisture, oxygen and dust particles.

[0097] The sensor layer 200 can be formed on the display layer 100 via a continuous process. In this case, it can be said that the sensor layer 200 is directly disposed on the display layer 100. The expression "directly disposed" can mean that no third component is disposed between the sensor layer 200 and the display layer 100. That is, no separate adhesive member may be disposed between the sensor layer 200 and the display layer 100. Alternatively, the sensor layer 200 can be bonded to the display layer 100 by an adhesive member. The adhesive member may include a typical adhesive or a typical separable adhesive.

[0098] Figure 3B This is a cross-sectional view of an electronic device according to an embodiment.

[0099] Reference Figure 3B The electronic device 1000-1 may include a display layer 100-1 and a sensor layer 200-1. The display layer 100-1 may include a substrate 110-1, a circuit layer 120-1, a light-emitting element layer 130-1, a packaging substrate 140-1, and a bonding member 150-1.

[0100] Each of the substrate 110-1 and the encapsulation substrate 140-1 may be a glass substrate, a metal substrate or a polymer substrate, but is not particularly limited thereto.

[0101] A bonding member 150-1 may be disposed between the substrate 110-1 and the encapsulation substrate 140-1. The bonding member 150-1 can bond the encapsulation substrate 140-1 to the substrate 110-1 or the circuit layer 120-1. The bonding member 150-1 may comprise inorganic or organic materials. For example, inorganic materials may include glass frit seals, and organic materials may include photocurable resins or photoplastic resins. However, the materials constituting the bonding member 150-1 are not limited to the examples described above.

[0102] The sensor layer 200-1 can be directly disposed on the encapsulation substrate 140-1. The phrase "directly disposed" indicates that no third component is disposed between the sensor layer 200-1 and the encapsulation substrate 140-1. That is, a separate adhesive component is not required between the sensor layer 200-1 and the display layer 100-1. However, the embodiments are not limited to this; an adhesive layer may be further disposed between the sensor layer 200-1 and the encapsulation substrate 140-1.

[0103] Figure 4 This is a cross-sectional view of an electronic device according to an embodiment. When giving about Figure 4 When describing, refer to Figure 3A The components described are indicated by the same reference numerals, and for ease of explanation of the embodiments, their descriptions will not be given.

[0104] Reference Figure 4At least one inorganic layer may be formed on the top surface of the substrate layer 110. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. Multiple inorganic layers may be formed. Multiple inorganic layers may constitute a barrier layer and / or a buffer layer. In this embodiment, the display layer 100 is shown as including a buffer layer BFL.

[0105] The buffer layer BFL can improve the adhesion between the substrate layer 110 and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and silicon nitride layer may be stacked alternately.

[0106] Semiconductor patterns can be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the semiconductor pattern is not limited to this and may include amorphous silicon, low-temperature polycrystalline silicon, or oxide semiconductors. Multiple semiconductor patterns may be disposed.

[0107] Figure 4 Only some of the semiconductor patterns are shown, and another semiconductor pattern can be further disposed in another region. The semiconductor patterns can be arranged throughout the pixels according to a specific rule. Depending on whether the semiconductor patterns are doped, they can have different electrical properties. A semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with N-type or P-type dopant. A P-type transistor may include a doped region doped with P-type dopant, and an N-type transistor may include a doped region doped with N-type dopant. The second region may be an undoped region or a region doped at a lower concentration than the first region.

[0108] The first region can have higher conductivity than the second region and can be used substantially as an electrode or signal line. The second region can substantially correspond to the active region (or channel) of a transistor. In other words, one part of the semiconductor pattern can be the active region of a transistor, another part can be the source or drain of a transistor, and yet another part can be a connecting electrode or a connecting signal line.

[0109] Each pixel can have an equivalent circuit consisting of seven transistors, a capacitor, and a light-emitting element, and the equivalent circuit of a pixel can be modified in various forms. Figure 4 An exemplary illustration shows a transistor 100PC and a light-emitting element 100PE included in a pixel.

[0110] Transistor 100PC may include a source SC1, an active region A1, a drain D1, and a gate G1. The source SC1, active region A1, and drain D1 may be formed from a semiconductor pattern. When viewed in cross-section, the source SC1 and drain D1 may extend from the active region A1 in opposite directions, respectively. Figure 4A portion of the connection signal line SCL, formed by a semiconductor pattern, is shown. Although not shown separately, when viewed in a plane, the connection signal line SCL is electrically connected to the drain D1 of transistor 100PC.

[0111] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may be stacked commonly with multiple pixels and may cover a semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. In addition to the first insulating layer 10, the insulating layers of the circuit layer 120, which will be described later, may also be inorganic and / or organic layers, and may also have a single-layer or multi-layer structure. Inorganic layers may include at least one of the materials described above, but are not limited thereto.

[0112] Gate G1 is disposed on the first insulating layer 10. Gate G1 may be part of a metal pattern. Gate G1 is stacked with the active region A1. In the process of doping the semiconductor pattern, gate G1 may be used as a mask.

[0113] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate G1. The second insulating layer 20 may be stacked with the pixel in common. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the second insulating layer 20 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0114] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may have a single-layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0115] The first connection electrode CNE1 can be disposed on the third insulating layer 30. The first connection electrode CNE1 can be connected to the connection signal line SCL through the contact hole CNT-1 that penetrates the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30.

[0116] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single layer of silicon oxide. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0117] The second connecting electrode CNE2 can be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the contact hole CNT-2 that penetrates the fourth insulating layer 40 and the fifth insulating layer 50.

[0118] The sixth insulating layer 60 can be disposed on the fifth insulating layer 50 and can cover the second connecting electrode CNE2. The sixth insulating layer 60 can be an organic layer.

[0119] The light-emitting element layer 130 may be disposed on the circuit layer 120. The light-emitting element layer 130 may include a light-emitting element 100PE. For example, the light-emitting element layer 130 may include organic light-emitting materials, quantum dots, quantum rods, microLEDs, or nanoLEDs. In the following, by way of example, the light-emitting element 100PE is described as an organic light-emitting element, but is not particularly limited thereto.

[0120] The light-emitting element 100PE may include a first electrode AE, a light-emitting layer EL, and a second electrode CE. The first electrode AE ​​may be disposed on a sixth insulating layer 60. The first electrode AE ​​may be connected to a second connecting electrode CNE2 through a contact hole CNT-3 penetrating the sixth insulating layer 60.

[0121] A pixel defining film 70 may be disposed on a sixth insulating layer 60 and may cover a portion of the first electrode AE. An opening 70-OP is defined in the pixel defining film 70. The opening 70-OP of the pixel defining film 70 exposes at least a portion of the first electrode AE.

[0122] Valid area 1000A (see) Figure 1A The electrode may include a light-emitting region PXA and a non-light-emitting region NPXA adjacent to the light-emitting region PXA. The non-light-emitting region NPXA may surround the light-emitting region PXA. In this embodiment, the light-emitting region PXA is defined to correspond to the portion of the first electrode AE ​​exposed by the opening 70-OP.

[0123] A light-emitting layer (EL) can be disposed on the first electrode (AE). Multiple light-emitting layers (ELs) can be configured. The ELs can be disposed in the region corresponding to the opening 70-OP. That is, the ELs can be formed individually in each pixel. When the ELs are formed individually in each pixel, each EL can emit light of at least one color among blue, red, and green. However, the ELs are not limited to this and can be connected and shared among multiple pixels. In this case, the ELs can provide blue light or white light.

[0124] The second electrode CE can be disposed on the light-emitting layer EL. The second electrode CE can have a monolithic shape and can be disposed commonly in multiple pixels.

[0125] A hole control layer can be disposed between the first electrode AE ​​and the light-emitting layer EL. The hole control layer can be commonly disposed within the light-emitting region PXA and the non-light-emitting region NPXA. The hole control layer may include a hole transport layer and may also include a hole injection layer. An electron control layer can be disposed between the light-emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may also include an electron injection layer. The hole control layer and the electron control layer can be commonly formed in multiple pixels using an aperture mask.

[0126] The encapsulation layer 140 may be disposed on the light-emitting element layer 130. The encapsulation layer 140 may include inorganic layers, organic layers and inorganic layers stacked in sequence, but the layers constituting the encapsulation layer 140 are not limited to these.

[0127] The inorganic layer protects the light-emitting element layer 130 from moisture and oxygen, while the organic layer protects it from foreign substances such as dust particles. The inorganic layer may include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, etc. The organic layer may include, but is not limited to, acrylate-based organic layers.

[0128] The sensor layer 200 can be formed on the display layer 100 via a continuous process. In this case, it can be said that the sensor layer 200 is directly disposed on the display layer 100. The expression "directly disposed" can mean that no third component is disposed between the sensor layer 200 and the display layer 100. That is, a separate adhesive member is not required between the sensor layer 200 and the display layer 100. Alternatively, the sensor layer 200 can be bonded to the display layer 100 by an adhesive member. The adhesive member can include a typical adhesive or a typical separable adhesive.

[0129] The sensor layer 200 may include a substrate insulating layer 201, a first conductive layer 202, a sensing insulating layer 203, a second conductive layer 204, and a covering insulating layer 205.

[0130] The substrate insulating layer 201 may be an inorganic layer comprising at least one of silicon nitride, silicon oxynitride, and silicon oxide. Optionally, the substrate insulating layer 201 may be an organic layer comprising epoxy resin, acrylic resin, or imide resin. The substrate insulating layer 201 may have a single-layer structure or a multilayer structure stacked along the third direction DR3.

[0131] Each of the first conductive layer 202 and the second conductive layer 204 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0132] The conductive layer of a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, graphene, etc.

[0133] The conductive layer in a multilayer structure may include a metal layer. The metal layer may have a three-layer structure, such as titanium / aluminum / titanium. The conductive layer in a multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0134] At least one of the sensing insulating layer 203 and the covering insulating layer 205 may include an inorganic film. The inorganic film may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0135] At least one of the sensing insulating layer 203 and the covering insulating layer 205 may include an organic film. The organic film may include at least one of acrylate resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0136] Parasitic capacitance Cb is generated between sensor layer 200 and second electrode CE. As the distance between sensor layer 200 and second electrode CE decreases, the value of parasitic capacitance Cb increases. As parasitic capacitance Cb increases, the ratio of capacitance change to a reference value decreases. The capacitance change can refer to the capacitance change that occurs before and after input is applied through an input device (e.g., input device 2000 (see Figure 3) and user's body 3000 (see Figure 3)).

[0137] Control unit 200C (see) processes signals sensed by sensor layer 200. Figure 2 It can perform a balancing operation to remove the value corresponding to the parasitic capacitance Cb from the sensed signal. By performing the balancing operation, the ratio of the capacitance change to the reference value can be increased, thus improving the sensing sensitivity.

[0138] Figure 5 This is a block diagram of the display layer and display driving unit according to an embodiment.

[0139] Reference Figure 5The display layer 100 may include multiple scan lines SL1 to SLn, multiple data lines DL1 to DLm, and multiple pixels PX. Each of the multiple pixels PX may be connected to a corresponding one of the multiple data lines DL1 to DLm and to a corresponding one of the multiple scan lines SL1 to SLn. In an embodiment, the display layer 100 may further include light emission control lines, and the display driving unit 100C may further include a light emission driving circuit that provides control signals to the light emission control lines. The construction of the display layer 100 is not particularly limited.

[0140] The display driving unit 100C may include a signal control circuit 100C1, a scan driving circuit 100C2, and a data driving circuit 100C3.

[0141] The signal control circuit 100C1 can be controlled from the main control unit 1000C (see...) Figure 2 It receives image data (RGB) and control signals (D-CS). The control signals (D-CS) can include various signals. For example, the control signals (D-CS) can include input vertical synchronization signals, input horizontal synchronization signals, master clock, data enable signals, etc.

[0142] Based on the control signal D-CS, the signal control circuit 100C1 can generate a first control signal CONT1 and a vertical synchronization signal Vsync, and can output the first control signal CONT1 and the vertical synchronization signal Vsync to the scan drive circuit 100C2. The vertical synchronization signal Vsync can be included in the first control signal CONT1.

[0143] Based on the control signal D-CS, the signal control circuit 100C1 can generate a second control signal CONT2 and a horizontal synchronization signal Hsync, and can output the second control signal CONT2 and the horizontal synchronization signal Hsync to the data drive circuit 100C3. The horizontal synchronization signal Hsync can be included in the second control signal CONT2.

[0144] Additionally, the signal control circuit 100C1 can output the data signal DS, obtained by processing the image data RGB according to the operating conditions of the display layer 100, to the data drive circuit 100C3. The first control signal CONT1 and the second control signal CONT2 are the signals required for the operation of the scan drive circuit 100C2 and the data drive circuit 100C3, respectively, and are not particularly limited.

[0145] The scan drive circuit 100C2 can drive multiple scan lines SL1 to SLn in response to the first control signal CONT1 and the vertical synchronization signal Vsync. In an embodiment, the scan drive circuit 100C2 can be connected to the circuit layer 120 in the display layer 100 (see...). Figure 4The scan drive circuit 100C2 is formed using the same process, but it is not limited to this. For example, the scan drive circuit 100C2 can be implemented as an integrated circuit (IC) and can then be directly mounted in a predetermined area of ​​the display layer 100, or mounted on a separate printed circuit board using a chip-on-film (COF) method to be electrically connected to the display layer 100.

[0146] The data driving circuit 100C3 can output grayscale voltages to drive multiple data lines DL1 to DLm in response to the second control signal CONT2, the horizontal synchronization signal Hsync, and the data signal DS from the signal control circuit 100C1. The data driving circuit 100C3 can be implemented as an integrated circuit and then directly mounted in a predetermined area of ​​the display layer 100, or mounted on a separate printed circuit board using a chip-on-film method for electrical connection to the display layer 100; however, there are no particular limitations on the data driving circuit 100C3. For example, the data driving circuit 100C3 can be integrated with the circuit layer 120 in the display layer 100 (see...). Figure 4 They are formed using the same process.

[0147] Figure 6 This is a block diagram of the sensor layer and control unit according to an embodiment.

[0148] Reference Figure 6 The effective region 200A and the peripheral region 200N can be defined within the sensor layer 200. The effective region 200A can be a region activated according to an electrical signal. For example, the effective region 200A can be a region sensing an input. The effective region 200A can be integrated with the electronic device 1000 (see...). Figure 1A The effective area is 1000A (see) Figure 1A The outer region 200N can be superimposed on the effective region 200A. The outer region 200N can be connected to the electronic device 1000 (see...). Figure 1A The outer region of 1000NA (see) Figure 1A Stacked.

[0149] The sensor layer 200 may include a plurality of electrodes 210 and a plurality of cross electrodes 220. The plurality of electrodes 210 may each extend in a first direction DR1 and may be arranged to be spaced apart from each other in a second direction DR2. The plurality of cross electrodes 220 may each extend in the second direction DR2 and may be arranged to be spaced apart from each other in the first direction DR1.

[0150] Multiple cross electrodes 220 may cross the multiple electrodes 210 in an insulated manner. Each of the multiple electrodes 210 and the multiple cross electrodes 220 may be strip-shaped or strip-shaped. Multiple electrodes 210 and multiple cross electrodes 220 having this shape can improve the sensing characteristics of continuous linear input. However, the shape of each of the multiple electrodes 210 and multiple cross electrodes 220 is not limited thereto.

[0151] Control unit 200C can be electrically connected to sensor layer 200. Control unit 200C can control sensor layer 200. Control unit 200C can control the main control unit 1000C (see main control unit 1000C). Figure 2 ) receives control signal I-CS and sends it to main control unit 1000C (see Figure 2 It provides coordinate signals I-SS.

[0152] The control unit 200C may include a sensor control circuit 200C1, a signal generation circuit 200C2, an input detection circuit 200C3, and a switching circuit 200C4. The sensor control circuit 200C1, the signal generation circuit 200C2, and the input detection circuit 200C3 may be implemented on a single chip, or some of the sensor control circuit 200C1, the signal generation circuit 200C2, and the input detection circuit 200C3, along with the rest, may be implemented on different chips.

[0153] The sensor control circuit 200C1 can control the operation of the signal generation circuit 200C2 and the switching circuit 200C4, and can calculate the coordinates of the external input based on the drive signal received from the input detection circuit 200C3, or analyze the input device 2000 (see [reference]) based on the modulation signal received from the input detection circuit 200C3. Figure 2 The information has already been sent. The sensor control circuit 200C1 can provide the sensor layer 200 with a first uplink signal or a second uplink signal having a phase different from the first uplink signal. A description of this will be given later.

[0154] The signal generation circuit 200C2 can provide an output signal (or drive signal) called the TX signal to the sensor layer 200. The signal generation circuit 200C2 can output an output signal corresponding to the operating mode to the sensor layer 200.

[0155] The input detection circuit 200C3 converts the analog signal, known as the RX signal (or sensing signal), received from the sensor layer 200 into a digital signal. The input detection circuit 200C3 amplifies the received analog signal and then filters the amplified signal. Afterward, the input detection circuit 200C3 converts the filtered signal back into a digital signal.

[0156] According to the control of the sensor control circuit 200C1, the switch circuit 200C4 can selectively control the electrical connection between the sensor layer 200 and the signal generation circuit 200C2 and / or between the sensor layer 200 and the input detection circuit 200C3.

[0157] Switching circuit 200C4 can connect each of the plurality of electrodes 210 and the plurality of cross electrodes 220 to signal generation circuit 200C2. Optionally, switching circuit 200C4 can connect each of the plurality of electrodes 210 and the plurality of cross electrodes 220 to input detection circuit 200C3. In this case, sensor layer 200 can operate in a first mode.

[0158] Under the control of sensor control circuit 200C1, switching circuit 200C4 can connect any one set of multiple electrodes 210 and multiple cross electrodes 220 to signal generation circuit 200C2, and can connect another set of multiple electrodes 210 and multiple cross electrodes 220 to input detection circuit 200C3. In this case, sensor layer 200 can operate in a second mode.

[0159] Figure 7A and Figure 7B Each shows a portion of the sensor layer operating in a first mode according to an embodiment.

[0160] Reference Figures 6 to 7B A portion of an electrode 210 and a portion of a cross electrode 220 can be defined as a sensing unit 200U. Figure 7A and Figure 7B In each of the images, a magnified view shows a sensing unit 200U.

[0161] The cross electrode 220 may include a cross pattern 221 and a bridging pattern 222 electrically connected to the cross pattern 221. The cross patterns 221 may be spaced apart and the electrode 210 is disposed therebetween. The bridging pattern 222 may overlap with the electrode 210 and may cross the electrode 210 in an insulated manner.

[0162] The cross pattern 221 and the electrode 210 can be disposed in the same layer, and the bridging pattern 222 can be disposed in a different layer than the cross pattern 221 and the electrode 210. For example, the cross pattern 221 and the electrode 210 can be included in the second conductive layer 204 (see...). Figure 4 In the first conductive layer 202, the bridging pattern 222 may be included. Figure 4 In this structure, it can be referred to as a bottom bridging structure. However, the embodiments are not particularly limited thereto. For example, the cross pattern 221 and the electrode 210 can be included in the first conductive layer 202 (see...). Figure 4In the second conductive layer 204, the bridging pattern 222 may be included. Figure 4 In this context, the structure can be referred to as a top-bridge structure.

[0163] Additionally, the sensor layer 200 may also include a dummy pattern 250 disposed in areas where the cross pattern 221 and the electrode 210 are not disposed. The dummy pattern 250 may be a component configured to prevent the electrode 210 and the cross electrode 220 from being seen from the outside. The dummy pattern 250 may be an electrically floating pattern.

[0164] Each of the cross pattern 221, electrode 210, and dummy pattern 250 may have a mesh structure. In this case, an opening may be defined in each of the cross pattern 221, electrode 210, and dummy pattern 250. However, the embodiment is not limited thereto, and each of the cross pattern 221, electrode 210, and dummy pattern 250 may be made of a transparent electrode without an opening.

[0165] The first mode could be one of the electronic devices 1000 (see...) Figure 1A ) and input device 2000 (see Figure 1A The control unit 200C can detect the data exchange pattern between the two devices via the input device 2000 (see...). Figure 2 The first input. Figure 7A The operation shown can be performed by electronic device 1000 (see...) Figure 1A ) to input device 2000 (see Figure 1A It provides operation of uplink signals S1a and S1b.

[0166] Although reference Figure 7A Electrode 210 and cross electrode 220 are shown as examples of transmitting electrodes to input device 2000 (see [link to example]). Figure 1A The uplink signals S1a and S1b are provided from the control unit 200C, but electrode 210 and cross electrode 220 are not particularly limited thereto. For example, electrode 210 or cross electrode 220 can be used as transmitting electrodes. The uplink signals S1a and S1b can be... Figure 2 The uplink signal ULS.

[0167] Reference Figure 7B Electrode 210 and cross electrode 220 can be used as receiving electrodes to transmit data from input device 2000 (see [link to relevant documentation]) to control unit 200C, respectively. Figure 1A The control unit 200C can receive the first sensing signal S2a from the electrode 210 and the second sensing signal S2b from the cross electrode 220.

[0168] Figure 8A portion of the sensor layer operating in a second mode according to an embodiment is shown.

[0169] Reference Figure 6 and Figure 8 The control unit 200C can detect the user's body 3000 in the second mode (see...). Figure 2 The second input. In the second mode, the control unit 200C can detect the external input by detecting the change in the mutual capacitance formed between the electrode 210 and the cross electrode 220.

[0170] The control unit 200C can provide an output signal S3 to the electrode 210 and can receive a sensing signal S4 from the cross electrode 220. That is, in the second mode, the electrode 210 can be used as a transmitting electrode and the cross electrode 220 can be used as a receiving electrode. However, the electrode 210 and the cross electrode 220 are not particularly limited thereto. For example, the electrode 210 can be used as a receiving electrode and the cross electrode 220 can be used as a transmitting electrode.

[0171] Figure 9 This is a conceptual diagram used to describe the operation of the display layer and sensor layer according to an embodiment.

[0172] Reference Figure 2 and Figure 9 The display layer 100 can display an image for each frame period. The vertical synchronization signal Vsync can be provided as multiple vertical synchronization signals. The frame period can be defined as the time interval from the rising edge of one vertical synchronization signal Vsync to the rising edge of the next vertical synchronization signal Vsync.

[0173] When the operating frequency of the display layer 100 is approximately 60 Hz, the time corresponding to the frame period can be approximately 16.44 ms, and when the operating frequency of the display layer 100 is approximately 120 Hz, the time corresponding to the frame period can be approximately 8.33 ms. Figure 9 An example is shown where the operating frequency of the display layer 100 is approximately 60 Hz.

[0174] The sensor layer 200 can operate in a first mode MD1, in which it senses a first input via the input device 2000, or in a second mode MD2, in which it senses a second input via the user's body 3000. When an image is displayed on the display layer 100 during a frame period, the control unit 200C can operate sequentially from the first mode MD1 to the second mode MD2.

[0175] During the nth frame period (n is a positive integer), sensor layer 200 can operate in first mode MD1 and second mode MD2.

[0176] The first mode MD1 may include a first time period PU1 and a second time period PS. The second time period PS may occur after the first time period PU1. Synchronized with the corresponding vertical synchronization signal Vsync, the control unit 200C can determine the start time of the first time period PU1. The start time of the first time period PU1 can be determined based on the time point of the level change of the vertical synchronization signal Vsync. For example, the start time of the first time period PU1 can be defined as the time point when the vertical synchronization signal Vsync transitions from a high level to a low level.

[0177] During the first time period PU1, the control unit 200C can output the first uplink signal ULS1 to the sensor layer 200. The frame period that provides the first uplink signal ULS1 can be referred to as the first uplink frame period. The vertical synchronization signal Vsync that outputs the frame period of the first uplink signal ULS1 can be referred to as the first uplink vertical synchronization signal.

[0178] During the second time period PS, sensor layer 200 can receive a first downlink signal DLS1 provided by input device 2000. Sensor layer 200 can sense a first input from input device 2000 based on the first downlink signal DLS1.

[0179] The input device 2000 can output a first downlink signal DLS1 based on the first uplink signal ULS1. The input device 2000 can provide the first downlink signal DLS1 to the control unit 200C during the second time period PS.

[0180] The second mode MD2 can occur after the first mode MD1.

[0181] During the (n+1)th frame period, sensor layer 200 can operate in first mode MD1 and second mode MD2.

[0182] The first mode MD1 may include a first time period PU2 and a second time period PS. The second time period PS may occur after the first time period PU2. Synchronized with the corresponding vertical synchronization signal Vsync, the control unit 200C can determine the start time of the first time period PU2. The start time of the first time period PU2 can be determined based on the time point of the level change of the vertical synchronization signal Vsync. For example, the start time of the first time period PU2 can be defined as the time point when the vertical synchronization signal Vsync changes from a high level to a low level.

[0183] During the first time period PU2, the control unit 200C can output a second uplink signal ULS2 to the sensor layer 200. The second uplink signal ULS2 may have a phase different from the first uplink signal ULS1. This will be described later. The frame period providing the second uplink signal ULS2 can be referred to as the second uplink frame period. The vertical synchronization signal Vsync that outputs the frame period of the second uplink signal ULS2 can be referred to as the second uplink vertical synchronization signal.

[0184] During the second time period PS, sensor layer 200 can receive a second downlink signal DLS2 provided from input device 2000. Sensor layer 200 can sense the first input of input device 2000 based on the second downlink signal DLS2.

[0185] The input device 2000 can output a second downlink signal DLS2 based on the second uplink signal ULS2. The input device 2000 can provide the second downlink signal DLS2 to the control unit 200C during the second time period PS.

[0186] The first uplink frame period and the second uplink frame period can be repeated. That is, during the (n+2)th frame period, the control unit 200C can output the first uplink signal ULS1 to the sensor layer 200 in the first mode MD1.

[0187] The first mode MD1 and the second mode MD2 can each be set to multiple first modes and multiple second modes, and can repeat each other. In the first mode MD1 (2a-1) (where a is a positive integer), the control unit 200C can output the first uplink signal ULS1 to the sensor layer 200. In the first mode MD1 (2a), the control unit 200C can output the second uplink signal ULS2 to the sensor layer 200.

[0188] In addition, the control unit 200C can output the first uplink signal ULS1 to the sensor layer 200 in sync with the 2a-1 vertical synchronization signal, and can also output the second uplink signal ULS2 to the sensor layer 200 in sync with the 2a vertical synchronization signal.

[0189] The first period of the multiple frame cycles can be different from the second period PR, and the first uplink signal ULS1 is output to the sensor layer 200 according to the second period PR. The first period can be approximately 16.44 ms, and the multiple frame cycles can have a frequency of approximately 60 Hz. The second period PR can be approximately 33.33 ms, and the frequency at which the first uplink signal ULS1 is output to the sensor layer 200 can be approximately 30 Hz.

[0190] Figure 10 The waveforms of each of the first uplink signal and the second uplink signal according to an embodiment are shown.

[0191] Reference Figure 9 and Figure 10 The control unit 200C can output a first uplink signal ULS1 to the sensor layer 200 during the first uplink frame period, and can output a second uplink signal ULS2 to the sensor layer 200 during the second uplink frame period.

[0192] The second uplink signal ULS2 and the first uplink signal ULS1 can have a phase difference of approximately 180 degrees. That is, the second uplink signal ULS2 can have a phase that is the opposite of the phase of the first uplink signal ULS1. The first uplink signal ULS1 and the second uplink signal ULS2 can be... Figure 2 The uplink signal ULS.

[0193] The first uplink signal ULS1 may be affected by the formation on sensor layer 200 and second electrode CE (see...). Figure 4 The parasitic capacitance Cb between ) (see Figure 4 Under the influence of ) transmission to the second electrode CE (see Figure 4 Transmitted to the second electrode CE (see...) Figure 4 The first uplink signal ULS1 can be transmitted to multiple data lines DL1 to DLm (see...). Figure 5 Each of the following. Therefore, the first uplink signal ULS1 may generate the first noise. The first noise and the data signal DS (see Figure 5 These signals may interfere with each other, potentially causing the first flicker. However, according to an embodiment, the phase of the second uplink signal ULS2 may be the inverse of the phase of the first uplink signal ULS1. The second uplink signal ULS2 may be affected by parasitic capacitance Cb (see...). Figure 4 Under the influence of ) transmission to the second electrode CE (see Figure 4 Transmitted to the second electrode CE (see...) Figure 4 The second uplink signal ULS2 can be transmitted to multiple data lines DL1 to DLm (see...). Figure 5 Each of the following. The second uplink signal ULS2 may generate second noise. The second noise and the data signal DS (see Figure 5 The first and second flickers may conflict (interfere) with each other, potentially causing a second flicker. The first and second flickers can be repeated over multiple frame periods, thus creating an optical illusion where the first and second flickers cancel each other out. Therefore, the image quality of display layer 100 can be improved.

[0194] Figure 11 The data of each of the first uplink signal and the second uplink signal according to an embodiment are schematically shown.

[0195] Reference Figure 9 and Figure 11 Each of the first uplink signal ULS1 and the second uplink signal ULS2 can have a size of 33 bits.

[0196] The first uplink signal ULS1 may include first synchronization data PD1 and first information data UP1. The second uplink signal ULS2 may include second synchronization data PD2 and second information data UP2.

[0197] The first synchronization data PD1 and the second synchronization data PD2 can each have a size of 3 bits. The first synchronization data PD1 and the second synchronization data PD2 can be different from each other. For example, the first synchronization data PD1 can have data 001, and the second synchronization data PD2 can have data 110.

[0198] Based on the first synchronization data PD1 and the second synchronization data PD2, the input device 2000 (see...) Figure 2 It can distinguish between the first uplink signal ULS1 and the second uplink signal ULS2.

[0199] The first information data UP1 and the second information data UP2 can each be 30 bits in size. Each of the first information data UP1 and the second information data UP2 may include uplink information of 25 bits and check information of 5 bits. The uplink information may include information about electronic device 1000 (see...). Figure 2 This information is used to detect errors in the transmitted data. The verification information can be a cyclic redundancy check (CRC).

[0200] Input device 2000 (see) Figure 2 The device receives the first uplink signal ULS1 and can then output the first downlink signal DLS1 based on the first uplink signal ULS1. That is, based on the first synchronization data PD1, the input device 2000 (see...) Figure 2 The first uplink signal ULS1 can be identified. Based on the first information data UP1, the input device 2000 (see...) Figure 2 The first downlink signal DLS1 can be output to sensor layer 200 (see...). Figure 2 ).

[0201] Input device 2000 (see) Figure 2The device receives the second uplink signal ULS2 and can then output the second downlink signal DLS2 based on ULS2. In other words, based on the second synchronization data PD2, the input device 2000 (see...) Figure 2 It can identify the second uplink signal ULS2. Input device 2000 (see...) Figure 2 The second information data UP2 can be converted. For example, when the second synchronization data PD2 has been identified, the input device 2000 (see...) Figure 2 It can convert 0 to 1 and 1 to 0 for the second uplink signal ULS2.

[0202] According to an embodiment, the input device 2000 (see...) Figure 2 The phase of the second information data UP2 can be switched when the second uplink signal ULS2 has been identified. Input device 2000 (see...) Figure 2 The second downlink signal DLS2 can be output based on the converted second information data. This is based on the input device 2000 (see...). Figure 2 The electronic device 1000 (see the first downlink signal DLS1 and the second downlink signal DLS2 received) Figure 2 It can detect input device 2000 (see...) Figure 2 The coordinates or tilt of the input device 2000 (see...). Figure 2 ) Receive either the first uplink signal ULS1 or the second uplink signal ULS2 received in each of the multiple frame periods, and then the downlink signal DLS (see Figure 2 Output to sensor layer 200 (see) Figure 2 Therefore, sensor layer 200 can be improved (see...). Figure 2 ) sensing reliability.

[0203] Figure 12 This is a conceptual diagram used to describe the operation of the display layer and sensor layer according to an embodiment. When given regarding... Figure 12 When describing, refer to Figure 9 The components described are indicated by the same reference numerals, and for ease of explanation of the embodiments, their descriptions will not be given.

[0204] Reference Figure 2 and Figure 12 The input device 2000 can receive a first uplink signal ULS1 and a second uplink signal ULS2. The input device 2000 can output a first downlink signal DLS1 to the sensor layer 200 based solely on the first uplink signal ULS1.

[0205] The first period of the multiple frame cycles can be different from the second period PR, and the first uplink signal ULS1 is output to the sensor layer 200 according to the second period PR. The first period can be approximately 16.44 ms, and the multiple frame cycles can have a frequency of approximately 60 Hz. The second period PR can be approximately 33.33 ms, and the frequency at which the first uplink signal ULS1 is output to the sensor layer 200 can be approximately 30 Hz. That is, the sensor layer 200 can receive the first downlink signal DLS1 from the input device 2000 according to the second period PR.

[0206] Based on the input device 2000 (see Figure 2 The first downlink signal DLS1 received by the electronic device 1000 (see...) Figure 2 It can detect input device 2000 (see...) Figure 2 The coordinates or inclination of ().

[0207] The first uplink signal ULS1 may be affected by the formation on sensor layer 200 and second electrode CE (see...). Figure 4 The parasitic capacitance Cb between ) (see Figure 4 Under the influence of ) transmission to the second electrode CE (see Figure 4 Transmitted to the second electrode CE (see...) Figure 4 The first uplink signal ULS1 can be transmitted to multiple data lines DL1 to DLm (see...). Figure 5 Each of the following. Therefore, the first uplink signal ULS1 may generate the first noise. The first noise and the data signal DS (see Figure 5 These signals may interfere with each other, potentially causing the first flicker. However, according to an embodiment, the phase of the second uplink signal ULS2 may be the inverse of the phase of the first uplink signal ULS1. The second uplink signal ULS2 may be affected by parasitic capacitance Cb (see...). Figure 4 Under the influence of ) transmission to the second electrode CE (see Figure 4 Transmitted to the second electrode CE (see...) Figure 4 The second uplink signal ULS2 can be transmitted to multiple data lines DL1 to DLm (see...). Figure 5 Each of the following. The second uplink signal ULS2 may generate second noise. The second noise and the data signal DS (see Figure 5 The first and second flickers may conflict (interfere) with each other, potentially causing a second flicker. The first and second flickers can be repeated over multiple frame periods, thus creating an optical illusion where the first and second flickers cancel each other out. Therefore, the image quality of display layer 100 can be improved.

[0208] Figure 13This is a conceptual diagram used to describe the operation of the display layer and sensor layer according to an embodiment. When given regarding... Figure 13 When describing, refer to Figure 9 The components described are indicated by the same reference numerals, and for ease of explanation of the embodiments, their descriptions will not be given.

[0209] Reference Figure 2 and Figure 13 The sensor layer 200 can operate in a first mode MD1 and a second mode MD2 during each of multiple frame periods. The first uplink signal ULS1, the second uplink signal ULS2, and the vertical synchronization signal Vsync can each be provided as a plurality of first uplink signals, a plurality of second uplink signals, and a plurality of vertical synchronization signals, respectively.

[0210] Compared to the output timing of the first uplink signal ULS1, which is synchronized with the nth vertical sync signal provided to the sensor layer 200 in the n+2 frame period (n is a positive integer), the output timing of the first uplink signal ULS1, which is synchronized with the n+2th vertical sync signal provided to the sensor layer 200 in the n+2 frame period, can be delayed by a first time t1.

[0211] Compared to the output timing of the first uplink signal ULS1 provided to sensor layer 200 in the (n+2)th frame period, the output timing of the first uplink signal ULS1 provided to sensor layer 200 in the (n+4)th frame period, synchronized with the (n+4)th vertical synchronization signal, can be delayed by a predetermined time. Furthermore, compared to the output timing of the first uplink signal ULS1 provided to sensor layer 200 in the (n)th frame period, synchronized with the (n)th vertical synchronization signal, the output timing of the first uplink signal ULS1 provided to sensor layer 200 in the (n+4)th frame period can be delayed by a second time t1-1.

[0212] Compared to the output timing of the second uplink signal ULS2, which is synchronized with the (n+1)th vertical sync signal provided to sensor layer 200 in frame period n+1, the output timing of the second uplink signal ULS2, which is synchronized with the (n+3)th vertical sync signal provided to sensor layer 200 in frame period n+3, can be delayed by a third time t2. The third time t2 can be approximately equal to the first time t1.

[0213] According to an embodiment, the first uplink signal ULS1 output during the nth frame period may generate first noise. The first noise and the data signal DS (see...) Figure 5 These may conflict (interfere) with each other, potentially causing the first flicker. The first flicker can be output to the effective area 1000A (see...). Figure 1AThe first region of the data signal DS. The second uplink signal ULS2 output during the (n+1)th frame period may generate second noise. The second noise and the data signal DS (see...) Figure 5 The first and second flickers may conflict (interfere) with each other, potentially causing a second flicker. The first and second flickers can produce an optical illusion effect where they cancel each other out. Therefore, the image quality of display layer 100 can be improved.

[0214] Additionally, the first uplink signal ULS1 output during the (n+2)th frame period may generate third noise. This third noise and the data signal DS (see...) Figure 5 These may conflict (interfere) with each other, potentially causing a third flash. The third flash can be output to the valid area 1000A (see...). Figure 1A The second region is different from the first region. The second uplink signal ULS2 output during the (n+3)th frame period may generate fourth noise. The fourth noise and the data signal DS (see...) Figure 5 These third and fourth flickers may conflict (interfere) with each other, potentially causing a fourth flicker. The third and fourth flickers can produce an optical illusion where they cancel each other out. Therefore, the image quality of display layer 100 can be improved.

[0215] According to an embodiment, the output timing of a third flash occurring during the (n+2)th frame period can be delayed by a predetermined time t1 compared to the output timing of a first flash occurring during the (n+1)th frame period, and the output timing of a fourth flash occurring during the (n+3)th frame period can be delayed by a predetermined time t2 compared to the output timing of a second flash occurring during the (n+1)th frame period. That is, in electronic device 1000 (see...) Figure 1A The flicker cancellation effect can occur in the first region during the nth and (n+1)th frame periods, and in the second region during the (n+2)th and (n+3)th frame periods. It can occur in the effective region 1000A (see...). Figure 1A The optical illusion of flickering caused by the uplink signal ULS is canceled out in different regions of the effective area. Therefore, it is possible to prevent the flickering effect visible from the outside in the effective area 1000A (see...). Figure 1A The same area of ​​the device continuously flickers.

[0216] Figure 14 This is a conceptual diagram used to describe the operation of the display layer and sensor layer according to an embodiment. When given regarding... Figure 14 When describing, refer to Figure 9 The components described are indicated by the same reference numerals, and for ease of explanation of the embodiments, their descriptions will not be given.

[0217] Reference Figure 2 and Figure 14 During each of the multiple frame periods, the sensor layer 200 can operate in a first mode MD1 and a second mode MD2. The first uplink signal ULS1, the second uplink signal ULS2, and the vertical synchronization signal Vsync can each be provided as a plurality of first uplink signals, a plurality of second uplink signals, and a plurality of vertical synchronization signals.

[0218] Sensor layer 200 can continuously provide the first uplink signal ULS1 for m frame periods (m is an integer greater than 1). Figure 14 In the example shown, the first uplink signal ULS1 is shown to be provided continuously for each of the three frame periods.

[0219] Compared with the output timing of the first uplink signal ULS1, which is synchronized with the output of the nth vertical synchronization signal to the sensor layer 200 in the n+1th frame period (n is a positive integer), the output timing of the first uplink signal ULS1, which is synchronized with the output of the n+1th vertical synchronization signal to the sensor layer 200 in the n+1th frame period, can be delayed by a first time t11.

[0220] Compared with the output timing of the first uplink signal ULS1, which is synchronized with the (n+1)th vertical synchronization signal output to the sensor layer 200, the output timing of the first uplink signal ULS1, which is synchronized with the (n+2)th vertical synchronization signal output to the sensor layer 200, can be delayed by a predetermined time in the (n+2)th frame period. Furthermore, compared with the output timing of the first uplink signal ULS1, which is synchronized with the nth vertical synchronization signal output to the sensor layer 200, in the n+1th frame period, the output timing of the first uplink signal ULS1, which is synchronized with the (n+2)th vertical synchronization signal output to the sensor layer 200, can be delayed by a second time t12.

[0221] The sensor layer 200 can continuously provide the second uplink signal ULS2 for k frame periods (k is an integer greater than 1).

[0222] Compared to the output timing of the second uplink signal ULS2, which is synchronized with the (n+3)th vertical synchronization signal output to sensor layer 200 in frame period n+3, the output timing of the second uplink signal ULS2, which is synchronized with the (n+4)th vertical synchronization signal output to sensor layer 200 in frame period n+4, can be delayed by a third time t21. The third time t21 can be substantially equal to the first time t11. However, the embodiment is not limited to this, and the third time t21 can be different from the first time t11.

[0223] According to an embodiment, the first uplink signal ULS1 output during the nth frame period may generate first noise. The first noise and the data signal DS (see...) Figure 5 These may conflict (interfere) with each other, potentially causing the first flicker. The first flicker can be output to the effective area 1000A (see...). Figure 1A The first region of the data signal DS. The second uplink signal ULS2 output during the (n+3)th frame period may generate second noise. The second noise and the data signal DS (see...) Figure 5 The first and second flickers may conflict (interfere) with each other, potentially causing a second flicker. The first and second flickers can produce an optical illusion effect where they cancel each other out. Therefore, the image quality of display layer 100 can be improved.

[0224] Additionally, the first uplink signal ULS1 output during the (n+1)th frame period may generate third noise. This third noise and the data signal DS (see...) Figure 5 These may conflict (interfere) with each other, potentially causing a third flash. The third flash can be output to the valid area 1000A (see...). Figure 1A The second region is different from the first region. The second uplink signal ULS2 output during the (n+4)th frame period may generate fourth noise. The fourth noise and the data signal DS (see...) Figure 5 These third and fourth flickers may conflict (interfere) with each other, potentially causing a fourth flicker. The third and fourth flickers can produce an optical illusion where they cancel each other out. Therefore, the image quality of display layer 100 can be improved.

[0225] According to an embodiment, the output timing of the third flash occurring during the (n+1)th frame period can be delayed by a predetermined time t11 compared to the output timing of the first flash occurring during the (n+3)th frame period, and the output timing of the fourth flash occurring during the (n+4)th frame period can be delayed by a predetermined time t21 compared to the output timing of the second flash occurring during the (n+3)th frame period. That is, in electronic device 1000 (see...) Figure 1A The optical illusion of flicker cancellation can occur in the first region during the nth and (n+3)th frame periods, and in the second region during the (n+1)th and (n+4)th frame periods. It can occur in the effective region 1000A (see...). Figure 1A The optical illusion of flickering caused by the uplink signal ULS is canceled out in different regions of the effective area. Therefore, it is possible to prevent the flickering effect visible from the outside in the effective area 1000A (see...). Figure 1A The same area of ​​the device continuously flickers.

[0226] According to an embodiment, during a first uplink frame period, a first uplink signal can be output to the sensor layer. During a second uplink frame period, a second uplink signal having a phase different from that of the first uplink signal can be output to the sensor layer. The first flicker generated in the image by the first uplink signal and the second flicker generated in the image by the second uplink signal can be repeated for multiple frame periods, thereby producing a visual illusion effect where the first flicker and the second flicker cancel each other out. Therefore, the image quality of the electronic device can be improved.

[0227] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. An electronic device, the electronic device comprising: The display layer is configured to display images for multiple frame cycles; A sensor layer is disposed on the display layer and configured to operate in a first mode in which it senses a first input via an input device and in a second mode in which it senses a second input via touch. as well as The control unit is configured to control the sensor layer. Specifically, in the first mode, the control unit outputs a first uplink signal to the sensor layer during a first uplink frame period within the plurality of frame periods, and in the first mode, outputs a second uplink signal having a phase different from the first uplink signal to the sensor layer during a second uplink frame period within the plurality of frame periods, which is different from the first uplink frame period. The first uplink signal and the second uplink signal are each provided as a plurality of first uplink signals and a plurality of second uplink signals, and when compared with the output timing of the first uplink signal in the nth frame period, the output timing of the first uplink signal in the (n+2)th frame period is delayed by a first time, where n is a positive integer.

2. An electronic device, the electronic device comprising: The display layer is configured to display images for multiple frame cycles; A sensor layer is disposed on the display layer and configured to operate in a first mode in which it senses a first input via an input device and in a second mode in which it senses a second input via touch. as well as The control unit is configured to control the sensor layer. Specifically, in the first mode, the control unit outputs a first uplink signal to the sensor layer during a first uplink frame period within the plurality of frame periods, and in the first mode, outputs a second uplink signal having a phase different from the first uplink signal to the sensor layer during a second uplink frame period within the plurality of frame periods, which is different from the first uplink frame period. Specifically, the first uplink signal and the second uplink signal are each provided as multiple first uplink signals and multiple second uplink signals, respectively. The control unit continuously outputs the first uplink signal to the sensor layer for m frame periods and continuously outputs the second uplink signal to the sensor layer for k frame periods, where m is an integer greater than 1 and k is an integer greater than 1. Specifically, when comparing the output timing of the first uplink signal in the nth frame period, the output timing of the first uplink signal in the (n+1)th frame period is delayed by a first time, where n is a positive integer, and When compared with the output timing of the second uplink signal in the i-th frame period, the output timing delay of the second uplink signal in the (i+1)-th frame period is different from the second time of the first time, where i is a positive integer.

3. The electronic device according to claim 1 or 2, wherein, The first uplink signal and the second uplink signal each include different synchronization data.

4. The electronic device according to claim 1 or 2, wherein, The first mode and the second mode are each provided as a plurality of first modes and a plurality of second modes, and they repeat each other. The control unit outputs the first uplink signal to the sensor layer in the 2n-1 first mode, and outputs the second uplink signal to the sensor layer in the 2n first mode, where n is a positive integer.

5. The electronic device according to claim 1, wherein, When compared with the output timing of the second uplink signal in the (n+1)th frame period, the output timing of the second uplink signal in the (n+3)th frame period is delayed by a second time.

6. The electronic device according to claim 1 or 2, wherein, The first period of the plurality of frame periods is different from the second period of the first uplink signal.

7. The electronic device according to claim 1 or 2, wherein, When an image of one frame period is displayed on the display layer, the control unit operates sequentially in the first mode and the second mode.

8. The electronic device according to claim 1 or 2, wherein, The first mode includes a first time period and a second time period. During the first time period, either the first uplink signal or the second uplink signal is transmitted to the input device. During the second time period, the first input is sensed based on a downlink signal provided from the input device. The second time period occurs after the first time period.

9. The electronic device according to claim 1 or 2, further comprising a display driving unit configured to generate a vertical synchronization signal for driving the display layer, and in, The control unit synchronizes with the vertical synchronization signal to output either the first uplink signal or the second uplink signal to the sensor layer.

10. An interface device comprising an electronic device and an input device configured to communicate with the electronic device. in, The electronic device includes: Display layer; A sensor layer is disposed on the display layer and configured to sense a first input through the input device; A display driving unit is configured to generate a synchronization signal for driving the display layer; and The control unit is configured to control the sensor layer. Specifically, the control unit synchronizes with a first uplink synchronization signal in the synchronization signal to output a first uplink signal to the sensor layer, and synchronizes with a second uplink synchronization signal in the synchronization signal that is different from the first uplink synchronization signal to output a second uplink signal with a phase different from the first uplink signal to the sensor layer. The first uplink signal, the second uplink signal, and the synchronization signal are each provided as a plurality of first uplink signals, a plurality of second uplink signals, and a plurality of synchronization signals, respectively. When compared with the output timing of the first uplink signal synchronized to the nth synchronization signal output to the sensor layer, the output timing of the first uplink signal synchronized to the (n+2)th synchronization signal output to the sensor layer is delayed by a first time, where n is a positive integer.

11. An interface device comprising an electronic device and an input device configured to communicate with the electronic device. in, The electronic device includes: Display layer; A sensor layer is disposed on the display layer and configured to sense a first input through the input device; A display driving unit is configured to generate a synchronization signal for driving the display layer; and The control unit is configured to control the sensor layer. Specifically, the control unit synchronizes with a first uplink synchronization signal in the synchronization signal to output a first uplink signal to the sensor layer, and synchronizes with a second uplink synchronization signal in the synchronization signal that is different from the first uplink synchronization signal to output a second uplink signal with a phase different from the first uplink signal to the sensor layer. Specifically, the first uplink signal, the second uplink signal, and the synchronization signal are each provided as multiple first uplink signals, multiple second uplink signals, and multiple synchronization signals for multiple frames. The control unit continuously outputs the first uplink signal to the sensor layer for m frame periods and continuously outputs the second uplink signal to the sensor layer for k frame periods, where m is an integer greater than 1 and k is an integer greater than 1. Specifically, when comparing the output timing of the first uplink signal synchronized with the nth synchronization signal output to the sensor layer, the output timing of the first uplink signal synchronized with the (n+1)th synchronization signal output to the sensor layer is delayed by a first time, where n is a positive integer, and When compared with the output timing of the second uplink signal synchronized to the sensor layer by the i-th synchronization signal, the output timing delay of the second uplink signal synchronized to the (i+1)-th synchronization signal is different from the second time of the first time, where i is a positive integer.

12. The interface device according to claim 10 or 11, wherein, The first uplink signal includes first synchronization data, and the second uplink signal includes second synchronization data. Based on the first synchronization data and the second synchronization data, the input device distinguishes between the first uplink signal and the second uplink signal.

13. The interface device according to claim 10 or 11, wherein, The input device is configured to receive the first uplink signal and the second uplink signal, output a first downlink signal based on the first uplink signal, and output a second downlink signal based on the second uplink signal.

14. The interface device according to claim 10 or 11, wherein, The input device is configured to receive the first uplink signal and the second uplink signal, and to output a downlink signal based only on the first uplink signal.

15. The interface device according to claim 10 or 11, wherein, The synchronization signal is a vertical synchronization signal, wherein the vertical synchronization signal is provided as multiple vertical synchronization signals respectively for multiple frames, and the control unit outputs the first uplink signal to the sensor layer in synchronization with the (2n-1)th vertical synchronization signal, and outputs the second uplink signal to the sensor layer in synchronization with the 2nth vertical synchronization signal, wherein n is a positive integer.

16. The interface device according to claim 10, wherein, When compared with the output timing of the second uplink signal that is synchronized with the (n+1)th synchronization signal output to the sensor layer, the output timing of the second uplink signal that is synchronized with the (n+3)th synchronization signal output to the sensor layer is delayed by a second time.

Images