Display device

Abstract

A display device is provided. The display device includes a display panel including a plurality of pixels, a source driver to output a target initialization voltage in an analog format to the pixels through a sense line, and a timing controller to provide a data control signal to the source driver, the data control signal including grouping information associated with the target initialization voltage. The grouping information can be in a digital format. The source driver includes a digital-to-analog converter to generate the target initialization voltage in the analog format based on the grouping information.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2020-0126344, filed on September 28, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to source drivers and display devices including source drivers. Background Technology

[0004] With the development of information technology, display devices, as the connection medium between users and information, have become increasingly important. Consequently, display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) are being used more and more frequently.

[0005] The display device may include pixels connected to scan lines and data lines respectively, a scan driver for driving scan lines, and a data driver for driving data lines.

[0006] A pixel circuit may include multiple transistors, capacitors, and light-emitting devices. When a scan signal is supplied from a scan line, a data voltage is supplied to the pixel circuit from a data line, and the current of the driving transistor, based on the data voltage, is supplied to the light-emitting device. The light-emitting device emits light with an intensity corresponding to the current of the driving transistor.

[0007] Specifically, the magnitude of the current driving the transistor is proportional to the square of the voltage difference between the gate and source electrodes of the transistor. In other words, the magnitude of the current driving the transistor can be affected not only by the data voltage applied to the gate electrode but also by the voltage at the source electrode. Therefore, a constant reference voltage (or initialization voltage) can be applied to the source electrode to easily adjust the voltage difference between the gate and source electrodes of the transistor. Summary of the Invention

[0008] However, the reference voltage (or initialization voltage) can be provided in analog form via a printed circuit board with a power supply, a source driver with a data driver, and a display panel with pixel circuitry. The value of the reference voltage can be varied due to factors such as the self-resistance of the power lines used to provide the reference voltage, the bonding resistance between the printed circuit board and the source driver, and the bonding resistance between the source driver and the display panel.

[0009] A trend has been shown to increase the size of display panels, and therefore, a greater number of source drivers are required. When the reference voltage values ​​between the source drivers differ from each other, a mura appearing vertically on a per-source-driver basis can be seen by the user of the display device.

[0010] The embodiments provide a display device capable of providing a reference voltage having a value that does not change even when the bonding resistance between the printed circuit board and the source driver, and the bonding resistance between the source driver and the display panel, increases in high-temperature and humid environments.

[0011] The embodiments also provide a display device capable of providing a reference voltage with substantially the same magnitude to multiple source drivers.

[0012] According to one aspect of this disclosure, a source driver is provided, comprising: an internal interface for receiving a data control signal and outputting packet information extracted from the data control signal and associated with a target initialization voltage, wherein the packet information is in digital format; and a digital-to-analog converter for generating an initialization voltage in analog format based on the packet information.

[0013] The source driver may also include a logic controller disposed between the internal interface and the digital-to-analog converter, and the logic controller may generate a first control signal for controlling the digital-to-analog converter based on the packet information.

[0014] The source driver may also include a level shifter disposed between the logic controller and the digital-to-analog converter, and the level shifter may boost the first control signal into a second control signal capable of operating the digital-to-analog converter.

[0015] The source driver may also include a buffer amplifier disposed between the sensing line and the digital-to-analog converter, and the sensing line may be connected to the pixel.

[0016] The digital-to-analog converter (DAC) may include: a DAC controller that converts a second control signal into an n-bit signal; and a DAC switching unit connected to the DAC controller via n channels, and including a configuration of 2 n Multiple switches arranged in a matrix of n rows and n columns. Here, n is a natural number.

[0017] The digital-to-analog converter may also include a voltage divider, the voltage divider comprising two components connected in series between the first and second terminals. n A resistor has an analog drive voltage applied to its first terminal and a ground voltage applied to its second terminal. The digital-to-analog converter switching unit can receive multiple initialization voltages generated by dividing the drive voltage by a voltage divider, and can select one of the multiple initialization voltages as the target initialization voltage.

[0018] The voltage divider can be connected to 2 n One channel is connected to the digital-to-analog converter switching unit, and through 2 n Each channel provides multiple initialization voltages to the digital-to-analog converter switching unit.

[0019] Multiple switches can be configured using a combination of N-type and P-type transistors. The N-type and P-type transistors can be arranged such that, in response to an n-bit signal, only 2 n All the switches in one row of each row are turned on.

[0020] According to another aspect of this disclosure, a display device is provided, the display device comprising: a display panel including a plurality of pixels; a source driver that outputs a target initialization voltage in analog format to the pixels via sensing lines; and a timing controller that provides a data control signal to the source driver, the data control signal including grouping information associated with the target initialization voltage.

[0021] The grouping information can be in digital format, and the source driver can include a digital-to-analog converter that generates a target initialization voltage in analog format based on the grouping information.

[0022] The source driver may further include: an internal interface for receiving data control signals and outputting packet information included in the data control signals; and a logic controller disposed between the internal interface and the digital-to-analog converter, wherein the logic controller is capable of generating a first control signal for controlling the digital-to-analog converter based on the packet information.

[0023] The source driver may also include a level shifter disposed between the logic controller and the digital-to-analog converter, and the level shifter may boost the first control signal into a second control signal capable of operating the digital-to-analog converter.

[0024] The display device may also include a buffer amplifier disposed between the sensing line and the digital-to-analog converter.

[0025] The digital-to-analog converter (DAC) may include: a DAC controller that converts a second control signal into an n-bit signal; and a DAC switching unit connected to the DAC controller via n channels, and including a configuration of 2 n Multiple switches arranged in a matrix of n rows and n columns. Here, n is a natural number.

[0026] The display device may also include a voltage divider, the voltage divider comprising two components connected in series between the first terminal and the second terminal. n A resistor has an analog-format drive voltage applied to its first terminal and a ground voltage applied to its second terminal. The voltage divider can output multiple divided voltages by dividing the drive voltage.

[0027] The voltage divider can be connected to 2 n One channel is connected to the digital-to-analog converter switching unit, and through 2 n Each channel supplies the divided voltage to the digital-to-analog converter switching unit.

[0028] Multiple switches can be configured using a combination of N-type and P-type transistors. The N-type and P-type transistors can be arranged such that, in response to an n-bit signal, only 2 n All switches in one row of the row are turned on.

[0029] Each of the plurality of pixels may be connected to a scan line, a data line, and a sensing control line. Each of the plurality of pixels may include: a driving transistor including a first electrode connected to a first power voltage line, a second electrode connected to the anode of a light-emitting device, and a gate electrode connected to a first node; a first transistor including a first electrode connected to a data line, a second electrode connected to the first node, and a gate electrode connected to a scan line; a second transistor including a first electrode connected to a sensing line, a second electrode connected to the anode of a light-emitting device, and a gate electrode connected to a sensing control line; and a capacitor connected between the first node and the anode of the light-emitting device.

[0030] The display panel and the printed circuit board with a timing controller installed can be connected to each other via a flexible film with an active electrode driver installed.

[0031] Flexible films can be fabricated using either chip-on-film (COF) or chip-on-plastic (COP) methods.

[0032] The data line can receive a portion of a data signal, and the data signal may include multiple line image data. Each of the multiple line image data may include line start (SOL) data, configuration control data, pixel data, and horizontal blank period data. Attached Figure Description

[0033] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0034] In the depicted figures, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intervening elements. Throughout the text, similar reference numerals indicate similar elements.

[0035] Figure 1 This is a perspective view of a display device according to the present disclosure.

[0036] Figure 2 This is a block diagram of a display device according to the present disclosure.

[0037] Figure 3 It is shown Figure 2 The circuit diagram shows an example of a pixel.

[0038] Figure 4 This is an enlarged schematic block diagram of the source driver, showing... Figure 1 The region AA shown in the image.

[0039] Figure 5 This is a diagram showing one of the line image data supplied through valid lines.

[0040] Figure 6 It is shown Figure 5 The graph shows the line starting (“SOL”) of the data.

[0041] Figure 7 It is shown Figure 5 The diagram shows the configuration control data.

[0042] Figure 8 It is shown Figure 4 The diagram shows the grouping information.

[0043] Figure 9 and Figure 10 This is a diagram illustrating the generation of an initialization voltage using a digital-to-analog converter according to an embodiment of the present disclosure. Detailed Implementation

[0044] In the following, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Throughout the drawings, the same reference numerals are assigned to the same elements, and overlapping descriptions will be omitted. It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Thus, without departing from the teachings herein, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion. The wording used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the content clearly indicates otherwise, as used herein, the singular forms “a(a),” “an,” and “the” are intended to include the plural forms, including “at least one.” “At least one” will not be construed as limiting “a(a)” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprise” and / or “comprising” or “include” and / or “including”, when used in this specification, indicate the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or groups thereof.

[0045] Figure 1 This is a perspective view of a display device according to the present disclosure. Figure 2 This is a block diagram of a display device according to the present disclosure.

[0046] Reference Figure 1 and Figure 2 The display device 1 may include a display panel 100, a scan driver 400, a data driver 500, a flexible film 130, a first printed circuit board (“PCB”) 140, a connector 150, a second PCB 160, a timing controller (“T-con”) 200, and a host system 300. In the following description, for convenience, it will be assumed and described that the display device 1 is an organic light-emitting display device. However, the present disclosure according to the invention is not limited thereto, and can be applied to various types of display devices such as liquid crystal displays (“LCD”), electrophoretic displays (“EPD”), and inorganic light-emitting display devices.

[0047] The display panel 100 may include a lower substrate 110 and an upper substrate 120. The lower substrate 110 may be a thin-film transistor substrate made of plastic or glass. The upper substrate 120 may be an encapsulation substrate configured as a plastic film, a glass substrate, or a protective film.

[0048] The lower substrate 110 may include a display area and a non-display area disposed around the periphery of the display area. The display area is an area provided with pixels PX to display an image. Scan lines SL1 to SLn (n is a positive integer of 2 or greater), data lines DL1 to DLm (m is a positive integer of 2 or greater), and sensing lines SSL1 to SSLm may be arranged on the lower substrate 110. The data lines DL1 to DLm and the sensing lines SSL1 to SSLm may be arranged parallel to each other. The data lines DL1 to DLm and the sensing lines SSL1 to SSLm may be arranged to intersect with the scan lines SL1 to SLn.

[0049] The scan driver 400 can receive a scan control signal SCS input from the T-con 200. The scan driver 400 can supply scan signals to scan lines SL1 to SLn according to the scan control signal SCS. The scan signals may include scan signals and sensing signals. The scan driver 400 can be formed in a non-display area outside one side or opposite sides of the display area of ​​the display panel 100 as an in-panel gate driver (“GIP”).

[0050] The data driver 500 can receive compensated image data CDATA and data control signal DCS from the T-con 200 input. The compensated image data CDATA can be obtained by performing compensation drive transistor DT on the image data DATA (see [link to relevant documentation]). Figure 3 External compensation for the threshold voltage of ) and for compensation of light-emitting devices (LD) (see Figure 3 Image data is corrected by afterimage compensation to adjust the degree of degradation. The data driver 500 converts the compensated image data CDATA into an analog data voltage according to the data control signal DCS and supplies the analog data voltage to data lines DL1 to DLm. Pixels PX to which the analog data voltage will be supplied can be selected by a scan signal supplied from the scan driver 400. The selected pixel PX can be supplied with the data voltage to emit light with a predetermined brightness.

[0051] Sensing voltage or sensing current can be supplied to data driver 500 from sensing lines SSL1 to SSLm. Data driver 500 can generate sensing data SEN using the sensing voltage or sensing current. Sensing data SEN includes information about the threshold voltage of the driving transistor DT in each pixel PX and the degree of degradation of the light-emitting device LD. Data driver 500 can supply sensing data SEN to timing controller 200.

[0052] The data driver 500 may include multiple source drivers 510. The source drivers 510 may be mounted on the flexible film 130. The flexible film 130 may be attached to pads disposed on the lower substrate 110 using an anisotropic conductive film (“ACF”) in an auto-bonding manner. Since the pads are connected to data lines DL1 to DLm, the source drivers 510 may be connected to the data lines DL1 to DLm.

[0053] Each of the flexible films 130 may be disposed in a die-on-film (“COF”) manner or a chip-on-plastic (“COP”) manner. The COF may include a base film such as polyimide and a plurality of conductive leads disposed on the base film. Each of the flexible films 130 may be bent or folded. Each of the flexible films 130 may be attached to the lower substrate 110 and the first PCB 140 of the display panel 100.

[0054] The first PCB 140 may be attached to the flexible film 130. The first PCB 140 may allow the T-con 200 to be mounted thereon. The first PCB 140 may be a flexible printed circuit board (“FPCB”). The first PCB 140 may be connected to the second PCB 160 via a connector 150.

[0055] The connection portion 150 can connect to the first PCB 140 and the second PCB 160. The connection portion 150 can correspond to multiple lines including a bus between the timing controller 200 and the host system 300, which serves as an input / output terminal using an internal interface. The internal interface is an interface capable of processing multiple input data at high speed. However, according to this disclosure, the present invention is not limited thereto, and the connection portion 150 can be implemented using any interface capable of transmitting data and multiple lines including arbitrary input / output terminals.

[0056] The second PCB 160 can supply power voltage and drive signals to the display device 1. The second PCB 160 allows the host system 300 to be mounted thereon. The second PCB 160 can be connected to the first PCB 140 via the connector 150.

[0057] The timing controller 200 can receive image data DATA and control signals CS input from the host system 300. The host system 300 may include a system-on-chip (“SoC”) with a built-in scaler. The host system 300 can convert externally input image data into a format suitable for display on the display panel 100 (i.e., image data DATA).

[0058] The control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock, etc. The vertical synchronization signal defines a frame time period. The horizontal synchronization signal defines a horizontal time period (e.g., ...) required to supply data voltage to a pixel PX of a horizontal line on the display panel 100. Figure 5 The signal in 1H). The data enable signal is a signal that limits the period of time during which valid input data is received. The point clock is a signal that repeats within a predetermined short period of time.

[0059] The timing controller 200 can generate a scan control signal SCS for controlling the operating timing of the scan driver 400 and a data control signal DCS for controlling the operating timing of the data driver 500 based on the control signal CS, so as to control the operating timing of the scan driver 400 and the data driver 500. The timing controller 200 can output the scan control signal SCS to the scan driver 400 and the data control signal DCS to the data driver 500.

[0060] The timing controller 200 can receive sensing data SEN input from the data driver 500. The timing controller 200 can generate compensation data that performs external compensation and ghost image compensation on the sensing data SEN. The timing controller 200 can perform external compensation and ghost image compensation using the compensation data. The timing controller 200 can provide the data driver 500 with compensated image data CDATA, on which external compensation and ghost image compensation have been performed.

[0061] Figure 3 It is shown Figure 2 The circuit diagram shows an example of the pixels shown. For ease of description, Figure 3 The image illustrates a pixel PX connected to the i-th (i is a positive integer satisfying 1≤i≤n) scan line SLi, the i-th sensing control line SEi, the j-th (j is a positive integer satisfying 1≤j≤m) data line DLj, the first power voltage line VDDL, and the j-th (j is a positive integer satisfying 1≤j≤m) sensing line SSLj.

[0062] Reference Figure 3 A pixel PX may include a light-emitting device LD and a pixel circuit PXC for supplying driving current to the light-emitting device LD. The pixel circuit PXC may include a driving transistor DT, a first transistor ST1 and a second transistor ST2, and a capacitor C.

[0063] The light-emitting device (LD) emits light according to the current flowing through the driving transistor (DT). The anode of the LD can be connected to the source electrode of the driving transistor (DT), and the cathode of the LD can be connected to a second power voltage line VSSL supplied with a low-potential driving voltage lower than the driving voltage.

[0064] In an embodiment, the light-emitting device (LD) may include an anode, a hole transport layer, an organic light-emitting layer, an electron transport layer, and a cathode. In the LD, when a voltage is applied to the anode and cathode, holes and electrons move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic light-emitting layer, thereby emitting light.

[0065] The gate electrode of the driving transistor DT can be connected to the first electrode of the first transistor ST1 or the first node N1, the source electrode of the driving transistor DT can be connected to the anode of the light-emitting device LD, and the drain electrode of the driving transistor DT can be connected to the first power voltage line VDDL. The driving transistor DT can control the current flowing from the first power voltage line VDDL to the light-emitting device LD according to the voltage difference between its gate electrode and source electrode.

[0066] The gate electrode of the first transistor ST1 can be connected to the i-th scan line SLi, the first electrode of the first transistor ST1 can be connected to the gate electrode of the driving transistor DT or the first node N1, and the second electrode of the first transistor ST1 can be connected to the j-th data line DLj. When the i-th scan signal with a gate on-state voltage is supplied to the i-th scan line SLi, the first transistor ST1 can be turned on to supply the voltage of the j-th data line DLj to the gate electrode of the driving transistor DT.

[0067] The gate electrode of the second transistor ST2 can be connected to the i-th sensing control line SEi, the first electrode of the second transistor ST2 can be connected to the j-th sensing line SSLj, and the second electrode of the second transistor ST2 can be connected to the source electrode of the driving transistor DT. When the i-th sensing signal with a gate on-state voltage is supplied to the i-th sensing control line SEi, the second transistor ST2 can be turned on to supply the reference voltage (or target initialization voltage Vint) of the j-th sensing line SSLj to the source electrode of the driving transistor DT.

[0068] exist Figure 3 In this configuration, the first electrode of each of the first transistor ST1 and the second transistor ST2 can be either a source electrode or a drain electrode, and the second electrode of each of the first transistor ST1 and the second transistor ST2 can be an electrode different from the first electrode. For example, when the first electrode is a source electrode, the second electrode can be a drain electrode.

[0069] The capacitor C may include a first electrode connected to the gate electrode or the first node N1 of the driving transistor DT and a second electrode connected to the source electrode of the driving transistor DT. The voltage difference between the gate electrode and the source electrode of the driving transistor DT may be stored in the capacitor C.

[0070] Despite Figure 3The present invention has primarily described the implementation of the drive transistor DT, the first transistor ST1, and the second transistor ST2 using an N-type metal-oxide-semiconductor field-effect transistor (“MOSFET”), but is not limited thereto. The drive transistor DT, the first transistor ST1, and the second transistor ST2 can also be implemented using a P-type MOSFET.

[0071] A pixel PX according to an embodiment of the present disclosure includes a first transistor ST1 connected to the gate electrode of a j-th data line DLj and a driving transistor DT, and a second transistor ST2 connected to the source electrode of a j-th sensing line SSLj and the driving transistor DT. In the pixel PX according to an embodiment of the present disclosure, controlling the conduction of the first transistor ST1 and the second transistor ST2 and the voltage supplied to the j-th data line DLj enables the sensing of a threshold voltage of the driving transistor DT.

[0072] Figure 4 This is an enlarged schematic block diagram of the source driver, showing... Figure 1 The region AA shown in the image. Figure 5 This is a diagram showing one of the line image data supplied through valid lines. Figure 6 It is shown Figure 5 The graph shows the line starting (“SOL”) of the data. Figure 7 It is shown Figure 5 The diagram shows the configuration control data. Figure 8 It is shown Figure 4 The diagram shows the grouping information. Figure 9 and Figure 10 This is a diagram illustrating the generation of an initialization voltage using a digital-to-analog converter according to an embodiment of the present disclosure.

[0073] Reference Figure 4 The source driver 510 may include an internal interface 511, a logic controller 512, a level shifter 513, a digital-to-analog converter (“DAC”) 514, a buffer amplifier 515, and an initialization voltage switch 516.

[0074] According to embodiments of this disclosure, the timing controller 200 may provide a data control signal (DCS) for each image frame to the internal interface 511. An image frame may represent a unit of time interval during which the display panel 100 displays a still image. Moving images, formed by combining multiple image frames, can be displayed via the display panel 100.

[0075] Each image frame's frame duration may include a vertical blank period and a valid data period. The valid data period may be the period during which the grayscale values ​​of the image frame will be supplied to the pixels PX constituting the display panel 100. The vertical blank period may be located between the valid data period of the previous frame and the valid data period of the current frame. That is, the valid data period may be performed after the vertical blank period. For example, clock training, frame configuration, and virtual pixel data supply may be performed during the vertical blank period. During the valid data period, multiple line image data LDCS may be supplied to each of multiple valid lines. Each valid line may correspond to a pixel row corresponding to each of the scan lines SL1 to SLn.

[0076] like Figure 5 As shown, each line image data LDCS may include SOL data (SOL), configuration control data (CONF), pixel data (PXD), and horizontal blank period data (HBP). During the valid data period, the pixel data (PXD) and control data (SOL, CONF, and HBP) ​​for each of the multiple valid lines may be supplied to the data driver 500.

[0077] like Figure 6 and Figure 7 As shown, the SOL data SOL, configuration control data CONF, and initialization voltage control data VINT_D can include multiple unit data, and each of the unit data can be configured using 10 bits (AD, D0, D1, D2, D3, D4, D5, D6, D7, and D8).

[0078] A time period for supplying one unit of data may be referred to as a time period 1T. Each unit of data may include a transition bit AD. Although the transition bit AD may be configured differently depending on the product, it can be configured to have a different level than the immediately preceding bit. Depending on the product, the transition bit AD may be configured to have a different level than the next bit. For example, the transition bit AD may indicate the start of each unit of data.

[0079] Reference Figure 6 SOL data SOL can notify the source driver ( Figure 4 (510 shown in the diagram): The supply of signals for changing pixel rows will begin. In this embodiment, the unit data column of SOL data SOL is configured using 1111111111, but this may vary depending on the product. Configuration control data CONF may be provided after SOL data SOL is provided.

[0080] Reference Figure 7The configuration control data CONF may include a 10-bit unit data column starting with 001 and ending with 1, and may include operation option data CONFD in the middle for controlling the operation options of the source driver 510. For example, the operation option data CONFD may indicate the type of subsequent data. The data following the configuration control data CONF may be pixel data PXD or virtual pixel data (not shown). When no clock training is supplied, a high-level clock control signal SFC is applied.

[0081] At least a portion of the unit data included in the configuration control data CONF may include initialization voltage control data VINT_D. Initialization voltage control data VINT_D may be data used to control the magnitude of the target initialization voltage Vint.

[0082] In an embodiment, for example, the configuration control data CONF may include first initialization voltage control data VINT_D1, second initialization voltage control data VINT_D2, third initialization voltage control data VINT_D3, and fourth initialization voltage control data VINT_D4. Regarding the initialization voltage control data VINT_D1, VINT_D2, VINT_D3, and VINT_D4, as follows... Figure 7 As shown, the two initialization voltage control data VINT_D can be included in a single data column. However, the present disclosure according to the invention is not limited thereto, and one initialization voltage control data VINT_D can be included in a single data column.

[0083] Pixel data (PXD) may include pixel grayscale data (RGBD), such that the remaining bits (D0, D1, D2, D3, D4, D5, D6, D7, and D8) of each unit of data, excluding the transformation bits (AD), represent the grayscale value of the corresponding pixel. The configuration of the pixel data (PXD) may vary depending on the product. Horizontal blanking period data (HBP) may be provided after the pixel data (PXD).

[0084] The supply period of the horizontal blank period data HBP can be controlled by the configuration control data CONF. The source driver 510 can determine whether to change the pixel row corresponding to the pixel data PXD (e.g., pixels connected to the same scan line).

[0085] According to embodiments of this disclosure, digital format initialization voltage control data VINT_D is provided from a timing controller 200 mounted on a first PCB 140 to an internal interface 511 of a source driver 510 mounted on a flexible film 130, such that a digital format signal relative to a target initialization voltage Vint can be transmitted to the source driver 510 regardless of variations in the resistance of the wires between the timing controller 200 and the internal interface 511 and / or the bonding resistance between the first PCB 140 and the flexible film 130.

[0086] Return to reference Figure 4 The internal interface 511 can extract only the packet information PK associated with the initialization voltage control data VINT_D from the data control signal DCS, and provide the extracted packet information PK to the logic controller 512.

[0087] The logic controller 512 can output a first control signal CS_DACL for controlling the level shifter 513 based on the packet information PK. The first control signal CS_DACL can be in digital format.

[0088] Reference Figure 7 and Figure 8 The grouping information PK can be configured using 4 bits of data. The value of the target initialization voltage Vint can be controlled to be subdivided into 16 types based on the value of the initialization voltage control data VINT_D included in the grouping information PK. However, the present disclosure according to the invention is not limited thereto, and when the configuration control data CONF includes a greater number of bits of initialization voltage control data VINT_D, the value of the target initialization voltage Vint can be controlled to be further subdivided.

[0089] In an embodiment, for example, when the group information PK has data 0000 in the order of the fourth initialization voltage control data VINT_D4, the third initialization voltage control data VINT_D3, the second initialization voltage control data VINT_D2, and the first initialization voltage control data VINT_D1, the logic controller 512 can output a first control signal CS_DACL with the target initialization voltage Vint having a value of V0[V].

[0090] Similarly, when the packet information PK has data 0001, the logic controller 512 can output a first control signal CS_DACL with a target initialization voltage Vint value of V1 [V]. When the packet information PK has data 1110, the logic controller 512 can output a first control signal CS_DACL with a target initialization voltage Vint value of V14 [V]. When the packet information PK has data 1111, the logic controller 512 can output a first control signal CS_DACL with a target initialization voltage Vint value of V15 [V]. The value of the target initialization voltage Vint can increase as it approaches V15 [V] from V0 [V].

[0091] Return to reference Figure 4 The level shifter 513 can receive the first control signal CS_DACL and output the second control signal CS_DACH.

[0092] In an embodiment, for example, the second control signal CS_DACH may be a pulse signal that oscillates between a gate high voltage and a gate low voltage. The second control signal CS_DACH may be set to a sufficient voltage level to turn on what will be later... Figure 10 The digital-to-analog converter (DAC) switching unit 514b described herein includes switches TR11 to TR164.

[0093] The DAC 514 can generate the target initialization voltage Vint based on the second control signal CS_DACH.

[0094] Reference Figure 9 and Figure 10 The DAC 514, buffer amplifier 515, initialization voltage switch 516, and voltage divider R can be mounted on the flexible film 130 connected to the display panel 100. However, this is for the sake of description, and the location of the voltage divider R according to the invention is not limited thereto. For example, the voltage divider R can be arranged on the first PCB 140 or the second PCB 160.

[0095] Voltage divider R divides the analog-formatted drive voltage AVDD and generates multiple initialization voltages (V0 to V15). The initialization voltages can be used to compensate for pixel initialization operations and threshold voltages.

[0096] The voltage divider R can be connected via 2 n One channel is connected to the input terminal of the DAC switching unit 514b, and can be connected via 2 n Each channel supplies a divided voltage V0 to V15 to the DAC switching unit 514b (see...). Figure 10 ).

[0097] In an embodiment, for example, a drive voltage AVDD can be applied to the first terminal of the voltage divider R, and a ground voltage can be applied to the second terminal of the voltage divider R. The voltage divider R may include two voltage dividers connected in series between the first and second terminals. n A voltage divider R may include a first resistor R1 to a sixteenth resistor R16 connected in series. The first resistor R1 to the sixteenth resistor R16 may be resistors with the same value. Therefore, the voltage divider R linearly generates multiple initial voltages (V0 to V15) by dividing the drive voltage AVDD using the first resistor R1 to the sixteenth resistor R16.

[0098] DAC 514 may include DAC controller 514a and DAC switching unit 514b.

[0099] The DAC controller 514a can receive a second control signal CS_DACH from the level shifter 513. The DAC controller 514a can convert the second control signal CS_DACH into an n-bit signal.

[0100] In an embodiment, for example, the DAC controller 514a may change the second control signal CS_DACH into a 4-bit signal. The 4-bit signal may include signals corresponding to... Figure 8 The fourth initialization control data VINT_D4, the third initialization control data VINT_D3, the second initialization control data VINT_D2, and the first initialization control data VINT_D1, shown as the (4_1) initialization voltage control data VINT_D4', (3_1) initialization voltage control data VINT_D3', (2_1) initialization voltage control data VINT_D2', and (1_1) initialization voltage control data VINT_D1', can be set to a sufficient voltage level to turn on. Figure 10 The DAC switching unit 514b shown includes switches TR11 to TR164.

[0101] The DAC switching unit 514b can be connected to the DAC controller 514a through n channels, and includes a configuration of 2 n Multiple switches TR11 to TR164 are arranged in a matrix form with n rows and n columns.

[0102] Multiple switches TR11 to TR164 can be configured using a combination of N-type and P-type transistors, and the N-type and P-type transistors can be arranged such that, in response to an n-bit signal provided from the DAC controller 514a, only 2 n All switches in any row of the row are turned on.

[0103] In an embodiment, for example, each of the rows of a plurality of switches TR11 to TR164 arranged in a matrix may correspond to a value obtained by converting any one of the decimal numbers 0 to 15 into a binary number. "0" may be configured using a P-type transistor, and "1" may be configured using an N-type transistor.

[0104] Since the transistors in the first row, configured using the eleventh transistor TR11, the twelfth transistor TR12, the thirteenth transistor TR13, and the fourteenth transistor TR14, correspond to "0000" obtained by converting 0, represented as a decimal number, to a binary number, all transistors in the first row can be configured using P-type transistors. Since the transistors in the second row, configured using the twenty-first transistor TR21, the twenty-second transistor TR22, the twenty-third transistor TR23, and the twenty-fourth transistor TR24, correspond to "0001" obtained by converting 1, represented as a decimal number, the twenty-first transistor TR21, the twenty-second transistor TR22, and the twenty-third transistor TR23 can be configured using P-type transistors, and the twenty-fourth transistor TR24 can be configured using N-type transistors.

[0105] By applying the same rules to the other rows, the types of other transistors can be determined, and the other transistors can be arranged. Since the transistors in the last sixteenth row, configured using transistors TR161 (161), TR162 (162), TR163 (163), and TR164 (164), correspond to "1111" obtained by converting "15" (represented as a decimal number) to a binary number, the transistors in the sixteenth row can all be configured using N-type transistors.

[0106] When the 4-bit signal provided from the DAC controller 514a has the data “0000” in the order of initialization voltage control data VINT_D4' (4_1), VINT_D3' (3_1), VINT_D2' (2_1), and VINT_D1' (1_1), all the transistors in the first row configured using the eleventh transistor TR11, the twelfth transistor TR12, the thirteenth transistor TR13, and the fourteenth transistor TR14 are turned on. Therefore, the first initialization voltage Vint1, with a value of V0[V] connected to one terminal of the eleventh transistor TR11, can be provided to the non-inverting input terminal of the buffer amplifier 515. 0 can correspond to a logic low level, and 1 can correspond to a logic high level.

[0107] Since the transistors in rows 2 through 16 include at least one N-type transistor, at least one N-type transistor is turned off in response to the data "0000", and therefore, an electrical disconnection can occur. Accordingly, among the transistors in rows 1 through 16 arranged between the input and output terminals of the DAC switching unit 514b, only the transistors in the first row can be electrically connected.

[0108] The buffer amplifier 515 can be configured as an operational amplifier and has a negative feedback structure in which the non-inverting input terminal is connected to the output terminal of the DAC 514, and the output terminal and the inverting input terminal of the operational amplifier are connected to each other.

[0109] The buffer amplifier 515 can be connected to multiple sensing lines SSL via multiple initialization voltage switches 516.

[0110] Reference Figure 4 The buffer amplifier 515 may be installed at each of the opposite ends of the source driver 510. However, this is merely illustrative, and the number of buffer amplifiers 515 may be one, two, or more. For example, the number of buffer amplifiers 515 may be equal to the number of sensing lines SSLi to SSLm.

[0111] The buffer amplifier 515 can be connected to multiple sensing lines SSLi to SSLm via multiple initialization voltage switches 516. According to an embodiment of this disclosure, the output terminals of two buffer amplifiers 515 mounted at opposite ends of the source driver 510 can be electrically connected to each other via a line LL, and the line LL can be connected to the first terminal of a plurality of initialization voltage switches 516 corresponding to the multiple sensing lines SSLi to SSLm in a one-to-one manner. The first terminal of each of the initialization voltage switches 516 can be connected to the output terminal of the buffer amplifier 515 and the line LL, and the second terminal (i.e., the other terminal) of each of the initialization voltage switches 516 can be connected to one of the multiple sensing lines SSLi to SSLm.

[0112] Each of the initialization voltage switches 516, directly connected to the output terminals of two buffer amplifiers 515 mounted at opposite ends of the source driver 510, has its first terminal connected to the output terminal of an operational amplifier, and its second terminal (i.e., the other terminal) connected to the inverting input terminal of the operational amplifier. Therefore, when the initialization voltage switches 516 are turned on, the magnitude of the first initialization voltage Vint1 input to the non-inverting input terminal of the operational amplifier and the magnitude of the second initialization voltage Vint2 output to the output terminal of the operational amplifier remain substantially equal to each other. In other words, the target initialization voltage Vint output from the DAC 514 is maintained constant regardless of changes in the bonding resistance between the display panel 100 and the flexible film 130. The first initialization voltage Vint1 and the second initialization voltage Vint2 may be in analog format.

[0113] In the display device according to this disclosure, a reference voltage (or initialization voltage) is provided to the source driver in digital format to minimize variations in the reference voltage.

[0114] Furthermore, in the display device according to this disclosure, a reference voltage is provided from the source driver to the display panel via a buffer amplifier, so as to enable compensation for changes in the reference voltage.

[0115] Example embodiments have been disclosed herein, and although specific terminology has been used, it will be used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some cases, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: The display panel includes multiple pixels; The source driver outputs a target initialization voltage in analog format to the pixel via a sensing line; as well as A timing controller provides data control signals to the source driver, the data control signals including packet information associated with the target initialization voltage, wherein the packet information is in digital format, and The source driver includes: A digital-to-analog converter, which generates the target initialization voltage in the analog format based on the grouping information; An internal interface receives the data control signal and outputs the packet information included in the data control signal; and A logic controller is arranged between the internal interface and the digital-to-analog converter. The grouping information is configured using n-bit data. The internal interface provides the n-bit grouping information to the logic controller, which then generates a first control signal for controlling the digital-to-analog converter based on the n-bit grouping information. Where n is a natural number.

2. The display device according to claim 1, wherein, The source driver further includes a level shifter disposed between the logic controller and the digital-to-analog converter, and the level shifter boosts the first control signal into a second control signal capable of operating the digital-to-analog converter.

3. The display device according to claim 2, further comprising: A buffer amplifier is arranged between the sensing line and the digital-to-analog converter.

4. The display device according to claim 2, wherein, The digital-to-analog converter includes: The digital-to-analog converter controller converts the second control signal into an n-bit signal; and A digital-to-analog converter switching unit, connected to the digital-to-analog converter controller via n channels, and including a configuration of 2 n Multiple switches arranged in a matrix of n rows and n columns. Where n is a natural number.

5. The display device according to claim 4, further comprising a voltage divider, the voltage divider comprising two components connected in series between the first terminal and the second terminal. n A resistor, with an analog-formatted drive voltage applied to its first terminal and a ground voltage applied to its second terminal. in, The voltage divider outputs multiple divided voltages by dividing the driving voltage.

6. The display device according to claim 5, wherein, The voltage divider passes through 2 n One channel is connected to the digital-to-analog converter switching unit, and through the 2 n Each channel provides the voltage after voltage division to the digital-to-analog converter switching unit.

7. The display device according to claim 6, wherein, The multiple switches are configured using a combination of N-type and P-type transistors, and The N-type transistors and the P-type transistors are arranged such that, in response to the n-bit signal, only the 2 n All switches in one row of the row are turned on.

8. The display device according to claim 1, wherein, Each of the plurality of pixels is connected to a scan line, a data line, and a sensing control line, and Each of the plurality of pixels includes: The driving transistor includes a first electrode connected to a first power voltage line, a second electrode connected to the anode of a light-emitting device, and a gate electrode connected to a first node; The first transistor includes a first electrode connected to the data line, a second electrode connected to the first node, and a gate electrode connected to the scan line; The second transistor includes a first electrode connected to the sensing line, a second electrode connected to the anode of the light-emitting device, and a gate electrode connected to the sensing control line; and A capacitor is connected between the first node and the anode of the light-emitting device.

9. The display device according to claim 1, further comprising: A printed circuit board, wherein the timing controller is mounted on the printed circuit board, and A flexible membrane, on which the source driver is mounted. The display panel and the printed circuit board are connected to each other via the flexible film.

10. The display device according to claim 9, wherein, The flexible film is disposed in the form of a flip-chip film or a chip on plastic.

11. The display device according to claim 8, wherein, The data line receives a portion of the data signal. The data signal includes multiple line image data, and Each of the plurality of line image data includes line start data, configuration control data, pixel data, and horizontal blank time period data.

Images