A power device packaging method and a packaging frame

Abstract

The application discloses a power device packaging method, and provides a packaging frame for packaging a power MOS tube, the packaging frame comprising a metal pad, a first metal layer, a second metal layer, an insulating heat-conducting layer and three metal electrodes arranged at intervals, the insulating heat-conducting layer is annularly arranged at the periphery of the metal pad, the first metal layer and the second metal layer are symmetrically arranged at the two sides of the insulating heat-conducting layer, the first metal layer is connected with the second metal electrode, the second metal layer is connected with the first metal electrode, and the metal pad is connected with the third metal electrode; the drain electrode of the power MOS tube is welded with the metal pad, a metal evaporation process is carried out on the surface of the packaging frame, photolithography is carried out on the surface of the evaporated metal, part of the evaporated metal is removed to form a gate connecting line and a source connecting line on the packaging frame, and the surface of the packaging frame is wrapped with resin and molded to form a straight insertion type package of the power MOS tube, so that the repeated wire bonding process of a single chip is effectively avoided, and the packaging efficiency of the power MOS tube is improved.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor chip packaging technology, and particularly relates to a power device packaging method and packaging framework. Background Technology

[0002] Power electronic devices are evolving towards modularity and intelligence. The emergence of large-scale and very large-scale integrated circuits has led to increasingly higher integration levels in power electronic devices. Essentially, the number and density of assembled chips are also increasing, necessitating a reduction in the size of power electronic modules to further improve power density. Power devices primarily have three electrode terminals: drain, source, and gate. The source and gate are located on the front of the chip, while the drain is on the back. In actual packaging, the chip is soldered onto a copper-clad ceramic substrate, and the drain is led out through the substrate. The gate and source on the front are connected to the electrodes of the package via aluminum wires, and finally, a plastic package is added to the outside of the chip. Because the source and gate are connected to external electrodes via wire bonding, two issues arise: firstly, the wire bonding process itself can damage the chip, leading to a decrease in chip packaging yield; secondly, for high-current power chips, when operating in the high-power range, the metal leads are prone to burnout due to heat generated by the high current, causing device failure. Summary of the Invention

[0003] In view of this, the present invention provides a power device packaging method and packaging framework with a large metal coverage area, which avoids lead burn-out of the device under high current and improves packaging efficiency, in order to solve the above-mentioned technical problems. Specifically, the following technical solutions are adopted to achieve this.

[0004] This invention provides a power device packaging method, comprising the following steps:

[0005] A packaging frame for packaging a power MOSFET is provided. The packaging frame includes a metal pad, a first metal layer, a second metal layer, an insulating and thermally conductive layer, and three metal electrodes arranged at intervals. The insulating and thermally conductive layer is disposed around the metal pad. The first metal layer and the second metal layer are symmetrically disposed on both sides of the insulating and thermally conductive layer. The first metal layer is connected to the second metal electrode, the second metal layer is connected to the first metal electrode, and the metal pad is connected to the third metal electrode.

[0006] The drain of the power MOSFET is soldered to a metal pad, the source PAD of the power MOSFET is adjacent to the first metal layer, the gate PAD of the power MOSFET is adjacent to the second metal layer, and the cross-sectional area of ​​the power MOSFET is larger than the cross-sectional area of ​​the metal pad.

[0007] A metal evaporation process is performed on the surface of the packaging frame to form evaporated metal;

[0008] A layer of photoresist is coated onto the surface of the evaporated metal for photolithography. Part of the evaporated metal is removed to form gate connection lines and source connection lines on the packaging frame. The gate of the power MOSFET is connected to the first metal electrode through the gate connection line, and the source of the power MOSFET is connected to the second metal electrode through the source connection line.

[0009] The surface of the packaging frame is coated with resin and encapsulated to form a through-hole package for the power MOSFET.

[0010] As a further improvement to the above technical solution, multiple packaging frames are first connected in parallel, and multiple power MOSFETs are packaged at the same time. Multiple gate connection lines and source connection lines are formed by evaporation, and then multiple chips are separated by cutting.

[0011] As a further improvement to the above technical solution, the first metal layer and the second metal layer are made of aluminum or copper, and the insulating and thermally conductive layer is made of resin or thermally conductive adhesive.

[0012] As a further improvement to the above technical solution, the metal gasket is made of aluminum or copper, and the metal gasket is separated from the first metal layer and the second metal layer by the insulating and thermally conductive layer.

[0013] As a further improvement to the above technical solution, the cross-sectional area of ​​the gate PAD is smaller than that of the source PAD, the material of the evaporated metal is aluminum, and the thickness of the evaporated metal is 6-10μm.

[0014] As a further improvement to the above technical solution, wet corrosion is used to remove part of the evaporated metal.

[0015] Secondly, the present invention also provides a packaging frame, the packaging frame including a metal pad, a first metal layer, a second metal layer, an insulating and thermally conductive layer and three metal electrodes arranged at intervals, the insulating and thermally conductive layer being disposed around the metal pad, the first metal layer and the second metal layer being symmetrically disposed on both sides of the insulating and thermally conductive layer, the first metal layer being connected to the second metal electrode, the second metal layer being connected to the first metal electrode, and the metal pad being connected to the third metal electrode;

[0016] The metal pad is soldered to the drain of the power MOSFET, the source PAD of the power MOSFET is adjacent to the first metal layer, the gate PAD of the power MOSFET is adjacent to the second metal layer, the gate of the power MOSFET is connected to the first metal electrode through a gate connection line, and the source of the power MOSFET is connected to the second metal electrode through a source connection line.

[0017] As a further improvement to the above technical solution, the cross-sectional area of ​​the power MOSFET is larger than the cross-sectional area of ​​the metal pad.

[0018] As a further improvement to the above technical solution, the formation process of the gate connection line and the source connection line is as follows: a metal evaporation process is performed on the surface of the packaging frame to form evaporated metal, a layer of photoresist is coated on the surface of the evaporated metal for photolithography, and part of the evaporated metal is removed.

[0019] As a further improvement to the above technical solution, the surface of the packaging frame is coated with resin and encapsulated to form a through-hole package for the power MOSFET.

[0020] This invention provides a power device packaging method and packaging framework, which has the following advantages compared to the prior art:

[0021] By providing a packaging frame for packaging power MOSFETs, the packaging frame includes a metal pad, a first metal layer, a second metal layer, an insulating and thermally conductive layer, and three spaced metal electrodes. The insulating and thermally conductive layer is arranged around the metal pad, and the first and second metal layers are symmetrically arranged on both sides of the insulating and thermally conductive layer. The first metal layer is connected to the second metal electrode, the second metal layer is connected to the first metal electrode, and the metal pad is connected to the third metal electrode. The drain of the power MOSFET is soldered to the metal pad. A metal evaporation process is performed on the surface of the packaging frame to improve the contact between the electrodes of the power MOSFET and the packaging frame and reduce the resistivity. A layer of photoresist is coated on the evaporated metal surface for photolithography, and part of the evaporated metal is removed to form the gate connection line and source connection line on the packaging frame. This can improve the integration of the chip package and avoid the damage caused by wire bonding. The surface of the packaging frame is then encapsulated with resin to form a through-hole package of the power MOSFET. The use of metal evaporation, photolithography, and wet etching effectively avoids the repeated wire bonding process for a single chip, improving the packaging efficiency of the power MOSFET. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart of a power device packaging method provided in an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the packaging framework provided in an embodiment of the present invention;

[0025] Figure 3 This is a cross-sectional view of the encapsulation frame at AA' provided in an embodiment of the present invention;

[0026] Figure 4 This is a top view of the encapsulation frame at BB' provided in an embodiment of the present invention;

[0027] Figures 5 to 7 This is a process diagram of a power device packaging method provided in an embodiment of the present invention;

[0028] Figure 8 for Figure 5 Sectional view along AA';

[0029] Figure 9 This is a schematic diagram of a power device package provided for another embodiment of the present invention.

[0030] The symbols for the main components are explained below:

[0031] 10-Packaging frame; 11-Metal pad; 12-First metal layer; 13-Second metal layer; 14-Insulating and thermally conductive layer; 15-First metal electrode; 16-Second metal electrode; 17-Third metal electrode; 20-Source PAD; 30-Gate PAD; 40-Evaporated metal; 41-Gate connection line; 42-Source connection line; 50-Power MOSFET. Detailed Implementation

[0032] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0033] It should be noted that when an element is said to be "fixed" to another element, it can be directly on the other element or there may be an intervening element. When an element is said to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is said to be "directly" on another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0034] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0035] See Figure 1 , Figures 5 to 7 This invention provides a power device packaging method, comprising the following steps:

[0036] S1: A packaging frame 10 for packaging a power MOSFET is provided. The packaging frame 10 includes a metal pad 11, a first metal layer 12, a second metal layer 13, an insulating and thermally conductive layer 14, and three metal electrodes arranged at intervals. The insulating and thermally conductive layer 14 is disposed around the metal pad 11. The first metal layer 12 and the second metal layer 13 are symmetrically disposed on both sides of the insulating and thermally conductive layer 14. The first metal layer 12 is connected to the second metal electrode 15, the second metal layer 13 is connected to the first metal electrode 15, and the metal pad 11 is connected to the third metal electrode 17.

[0037] See Figure 2 and Figure 3In this embodiment, the power MOSFET 50 has three electrode terminals: drain, source, and gate. The power MOSFET is a field-effect transistor that uses an electric field to control a semiconductor through a metal gate separated by an oxide layer. When the power MOSFET 50 is turned on, a positive voltage is applied between the gate and source. The gate is insulated, so no gate current flows through it. However, the positive voltage on the gate pushes away holes in the P-region below it, attracting minority carriers (electrons) to the surface of the P-region below the gate. When the power MOSFET 50 is turned off, a positive power supply is applied between the drain and source, the gate-source voltage is zero, the PN junction formed between the P-base region and the N-drift region is reverse-biased, and no current flows between the drain and source. A package frame refers to the outer casing used to mount a semiconductor integrated circuit chip. It serves to house, fix, seal, and protect the chip, enhance its electrothermal performance, and establish connections between the chip's internal and external circuits. The chip's contacts are connected to the package's pins via wires. These pins can then be connected to other devices via wires on a printed circuit board or substrate. The package frame can be made of materials such as plastic, ceramic, glass, or metal, with copper being preferred. The first metal electrode 15 is the gate, the second metal electrode 16 is the source, and the third metal electrode 17 is the drain. The second metal electrode 16 is located between the first metal electrode 15 and the third metal electrode 17. The first metal layer 12 and the second metal layer 13 are symmetrically arranged about the metal pad 11. An insulating and thermally conductive layer 14 wraps around the metal pad 11, isolating it from the first metal layer 12 and the second metal layer 13. The insulating and thermally conductive layer 14 can be resin or thermally conductive adhesive, and the metal pad 11 can be aluminum or copper, thus improving the chip's thermal conductivity.

[0038] It should be noted that the first metal layer 12 and the second metal layer 13 are made of aluminum or copper, the insulating and thermally conductive layer 14 is made of resin or thermally conductive adhesive, and the metal pad 11 is made of aluminum or copper. The metal pad 11 is separated from the first metal layer 12 and the second metal layer 13 by the insulating and thermally conductive layer 14. The packaging process eliminates the need for wire bonding, thereby reducing damage to the power MOSFET 50 and improving the device's operational reliability.

[0039] S2: Solder the drain of the power MOSFET to the metal pad 11. The source PAD20 of the power MOSFET 50 is adjacent to the first metal layer 12, and the gate PAD30 of the power MOSFET 50 is adjacent to the second metal layer 13. The cross-sectional area of ​​the power MOSFET is larger than the cross-sectional area of ​​the metal pad 11.

[0040] See Figure 4 and Figure 5In this embodiment, before soldering, the chip electrodes are checked for integrity and damage, and the pads are inspected for defects and defects. Soldering is then performed by aligning the drain of the power MOSFET 50 with the metal pad. Solder is then applied to one solder joint on the pad to position the chip and prevent displacement. The chip is then positioned correctly and fixed to the pad on the metal pad to ensure proper placement and prevent displacement during soldering. The chip position is checked again, and then another pin is fixed. Solder is applied to the chip pin, and the soldering iron is swung back and forth to ensure successful soldering between the pin and the pad. Finally, excess solder is scraped off the pin, and the pin is checked for cold solder joints, short circuits, etc. The cross-sectional area of ​​the power MOSFET 50 is larger than the area of ​​the metal pad, which improves soldering accuracy.

[0041] S3: A metal evaporation process is performed on the surface of the packaging frame 10 to form evaporated metal 40;

[0042] See again Figure 5 and Figure 8 In this embodiment, wet etching is used to remove part of the evaporated metal 40. The cross-sectional area of ​​the gate PAD 30 is smaller than that of the source PAD 20. The evaporated metal 40 is made of aluminum and has a thickness of 6-10 μm. Metal evaporation typically involves heating the evaporation material to a high temperature, causing its atoms or molecules to gain sufficient energy to escape the material surface and evaporate into a vacuum as vapor atoms or molecules. These vapor atoms or molecules then travel in a straight line through space and, upon encountering the substrate to be deposited, deposit on the substrate surface to form a thin metal film. The aforementioned evaporation process evaporates a thick layer of aluminum onto the surface of the packaging frame, completely covering the surface. The evaporation process requires heating. When the temperature reaches a certain value, the vapor pressure of the evaporation source material reaches a certain level, allowing for effective evaporation and deposition. Different materials have different evaporation temperatures. Aluminum has an evaporation temperature of 1148℃, which allows for the formation of low-resistivity contact surfaces, facilitates photolithography, and is easy to hot-press, thereby improving the performance of the power MOSFET.

[0043] S4: Coat the surface of the evaporated metal 40 with a layer of photoresist and perform photolithography to remove part of the evaporated metal 40 to form the gate connection line 41 and the source connection line 42 located on the packaging frame 10. Connect the gate of the power MOS transistor to the first metal electrode 16 through the gate connection line 41, and connect the source of the power MOS transistor 50 to the second metal electrode 15 through the source connection line 42.

[0044] See Figure 6In this embodiment, a layer of photoresist is first coated on the surface of the evaporated metal, and then etched using photolithography. Afterward, wet etching is used to remove some of the aluminum, thereby forming good contact between the electrode of the power MOSFET 50 and the packaging frame. Gate connection lines and source connection lines are formed on the evaporated metal. The gate connection line connects the gate of the power MOSFET 50 to the first metal electrode 15, and the source connection line 42 connects the source of the power MOSFET 50 to the second metal electrode 16. The third metal electrode 17 is connected to the drain via a metal pad 11. This improves the integration of the chip package without increasing the chip size, thus reducing manufacturing costs.

[0045] S5: The surface of the packaging frame 10 is encapsulated with resin and plastic-sealed to form a through-hole package of the power MOSFET 50.

[0046] See Figure 7 and Figure 9 In this embodiment, multiple packaging frames 10 are first connected in parallel, and multiple power MOSFETs 50 are packaged simultaneously. Multiple gate connection lines 41 and source connection lines 42 are formed by evaporation. Then, the multiple chips are separated by dicing. This method employs metal evaporation, photolithography, and wet etching, and allows for batch processing. Multiple packaging frames are connected in parallel, creating packaging frames for multiple chips, followed by evaporation and electrode formation. This effectively avoids the repeated wire bonding process for individual chips. After the gate and source connection lines are formed, multiple chips can be separated by dicing. This method has a wide range of applications, simplifies the packaging process, and improves the packaging efficiency of the power MOSFETs 50.

[0047] See again Figure 2 , Figure 3 and Figure 4In one feasible embodiment, the present invention also provides a packaging frame 10, the packaging frame 10 including a metal pad 11, a first metal layer 12, a second metal layer 13, an insulating and thermally conductive layer 14, and three metal electrodes arranged at intervals. The insulating and thermally conductive layer 14 is disposed around the metal pad 11. The first metal layer 12 and the second metal layer 13 are symmetrically disposed on both sides of the insulating and thermally conductive layer 14. The first metal layer 12 is connected to the second metal electrode 16, the second metal layer 13 is connected to the first metal electrode 15, and the metal pad 11 is connected to the third metal electrode 17. The metal pad 11 is soldered to the drain of a power MOSFET 50. The source PAD 20 of the power MOSFET 50 is adjacent to the first metal layer 12, the gate PAD 30 of the power MOSFET 50 is adjacent to the second metal layer 13, the gate of the power MOSFET 50 is connected to the first metal electrode 15 through a gate connection line 41, and the source of the power MOSFET 50 is connected to the second metal electrode 16 through a source connection line 42. The cross-sectional area of ​​the power MOSFET 50 is larger than the cross-sectional area of ​​the metal pad 11. The formation process of the gate connection line 41 and the source connection line 42 is as follows: a metal evaporation process is performed on the surface of the packaging frame 10 to form evaporated metal 40, a layer of photoresist is coated on the surface of the evaporated metal 40 for photolithography, part of the evaporated metal 40 is removed, and the surface of the packaging frame 10 is encapsulated with resin and plastic-sealed to form a through-hole package of the power MOSFET 50.

[0048] This invention provides a power device packaging method and packaging frame. A packaging frame 10 for packaging a power MOSFET 50 is provided. The packaging frame 10 includes a metal pad 11, a first metal layer 12, a second metal layer 13, an insulating and thermally conductive layer 14, and three spaced-apart metal electrodes. The insulating and thermally conductive layer 14 is arranged around the metal pad 11. The first metal layer 12 and the second metal layer 13 are symmetrically arranged on both sides of the insulating and thermally conductive layer 14. The first metal layer 12 is connected to the second metal electrode 16, the second metal layer 13 is connected to the first metal electrode 15, and the metal pad 11 is connected to the third metal electrode 17. The drain of the power MOSFET 50 is soldered to the metal pad 11. A metal evaporation process is performed on the surface of the packaging frame 10 to improve the contact between the electrodes of the power MOSFET 50 and the packaging frame, thereby reducing resistivity. A layer of photoresist is coated on the surface of the evaporated metal for photolithography. Part of the evaporated metal 40 is removed to form gate connection lines and source connection lines on the packaging frame. This can improve the integration of the chip package and avoid damage caused by wire bonding. The surface of the packaging frame is then wrapped with resin and plastic-encapsulated to form a through-hole package of the power MOSFET 50. The use of metal evaporation process, photolithography and wet etching effectively avoids repeated wire bonding processes for a single chip and improves the packaging efficiency of the power MOSFET 50.

[0049] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.

[0050] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0051] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A method for packaging a power device, characterized in that, Includes the following steps: A packaging frame for packaging a power MOSFET is provided. The packaging frame includes a metal pad, a first metal layer, a second metal layer, an insulating and thermally conductive layer, and three metal electrodes arranged at intervals. The insulating and thermally conductive layer is disposed around the metal pad. The first metal layer and the second metal layer are symmetrically disposed on both sides of the insulating and thermally conductive layer. The first metal layer is connected to the second metal electrode, the second metal layer is connected to the first metal electrode, and the metal pad is connected to the third metal electrode. The drain of the power MOSFET is soldered to a metal pad, the source PAD of the power MOSFET is adjacent to the first metal layer, the gate PAD of the power MOSFET is adjacent to the second metal layer, and the cross-sectional area of ​​the power MOSFET is larger than the cross-sectional area of ​​the metal pad. A metal evaporation process is performed on the surface of the packaging frame to form evaporated metal; A layer of photoresist is coated onto the surface of the evaporated metal for photolithography. Part of the evaporated metal is removed to form gate connection lines and source connection lines on the packaging frame. The gate of the power MOSFET is connected to the first metal electrode through the gate connection line, and the source of the power MOSFET is connected to the second metal electrode through the source connection line. The surface of the packaging frame is encapsulated with resin and then plastic-encapsulated to form a through-hole package for the power MOSFET. First, multiple packaging frames are connected in parallel, and multiple power MOSFETs are packaged simultaneously. Multiple gate connection lines and source connection lines are formed by evaporation. Then, multiple chips are separated by cutting. The cross-sectional area of ​​the gate PAD is smaller than that of the source PAD. The material of the evaporated metal is aluminum, and the thickness of the evaporated metal is 6-10μm. The material of the metal pad is aluminum or copper, and the metal pad is separated from the first metal layer and the second metal layer by the insulating and thermally conductive layer.

2. The power device packaging method according to claim 1, characterized in that, The first metal layer and the second metal layer are made of aluminum or copper, and the insulating and thermally conductive layer is made of resin or thermally conductive adhesive.

3. The power device packaging method according to claim 1, characterized in that, Wet etching was used to remove some of the evaporated metal.

4. An encapsulation framework, characterized in that, The encapsulation frame includes a metal pad, a first metal layer, a second metal layer, an insulating and thermally conductive layer, and three metal electrodes arranged at intervals. The insulating and thermally conductive layer is arranged around the metal pad. The first metal layer and the second metal layer are symmetrically arranged on both sides of the insulating and thermally conductive layer. The first metal layer is connected to the second metal electrode, the second metal layer is connected to the first metal electrode, and the metal pad is connected to the third metal electrode. The metal pad is soldered to the drain of the power MOSFET, the source PAD of the power MOSFET is adjacent to the first metal layer, the gate PAD of the power MOSFET is adjacent to the second metal layer, the gate of the power MOSFET is connected to the first metal electrode through a gate connection line, and the source of the power MOSFET is connected to the second metal electrode through a source connection line. The cross-sectional area of ​​the power MOSFET is larger than the cross-sectional area of ​​the metal pad.

5. The packaging frame according to claim 4, characterized in that, The formation process of the gate connection line and the source connection line is as follows: a metal evaporation process is performed on the surface of the packaging frame to form evaporated metal, a layer of photoresist is coated on the surface of the evaporated metal for photolithography, and part of the evaporated metal is removed.

6. The packaging frame according to claim 4, characterized in that, The surface of the packaging frame is coated with resin and encapsulated to form a through-hole package for the power MOSFET.

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