Substrate processing system

Abstract

The present invention provides a technique for improving the ease of transport control of substrates in a substrate processing system having both a batch processing section and a single-wafer processing section. The substrate processing system of the present invention has a substrate-in section, a batch processing section, a single-wafer processing section, an interface section, and a substrate-out section. The substrate-in section includes a first substrate placement section capable of placing a carrier that houses a plurality of substrates. The batch processing section processes a substrate group containing a plurality of substrates as a whole. The single-wafer processing section processes the substrates contained in the substrate group one by one. The interface section transfers the substrates one by one between the batch processing section and the single-wafer processing section. The substrate-out section includes a second substrate placement section capable of placing a carrier that houses the substrates processed by the single-wafer processing section. Furthermore, the substrate-in section, the batch processing section, the interface section, the single-wafer processing section, and the substrate-out section are arranged in this order.

Description

Technical Field

[0001] This invention relates to a substrate processing system. Background Technology

[0002] A substrate processing system has been known to include both a monolithic processing unit (monolithic processing unit) that processes substrates such as semiconductor wafers one by one, and a batch processing unit (batch processing unit) that processes multiple substrates at the same time.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2006-147779. Summary of the Invention

[0006] The problem the invention aims to solve

[0007] This invention provides a technique for improving the ease of substrate transport control in a substrate processing system that includes both a batch processing unit and a single-wafer processing unit.

[0008] Technical means for solving problems

[0009] One aspect of the substrate processing system of the present invention includes an input section, a batch processing section, a single-substrate processing section, an interface section, and a output section. The input section includes a first mounting section capable of mounting a carrier, which houses multiple substrates. The batch processing section processes substrate groups containing multiple substrates together. The single-substrate processing section processes each substrate in a substrate group individually. The interface section sequentially transfers substrates between the batch processing section and the single-substrate processing section. The output section includes a second mounting section capable of mounting a carrier, which houses the substrates processed by the single-substrate processing section. Furthermore, the input section, batch processing section, interface section, single-substrate processing section, and output section are arranged sequentially.

[0010] Invention Effects

[0011] According to the present invention, in a substrate processing system that includes both a batch processing unit and a single-chip processing unit, the ease of substrate transport control can be improved. Attached Figure Description

[0012] Figure 1 This is a block diagram showing the schematic structure of the substrate processing system according to the first embodiment.

[0013] Figure 2 This is a schematic plan view of the feed area, batch processing area, and IF area in the substrate processing system of the first embodiment.

[0014] Figure 3This is a schematic plan view of the IF region, single-chip processing region, and output region in the substrate processing system of the first embodiment.

[0015] Figure 4 This is a block diagram showing the structure of the etching treatment tank in the first embodiment.

[0016] Figure 5 This is a schematic diagram showing the structure of the liquid treatment unit in the first embodiment.

[0017] Figure 6 This is a schematic diagram showing the structure of the drying treatment unit in the first embodiment.

[0018] Figure 7 This is a flowchart showing the sequence of processes performed by the substrate processing system of the first embodiment.

[0019] Figure 8 This is a schematic plan view of the substrate processing system according to the second embodiment.

[0020] Figure 9 This is a schematic front view of the first mounting section in the second embodiment.

[0021] Figure 10 This is a schematic front view of the second mounting section in the second embodiment.

[0022] Figure 11 This is a schematic side view of the substrate processing system according to the third embodiment.

[0023] Figure 12 This is a schematic plan view of the single-piece processing area in the modified example.

[0024] Explanation of reference numerals in the attached figures

[0025] 1: Substrate Processing System

[0026] 2: Carrier feeding section

[0027] 3: Wafer assembly section

[0028] 4_1: Pre-processing unit

[0029] 4_2: Etching Processing Department

[0030] 4_3: Post-processing unit

[0031] 6: Liquid Treatment Department

[0032] 7: Drying Processing Department

[0033] 8: Fifth Conveying Mechanism

[0034] 11: Control device

[0035] 12: Control Department

[0036] 13: Storage Department

[0037] 20: First mounting section

[0038] 21: First conveying mechanism

[0039] 22, 23: Carrier Library

[0040] 24: Loading platform

[0041] 25: Seventh Conveying Mechanism

[0042] 30: Second conveying mechanism

[0043] 31: Chipset Holding Section

[0044] 40, 41, 43, 44, 47, 48: Processing tanks

[0045] 42, 45, 46, 49: Wafer set immersion mechanism

[0046] 50: Third conveying mechanism

[0047] 55: Fourth Conveying Mechanism

[0048] 91: Chip mounting stage

[0049] 92: Sixth Conveying Mechanism

[0050] 93: Second mounting section

[0051] 94: Platform

[0052] 95: Platform

[0053] 96: Platform

[0054] 97: Eighth Conveying Mechanism

[0055] A1: Input Area

[0056] A2: Batch processing area

[0057] A3: IF area

[0058] A4: Single-chip processing area

[0059] A5: Sending Area

[0060] A6: Carrier Conveying Area

[0061] C: Carrier

[0062] W: Chip Detailed Implementation

[0063] Hereinafter, with reference to the accompanying drawings, a detailed description will be provided of embodiments of the substrate processing system of the present invention (hereinafter referred to as "Embodiments"). However, the present invention is not limited to these embodiments. Furthermore, the embodiments can be appropriately combined without contradicting the processing content. In the following embodiments, the same reference numerals are used to label the same parts, and repeated descriptions are omitted.

[0064] Furthermore, in the embodiments shown below, expressions such as "certain," "orthogonal," "perpendicular," or "parallel" are sometimes used; however, these expressions are not strictly required to be "certain," "orthogonal," "perpendicular," or "parallel." That is, each of these expressions allows for deviations in manufacturing precision, setting precision, etc.

[0065] Furthermore, in the accompanying figures below, for ease of explanation, an orthogonal coordinate system is sometimes shown, with defined X-axis, Y-axis, and Z-axis directions that are orthogonal to each other, and the positive Z-axis direction being the vertically upward direction. Additionally, the direction of rotation about the vertical axis is referred to as the θ direction.

[0066] Patent Document 1 discloses a substrate processing system, which includes: a substrate feeding and feeding unit; a batch processing unit that processes multiple substrates at the same time; a single-substrate processing unit that processes substrates one by one; and a substrate transport mechanism.

[0067] In Patent Document 1, a conveying mechanism is configured in an area capable of accommodating a batch processing unit, and performs substrate feeding and discharging for the batch processing unit. Additionally, the conveying mechanism also feeds and discharging substrates in an area capable of accommodating multiple single-wafer processing units. Furthermore, the conveying mechanism also performs the processes of receiving unprocessed substrates from the feed-in / discharge unit or transferring processed substrates to the feed-in / discharge unit. In the substrate processing system described in Patent Document 1, conveying control can sometimes become complex. Therefore, a substrate processing system with simplified conveying control is desired.

[0068] (First Implementation)

[0069] <Structure of the Substrate Processing System>

[0070] First, refer to Figure 1 This section describes the general structure of the substrate processing system according to the first embodiment. Figure 1 This is a block diagram showing the general structure of the substrate processing system 1 according to the first embodiment.

[0071] like Figure 1 As shown, the substrate processing system 1 of the first embodiment has an input area A1, a batch processing area A2, an IF (interface) area A3, a single-chip processing area A4, and an output area A5. The input area A1, batch processing area A2, IF area A3, single-chip processing area A4, and output area A5 are arranged in this order.

[0072] In the substrate processing system 1 of the first embodiment, semiconductor wafers (hereinafter referred to simply as "wafers") are first fed into the delivery area A1. The delivery area A1 is provided with a first mounting section, etc., capable of holding a carrier, which houses multiple wafers. In the delivery area A1, processes are performed such as removing multiple wafers from the carrier placed in the first mounting section to form a wafer group, and transferring the formed wafer group to a batch processing area.

[0073] A batch processing unit is provided in batch processing area A2 to process wafers on a wafer-by-wafer-group basis. In the first embodiment, the batch processing unit performs wafer etching and other processes on a wafer-by-wafer-group basis in batch processing area A2. Additionally, a wafer-group transport mechanism is provided in batch processing area A2 to transport wafer-groups. The wafer-group transport mechanism transports wafer-groups formed in delivery area A1 to batch processing area A2.

[0074] In IF region A3, wafers are transferred from the batch processing region to the single-wafer processing region. An interface section for transporting wafers one by one is provided in IF region A3, and wafers are transported one by one from the batch processing region to the single-wafer processing region using this interface section.

[0075] A single-wafer processing area A4 is provided with a single-wafer processing unit that processes wafers one by one. In the first embodiment, a first single-wafer processing unit that receives wafers from the IF region and a second single-wafer processing unit that processes the wafers processed by the first single-wafer processing unit are provided in the single-wafer processing area A4.

[0076] Specifically, the first single-wafer processing unit is a liquid processing unit that forms a liquid film on the surface of a wafer. The second single-wafer processing unit consists of multiple drying processing units that bring the wafer with the liquid film formed on its surface into contact with a supercritical fluid to dry the wafer.

[0077] That is, in the substrate processing system 1 of the first embodiment, the wafers are etched in batch processing area A2 on a wafer-by-wafer-group basis, and then the wafers are dried one by one in single-wafer processing area A4.

[0078] The delivery area A5 is equipped with a second mounting section, which has an empty carrier. In the delivery area A5, a process is performed where wafers that have completed the drying process in the single-wafer processing area A4 are placed in the carrier of the second mounting section.

[0079] As described above, in the substrate processing system 1 of the first embodiment, the interface section provided in the IF region A3 is used to transport wafers from the batch processing region A2 to the single-wafer processing region A4. Therefore, the wafer pack transport mechanism does not need to transport wafers to the single-wafer processing region A4.

[0080] Furthermore, in the substrate processing system 1 of the first embodiment, a feed area A1 is arranged at one end of the arrangement direction of each area A1 to A5, and a delivery area A5 is arranged at the other end. In this substrate processing system 1, the wafer is transported in one direction from the feed area A1 to the delivery area A5. Therefore, the wafer assembly transport mechanism, for example, does not need to transport wafers that have been processed in the single-wafer processing area A4, that is, wafers that have completed the drying process.

[0081] Therefore, the substrate processing system 1 according to the first embodiment can improve the ease of wafer transport control.

[0082] Next, refer to Figure 2 and Figure 3 This section describes the specific structure of the substrate processing system 1 in the first embodiment. Figure 2 This is a schematic plan view of the feed area, batch processing area, and IF area in the substrate processing system 1 of the first embodiment. Additionally, Figure 3 This is a schematic plan view of the IF region, single-chip processing region and output region in the substrate processing system 1 of the first embodiment.

[0083] First, refer to Figure 2 This describes the structure of the input area A1, the batch processing area A2, and the IF area A3.

[0084] (Regarding delivery to area A1)

[0085] like Figure 2 As shown, a carrier feeding section 2 and a wafer assembly forming section 3 are arranged in the feeding area A1. The carrier feeding section 2 and the wafer assembly forming section 3 are arranged along the arrangement direction (X-axis direction) of areas A1 to A5. In addition, the wafer assembly forming section 3 is adjacent to the batch processing area A2.

[0086] The carrier feeding section 2 has a first placement section 20, a first conveying mechanism 21, carrier magazines 22 and 23, and a carrier placement platform 24.

[0087] Multiple carriers C, transported from the outside, are placed in the first placement section 20. Each carrier C is a container that holds multiple (e.g., 25) wafers W arranged vertically in a horizontal orientation. The first transport mechanism 21 transports the carriers C between the first placement section 20, the carrier libraries 22 and 23, and the carrier placement stage 24.

[0088] The wafer assembly forming unit 3 includes a second transport mechanism 30 and multiple (e.g., two) wafer assembly holding units 31, forming a wafer assembly composed of multiple wafers W. In the first embodiment, the wafer assembly is formed by combining a total of 50 wafers W housed in two carriers C. The multiple wafers W forming a substrate assembly are arranged at a certain interval with their wafer surfaces facing each other. Furthermore, the number of wafers W constituting the wafer assembly is not limited to 50. For example, the wafer assembly may also consist of 100 wafers W.

[0089] The second transport mechanism 30 transports multiple wafers W between the carrier C, which is placed on the carrier stage 24, and the wafer group holding part 31. The second transport mechanism 30 is, for example, composed of a multi-joint robotic arm, and transports multiple (e.g., 25) wafers W at the same time. In addition, the second transport mechanism 30 is capable of changing the posture of the multiple wafers W from a horizontal posture to a vertical posture during transport.

[0090] The wafer set holding section 31 holds multiple wafers W of a wafer set in a vertical position. The second transport mechanism 30 removes multiple wafers W from the carrier C placed on the carrier stage 24 and places them in the wafer set holding section 31 in a vertical position. For example, by repeating this operation twice, a wafer set is formed.

[0091] (Regarding batch processing area A2)

[0092] The batch processing area A2 is equipped with a pre-processing unit 4_1, multiple (in this case, two) etching processing units 4_2, and a post-processing unit 4_3. The pre-processing unit 4_1, the multiple etching processing units 4_2, and the post-processing unit 4_3 are examples of batch processing units.

[0093] The pre-processing unit 4_1, multiple etching processing units 4_2, and post-processing unit 4_3 are arranged sequentially along the arrangement direction (X-axis direction) of regions A1 to A5. In addition, the pre-processing unit 4_1 is adjacent to the feeding region A1, and the post-processing unit 4_3 is adjacent to the IF region A3.

[0094] The pre-processing unit 4_1 includes a pre-processing tank 40, a rinsing tank 41, and a wafer assembly immersion mechanism 42.

[0095] Processing tanks 40 and 41 are capable of accommodating wafers W arranged in a vertical orientation. Processing tank 40 contains a pretreatment solution. For example, DHF (diluted fluoride) is stored in processing tank 40 as a pretreatment solution for removing natural oxide film. Additionally, processing tank 41 contains a rinsing solution (e.g., deionized water).

[0096] The wafer assembly immersion mechanism 42 holds multiple wafers W forming a wafer assembly in a vertical position. The wafer assembly immersion mechanism 42 has a lifting mechanism that raises and lowers the held wafer assembly, allowing it to descend from above the processing tanks 40 and 41 for immersion, or to rise from the processing tanks 40 and 41 for removal. Additionally, the wafer assembly immersion mechanism 42 has a horizontal movement mechanism that allows the wafer assembly to move horizontally between a position above the processing tank 40 and a position above the processing tank 41.

[0097] Furthermore, this example illustrates a case where the pretreatment tank 40 is positioned on the positive X-axis side of the rinsing tank 41. However, the pretreatment tank 40 may also be positioned on the negative X-axis side of the rinsing tank 41.

[0098] The etching processing unit 4_2 has an etching processing tank 43, a rinsing processing tank 44, and wafer assembly immersion mechanisms 45 and 46.

[0099] Processing tanks 43 and 44 are capable of accommodating wafers W arranged in a vertical orientation. Processing tank 43 contains an etching solution (hereinafter also referred to as "etching solution"). Details of processing tank 43 will be described later. Processing tank 44 contains a rinsing solution (e.g., deionized water).

[0100] The wafer assembly immersion mechanisms 45 and 46 hold multiple wafers W forming a wafer assembly in a vertical orientation. The wafer assembly immersion mechanism 45 has a lifting mechanism for raising and lowering the held wafer assembly, causing it to descend from above the processing tank 43 for immersion in the processing tank 43, or raising the wafer assembly immersed in the processing tank 43 for removal from the processing tank 43. Similarly, the wafer assembly immersion mechanism 46 also has a lifting mechanism for raising and lowering the held wafer assembly, causing it to descend from above the processing tank 44 for immersion in the processing tank 44, or raising the wafer assembly immersed in the processing tank 44 for removal from the processing tank 44.

[0101] Furthermore, this example illustrates a case where the etching processing tank 43 is positioned on the positive X-axis side of the rinsing processing tank 44. However, the etching processing tank 43 may also be positioned on the negative X-axis side of the rinsing processing tank 44.

[0102] The post-processing unit 4_3 includes a post-processing tank 47, a rinsing tank 48, and a wafer assembly immersion mechanism 49.

[0103] Processing tanks 47 and 48 are capable of accommodating wafers W arranged in a vertical orientation. Processing tank 47 contains a post-processing solution. For example, processing tank 40 contains SC1 (a mixture of ammonia, hydrogen peroxide, and water), which serves as a cleaning solution in post-processing. Additionally, processing tank 48 contains a rinsing solution (e.g., deionized water). This rinsing processing tank 48 is adjacent to IF region A3.

[0104] The wafer assembly immersion mechanism 49 holds multiple wafers W forming a wafer assembly in a vertical orientation. The wafer assembly immersion mechanism 49 has a lifting mechanism that raises and lowers the held wafer assembly, immersing it in the processing tanks 47 and 48, or raising the wafer assembly immersed in the processing tanks 47 and 48 to remove it. Additionally, the wafer assembly immersion mechanism 49 has a horizontal movement mechanism that allows the wafer assembly to move horizontally between a position above the processing tank 47 and a position above the processing tank 48.

[0105] This example illustrates a configuration of four batch processing units (pre-processing unit 4_1, multiple etching processing units 4_2, and post-processing unit 4_3) in batch processing area A2. However, the number of batch processing units is not limited to this example; for instance, it could be one.

[0106] (Regarding the third conveyor mechanism 50)

[0107] The substrate processing system 1 has a third transport mechanism 50 (an example of a wafer assembly transport mechanism). The third transport mechanism 50 is configured to span the input area A1 and the batch processing area A2, and transports wafer assemblies from the input area A1 to the batch processing area A2.

[0108] The third transport mechanism 50 includes a holding body 51, a guide rail 52, and a moving body 53. The holding body 51 holds a wafer group with multiple wafers W in a vertical position. The guide rail 52 extends along the X-axis from the wafer group holding section 31 in the feed area A1 to the processing slot 48 in the batch processing area A2. The moving body 53 is disposed on the guide rail 52, allowing the holding body 51 to move along the guide rail 52.

[0109] The third transport mechanism 50 uses a holder 51 to hold the wafer set held by the wafer set holder 31 and transports the held wafer set to the batch processing area A2. Then, the third transport mechanism 50 transports the wafer set in the order of preprocessing unit 4_1, etching unit 4_2 and postprocessing unit 4_3.

[0110] Here, refer to Figure 4 This indicates the etching treatment tank 43. Figure 4 This is a block diagram showing the structure of the etching processing tank 43 in the first embodiment.

[0111] In processing tank 43, a prescribed etching solution is used to selectively etch the silicon nitride film among the silicon nitride film (SiN) and silicon oxide film (SiO2) formed on wafer W. In this etching process, a solution formed by adding a silicon-containing (Si) compound to an aqueous phosphoric acid (H3PO4) solution to adjust the silicon concentration is used as the etching solution.

[0112] As a method for adjusting the silicon concentration in the etching solution, one can use a method of dissolving silicon by immersing a dummy substrate in an aqueous phosphoric acid solution (mixing), or a method of dissolving silicon-containing compounds such as colloidal silicon dioxide in an aqueous phosphoric acid solution. Alternatively, an aqueous solution containing a silicon compound can be added to the aqueous phosphoric acid solution to adjust the silicon concentration.

[0113] like Figure 4 As shown, the etching processing tank 43 has an inner tank 101 and an outer tank 102. The inner tank 101 is a box-shaped tank that is open at the top and stores etching solution inside. A wafer group formed by multiple wafers W is immersed in the inner tank 101. The outer tank 102 is open at the top and is disposed around the upper part of the inner tank 101. Etching solution overflowing from the inner tank 101 flows into the outer tank 102.

[0114] In addition, the processing tank 43 has a phosphoric acid aqueous solution supply unit 103, a silicon supply unit 104, and a DIW supply unit 105.

[0115] The phosphoric acid aqueous solution supply unit 103 includes a phosphoric acid aqueous solution supply source 131, a phosphoric acid aqueous solution supply line 132, and a flow regulator 133.

[0116] Phosphoric acid solution supply source 131 supplies phosphoric acid solution to concentrate phosphoric acid to the desired concentration. Phosphoric acid solution supply line 132 connects phosphoric acid solution supply source 131 and external tank 102, supplying phosphoric acid solution from phosphoric acid solution supply source 131 to external tank 102.

[0117] A flow regulator 133 is installed on the phosphoric acid aqueous solution supply line 132 to regulate the supply amount of phosphoric acid aqueous solution to the external tank 102. The flow regulator 133 consists of an on / off valve, a flow control valve, a flow meter, etc.

[0118] The silicon supply unit 104 includes a silicon supply source 141, a silicon supply line 142, and a flow regulator 143.

[0119] Silicon supply source 141 is a tank containing an aqueous solution of silicon-containing compound. Silicon supply line 142 connects silicon supply source 141 and outer tank 102, supplying the aqueous solution of silicon-containing compound from silicon supply source 141 to outer tank 102.

[0120] A flow regulator 143 is installed on the silicon supply line 142 to regulate the supply amount of the silicon-containing aqueous solution to the outer tank 102. The flow regulator 143 consists of an on / off valve, a flow control valve, a flow meter, etc. By regulating the supply amount of the silicon-containing aqueous solution through the flow regulator 143, the silicon concentration of the etching solution can be adjusted.

[0121] The DIW supply unit 105 includes a DIW supply source 151, a DIW supply line 152, and a flow regulator 153. The DIW supply unit 105 replenishes the water that has evaporated due to the heating of the etching solution, and thus supplies DIW (Deionized Water) to the outer tank 102.

[0122] The DIW supply line 152 connects the DIW supply source 151 and the outer tank 102, supplying DIW at a specified temperature from the DIW supply source 151 to the outer tank 102.

[0123] A flow regulator 153 is installed on the DIW supply line 152 to regulate the amount of DIW supplied to the outer tank 102. The flow regulator 153 consists of an on / off valve, a flow control valve, a flow meter, etc. By regulating the amount of DIW supplied through the flow regulator 153, the temperature, phosphoric acid concentration, and silicon concentration of the etching solution can be adjusted.

[0124] Additionally, the processing tank 43 has a circulation section 106. The circulation section 106 circulates the etching solution between the inner tank 101 and the outer tank 102. The circulation section 106 includes a circulation line 161, multiple processing solution supply nozzles 162, a filter 163, a heater 164, and a pump 165.

[0125] The circulation line 161 connects the outer tank 102 and the inner tank 101. One end of the circulation line 161 is connected to the outer tank 102, and the other end of the circulation line 161 is connected to a plurality of treatment fluid supply nozzles 162 disposed inside the inner tank 101.

[0126] A filter 163, a heater 164, and a pump 165 are arranged on a circulation line 161. The filter 163 removes impurities from the etching solution flowing in the circulation line 161. The heater 164 heats the etching solution flowing in the circulation line 161 to a temperature suitable for etching. The pump 165 delivers the etching solution from the outer tank 102 to the circulation line 161. The filter 163, heater 164, and pump 165 are arranged sequentially from the upstream side.

[0127] The circulation unit 106 delivers the etching solution from the outer tank 102 to the inner tank 101 via the circulation line 161 and multiple processing liquid supply nozzles 162. The etching solution delivered to the inner tank 101 overflows from the inner tank 101 and flows out again to the outer tank 102. In this way, the etching solution circulates between the inner tank 101 and the outer tank 102.

[0128] In addition, the circulation section 106 can also heat the etching solution through the heater 164 to make the etching solution boil.

[0129] (Regarding IF area A3)

[0130] A fourth transport mechanism 55 (an example of an interface section) is configured in IF region A3. The fourth transport mechanism 55 is, for example, composed of a multi-joint robotic arm, which transports the wafers W one by one. In addition, the fourth transport mechanism 55 is capable of changing the orientation of multiple wafers W from a vertical orientation to a horizontal orientation during transport.

[0131] The fourth conveying mechanism 55 takes out a wafer W from the wafer group immersed in the rinsing tank 48 of the post-processing unit 4_3, changes the orientation of the taken wafer W from vertical to horizontal, and then sends it into the liquid processing unit 6 of the single-wafer processing area A4, which will be described later.

[0132] (Regarding the single-chip processing area A4)

[0133] Next, refer to Figure 3 This describes the structure of the single-chip processing area A4 and the output area A5.

[0134] A liquid processing unit 6, a drying processing unit 7, and a fifth conveying mechanism 8 are arranged in the single-wafer processing area A4. The liquid processing unit 6 is an example of the first single-wafer processing unit, and the drying processing unit 7 is an example of the second single-wafer processing unit. In addition, the fifth conveying mechanism 8 is an example of a single-wafer conveying mechanism.

[0135] The liquid treatment unit 6, the drying treatment unit 7, and the fifth conveying mechanism 8 are arranged sequentially along a direction orthogonal to the arrangement direction of regions A1 to A5 (Y-axis direction). Specifically, the fifth conveying mechanism 8 is positioned in the center of the single-piece processing area A4, and the liquid treatment unit 6 is positioned on one side of the fifth conveying mechanism 8 in the Y-axis direction (here, the negative Y-axis side). Furthermore, the drying treatment unit 7 is positioned on the opposite side of the liquid treatment unit 6, separated from the fifth conveying mechanism 8.

[0136] The liquid treatment unit 6 performs liquid treatment on the wafer W transported by the fourth transport mechanism 55. Specifically, the liquid treatment unit 6 forms a liquid film of drying treatment liquid on the surface of the wafer W. The wafer W with the liquid film formed by the liquid treatment unit 6 is taken out of the liquid treatment unit 6 by the fifth transport mechanism 8 and transported to the drying treatment unit 7.

[0137] The fifth transport mechanism 8 has a holder for holding the wafer W. Furthermore, the fifth transport mechanism 8 is capable of moving horizontally and vertically, and rotating about a vertical axis, using the holder to transport the wafer W. Specifically, the fifth transport mechanism 8 transports the wafer W from the liquid processing unit 6 to the drying processing unit 7, and from the drying processing unit 7 to the wafer mounting stage 91 of the delivery area A5 (described later).

[0138] The drying process unit 7 performs supercritical drying on the wafer W on which a liquid film has been formed by the liquid processing unit 6. Specifically, the drying process unit 7 dries the wafer W by contacting the wafer W on which the liquid film has been formed with a supercritical processing fluid.

[0139] The drying processing unit 7 has a processing area 71 for supercritical drying and a transfer area 72 for transferring the wafer W between the fifth transport mechanism 8 and the processing area 71.

[0140] Furthermore, in the single-piece processing area A4, a supply unit 73 is arranged adjacent to the processing area 71 of the drying processing unit 7. The supply unit 73 supplies processing fluid to the processing area 71 of the drying processing unit 7. The supply unit 73 has a supply device assembly including a flow meter, a flow regulator, a back pressure valve, and a heater, and a housing for housing the supply device assembly. In the first embodiment, the supply unit 73 supplies CO2 as a processing fluid to the drying processing unit 7.

[0141] The liquid treatment unit 6 has an inlet 61 and an outlet 62 for a wafer W. The inlet 61 is located opposite the IF region A3, and the wafer W can be fed in via the fourth transport mechanism 55. The outlet 62 is located opposite the fifth transport mechanism 8 and is used to discharge the wafer W. As described above, by setting the inlet 61 and outlet 62 at different locations, the feeding and discharging of the wafer W relative to the liquid treatment unit 6 can be performed efficiently. Furthermore, the outlet 62 can be located opposite the junction region 72. In this case, the distance that the wafer W with the liquid film formed is transported from the liquid treatment unit 6 to the drying treatment unit 7 via the fifth transport mechanism 8 is minimized, thus suppressing the drying of the liquid film.

[0142] Here, the structure of the liquid treatment unit 6 and the drying treatment unit 7 will be explained. First, refer to... Figure 5 Explain the structure of the liquid treatment unit 6. Figure 5 This is a schematic diagram showing the structure of the liquid treatment unit 6 in the first embodiment.

[0143] like Figure 5As shown, the liquid treatment unit 6 holds the wafer W approximately horizontally by means of a rotating chuck 205 disposed within the outer chamber 203 forming the processing space, and rotates the wafer W by rotating the rotating chuck 205 about a vertical axis. Then, the liquid treatment unit 6 brings the nozzle arm 206 above the rotating wafer W and supplies a drying processing liquid, in this case, IPA (isopropyl alcohol), from the nozzle 261 provided at the front end of the nozzle arm 206.

[0144] Furthermore, in the liquid processing unit 6, a liquid supply path 251 is formed inside the rotary chuck 205. Then, the lower surface of the wafer W can be processed by the IPA supplied from the liquid supply path 251.

[0145] IPA is received by the outer chamber 203 and the inner cup 204 disposed within the outer chamber 203, and discharged from the drain port 231 at the bottom of the outer chamber 203 and the drain port 241 at the bottom of the inner cup 204. Furthermore, the atmosphere within the outer chamber 203 is discharged from the vent port 232 at the bottom of the outer chamber 203.

[0146] While rotating the rotary chuck 205, the liquid treatment unit 6 supplies IPA to the upper and lower surfaces of the wafer W. As a result, the DIW remaining on both sides of the wafer W is replaced with IPA. Afterwards, the liquid treatment unit 6 slowly stops the rotation of the rotary chuck 205.

[0147] Subsequently, with an IPA liquid film formed on its upper surface, the wafer W is transferred from the rotary chuck 205 to the fifth transport mechanism 8, and then conveyed out from the liquid processing unit 6 by the fifth transport mechanism 8. The liquid film formed on the wafer W prevents the liquid on the upper surface of the wafer W from evaporating (vaporizing) and causing pattern collapse during the transport of the wafer W from the liquid processing unit 6 to the drying processing unit 7.

[0148] Next, refer to Figure 6 Explain the structure of the drying treatment section 7. Figure 6 This is a schematic diagram showing the structure of the drying treatment unit 7 in the first embodiment.

[0149] like Figure 6 As shown, the drying processing unit 7 includes a main body 301, a holding plate 302, and a cover member 303. An opening 304 for feeding and discharging a wafer W is formed in the frame-shaped main body 301. The holding plate 302 holds the wafer W to be processed in a horizontal direction. The cover member 303 supports the holding plate 302 and seals the opening 304 when the wafer W is fed into the main body 301.

[0150] The main body 301 is a container with a processing space inside capable of accommodating a wafer W, and its walls are provided with supply ports 305 and 306 and discharge port 307. The supply ports 305, 306 and discharge port 307 are respectively connected to the supply flow path and discharge flow path for allowing supercritical fluid to flow in the drying processing unit 7.

[0151] The supply port 305 is connected to the side of the frame-shaped main body 301 opposite to the opening 304. Additionally, the supply port 306 is connected to the bottom surface of the main body 301. Furthermore, the discharge port 307 is connected to the lower side of the opening 304. Figure 6 The diagram shows two supply ports 305 and 306 and one discharge port 307, but the number of supply ports 305 and 306 and discharge port 307 is not particularly limited.

[0152] In addition, fluid supply terminals 308 and 309 and fluid discharge terminal 300 are provided inside the main body 301. Moreover, multiple supply ports are formed in the long side direction of the fluid supply terminals 308 and 309, and multiple discharge ports are formed in the long side direction of the fluid discharge terminal 300.

[0153] The fluid supply end 308 is connected to the supply port 305 and is disposed adjacent to the side opposite to the opening 304 inside the frame-shaped main body 301. In addition, a plurality of supply ports arranged in the fluid supply end 308 face the opening 304.

[0154] The fluid supply end 309 is connected to the supply port 306 and is located in the center of the bottom surface inside the frame-shaped main body 301. In addition, the multiple supply ports arranged in the fluid supply end 309 face upward.

[0155] The fluid discharge end 300 is connected to the discharge port 307, is located inside the frame-shaped main body 301, adjacent to the side of the opening 304, and is positioned below the opening 304. Furthermore, the plurality of discharge ports arranged in the fluid discharge end 300 face upwards.

[0156] Fluid supply terminals 308 and 309 supply supercritical fluid into the body 301. Additionally, fluid discharge terminal 300 guides the supercritical fluid within the body 301 to the outside of the body 301 and discharges it. Furthermore, the supercritical fluid discharged to the outside of the body 301 via fluid discharge terminal 300 includes IPA liquid dissolved from the surface of the wafer W into the supercritical state.

[0157] Within the drying process 7, the IPA liquid between the patterns formed on the wafer W comes into contact with a supercritical fluid under high pressure (e.g., 16 MPa), thereby gradually dissolving in the supercritical fluid and being gradually replaced between the patterns by the supercritical fluid. Finally, only the supercritical fluid fills the spaces between the patterns.

[0158] Then, after removing the IPA liquid between the patterns, the pressure inside the body 301 is reduced from a high-pressure state to atmospheric pressure. This causes the CO2 to change from a supercritical state to a gaseous state, and the spaces between the patterns are now filled only with gas. In this way, the IPA liquid between the patterns is removed, and the drying process of the wafer W is complete.

[0159] (Regarding the sending area A5)

[0160] A wafer mounting stage 91, a sixth transport mechanism 92, and a second mounting section 93 are arranged in the delivery area A5. The wafer mounting stage 91, the sixth transport mechanism 92, and the second mounting section 93 are arranged sequentially along the arrangement direction (X-axis direction) of areas A1 to A5. In addition, the wafer mounting stage 91 is arranged adjacent to the single-wafer processing area A4.

[0161] On the wafer mounting stage 91, the wafer W is mounted in a horizontal position. Both the fifth transport mechanism 8 and the sixth transport mechanism 92 are able to reach the wafer mounting stage 91.

[0162] The sixth transport mechanism 92 has a holder for holding the wafer W. Furthermore, the sixth transport mechanism 92 is capable of horizontal and vertical movement and rotation about a vertical axis, using the holder to transport the wafer W between the wafer stage 91 and the second mounting section 93. The second mounting section 93 can hold multiple carriers C.

[0163] (Regarding control device 11)

[0164] The substrate processing system 1 includes a control device 11. The control device 11 is, for example, a computer, and has a control unit 12 and a storage unit 13. The storage unit 13 stores programs for controlling various processes performed in the substrate processing system 1. The control unit 12 controls the operation of the substrate processing system 1 by reading and executing the programs recorded in the storage unit 13.

[0165] Furthermore, the program is stored in a computer-readable storage medium and can be installed from this storage medium into the storage unit 13 of the control device 11. Examples of computer-readable storage media include hard disks (HD), floppy disks (FD), optical disks (CD), magnetic disks (MO), and memory cards.

[0166] <Specific Actions of Substrate Processing System 1>

[0167] Next, refer to Figure 7Explain the processing steps performed by substrate processing system 1. Figure 7 This is a flowchart illustrating the processing steps performed by the substrate processing system 1 of the first embodiment. Figure 7 Each of the processes shown is executed under the control of the control unit 12.

[0168] like Figure 7 As shown, the substrate processing system 1 takes out multiple wafers W from each of the two carriers C via the second conveying mechanism 30, and forms a wafer group from the multiple (e.g., 25) wafers W stored in each carrier C (step S101).

[0169] Reference Figure 2 The process of step S101 is explained below. First, the first transport mechanism 21 removes the carrier C from the first placement section 20 and places it on the carrier placement stage 24. Then, the second transport mechanism 30 removes multiple wafers W from the carrier C placed on the carrier placement stage 24, changes the orientation of the removed multiple wafers W from a horizontal orientation to a vertical orientation, and places the multiple wafers W on the wafer group holding section 31. By repeating this operation twice, a wafer group is formed.

[0170] Next, the substrate processing system 1 performs preprocessing on the formed wafer assembly (step S102).

[0171] Specifically, the third transport mechanism 50 receives the wafer set from the wafer set holding section 31 and hands it over to the wafer set immersion mechanism 42 of the preprocessing section 4_1. Then, the wafer set immersion mechanism 42 immerses the received wafer set in the DHF stored in the processing tank 40. Afterwards, the wafer set immersion mechanism 42 removes the wafer set from the processing tank 40 and immerses it in the DIW stored in the processing tank 41. Thus, the DHF adhering to the wafer W is washed away by the DIW stored in the processing tank 41.

[0172] Next, the substrate processing system 1 performs an etching process on the wafer assembly processed by the preprocessing unit 4_1 (step S103).

[0173] Specifically, the third transport mechanism 50 receives the wafer set from the wafer set immersion mechanism 42 of the preprocessing unit 4_1 and transfers it to the wafer set immersion mechanism 45 of the etching processing unit 4_2. Then, the wafer set immersion mechanism 45 immerses the received wafer set in the etching solution stored in the processing tank 43. Afterwards, the wafer set immersion mechanism 45 removes the wafer set from the processing tank 43 and transfers it to the third transport mechanism 50. Next, the third transport mechanism 50 transfers the wafer set received from the wafer set immersion mechanism 45 to the wafer set immersion mechanism 46. Then, the wafer set immersion mechanism 46 immerses the received wafer set in the DIW stored in the processing tank 44. As a result, the etching solution adhering to the wafer W is washed away by the DIW stored in the processing tank 44.

[0174] Next, the substrate processing system 1 cleans the wafer assembly that has been processed by the etching processing unit 4_2 (step S104).

[0175] Specifically, the third transport mechanism 50 receives the wafer set from the wafer set immersion mechanism 46 and transfers it to the wafer set immersion mechanism 49 of the post-processing unit 4_3. Then, the wafer set immersion mechanism 49 immerses the received wafer set in the SC1 stored in the processing tank 47. Afterwards, the wafer set immersion mechanism 49 removes the wafer set from the processing tank 47 and immerses it in the DIW stored in the processing tank 48. Thus, the SC1 attached to the wafer W is washed away by the DIW stored in the processing tank 48.

[0176] Next, the substrate processing system 1 performs liquid film formation processing on the wafer W processed by the post-processing unit 4_3 (step S105). The liquid film formation processing is performed on a per-wafer W unit, not on a per-wafer-group basis.

[0177] Specifically, the fourth transport mechanism 55 removes a wafer W from the wafer set held in the wafer set immersion mechanism 49 inside the processing tank 48. Then, after the fourth transport mechanism 55 changes the wafer W from a vertical position to a horizontal position, it passes through the feed inlet 61 (see reference). Figure 3 The wafer W is transferred to the rotary chuck 205 inside the liquid handling unit 6 (see reference). Figure 5 ).

[0178] The liquid treatment unit 6 supplies IPA to the upper and lower surfaces of the wafer W while rotating the rotary chuck 205. As a result, the DIW remaining on both sides of the wafer W is replaced with IPA. Furthermore, a liquid film of IPA is formed on the upper surface of the wafer W.

[0179] Next, the substrate processing system 1 dries the wafer W after the liquid film formation process (step S106).

[0180] Specifically, the fifth conveying mechanism 8 retrieves the wafer W from the liquid treatment unit 6 via the outlet 62 and transfers the retrieved wafer W to the transfer area 72 (see reference). Figure 3 The retaining plate 302 (refer to) Figure 6 Next, the drying process 7 moves the holding plate 302 toward the processing area 71, and places the wafer W inside the body 301.

[0181] Next, the drying unit 7 supplies supercritical fluid into the main body 301. This causes the pressure within the main body 301 to rise from atmospheric pressure to a predetermined first pressure. Here, the first pressure is a pressure greater than or equal to the critical pressure (approximately 7.2 MPa) required for CO2, as a supercritical fluid, to reach a supercritical state, for example, around 16 MPa. Therefore, by supplying supercritical fluid into the main body 301, the supercritical fluid within the main body 301 undergoes a phase transition to a supercritical state. Then, the IPA on the wafer W begins to dissolve into this supercritical fluid in its supercritical state.

[0182] Subsequently, by reducing the pressure inside the body 301 from a high-pressure state to atmospheric pressure, the CO2 changes from a supercritical state to a gaseous state, and the spaces between the patterns are occupied solely by gas. In this way, the IPA liquid between the patterns is removed, and the drying process of the wafer W is completed.

[0183] Next, the substrate processing system 1 performs a delivery process (step S107) to house the dried wafer W into the carrier C.

[0184] Specifically, the drying process 7 moves the holding plate 302 to the transfer area 72, and the fifth transport mechanism 8 receives the dried wafer W from the holding plate 302. Next, the fifth transport mechanism 8 places the received wafer W onto the wafer mounting stage 91. Then, the sixth transport mechanism 92 removes the wafer W from the wafer mounting stage 91 and stores it in the carrier C placed in the second mounting section 93.

[0185] (Second Implementation)

[0186] Next, refer to Figures 8-10 The structure of the substrate processing system in the second embodiment is explained. Figure 8 This is a schematic plan view of the substrate processing system according to the second embodiment. Additionally, Figure 9 This is a schematic front view of the first mounting section in the second embodiment. Additionally, Figure 10 This is a schematic front view of the second mounting section according to the second embodiment. Furthermore, in Figure 8 Batch processing area A2 is omitted in the original text. The batch processing area A2 in the second embodiment has the same structure as the batch processing area A2 in the first embodiment.

[0187] like Figure 8 As shown, the substrate processing system 1A of the second embodiment has a carrier delivery section 2A in the delivery region A1. The carrier delivery section 2A has a first mounting section 20A. The first mounting section 20A is disposed adjacent to the wafer assembly forming section 3.

[0188] like Figure 9As shown, a plurality of mounting platforms 26, 27, and 28 and a seventh conveying mechanism 25 are provided in the first mounting section 20A. The plurality of mounting platforms 26, 27, and 28 are arranged on both sides of the seventh conveying mechanism 25. Figure 9 In the example shown, on the positive Y-axis side of the seventh conveyor mechanism 25, two platforms 28, one platform 27, and one platform 26 are arranged sequentially from bottom to top in the height direction (Z-axis direction). Additionally, in Figure 9 In the example shown, on the negative Y-axis side of the seventh conveyor 25, three mounting platforms 28 and one mounting platform 26 are arranged sequentially in the height direction from bottom to top.

[0189] The carrier C, which is transported from the outside, is placed on the mounting stage 26. The mounting stage 27 is adjacent to the feed inlet 27a leading to the wafer assembly forming section 3 and can hold the carrier C containing the wafer W to be sent into the wafer assembly forming section 3. The carrier C, which is to be sent into the wafer assembly forming section 3, is temporarily placed on the mounting stage 28, for example.

[0190] The seventh conveying mechanism 25 conveys the carrier C between multiple mounting platforms 26, 27, and 28. Specifically, the seventh conveying mechanism 25 includes: a guide rail 25a extending along the height direction (Z-axis direction); and a holder 25b holding the carrier C. The holder 25b is movable along the guide rail 25a.

[0191] The seventh transport mechanism 25 uses a holder 25b to hold the carrier C placed on the mounting stage 26 and transports it to the mounting stage 27 or the mounting stage 28. Multiple wafers W held in the carrier C on the mounting stage 27 are removed from the carrier C by the second transport mechanism 30 located in the wafer group forming section 3. The empty carrier C is transported by the seventh transport mechanism 25 to the mounting stage 26 or the mounting stage 28.

[0192] As described above, in the substrate processing system 1A of the second embodiment, the first mounting section 20A is disposed adjacent to the wafer assembly forming section 3, so that the proportion of the floor space occupied by the delivery area A1 in the cleanroom or the like can be kept small.

[0193] In addition, such as Figure 8 As shown, in the substrate processing system 1A of the second embodiment, an IF region A3 is arranged in the single-wafer processing region A4. Specifically, the fourth transport mechanism 55 of the IF region A3 is arranged adjacent to the liquid processing unit 6 in the single-wafer processing region A4.

[0194] Furthermore, in the substrate processing system 1A of the second embodiment, a second mounting section 93A of a delivery area A5 is arranged in the single-wafer processing area A4. In addition, the fourth conveying mechanism 55, the liquid processing section 6, and the second mounting section 93A are arranged sequentially along the X-axis direction.

[0195] like Figure 10 As shown, the second mounting section 93A is provided with multiple mounting platforms 94, 95, and 96 and an eighth conveying mechanism 97. The multiple mounting platforms 94, 95, and 96 are arranged on both sides of the eighth conveying mechanism 97. Figure 10 In the example shown, on the negative Y-axis side of the eighth conveyor mechanism 97, three mounting platforms 96 and one mounting platform 95 are arranged sequentially from bottom to top in the height direction (Z-axis direction). Additionally, in Figure 10 In the example shown, on the positive Y-axis side of the eighth conveyor mechanism 97, two mounting platforms 94 and one mounting platform 95 are arranged sequentially in the height direction from bottom to top.

[0196] The mounting stage 94 is adjacent to the outlet 94a from the monolithic processing area A4 and is capable of mounting a carrier C containing a wafer W to be shipped out from the monolithic processing area A4. An empty carrier C shipped from the outside is mounted on the mounting stage 95. An empty carrier C to be mounted on the mounting stage 96 is temporarily mounted, for example, before being mounted on the mounting stage 94.

[0197] The eighth conveying mechanism 97 conveys the carrier C between multiple mounting platforms 94, 95, and 96. Specifically, the eighth conveying mechanism 97 includes a guide rail 97a extending along the height direction (Z-axis direction) and a holder 97b holding the carrier C. The holder 97b is movable along the guide rail 97a.

[0198] The eighth transport mechanism 97 uses a holder 97b to hold the empty carrier C placed on the placement stage 95 and transports it to the placement stage 94 or the placement stage 96. The carrier C placed on the placement stage 94 contains the wafer W that has been processed by the fifth transport mechanism 8 located in the single-wafer processing area A4. The carrier C containing the processed wafer W is transported by the eighth transport mechanism 97 to the placement stage 95 or the placement stage 96.

[0199] As described above, in the substrate processing system 1A of the second embodiment, since the second mounting part 93A is arranged in the single-wafer processing area A4, the proportion of the floor space occupied by the substrate processing system 1A in the cleanroom and the like can be kept small.

[0200] (Third Implementation)

[0201] Next, refer to Figure 11 The structure of the substrate processing system in the third embodiment is described. Figure 11 This is a schematic side view of the substrate processing system according to the third embodiment.

[0202] like Figure 11As shown, the substrate processing system 1B of the third embodiment, in addition to the structure of the substrate processing system 1 of the second embodiment, also has a carrier transport area A6. The carrier transport area A6 is, for example, disposed above the feed area A1, the batch processing area A2, the IF area A3, the single-wafer processing area A4, and the output area A5.

[0203] A ninth conveying mechanism 500 (an example of a carrier conveying mechanism) is provided in the carrier conveying area A6. The ninth conveying mechanism 500 conveys the carrier C between the first mounting section 20A and the second mounting section 93A.

[0204] The ninth conveying mechanism 500 includes a holding body 501, a guide rail 502, and a moving part 503. The holding body 501 holds the carrier C. The guide rail 502 extends from a position above the first mounting part 20A to a position above the second mounting part 93A. The moving part 503 moves the holding body 501 along the guide rail 502.

[0205] In the third embodiment of the substrate processing system 1B, for example, an empty carrier C placed on a mounting stage 26 is transported from a first mounting section 20A to a second mounting section 93A using a ninth transport mechanism 500, and placed on a mounting stage 95 of the second mounting section 93A. The movement of the carrier C from the mounting stage 26 to the ninth transport mechanism 500 can be performed, for example, by a seventh transport mechanism 25, or by a dedicated transport mechanism (not shown). Similarly, the movement of the carrier C from the ninth transport mechanism 500 to the mounting stage 95 can be performed, for example, by an eighth transport mechanism 97, or by a dedicated transport mechanism (not shown). The processed wafer W is housed in the empty carrier C transported to the second mounting section 93A.

[0206] Furthermore, in the third embodiment of the substrate processing system 1B, a ninth transport mechanism 500 is used to transport a carrier C containing the processed wafer W from the second mounting section 93A to the first mounting section 20A, and place it on the mounting stage 26 of the first mounting section 20A. The carrier C placed on the mounting stage 26 is then sent outside the substrate processing system 1B.

[0207] According to this substrate processing system 1B, the first mounting section 20A and the second mounting section 93A can be arranged in different locations, and the location for external access to the substrate processing system 1B can be centralized in one place (e.g., the first mounting section 20A). Therefore, the convenience of the substrate processing system 1B can be improved.

[0208] (Other variations)

[0209] Figure 12 This is a schematic plan view of the single-chip processing area A4 in the modified example. For example... Figure 12As shown, a plurality of liquid treatment units 6, a plurality of drying treatment units 7 and a plurality of supply units 73 are arranged in the single-piece processing area A4.

[0210] One liquid treatment unit 6, one drying treatment unit 7, and one supply unit 73 are each arranged on the positive Y-axis side and the negative Y-axis side of the fifth conveying mechanism 8. In addition, the liquid treatment unit 6, the drying treatment unit 7, and the supply unit 73 are arranged along the X-axis direction and are arranged sequentially starting from the negative X-axis side.

[0211] Furthermore, the fourth transport mechanism 55 is positioned in the center of the IF region A3. This allows the fourth transport mechanism 55 to easily access the two liquid processing units 6. Additionally, the liquid processing unit 6 has an inlet / outlet 63 located opposite the fifth transport mechanism 8, through which the fourth transport mechanism 55 feeds the wafer W into the liquid processing unit 6.

[0212] As described above, multiple liquid processing units 6 and drying processing units 7 can be provided in the single-piece processing area A4. Alternatively, the liquid processing units 6 and drying processing units 7 can be arranged along the arrangement direction of areas A1 to A5.

[0213] In the above embodiments, the processing performed by the batch processing unit includes, for example, etching of the wafer W using an etching solution containing phosphoric acid, etc. However, the processing performed by the batch processing unit is not limited to the illustrated etching process. Furthermore, in the above embodiments, the processing performed by the single-wafer processing unit includes, for example, liquid film formation processing using a drying processing solution and drying processing using a supercritical fluid, but the processing performed by the single-wafer processing unit is not limited to the aforementioned liquid film formation and drying processes. For example, the processing performed by the single-wafer processing unit can use a processing solution such as a chemical solution, rinsing solution, or functional water to process the wafer W. Additionally, in the above embodiments, an example of drying processing being performed in a drying processing unit 7 other than the liquid processing unit 6 is given; however, for example, the wafer W can also be dried by rotating it at high speed in the liquid processing unit 6.

[0214] In the above embodiment, an example is shown where the input area A1, batch processing area A2, IF area A3, single-chip processing area A4, and output area A5 are arranged in a straight line. However, the arrangement of areas A1 to A5 does not necessarily have to be in a straight line. For example, the input area A1, batch processing area A2, IF area A3, single-chip processing area A4, and output area A5 can also be arranged in an L-shape or a U-shape.

[0215] As described above, the substrate processing system of the embodiments (for example, substrate processing systems 1, 1A, and 1B) includes a feeding section (for example, feeding area A1), a batch processing section (for example, preprocessing section 4_1, etching section 4_2, and post-processing section 4_3), a single-wafer processing section (for example, liquid processing section 6 and drying section 7), an interface section (for example, a fourth transport mechanism), and a delivery section (for example, delivery area A5). The feeding section includes a first mounting section (for example, first mounting section 20, 20A) capable of mounting a carrier (for example, a wafer W) containing multiple substrates (for example, a carrier C). The batch processing section processes substrate groups containing multiple substrates together. The single-wafer processing section processes each substrate contained in a substrate group individually. The interface section transfers substrates one by one between the batch processing section and the single-wafer processing section. The delivery unit includes a second mounting unit (for example, second mounting units 93 and 93A) capable of holding a carrier that houses the substrate processed by the single-chip processing unit. Furthermore, the input unit, batch processing unit, interface unit, single-chip processing unit, and delivery unit are arranged sequentially. Therefore, in a substrate processing system having both a batch processing unit and a single-chip processing unit, the ease of substrate transport control can be improved.

[0216] The substrate processing system of the embodiment may also include a wafer group transport mechanism for transporting substrate groups to the batch processing unit (for example, a third transport mechanism 50). In addition, the interface unit can remove one substrate contained in a substrate group that has been transported to and processed by the batch processing unit from the batch processing unit and transport it to the single-wafer processing unit.

[0217] The substrate processing system of the embodiment may have multiple batch processing units. These multiple batch processing units may include: a first batch processing unit (for example, an etching processing unit 4_2); and a second batch processing unit (for example, a post-processing unit 4_3) adjacent to the interface unit, which processes the substrate group processed by the first batch processing unit together. Alternatively, a wafer assembly transport mechanism may be able to remove the substrate group from the first batch processing unit and transport it to the second batch processing unit, and the interface unit may be able to remove a substrate from the second batch processing unit and transport that substrate to a single-wafer processing unit.

[0218] As described above, the wafer transport mechanism of this embodiment does not require transporting substrates from the batch processing unit to the single-wafer processing unit. Therefore, substrate transport control can be simplified.

[0219] The substrate processing system of the embodiment may have a single-wafer transport mechanism (for example, the fifth transport mechanism 8) capable of transporting the substrate processed by the single-wafer processing unit to the delivery unit.

[0220] The single-wafer processing unit may include: a substrate feeding inlet (for example, feeding inlet 61) located opposite to the interface unit; and a substrate discharging outlet (for example, discharging outlet 62) located opposite to the single-wafer transport mechanism. This allows for efficient feeding and discharging of wafers relative to the single-wafer processing unit.

[0221] The substrate processing system of this embodiment may also have multiple single-wafer processing units. These multiple single-wafer processing units may include: a first single-wafer processing unit (for example, a liquid processing unit 6), wherein the substrate is fed into the first single-wafer processing unit from an interface unit; and a second single-wafer processing unit (for example, a drying processing unit 7), which processes the substrate processed by the first single-wafer processing unit. In this case, a single-wafer transport mechanism may remove the substrate from the first single-wafer processing unit and transport it to the second single-wafer processing unit, and then remove the substrate from the second single-wafer processing unit and transport it to a delivery unit.

[0222] The substrate processing system of the embodiment may include a carrier transport mechanism (for example, a ninth transport mechanism 500) capable of transporting a carrier from a first mounting section to a second mounting section. Furthermore, the carrier transport mechanism can also transport a carrier containing substrates processed by the batch processing section and the single-wafer processing section from the second mounting section to the first mounting section. This improves the convenience of the substrate processing system.

[0223] The embodiments disclosed in this specification are illustrative in all respects and should not be considered limiting. In fact, the above embodiments can be implemented in various ways. Furthermore, the above embodiments can be omitted, substituted, or modified in various ways without departing from the appended claims and their spirit.

Claims

1. A substrate processing system, characterized in that, have: The feeding section includes a first mounting section capable of mounting a carrier, which houses multiple substrates; A batch processing unit that processes a substrate group containing multiple said substrates together; A single-chip processing unit processes each of the substrates contained in the substrate group individually; An interface section that sequentially connects the substrates between the batch processing section and the single-chip processing section; The delivery unit includes a second mounting unit capable of mounting a carrier that houses the substrate processed by the monolithic processing unit. and A carrier conveying mechanism that conveys the carrier from the first mounting section to the second mounting section. The infeed unit, the batch processing unit, the interface unit, the single-chip processing unit, and the outfeed unit are arranged in sequence. The carrier conveying mechanism is capable of conveying the carrier containing the substrate processed by the batch processing unit and the single-wafer processing unit from the second placement unit to the first placement unit.

2. The substrate processing system as described in claim 1, characterized in that: A substrate group transport mechanism is provided for transporting the substrate group to the batch processing unit. The interface unit is capable of taking out one of the substrates contained in the substrate group that has been transported to the batch processing unit by the substrate group transport mechanism and processed by the batch processing unit from the batch processing unit and transporting it to the single-wafer processing unit.

3. The substrate processing system as described in claim 2, characterized in that: It has multiple batch processing units, The plurality of said batch processing units include: First batch of processing departments; and The second batch processing unit, which is adjacent to the interface unit, processes the substrate group that has been processed by the first batch processing unit together. The substrate assembly conveying mechanism is capable of removing the substrate assembly from the first batch processing unit and conveying it to the second batch processing unit. The interface unit is capable of retrieving one of the substrates from the second batch processing unit and transporting the substrate to the single-chip processing unit.

4. The substrate processing system as described in any one of claims 1 to 3, characterized in that: It has a single-wafer conveying mechanism that can convey the substrate processed by the single-wafer processing unit to the delivery unit.

5. The substrate processing system as described in claim 4, characterized in that: The single-chip processing unit has: A feed inlet for feeding the substrate is located opposite the interface section; and An outlet for discharging the substrate is located at a position opposite to the single-piece conveying mechanism.

6. The substrate processing system as described in claim 5, characterized in that: It has multiple of the aforementioned single-chip processing units, The plurality of said single-chip processing units include: The first single-chip processing unit, wherein the substrate is fed into the first single-chip processing unit from the interface unit; and The second single-chip processing unit processes the substrate that has been processed by the first single-chip processing unit. The single-wafer conveying mechanism can remove the substrate from the first single-wafer processing unit and convey it to the second single-wafer processing unit, and then remove the substrate from the second single-wafer processing unit and convey it to the delivery unit.

7. The substrate processing system as described in claim 6, characterized in that: The second single-piece processing unit is disposed on the opposite side of the first single-piece processing unit, separated from the single-piece conveying mechanism.

8. The substrate processing system as described in claim 6, characterized in that: The first single-chip processing unit and the second single-chip processing unit are arranged along the arrangement direction of the feed unit, the batch processing unit, the interface unit, the single-chip processing unit and the output unit.

9. The substrate processing system as described in claim 6, characterized in that: The first single-piece processing unit is a liquid processing unit that forms a liquid film on the surface of the substrate. The second single-piece processing unit is a drying processing unit that dries the substrate by contacting it with a supercritical fluid, whereby the substrate on which a liquid film is formed is formed.

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