Method of manufacturing a semiconductor structure

Abstract

The application relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure, which comprises the following steps: forming a metal interconnection line on a semiconductor substrate; forming a first IMD layer above the metal interconnection line, patterning the first IMD layer to form a first half-via hole penetrating through the first IMD layer; forming a second IMD layer above the first IMD layer, patterning the second IMD layer to form a second half-via hole penetrating through the second IMD layer; wherein the position of the first half-via hole corresponds to the position of the second half-via hole, and the first half-via hole and the second half-via hole are communicated to form a via hole. By depositing twice IMD layers, the via hole can be formed through 2 times etching, so that the upper dimension of the via hole can be controlled, the reliability of the metal interconnection line and the IMD is improved, and the performance of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a preparation method of a semiconductor structure. BACKGROUND

[0002] With the line width of electronic integrated circuits gradually narrowing, the reliability is also gradually declining. In order to reduce the metal wiring resistance, low-resistance copper is currently used as a material to form the wiring, and when the damascene method is used to form a multi-layer wiring, the smaller the line width, the worse the reliability (TDDB) of the metal interconnection line and the inter-metal dielectric (IMD), which also becomes a limiting condition for the design of semiconductor elements, causing difficulties in design and process. SUMMARY

[0003] The present application at least partially solves the above technical problems in the related art. To this end, the present application provides a preparation method of a semiconductor structure to solve the problem of poor reliability of the metal interconnection line and the IMD.

[0004] To achieve the above-mentioned purpose, the first aspect of the present application provides a preparation method of a semiconductor structure, comprising the following steps:

[0005] providing a semiconductor substrate;

[0006] forming a first metal interconnection line on the semiconductor substrate;

[0007] forming a first IMD layer above the first metal interconnection line, patterning the first IMD layer to form a first semi-via penetrating through the first IMD layer;

[0008] forming a second IMD layer above the first IMD layer, patterning the second IMD layer to expose the top surface of the first metal interconnection line to form a second semi-via penetrating through the second IMD layer;

[0009] wherein the position of the first semi-via corresponds to the position of the second semi-via, and the first semi-via and the second semi-via are in communication to form a via;

[0010] forming a via contact in the via. BRIEF DESCRIPTION OF DRAWINGS

[0011] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments, and are not intended to limit the scope of the present application. Moreover, the same reference numerals are used throughout the various drawings to designate the same or similar parts. In the drawings:

[0012] Figure 1A top view of a via and a metal interconnect line in the prior art is shown.

[0013] Figure 2 A top view of a via and a metal interconnect line in one embodiment of the present application is shown.

[0014] Figure 3 A top view of a first half-via in one embodiment of the present application is shown.

[0015] Figure 4 A top view of a second IMD layer thick deposited on the first half-via is shown. Figure 3 A top view of a first mask plate used on the second IMD layer thick is shown.

[0016] Figure 5 A top view of a second mask plate used on the first mask plate is shown. Figure 4 A top view of the via formed after etching using the second mask plate is shown.

[0017] Figure 6 A top view of a via contact and a second metal interconnect line formed on the via is shown. Figure 5 A top view of a via contact and a second metal interconnect line formed on the via is shown.

[0018] Figure 7 A top view of a via contact and a second metal interconnect line formed on the via is shown. Figure 6 A top view of a via contact and a second metal interconnect line formed on the via is shown. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, the description is merely exemplary of the present disclosure, but not to be used to limit the scope of the present disclosure. Also, in the following description, the description of known structures and techniques will be omitted to avoid obscuring the concept of the present disclosure.

[0020] Various structural diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships among them shown in the drawings are merely exemplary, and can be varied in actual implementation due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0021] In the context of the present disclosure, when a layer / element is said to be located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0022] In the prior art, as shown in FIG. 1, a first metal interconnect line 10 is formed on a substrate 20. A first IMD layer 30 is deposited on the first metal interconnect line 10. A first mask plate 40 is used on the first IMD layer 30. A first half-via 50 is formed after etching using the first mask plate 40. A second IMD layer 60 is deposited on the first half-via 50. A second mask plate 70 is used on the second IMD layer 60. A via 80 is formed after etching using the second mask plate 70. A via contact 90 and a second metal interconnect line 100 are formed on the via 80. Figure 1As shown, in order to reduce the resistance of the contact hole in the semiconductor multi-layer metal interconnection line structure, the contact hole is usually made larger, and the line width between the metal interconnection lines 11' is continuously reduced. In a conventional preparation process, the edge of the metal interconnection line 11' and the edge of the contact hole 12' are kept consistent in design, but in the process preparation, due to continuous etching, the upper part of the contact hole 12' is always etched preferentially, resulting in the upper part of the contact hole 12' being oversized, deviating from the upper part size of the metal interconnection line 11', and causing the TDDB of the metal interconnection line 11' and the inter-metal dielectric to deteriorate, affecting the performance of the device.

[0023] To solve the above problems, please refer to Figure 2 The first aspect of the present application provides a semiconductor structure 100, comprising: a semiconductor substrate (not shown in the figure), a third IMD layer 10, a first metal interconnection line 11, a first inter-metal dielectric (IMD) layer 12, a second inter-metal dielectric (IMD) layer 13, a contact hole 14, and a second metal interconnection line 15.

[0024] The first metal interconnection line 11 is formed in the third IMD layer 10, and the top surface of the first metal interconnection line 11 is flush with the surface of the third IMD layer 10. The first IMD layer 12 and the second IMD layer 13 are stacked from bottom to top on the third IMD layer 10.

[0025] The semiconductor substrate can include a semiconductor material such as silicon, germanium, silicon-germanium, or a III-V semiconductor compound such as GaP, GaAs, GaSb, etc. In some embodiments, the semiconductor substrate can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0026] In addition, although not shown, the semiconductor substrate can include a conductive pattern. The conductive pattern can be a metal line, a contact, a conductive pad, etc., and can be a gate electrode of a transistor, a source / drain of a transistor, or a diode, but embodiments are not limited thereto.

[0027] It is noted that the first IMD layer 12 and the second IMD layer 13 can include low-k materials having a dielectric constant lower than that of silicon oxide (SiO2). For example, silicon oxide can have a dielectric constant of about 3.9 to about 4.5. The first IMD layer 12 and the second IMD layer 13 can have a dielectric constant of 3.5 or less. For example, the IMD layer 11 can have a dielectric constant of about 2.0 to about 3.5. In example embodiments, the first IMD layer 12 and the second IMD layer 13 can include silicon oxycarbide (SiCOH) containing carbon and hydrogen. For example, the first IMD layer 12 and the second IMD layer 13 can include about 10% to about 50% carbon. In some example embodiments, the first IMD layer 12 and the second IMD layer 13 can include fluorine-doped silicon oxide (F-SiO2), porous silicon oxide, or the like.

[0028] Further, the first IMD layer 12 is formed using a dielectric material having poor step coverage, and in particular, the dielectric material having poor step coverage is used when depositing the first IMD layer 12, so that the first semi-via does not need to be protected by another substance when depositing the second IMD layer 13 and dry etching the metal interconnection line, that is, the first semi-via does not need to be filled with a substance.

[0029] The via contact 14 penetrates the first IMD layer 12 and the second IMD layer 13 and contacts the first metal interconnection line 11, and the second metal interconnection line 15 penetrates the second IMD layer 13 and penetrates part of the first IMD layer 12, wherein the via contact 14, the first metal interconnection line 11, and the second metal interconnection line 15 each include a metal fill layer and a metal barrier layer covering the side surface and the bottom surface of the metal fill layer, and the metal fill layer can include at least one of aluminum, copper, tungsten, and cobalt. In example embodiments, the metal fill layer can include copper, and the metal barrier layer can include, for example, titanium, titanium nitride, tantalum, and tantalum nitride, or the like.

[0030] Further, continuing to refer to Figure 2 In the embodiment, the first etching stop layer 16 is arranged between the third IMD layer 10 and the first IMD layer 12, and the surface of the second IMD layer 13 is provided with the second etching stop layer 17, and in particular, the first etching stop layer 16 and the second etching stop layer 17 can be selected from materials having a high etching selectivity.

[0031] The following describes a method for manufacturing the semiconductor structure 100 in the embodiment.

[0032] The present application provides a method for manufacturing a semiconductor structure 100, including the following steps:

[0033] A semiconductor substrate is provided and placed in a reaction chamber. In this embodiment, the semiconductor substrate may include semiconductor materials such as silicon, germanium, silicon-germanium, or III-V semiconductor compounds such as GaP, GaAs, and GaSb. In some embodiments, the semiconductor substrate may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0034] When the semiconductor substrate is a silicon-based semiconductor substrate, it may include, for example, dangling bonded silicon atoms that are not bonded to oxygen ions. The operating characteristics of the transistor can be stabilized using a hydrogen annealing process, in which hydrogen atoms bond to the dangling bonded silicon atoms of the semiconductor substrate. In this case, hydrogen atoms can easily separate from silicon atoms, but boron can increase the binding energy between silicon and hydrogen atoms. Therefore, the variable hold time or charge hold time of the capacitor can be improved.

[0035] Next, as Figure 3 As shown, a third IMD layer 10 can be formed by a deposition process, and a first metal interconnect 11 can be formed within the third IMD layer 10 by a conventional damascene process. Next, a first etch stop layer 16 is deposited covering the top surface of the third IMD layer 10 and the first metal interconnect 11. Then, a first IMD layer 12 can be formed on the surface of the first etch stop layer 16 by depositing a low-k material with a dielectric constant lower than that of silicon oxide (SiO2). In an example embodiment, the first IMD layer 12 may be a silicon oxide (SiCOH) comprising carbon and hydrogen. For example, the first IMD layer 12 may include about 10% to about 50% carbon. In some example embodiments, the first IMD layer 12 may include fluorine-doped silicon oxide (F-SiO2) or porous silicon oxide. Finally, the first mask 18 is used to perform patterned etching on the first IMD layer 12, thereby forming a first half-via 19 that penetrates the first IMD layer 12 and part of the first etch stop layer 16; wherein, the etching process can be a dry etching process; at this time, the bottom size of the first half-via 19 formed is basically consistent with the via size formed by the conventional process;

[0036] Next, as Figure 4 As shown, a second IMD layer 13 is deposited on the first IMD layer 12, wherein the first IMD layer 12 is formed using a dielectric material with a step coverage difference.

[0037] It is worth mentioning that, compared with the traditional IMD layer thickness h, the thickness H of the first IMD layer 12 is at least half that of the traditional IMD layer thickness.

[0038] Next, as Figures 5-6As shown, the second mask 20 is used to pattern and etch the second IMD layer 13 to expose the top surface of the metal interconnect 11, so as to form a second half-via penetrating the second IMD layer 13. The second half-via corresponds to the first half-via 19 and is interconnected to form a via 21. At the same time, the second mask 20 is used to form wiring trenches 22 penetrating the second IMD layer 13 and part of the first IMD layer 12 in other areas of the second IMD layer 13.

[0039] At this time, the upper dimension of the second half via is smaller than the upper dimension of the first metal interconnect 11, which improves the problem of deterioration of the reliability (TDDB) between the metal interconnect 11 and the inter-metal dielectric (IMD), and improves the performance of the device.

[0040] Next, as Figure 7 As shown, a metal filler layer and a metal barrier layer are deposited in the via 21 and the metal wiring trench 22 using the conventional damascus inlay process, thereby forming a via contact 14 in the via 21 and a second metal interconnect 15 in the wiring trench 22.

[0041] Next, continue to refer to Figure 2 The planarization process was performed using a chemical mechanical planarization process, followed by the deposition of a second etch stop layer 17.

[0042] It is worth noting that in this embodiment, by depositing two IMD layers, the vias can be formed through two etching processes, which allows the upper size of the vias to be controlled, improving the problem of deterioration in the reliability (TDDB) of the metal interconnect 11 and improving the performance of the device.

[0043] The semiconductor structure in this embodiment can be a volatile memory device such as a DRAM device or an SRAM device, or a non-volatile memory device such as a flash memory device, a PRAM device, an MRAM device, or an RRAM device.

[0044] Furthermore, the semiconductor structure in this embodiment can be used in various chips.

[0045] Furthermore, chips with the aforementioned semiconductor structure can be used in various electronic devices, specifically smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.

[0046] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, it should be understood by those skilled in the art that the layers, regions, etc. of the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0047] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a semiconductor substrate; forming a first metal interconnection line on the semiconductor substrate; forming a first IMD layer above the first metal interconnection line, patterning the first IMD layer to form a first half-via through the first IMD layer; forming a second IMD layer above the first IMD layer, patterning the second IMD layer to expose a top surface of the first metal interconnection line to form a second half-via through the second IMD layer; wherein the first half-via is positioned corresponding to the position of the second half-via, and the first half-via and the second half-via are in communication to form a via; the upper dimension of the second half-via is smaller than the upper dimension of the first metal interconnection line; forming a via contact in the via. At the same time of forming the second half-via, a wiring slot through the second IMD layer and part of the first IMD layer is also formed, and at the same time of forming the via contact, a second metal interconnection line is formed in the wiring slot.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The thickness H of the first IMD layer is smaller than h / 2, wherein h is the thickness of the IMD layer required to be formed for forming the second metal interconnection line.

3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: Before forming the first IMD layer, the following steps are further included:

4. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: forming a first etching stop layer on the first metal interconnection line, wherein part of the first half-via is formed in the first etching stop layer. The first IMD layer is formed by using a low-k material with a dielectric constant lower than that of silicon oxide. After forming the via contact, the following steps are further included:

5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: planarization processing, and then forming a second etching stop layer on the second IMD layer.

6. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Before forming the first metal interconnection line, the following steps are further included: forming a third IMD layer on the semiconductor substrate; the first metal interconnection line is formed in the third IMD layer and is flush with the top surface of the third IMD layer.

7. The method of claim 1, wherein the semiconductor structure is formed by a method comprising: The step of patterning the first IMD layer comprises: patterning and etching the first IMD layer by using a first mask plate. The step of patterning the second IMD layer comprises:

8. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: patterning and etching the second IMD layer by using a second mask plate. ​ 9. The method of claim 1, wherein ​ ​

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