Semiconductor structure and method of forming the same
By expanding the lateral spacing of the target pattern in the second region within the semiconductor structure, the problem of poor device electrical performance is solved, the contact area and uniformity of the gate structure are optimized, the bridging risk is reduced, and the electrical performance is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2020-09-30
- Publication Date
- 2026-05-22
AI Technical Summary
In existing semiconductor structures, as the size of pattern features shrinks, the electrical performance of devices deteriorates, especially since gate structures are prone to bridging, affecting electrical performance.
In a semiconductor structure, by forming a side core layer and a sidewall layer on the sidewall of the first core layer in the second region, the lateral spacing of the target pattern in the second region is expanded, while ensuring that the lateral spacing of the target pattern in the first region remains unchanged, thereby optimizing the electrical performance.
It improves the electrical performance of the semiconductor structure, reduces the risk of bridging between gate structures, and enhances the contact area and uniformity of the gate plug.
Smart Images
Figure CN114334817B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] Photolithography is a commonly used patterning method and one of the most critical production technologies in semiconductor manufacturing. With the continuous miniaturization of semiconductor process nodes, self-aligned double patterning (SADP) has become a favored patterning method in recent years. This method can increase the density of patterns formed on the substrate and further reduce the pitch between adjacent patterns, thus enabling photolithography to overcome the limitations of photolithography resolution.
[0003] As the critical dimension (CD) of patterns continues to shrink, the self-aligned quadruple patterning (SAQP) method has emerged. The density of patterns formed on the substrate using the self-aligned dual patterning method is twice that of patterns formed using photolithography, achieving a minimum pitch of 1 / 2. Furthermore, the self-aligned quadruple patterning method, without altering current photolithography technology (i.e., keeping the photolithographic window size unchanged), achieves a density of patterns four times that of patterns formed using photolithography, achieving a minimum pitch of 1 / 4. This significantly increases the density of semiconductor integrated circuits, reduces the feature size of patterns, and ultimately improves device performance. Summary of the Invention
[0004] The problem addressed by the embodiments of this application is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance of the device.
[0005] To address the aforementioned problems, embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region, the first region surrounding the side portion of the second region, the substrate including a patterned material layer and a first core layer disposed on the patterned material layer; forming a side core layer on the sidewall of the first core layer in the second region, the first core layer and the side core layer serving as a second core layer; forming a sidewall layer on the sidewall of the first core layer and the second core layer; removing the first core layer and the second core layer; and etching the patterned material layer using the sidewall layer as a mask to form a target pattern.
[0006] Accordingly, this application also provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region, the first region surrounding the side of the second region; and target patterns, disposed on the substrate, with the extension direction of the target patterns perpendicular to the first region as the lateral direction, and the lateral spacing between the target patterns in the second region being greater than the lateral spacing between the target patterns in the first region.
[0007] Compared with the prior art, the technical solution of this application has the following advantages:
[0008] In the semiconductor structure formation method provided in this application embodiment, the first region surrounds the side of the second region, and a side core layer is formed on the sidewall of the first core layer of the second region. The first core layer and the side core layer of the second region II serve as the second core layer, with the lateral direction being parallel to the surface of the pattern material layer and perpendicular to the extension direction of the first core layer. The lateral dimension of the second core layer is larger than that of the first core layer. A sidewall layer is formed on the sidewall of the second core layer. Correspondingly, the lateral spacing between the sidewall layers of the second region is larger than the lateral spacing between the sidewall layers of the first region, thereby the lateral spacing of the target pattern in the second region is larger than the lateral spacing of the target pattern in the first region. In summary, this application embodiment, while ensuring that the lateral spacing of the target pattern in the first region remains unchanged, only expands the lateral spacing of the target pattern in the second region surrounded by the first region, which can meet the requirements of diverse lateral spacing of the target pattern and is beneficial to improving the electrical performance of the semiconductor structure.
[0009] In an optional embodiment, the formed target pattern includes a dummy gate structure, and the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer covering the sidewalls of the dummy gate structure and exposing the top of the dummy gate structure; removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer; forming a gate structure in the gate opening; and forming a gate plug on the gate structure in the second region. In this embodiment, the lateral spacing of the target pattern in the second region is large, so the lateral spacing between the gate plugs formed on the gate structure in the second region is far, and bridging between the gate plugs on the gate structure in the second region is less likely. In this embodiment, the lateral spacing between the gate structures in the second region is large, and correspondingly, the spacing between the gate structures in the first region and the gate structures in the second region is small. Because the first region surrounds the side of the second region, the area with a small lateral spacing between the gate structures in the first region and the gate structures in the second region is small. Only the lateral spacing between the gate structures that need to connect the gate plugs is increased, which helps to reduce the risk of bridging between the gate structures in the first region and the gate structures in the second region and optimizes the electrical performance of the semiconductor structure.
[0010] In an optional embodiment, the formed target pattern includes fins, and the method for forming the semiconductor structure further includes: forming a gate structure spanning the fins, the gate structure covering the top wall and part of the sidewall of the fins, wherein the lateral dimension of the gate structure between the fins in the second region is large, thereby etching the gate structure between the fins in the second region along the extension direction of the fins, and during the process of forming an opening that disconnects the gate structure in the second region, it is not easy to accidentally etch the fins, and the formation window of the opening is large, which is beneficial to improving the electrical performance of the semiconductor structure. Attached Figure Description
[0011] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0012] Figures 8 to 24 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of this application;
[0013] Figure 25 This is a schematic diagram of the semiconductor structure of this application. Detailed Implementation
[0014] The devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.
[0015] refer to Figures 1 to 7 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.
[0016] refer to Figure 1 A substrate is provided, the substrate including a substrate 1, an etch resist layer 2 on the substrate 1 and a pattern definition layer 3 on the etch resist layer 2.
[0017] Combination Figure 1 ,refer to Figures 2 to 5 After multiple doping and film formation steps, multiple doped layers 9 are sequentially formed in the pattern definition layer 3 (e.g., ...). Figure 5 As shown), the doping film formation step includes: forming a first mask layer 7 on the pattern definition layer 3; forming an opening 8 in the first mask layer 7 to expose the pattern definition layer 3; doping ions in the pattern definition layer 3 exposed by the opening 8 to form a doped layer 9; after forming the doped layer 9, removing the first mask layer 7; the etching resistance of the doped layer 9 is greater than that of the pattern definition layer 3.
[0018] The first mask layer 7 includes: an organic material layer 4, an anti-reflective coating 5 located on the organic material layer 4, and a first photoresist layer 6 located on the anti-reflective coating 5.
[0019] refer to Figure 6 After forming multiple doped layers 9, the pattern definition layer 3 is removed.
[0020] refer to Figure 7 The substrate 1 is etched using the doped layer 9 as a mask to form the target pattern 10.
[0021] Specifically, the target pattern 10 is a pseudo-gate structure, which is subsequently replaced with a gate structure. A gate plug is formed on the gate structure. During the formation of the gate plug, in order to ensure that the gate plug can make smooth contact with the top of the gate structure and to reduce the probability of bridging between adjacent gate plugs, the spacing between adjacent gate plugs is usually increased. In order to ensure that the gate plug can still be formed on the gate structure, the lateral dimension of the corresponding gate structure is increased. Consequently, the spacing between gate structures is smaller, which easily increases the risk of bridging between gate structures, resulting in poor electrical performance of the semiconductor structure.
[0022] To address the aforementioned technical problem, this application provides a method for forming a semiconductor structure, comprising: a first region surrounding the side of a second region; forming a side core layer on the sidewall of the first core layer of the second region; the first core layer and the side core layer of the second region II serving as a second core layer; the second core layer being lateral, parallel to the surface of the pattern material layer and perpendicular to the extension direction of the first core layer; the lateral dimension of the second core layer being larger than that of the first core layer; forming a sidewall layer on the sidewall of the second core layer; and correspondingly, the lateral spacing between the sidewall layers of the second region being larger than the lateral spacing between the sidewall layers of the first region, thereby resulting in a greater lateral spacing of the target pattern in the second region than that in the first region. In summary, this application, while ensuring that the lateral spacing of the target pattern in the first region remains unchanged, only expands the lateral spacing of the target pattern in the second region surrounded by the first region, which can meet the requirements of diverse lateral spacing of the target pattern and is beneficial to improving the electrical performance of the semiconductor structure.
[0023] To make the above-mentioned objectives, features and advantages of the embodiments of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0024] Figures 8 to 24 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to this application.
[0025] refer to Figures 8 to 11 , Figure 9 for Figure 8 The cross-sectional view at AA provides a base 100 (e.g.) Figure 11 As shown), the substrate 100 includes a first region I and a second region II, the first region I surrounding the side of the second region II. The substrate 100 includes a patterned material layer 101 and a first core layer 102 discretely disposed on the patterned material layer 101 (e.g., ...). Figure 11 (As shown).
[0026] The substrate 100 is prepared for the subsequent formation of the target pattern.
[0027] The extension direction parallel to the surface of the graphic material layer 101 and perpendicular to the first core layer 102 is lateral. The substrate 100 includes a first region I and a second region II. Both the first region I and the second region II are used to form target graphics. The first region I is used to form target graphics with high lateral spacing uniformity. The second region II is used to form target graphics with a greater lateral spacing than the target graphics in the first region I.
[0028] In subsequent processes, the graphic material layer 101 is graphically represented to form the target graphic.
[0029] In this embodiment, the target pattern serves as a pseudo-gate structure, occupying space for the subsequent formation of the gate structure. In other embodiments, the target pattern may also be a fin.
[0030] In this embodiment, the material of the patterned material layer 101 includes amorphous silicon. Amorphous silicon is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the patterned material layer 101.
[0031] The first core layer provides a process platform for the subsequent formation of the side core layer of 102.
[0032] Specifically, the material of the first core layer 102 includes one or more of the following: amorphous silicon, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the material of the first core layer 102 includes silicon. Silicon is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the first core layer 102.
[0033] It should be noted that, in the step of providing the substrate 100, an etch stop material layer 103 is formed between the pattern material layer 101 and the first core layer 102.
[0034] During the subsequent formation of a side core layer on the sidewall of the first core layer 102 in the second region II, the etch stop material layer 103 is used to protect the pattern material layer 101 from damage. The first core layer and the side core layer on its sidewall in the second region serve as the second core layer. Before etching the pattern material layer 101 using the second core layer as a mask, the etch stop material layer 103 will be etched first to form an etch stop layer. The second core layer and the etch stop layer together serve as the etch mask layer for the pattern material layer 101, forming the etch mask layer for the target pattern.
[0035] Specifically, the steps for providing substrate 100 include:
[0036] like Figure 8 and Figure 9 As shown, Figure 9 for Figure 8 In the cross-sectional view at AA, a graphic material layer 101 is provided; a second core material film 104 is formed on the graphic material layer 101.
[0037] The second core material film 104 prepares for the formation of the first core layer 102.
[0038] In this embodiment, the material of the second core material film 104 includes one or more of the following: amorphous silicon, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the material of the second core material film 104 includes silicon. Silicon is a commonly used and low-cost dielectric material with high process compatibility, which helps reduce the process difficulty and cost of forming the second core material film 104.
[0039] like Figure 10 As shown, the second core material film 104 is doped to form a core material layer 105.
[0040] The core material layer 105 is then patterned to form a first core layer 102. The second core material film 104 is doped to improve its etching resistance; that is, the etching resistance of the core material layer 105 is greater than that of the second core material film 104.
[0041] Specifically, in the step of doping the second core material film 104, the dopant ions include one or both of B and C. Dopant ions can increase the activation energy of silicon, and silicon with dopant ions is less prone to chemical reactions during etching, thus reducing the formation of reaction byproducts. Consequently, the etching resistance of the core material layer 105 is greater than that of the second core material film 104. In this embodiment, the dopant ions include B.
[0042] In this embodiment, the second core material film 104 is doped using an ion implantation process to form a core material layer 105. Ion implantation has the advantages of simple operation and low process cost.
[0043] like Figure 11 As shown, the core material layer 105 is graphically represented, and the remaining core material layer 105 serves as the first core layer 102.
[0044] In this embodiment, the core material layer 105 is patterned using a self-aligned double patterning (SADP), a self-aligned quadruple patterning (SAQP), or a self-aligned multiple patterning (SAMP) process to form the first core layer 102. Correspondingly, the lateral spacing between the first core layers 102 in the first region I and the lateral spacing between the first core layers 102 in the second region II are equal.
[0045] In other embodiments, a dry etching process is used to pattern the core material layer to form the first core layer. The dry etching process has anisotropic etching characteristics, providing good control over the etching profile, which helps ensure the morphology of the first core layer meets process requirements and also improves the removal efficiency of the core material layer. During the patterning of the core material layer using the dry etching process, the top of the etching stop material layer can be used as the etching stop position, reducing damage to the patterned material layer.
[0046] refer to Figures 12 to 20 A side core layer 106 is formed on the sidewall of the first core layer 102 in the second region II (e.g., Figure 19 As shown), the first core layer 102 and the side core layer 106 of the second region II serve as the second core layer 107.
[0047] The first region I surrounds the side of the second region II. A side core layer 106 is formed on the sidewall of the first core layer 102 in the second region II. The first core layer 102 and the side core layer 106 in the second region II serve as a second core layer 107, which is parallel to the surface of the pattern material layer 101 and extends laterally perpendicular to the direction of the first core layer 102. That is, the lateral dimension of the second core layer 107 is larger than the lateral dimension of the first core layer 102. Subsequently, a sidewall layer is formed on the sidewall of the second core layer 107. Correspondingly, the lateral spacing between the sidewall layers in the second region II is larger than the lateral spacing between the sidewall layers in the first region I. Thus, the lateral spacing of the target pattern in the second region II is larger than the lateral spacing of the target pattern in the first region I. In summary, this embodiment of the application, while ensuring that the lateral spacing of the target pattern in the first region I remains unchanged, only expands the lateral spacing of the target pattern in the second region II surrounded by the first region I, which can meet the requirements of diverse lateral spacing of the target pattern and is beneficial to improving the electrical performance of the semiconductor structure.
[0048] In this embodiment, the material of the side core layer 106 is the same as that of the first core layer 102. In the subsequent step of etching the pattern material layer 101 using the second core layer 107 as a mask, the side core layer 106 and the first core layer 102 in the second core layer 107 have the same etching resistance. The second core layer 107 can effectively function as an etching mask, which is beneficial for improving the formation quality of the target pattern.
[0049] In this embodiment, the material of the side core layer 106 includes: B-doped amorphous silicon.
[0050] It should be noted that in the step of forming the side core layer 106, the lateral dimension D1 of the side core layer 106 should not be too large or too small. If the lateral dimension D1 of the side core layer 106 is too large, it will require too much process time and materials to form the side core layer 106. Furthermore, if the lateral dimension D1 of the side core layer 106 is too large, the lateral distance between the second core layer 107 in the second region and the first core layer 102 in the first region will be too small. Subsequently, when etching the pattern material layer 101 using the first core layer 102 and the second core layer 107 as masks to form the target pattern, the reactant impurities generated during this process are prone to accumulate between the first core layer 102 and the second core layer 107. The first core layer 102 and the second core layer 107 cannot function as masks respectively, causing the target pattern in the first region I and the target pattern in the second region II to easily bridge together. In this embodiment, the target pattern is a pseudo-gate structure. Later, the pseudo-gate structure will be replaced with a gate structure. Consequently, the gate structure in the first region I and the gate structure in the second region II are prone to bridging, resulting in poor electrical performance of the semiconductor structure. If the lateral dimension D1 of the side core layer 106 is too small, the target pattern is subsequently formed by etching the pattern material layer 101 using the first core layer 102 and the second core layer 107 as masks. The lateral dimension of the target pattern in the second region II is small compared to that in the first region I. In this embodiment, the target pattern is a pseudo-gate structure, which is subsequently replaced with a gate structure. A gate plug is formed on the gate structure in the second region II. Compared with the lateral dimension of the gate structure in the first region I, the lateral dimension of the gate structure in the second region II is not significantly increased. While increasing the spacing between the gate plugs, the contact area between the gate plug and the gate structure in the second region II is too small, or the gate plug does not contact the gate structure in the second region II, resulting in poor electrical performance of the semiconductor structure. In this embodiment, in the step of forming the side core layer 106 with the sidewall perpendicular to the core layer as the lateral dimension, the lateral dimension D1 of the side core layer 106 (e.g., Figure 19 (As shown) Greater than 2 nanometers and less than 20 nanometers.
[0051] Specifically, the step of forming a side core layer 106 on the sidewall of the first core layer 102 in the second region II includes:
[0052] like Figure 12 As shown, a first core material film 108 is formed on the first core layer 102 and the patterned material layer 101 exposed on the first core layer 102.
[0053] The first core material film 108 is prepared for the formation of the side core layer 106.
[0054] Specifically, the first core material film 108 conformally covers the first core layer 102 and the etch stop material layer 103 exposed on the first core layer 102.
[0055] Specifically, the material of the first core material film 108 includes amorphous silicon. In this embodiment, the material of the first core material film 108 includes amorphous silicon. Amorphous silicon is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the first core material film 108.
[0056] In this embodiment, the first core material film 108 is formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, which improves the thickness uniformity of the first core material film 108, enabling it to conformally cover the sidewalls of the first core layer 102, the top of the first core layer 102, and the etch stop material layer 103. Furthermore, ALD offers good gap-filling performance and step coverage, correspondingly improving the conformal coverage capability of the first core material film 108. In other embodiments, chemical vapor deposition (CVD) can also be used to form the first core material film.
[0057] like Figures 13 to 17 As shown, the first core material film 108 on the sidewall of the first core layer 102 in the second region II is doped to form the side core layer 106, and the etching resistance of the side core layer 106 is greater than that of the first core material film 108.
[0058] The side core layer 106 and the first core layer 102 of the second region II together serve as the second core layer 107, so that the lateral dimension of the second core layer 107 is larger than the lateral dimension of the first core layer 102.
[0059] Specifically, such as Figure 13 and Figure 14 As shown, Figure 14 for Figure 13 In the cross-sectional view at AA, the step of doping the first core material film 108 on the sidewall of the first core layer 102 of the second region II includes: forming a shielding layer 109, which covers the first region I and exposes the first core material film 108 on the sidewall of the first core layer 102 of the second region II.
[0060] During the subsequent doping process of the first core material film 108 exposed by the shielding layer 109, the shielding layer 109 can protect the first core material film 108 in the first region I from being easily doped.
[0061] The shielding layer 109 is made of a material that can act as a mask and is easy to remove, so that damage to the first core layer 102 and the second core layer 107 is reduced when the shielding layer 109 is removed in the future.
[0062] In this embodiment, the shielding layer 109 includes an organic material layer (not shown in the figure), an anti-reflective coating (not shown in the figure) located on the organic material layer, and a photoresist layer (not shown in the figure) located on the anti-reflective coating.
[0063] In this embodiment, the organic material layer includes ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), or SOC (spin on carbon) material.
[0064] In this embodiment, the anti-reflective coating material includes BARC (bottom anti-reflective coating) material or Si-ARC (silicon anti-reflective coating) material.
[0065] like Figures 15 to 17 As shown, Figure 16 for Figure 15 Cross-sectional view at point AA Figure 17 for Figure 15 Cross-sectional view at BB. Using the shielding layer 109 as a mask, the first core material film 108 on the sidewall of the first core layer 102 in the second region II is doped to form the side core layer 106.
[0066] In this embodiment, the first core material film 108 on the sidewall of the first core layer 102 in the second region II is doped using an ion implantation process to form a side core layer 106. Ion implantation has the advantages of simple operation and low process cost.
[0067] Specifically, in the step of doping the first core material film 108 on the sidewall of the first core layer 102 in the second region II, one or both of ions B and C are implanted. Doping ions can increase the activation energy of amorphous silicon. Amorphous silicon with doped ions is less prone to chemical reactions during etching, and correspondingly less likely to form reaction byproducts. Therefore, the etching resistance of the side core layer 106 is greater than that of the first core material film 108. In this embodiment, the implanted ion includes B.
[0068] It should be noted that the angle between the ion implantation direction and the surface normal of the patterned material layer 101 should not be too large or too small. If the angle is too large, the shadowing effect will be more pronounced, leading to excessive ion implantation into the shadowing layer 109. Consequently, the doping amount of the first core material film 108 on the sidewall of the first core layer 102 in the second region II will be less, and the etching resistance of the side core layer 106 will be less than that of the first core layer 102. During the subsequent etching of the patterned material layer 101 using the second core layer 107 as a mask, the side core layer 106 will be etched away prematurely, and the side core layer 106 will not function as a mask effectively. This will result in the lateral dimension of the target pattern being smaller than the preset lateral dimension, and the increase compared to the lateral dimension of the target pattern in the first region I will be insignificant. In this embodiment, the target pattern is a pseudo-gate structure. Correspondingly, the pseudo-gate structure is subsequently replaced with a gate structure, and gate plugs are formed on the gate structure of the second region II. Compared to the lateral dimension of the gate structure of the first region I, the lateral dimension of the gate structure of the second region II is not significantly increased. While increasing the spacing between the gate plugs, the contact area between the gate plugs and the gate structure of the second region II is too small, or the gate plugs do not contact the gate structure of the second region II, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the angle between the ion implantation direction and the surface normal of the patterned material layer 101 is less than 30°.
[0069] It should be noted that in the step of doping the first core material film 108 on the sidewall of the first core layer 102 in the second region II, the doping concentration should not be too high or too low. If the doping concentration is too high, too much process time is required to achieve the desired doping effect, resulting in low semiconductor structure formation efficiency. If the doping concentration is too low, the etch resistance improvement of the formed side core layer 106 compared to the first core material film 108 is not significant. During the subsequent removal of the remaining first core material film 108, the side core layer 106 is easily damaged, resulting in poor formation quality of the sidewall layer subsequently formed on the sidewall of the second core layer, and consequently, poor formation quality of the target pattern. In this embodiment, the doping concentration is between 1.0E15 atoms per cubic centimeter and 1.0E20 atoms per cubic centimeter.
[0070] It should be noted that during the ion doping process, a side core layer 106 is formed through multiple ion implantations. By controlling the energy of each ion implantation, ions can be doped relatively uniformly at various height positions of the side core layer 106. Subsequently, the pattern material layer 101 is etched using the first core layer 102 and the second core layer 107 as masks to form the target pattern. During this process, the etching resistance at various height positions of the side core layer 106 is the same, which is beneficial to improving the formation quality of the target pattern in the second region II.
[0071] It should be noted that during the doping process of the first core material film 108 on the sidewall of the first core layer 102 in the second region II, the first core material film 108 on the top of the first core layer 102 in the second region II is also doped.
[0072] like Figures 18 to 20 , Figure 19 for Figure 18 Cross-sectional view at point AA Figure 20 for Figure 18 Cross-sectional view at BB. The method for forming the semiconductor structure further includes: removing the shielding layer 109 after forming the side core layer 106 and before removing the remaining first core material film 108.
[0073] The material of the shielding layer 109 includes organic materials. After the side core layer 106 is formed, the shielding layer 109 is removed so that the organic materials are less likely to contaminate the machine.
[0074] In this embodiment, an ashing process is used to remove the masking layer 109. In other embodiments, a wet etching process can also be used to remove the masking layer. Specifically, the wet etching solution includes sulfuric acid.
[0075] The method for forming the semiconductor structure further includes: after forming the side core layer 106, removing the remaining first core material film 108.
[0076] Subsequently, sidewall layers are formed on the sidewalls of the first core layer 102 and the second core layer 107, and the remaining first core material film 108 is removed, so that the spacing between the sidewall layers on the sidewall of the second core layer 107 in the second region II is greater than the spacing between the sidewall layers on the sidewall of the first core layer 102 in the first region I.
[0077] In this embodiment, a wet etching process is used to remove the remaining first core material film 108. The wet etching process has advantages such as simple operation, fast etching rate, and low process cost.
[0078] Specifically, the etching solution for removing the remaining first core material film 108 includes: tetramethylammonium hydroxide solution (TMAH) and ammonia.
[0079] In other embodiments, the method for forming the semiconductor structure further includes: after forming the first core material film, before doping the first core material film on the sidewall of the first core layer of the second region II, removing the first core material film on the first core layer.
[0080] Subsequently, sidewall layers are formed on the sidewalls of the first core layer and the second core layer; the first core layer and the second core layer are removed; and the pattern material layer is etched using the sidewall layers as a mask to form the target pattern. Removing the first core material film on the top of the second core layer makes it easier to form sidewall layers of the same height on the sidewalls of the first core layer and the second core layer. In other words, the uniformity of the mask used for etching the pattern material layer 101 is high, which is beneficial to improving the uniformity of the target pattern and optimizing the electrical performance of the semiconductor structure.
[0081] Specifically, during the process of removing the first core material film on the first core layer, the first core material film on the surface of the etching stop material layer is also removed.
[0082] Specifically, a maskless dry etching process is used to remove the first core material film on top of the first core layer. The maskless dry etching process has anisotropic etching characteristics, which helps to ensure that while removing the first core material film at the top of the first core layer and on the surface of the resist material layer, damage to the first core material film on the sidewalls of the first core layer is minimized. This helps to avoid lateral etching of the first core material film on the sidewalls of the first core layer, making it less prone to thinning, thus ensuring that the lateral dimensions of the second core layer in the second region meet the process requirements. Furthermore, the maskless dry etching process eliminates the need for a photomask, reducing the process cost of forming the side core layer.
[0083] refer to Figures 21 to 23 , Figure 22 for Figure 21 Cross-sectional view at point AA Figure 23 for Figure 21 Cross-sectional view at BB. Sidewall layers 110 are formed on the sidewalls of the first core layer 102 and the second core layer 107.
[0084] The sidewall layer 110 serves as an etching mask for subsequent etching of the pattern material layer 101.
[0085] Specifically, the material of the sidewall layer 110 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the material of the sidewall layer 110 includes silicon nitride. Silicon nitride is a commonly used material in processes; it has high hardness and density and is a commonly used mask material.
[0086] The steps of forming the sidewall layer 110 include: conformally covering the first core layer 102 and the second core layer 107, and the etch-resistant material layer 103 exposed on the first core layer 102 and the second core layer 107 with a sidewall material layer (not shown in the figure); removing the sidewall material layer from the top of the first core layer 102 and the second core layer 107, and from the surface of the etch-resistant material layer 103, leaving the remaining sidewall material layer located on the sidewalls of the first core layer 102 and the second core layer 107 as the sidewall layer.
[0087] In this embodiment, atomic layer deposition (ALD) is used to form the sidewall material layer. ALD involves multiple ALD cycles, which improves the thickness uniformity of the sidewall material layer, enabling it to conformally cover the sidewalls of the first core layer 102 and the second core layer 107, and the etch stop material layer 103 exposed by the first and second core layers 102 and 107. Furthermore, ALD offers good gap-filling performance and step coverage, correspondingly improving the conformal coverage capability of the sidewall material layer. In other embodiments, chemical vapor deposition (CVD) can also be used to form the sidewall material layer.
[0088] In this embodiment, a maskless dry etching process is used to remove the sidewall material layer on top of the first core layer 102 and the second core layer 107, as well as the sidewall material layer on the surface of the anti-etching material layer 103.
[0089] While removing the sidewall material layers at the top of the first core layer 102 and the second core layer 107, as well as on the surface of the anti-etching material layer 103, it is difficult to laterally etch the sidewall material layers on the sidewalls of the first core layer 102 and the second core layer 107. This makes it difficult to thin the sidewall material layers on the sidewalls of the first core layer 102 and the second core layer 107, allowing the subsequent sidewall layer 110 to function as a better mask. This eliminates the need for a photomask, reducing the process cost of forming the sidewall layer 110.
[0090] Continue to refer to Figures 21 to 23 Remove the first core layer 102 and the second core layer 107.
[0091] Remove the first core layer 102 and the second core layer 107 to prepare for the subsequent etching of the pattern material layer 101 using the sidewall layer 110 as a mask.
[0092] In this embodiment, a dry etching process is used to remove the first core layer 102 and the second core layer 107. During the process of removing the first core layer 102 and the second core layer 107 using the dry etching process, the sidewall layer 110 suffers less damage.
[0093] In this embodiment, one or both of Cl2 and HBr are used to remove the first core layer 102 and the second core layer 107.
[0094] refer to Figure 24 The target pattern 111 is formed by etching the pattern material layer 101 using the sidewall layer 110 as a mask.
[0095] In this embodiment, the pattern material layer 101 is etched using the sidewall layer 110 as a mask to form the target pattern 111. The dry etching process is an anisotropic etching process, which results in a better morphological quality of the formed target pattern 111.
[0096] Before etching the pattern material layer 101 using the sidewall layer 110 as a mask, the sidewall layer 110 first etches an etching stop material layer 103 to form an etching stop layer. Accordingly, during the formation of the target pattern 111, the sidewall layer 110 and the etching stop layer are used together as a mask to etch the pattern material layer 101.
[0097] It should be noted that in the step of forming the target pattern 111, at the junction of the first region I and the second region II, the lateral spacing D2 between the target pattern 111 in the first region I and the target pattern 111 in the second region II should not be too large or too small. If the lateral spacing D2 between the target pattern 111 in the first region I and the target pattern 111 in the second region II is too large, the lateral dimension of the aforementioned side core layer 106 will be smaller, and the lateral dimension difference between the target pattern 111 in the second region II and the target pattern 111 in the first region I will be smaller. In this embodiment, the target pattern 111 is a pseudo-gate structure, which will be replaced by a gate structure later. A gate plug is formed on the gate structure in the second region II. Compared with the lateral dimension of the gate structure in the first region I, the lateral dimension of the gate structure in the second region II is not significantly increased. While expanding the spacing between the gate plugs, the contact area between the gate plug and the gate structure in the second region II is too small, or the gate plug does not contact the gate structure in the second region II, resulting in poor electrical performance of the semiconductor structure. If the lateral spacing D2 between the target pattern 111 in the first region I and the target pattern 111 in the second region II is too small, there is a risk of bridging between them. In this embodiment, the target pattern is a pseudo-gate structure, which will be replaced with a gate structure later. Consequently, the gate structure in the first region I and the gate structure in the second region II are prone to bridging, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the lateral spacing between the target pattern 111 in the first region I and the target pattern 111 in the second region II is 5 nanometers to 13 nanometers.
[0098] In this embodiment, in the step of etching the pattern material layer 101 using the sidewall layer 110 as a mask, the target pattern 111 formed includes a pseudo-gate structure.
[0099] The method for forming the semiconductor structure further includes: forming an interlayer dielectric layer that covers the sidewalls of the dummy gate structure and exposes the top of the dummy gate structure; removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer; forming a gate structure in the gate opening; and forming a gate plug on the gate structure in the second region II.
[0100] In this embodiment, the lateral spacing of the target pattern in the second region II is relatively large. Therefore, the lateral spacing between the gate plugs formed on the gate structure of the second region II is relatively far, and bridging between the gate plugs on the gate structure of the second region II is less likely to occur. In this embodiment, the lateral spacing between the gate structures in the second region II is relatively large. Correspondingly, the spacing between the gate structures in the first region I and the gate structures in the second region II is relatively small. Because the first region I surrounds the side of the second region II, the area with a small lateral spacing between the gate structures in the first region I and the gate structures in the second region II is relatively small. Only the lateral spacing between the gate structures that need to connect the gate plugs is increased, which helps to reduce the risk of bridging between the gate structures in the first region I and the gate structures in the second region II, and optimizes the electrical performance of the semiconductor structure.
[0101] In other embodiments, in the step of etching the pattern material layer using the sidewall layer as a mask, the target pattern formed includes fins;
[0102] The method for forming the semiconductor structure further includes: forming a gate structure spanning the fin, the gate structure covering the top wall and part of the sidewall of the fin; etching the gate structure between the fins in the second region along the extension direction of the fin, forming an opening in the second region that disconnects the gate structure.
[0103] The formed target pattern includes fins. The method for forming the semiconductor structure further includes: forming a gate structure spanning the fins, the gate structure covering the top wall and part of the sidewall of the fins, the gate structure between the fins in the second region having a large lateral dimension, etching the gate structure between the fins in the second region along the extension direction of the fins, and during the process of forming an opening that disconnects the gate structure in the second region, it is not easy to accidentally etch the fins. The formation window of the opening is large, which is beneficial to improving the electrical performance of the semiconductor structure.
[0104] In other embodiments, the method for forming the semiconductor structure is used to form a NAND Flash device. Accordingly, in the step of etching the pattern material layer using the sidewall layer as a mask, the formed target pattern includes a stacked structure consisting of a floating gate, a gate dielectric layer on the floating gate, and a control gate on the gate dielectric layer.
[0105] Accordingly, refer to Figure 25 This application also provides a semiconductor structure.
[0106] The semiconductor structure includes: a substrate, the substrate including a first region I and a second region II, the first region I surrounding the side of the second region II; and target patterns 211, which are disposed on the substrate, with the extension direction of the target patterns 211 perpendicular to the first region I as the lateral direction, and the lateral spacing between the target patterns 211 in the second region II being greater than the lateral spacing between the target patterns 211 in the first region I.
[0107] In the semiconductor structure provided by this application, the first region I surrounds the side of the second region II, and the lateral spacing of the target pattern 211 in the second region II is greater than the lateral spacing of the target pattern 211 in the first region I. In summary, this application embodiment, while ensuring the high uniformity of the spacing of the target pattern 211 in the first region I, only expands the lateral spacing of the target pattern 211 in the second region II, which can meet the diverse needs of the target pattern 211 and is beneficial to improving the electrical performance of the semiconductor structure.
[0108] It should be noted that at the boundary between the first region I and the second region II, the lateral spacing D2 between the target pattern 211 in the first region I and the target pattern 211 in the second region II should not be too large or too small. If the lateral spacing D2 is too small, there is a risk of bridging between the target pattern 211 in the first region I and the target pattern 211 in the second region II. In this embodiment, the target pattern is a pseudo-gate structure, which will be replaced with a gate structure later. Consequently, the gate structure in the first region I and the gate structure in the second region II are prone to bridging, resulting in poor electrical performance of the semiconductor structure. If the lateral spacing D2 between the target pattern 211 in the first region I and the target pattern 211 in the second region II is too large, the lateral dimensions of the target pattern 211 in the second region II and the target pattern 211 in the first region I will be relatively similar. In this embodiment, the target pattern 211 is a pseudo-gate structure, which is subsequently replaced with a gate structure. A gate plug is formed on the gate structure of the second region II. Compared with the lateral dimension of the gate structure of the first region I, the lateral dimension of the gate structure of the second region II is not significantly increased. While increasing the spacing between the gate plugs, the contact area between the gate plug and the gate structure of the second region II is too small, or the gate plug does not contact the gate structure of the second region II, resulting in poor electrical performance of the semiconductor structure. If the lateral spacing D2 between the target pattern 211 in the first region I and the target pattern 211 in the second region II is too small, in this embodiment, the lateral spacing D2 between the target pattern 211 in the first region I and the target pattern 211 in the second region II is 5 nanometers to 13 nanometers.
[0109] In this embodiment, the target pattern 211 is made of amorphous silicon. In this embodiment, the target pattern 111 includes a pseudo-gate structure.
[0110] Subsequently, an interlayer dielectric layer is formed that covers the sidewalls of the dummy gate structure and exposes the top of the dummy gate structure; the dummy gate structure is removed, and a gate opening is formed in the interlayer dielectric layer; a gate structure is formed in the gate opening; and a gate plug is formed on the gate structure in the second region II.
[0111] In this embodiment, the lateral spacing of the target pattern 211 in the second region II is relatively large. Therefore, the lateral spacing between the gate plugs formed on the gate structure of the second region II is relatively far, and bridging between the gate plugs on the gate structure of the second region II is less likely to occur. In this embodiment, the lateral spacing between the gate structures of the second region II is relatively large. Correspondingly, the spacing between the gate structures of the first region I and the gate structures of the second region II is relatively small. Because the first region I surrounds the side of the second region II, the area with a small lateral spacing between the gate structures of the first region I and the gate structures of the second region II is relatively small. Only the lateral spacing between the gate structures that need to connect the gate plugs is increased, which helps to reduce the risk of bridging between the gate structures of the first region I and the gate structures of the second region II and optimize the electrical performance of the semiconductor structure.
[0112] In other embodiments, the target pattern includes fins. The semiconductor structure further includes: a gate structure spanning the fins, the gate structure covering the top wall and part of the sidewalls of the fin portion; the semiconductor structure further includes: an opening that disconnects the gate structure between the fins in the second region.
[0113] The gate structure between the fins in the second region has a large lateral dimension. When the gate structure between the fins in the second region is etched along the extension direction of the fins, it is not easy to accidentally etch the fins during the process of forming an opening that disconnects the gate structure in the second region. The opening has a large window, which is beneficial to improving the electrical performance of the semiconductor structure.
[0114] In other embodiments, the semiconductor structure prepares for the subsequent formation of a NAND Flash device. Accordingly, the target pattern includes a stacked structure comprising a floating gate, a gate dielectric layer on the floating gate, and a control gate on the gate dielectric layer.
[0115] The semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.
[0116] While this application discloses the above information, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application shall be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region, the first region surrounding the side of the second region, the substrate including a pattern material layer and a first core layer discrete on the pattern material layer; A side core layer is formed on the sidewall of the first core layer in the second region, and the first core layer and the side core layer in the second region serve as the second core layer. Sidewall layers are formed on the sidewalls of the first core layer and the second core layer; Remove the first core layer and the second core layer; The target pattern is formed by etching the pattern material layer using the sidewall layer as a mask.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a side core layer on the sidewall of the first core layer in the second region, with the side dimension being parallel to the surface of the patterned material layer and perpendicular to the sidewall of the first core layer, the side core layer has a lateral dimension greater than 2 nanometers and less than 20 nanometers.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a side core layer on the sidewall of the first core layer in the second region includes: A first core material film is formed on the first core layer and the exposed patterned material layer of the first core layer; The first core material film on the sidewall of the first core layer in the second region is doped to form the side core layer, and the etching resistance of the side core layer is greater than that of the first core material film. The method for forming the semiconductor structure further includes: after forming the side core layer, removing the remaining first core material film.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The step of doping the first core material film on the sidewall of the first core layer in the second region includes: A shielding layer is formed, which covers the first region and exposes the first core material film on the sidewall of the first core layer in the second region; Using the shielding layer as a mask, the first core material film on the sidewall of the first core layer in the second region is doped to form the side core layer; The method for forming the semiconductor structure further includes: after forming the side core layer, and before removing the remaining first core material film, removing the shielding layer.
5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The material of the first core material film includes: amorphous silicon.
6. The method for forming a semiconductor structure as described in claim 3, characterized in that, The first core material film is formed using chemical vapor deposition or atomic layer deposition.
7. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for forming the semiconductor structure further includes: after forming the first core material film, before doping the first core material film on the sidewall of the first core layer in the second region, removing the first core material film on the top of the first core layer.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The first core material film on top of the first core layer is removed using a maskless dry etching process.
9. The method for forming a semiconductor structure as described in claim 3, characterized in that, The first core material film on the sidewall of the first core layer in the second region is doped using an ion implantation process to form a side core layer.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of doping the first core material film on the sidewall of the first core layer in the second region, the implanted ions include one or both of B and C, the doping concentration is 1.0E15 atoms per cubic centimeter to 1.0E20 atoms per cubic centimeter, and the angle between the ion implantation direction and the normal of the surface of the patterned material layer is less than 30°.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first and second core layers are removed using one or both of Cl2 and HBr.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of providing a substrate include: providing a patterned material layer; forming a second core material film on the patterned material layer; and doping the second core material film to form a core material layer. In the step of providing the substrate, the core material layer is patterned using a self-aligned dual imaging process, a self-aligned quadruple imaging process, or a self-aligned multiple imaging process to form the first core layer.
13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The direction of extension of the target graphic perpendicular to the first region is taken as the horizontal direction; In the step of forming the target pattern, at the boundary between the first region and the second region, the lateral spacing between the target pattern in the first region and the target pattern in the second region is 5 nanometers to 13 nanometers.
14. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of etching the pattern material layer using the sidewall layer as a mask, the target pattern formed includes a pseudo-gate structure; The method for forming the semiconductor structure further includes: forming an interlayer dielectric layer that covers the sidewalls of the dummy gate structure and exposes the top of the dummy gate structure; Remove the dummy gate structure and form a gate opening in the interlayer dielectric layer; A gate structure is formed in the gate opening; A gate plug is formed on the gate structure in the second region.
15. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of etching the pattern material layer using the sidewall layer as a mask, the target pattern formed includes fins; The method for forming the semiconductor structure further includes: forming a gate structure spanning the fin portion, the gate structure covering the top wall and part of the sidewall of the fin portion; Along the extending direction of the fin, the gate structure between the fins in the second region is etched to form an opening in the second region that disconnects the gate structure.
16. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of etching the pattern material layer using the sidewall layer as a mask, the target pattern formed includes a stacked structure consisting of a floating gate, a gate dielectric layer located on the floating gate, and a control gate located on the gate dielectric layer.
17. A semiconductor structure, characterized in that, include: A substrate, the substrate comprising a first region and a second region, the first region surrounding the side portion of the second region; The target graphics are distributed on the substrate, with the extension direction of the target graphics in the first region being the lateral direction. The lateral spacing between the target graphics in the second region is greater than the lateral spacing between the target graphics in the first region. In the extension direction of the target graphics, the first region is also located on both sides of the second region. The target pattern includes a pseudo-gate structure.
18. The semiconductor structure as claimed in claim 17, characterized in that, At the boundary between the first and second regions, the lateral spacing between the target graphic in the first region and the target graphic in the second region is 5 nanometers to 13 nanometers.
19. The semiconductor structure as claimed in claim 17, characterized in that, The target graphic includes a fin; The semiconductor structure further includes: a gate structure spanning the fin portion, the gate structure covering the top wall and part of the sidewall of the fin portion; The semiconductor structure further includes an opening that disconnects the gate structure between the fins in the second region.