Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: providing a substrate, the substrate including a first region and a second region, the substrate including a substrate and a plurality of fin portions located on the substrate, the fin portions including a first punch-through prevention layer, a second punch-through prevention layer located on the first punch-through prevention layer, and a first channel layer located on the second punch-through prevention layer, the first punch-through prevention layer being doped with first-type ions, the second punch-through prevention layer being doped with second-type ions; forming an isolation material layer on the substrate exposed by the fin portions; removing the second punch-through prevention layer and the first channel layer in the first region to form a groove; and forming a second channel layer in the groove. When the semiconductor structure operates, the first punch-through prevention layer reduces the probability of source and drain punch-through in the first region, and the second punch-through prevention layer reduces the probability of source and drain punch-through in the second region, which is beneficial to improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of very large scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) has also been continuously shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and drain of the device is also shortened. Therefore, the control ability of the gate structure over the channel becomes worse, and it becomes more and more difficult to pinch off the channel with the gate voltage, making the subthreshold leakage phenomenon, that is, the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to reduce the influence of short-channel effects, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field-Effect Transistors (FinFETs). In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has a stronger control ability over the channel and can well suppress short-channel effects; and compared with other devices, FinFETs have better compatibility with existing integrated circuit manufacturing.

[0004] With the development of semiconductor processes, in order to reduce power consumption, the integration degree of semiconductor structures is getting higher and higher, and the distance between the source and drain in transistors is getting shorter and shorter. When the semiconductor structure is working, the source and drain are prone to punch-through. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same to optimize the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first region and a second region, the substrate including a substrate and a plurality of fin portions located on the substrate, the fin portions including a first punch-through prevention layer, a second punch-through prevention layer located on the first punch-through prevention layer, and a first channel layer located on the second punch-through prevention layer, the first punch-through prevention layer being doped with first-type ions, the second punch-through prevention layer being doped with second-type ions, the conduction types of the first-type ions and the second-type ions being different; forming an isolation material layer on the substrate exposed by the fin portions, the isolation material layer covering the sidewalls of the fin portions; removing the second punch-through prevention layer and the first channel layer in the first region, and forming a groove in the isolation material layer; and forming a second channel layer in the groove.

[0007] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region; a first fin portion, separated on the substrate in the first region, the first fin portion including a punch-through prevention region and a first channel layer located on the punch-through prevention region, the punch-through prevention region being doped with first-type ions; and a second fin portion, separated on the substrate in the second region, the second fin portion including a first punch-through prevention layer and a second channel layer located on the first punch-through prevention layer, the first punch-through prevention layer being doped with second-type ions, the conduction type of the second-type ions being different from the conduction type of the first-type ions.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure provided by the embodiment of the present invention, in the step of providing the substrate, the fin portions include a first punch-through prevention layer, a second punch-through prevention layer located on the first punch-through prevention layer, and a first channel layer located on the second punch-through prevention layer, the conduction types of the second-type ions and the first-type ions being different. After forming the isolation material layer, the second punch-through prevention layer and the first channel layer in the first region are removed, a groove is formed in the isolation material layer, and a second channel layer is formed in the groove. In the embodiment of the present invention, when the semiconductor structure works, in the first region, the first punch-through prevention layer at the bottom of the second channel layer makes the depletion layers of the source and drain of the source-drain doping layer subsequently formed in the first region not easily expand, reducing the probability of punch-through of the source and drain in the first region; when the semiconductor structure works, in the second region, the second punch-through prevention layer at the bottom of the first channel layer makes the depletion layers of the source and drain of the source-drain doping layer subsequently formed in the second region not easily expand, reducing the probability of punch-through of the source and drain in the second region, which is beneficial to improving the electrical performance of the semiconductor structure.

[0010] In an alternative embodiment, in the step of removing the second punch-through layer and the first channel layer in the first region and forming a groove in the isolation material layer, the first punch-through layer in the first region is also removed. Generally, before removing the first punch-through layer, the first-type ions in the first punch-through layer have diffused to the bottom of the first punch-through layer to form a punch-through region doped with first-type ions. Removing the first punch-through layer increases the depth of the groove, correspondingly increases the space for forming the second channel layer, and increases the height of the formed second channel layer. When the semiconductor structure operates, the punch-through region is used to prevent the depletion layers of the source and drain of the source-drain doping layer subsequently formed in the first region from easily expanding. The relatively large height of the second channel layer increases the flow region of the channel carriers in the second region, reduces the confinement of the punch-through region to the carrier flow region, increases the spatial region for carrier flow, and is beneficial to the carrier migration rate. Description of the Drawings

[0011] Figures 1 to 5 are schematic structural diagrams of each step in a method for forming a semiconductor structure;

[0012] Figures 6 to 13 are schematic structural diagrams corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0013] Figure 14 and Figure 15 are schematic structural diagrams corresponding to key steps in the second embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0014] Figure 16 is a schematic structural diagram of the first embodiment of the semiconductor structure according to an embodiment of the present invention.

[0015] Figure 17 is a schematic structural diagram of the second embodiment of the semiconductor structure according to an embodiment of the present invention. Detailed Embodiments

[0016] As can be seen from the background art, the currently formed semiconductor structures still have problems with poor performance. Now, the reasons for the poor performance of semiconductor structures are analyzed in combination with a method for forming a semiconductor structure.

[0017] Refer to Figures 1 to 5 , which shows schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure.

[0018] As Figure 1 shown, a substrate is provided. The substrate includes an NMOS region I and a PMOS region II. The substrate includes a substrate 10 and fins 11 located on the substrate 10. The fins 11 include a punch-through layer 12 and a first channel layer 13 located on the punch-through layer 12.

[0019] Reference Figure 2 , an isolation material layer 14 is formed on the substrate 10 where the fin portion 11 (as Figure 1 shown) is exposed.

[0020] Reference Figure 3 , after the isolation material layer 14 is formed, the fin portion 11 in the first region I is removed to form a groove 15.

[0021] Reference Figure 4 , a second channel layer 16 is formed in the groove 15 (as Figure 2 shown).

[0022] Reference Figure 5 , a part of the thickness of the isolation material layer 14 is removed to form an isolation layer 17 covering part of the sidewalls of the first channel layer 13 and the second channel layer 16.

[0023] The method for forming the semiconductor structure further includes: forming source-drain doping layers in the first channel layer 13 and the second channel layer 16.

[0024] It should be noted that with the development of semiconductor processes, in order to reduce energy consumption, the integration degree of semiconductor structures is getting higher and higher. In order to reduce the probability of source-drain punch-through in PMOS, an anti-punch-through layer 12 is formed at the bottom of the first channel layer 13 in the PMOS region II. When the semiconductor structure works, the anti-punch-through layer 12 can prevent the depletion regions of the source and drain of the PMOS from expanding easily, and correspondingly, the source and drain of the PMOS are not easily punch-through. However, there is no corresponding anti-punch-through layer at the bottom of the NMOS region I, and the depletion regions of the source and drain of the NMOS are easy to expand, and the source and drain in the NMOS are easy to punch-through, resulting in poor electrical performance of the semiconductor structure.

[0025] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: in the step of providing a substrate, the fin portion includes a first punch-through prevention layer, a second punch-through prevention layer located on the first punch-through prevention layer, and a first channel layer located on the second punch-through prevention layer. The conductivity type of the second type of ions is different from that of the first type of ions. After forming the isolation material layer, the second punch-through prevention layer and the first channel layer in the first region are removed, a groove is formed in the isolation material layer, and a second channel layer is formed in the groove. When the semiconductor structure is operating, in the first region, the first punch-through prevention layer at the bottom of the second channel layer makes the depletion layers of the source and drain of the source-drain doping layer subsequently formed in the first region not easily expand, reducing the probability of punch-through of the source and drain in the first region; when the semiconductor structure is operating, in the second region, the second punch-through prevention layer at the bottom of the first channel layer makes the depletion layers of the source and drain of the source-drain doping layer subsequently formed in the second region not easily expand, reducing the probability of punch-through of the source and drain in the second region, which is beneficial to improving the electrical performance of the semiconductor structure.

[0026] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description will be given to the specific embodiments of the embodiments of the present invention with reference to the accompanying drawings.

[0027] Figures 6 to 13 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0028] Reference Figure 6 And Figure 7 , a substrate is provided. The substrate includes a first region I and a second region II. The substrate includes a substrate 100 and a plurality of fin portions 101 located on the substrate 100. The fin portion 101 includes a first punch-through prevention layer 102, a second punch-through prevention layer 103 located on the first punch-through prevention layer 102, and a first channel layer 104 located on the second punch-through prevention layer 103. The first punch-through prevention layer 102 is doped with first type of ions, the second punch-through prevention layer 103 is doped with second type of ions, and the conductivity type of the first type of ions is different from that of the second type of ions.

[0029] The substrate 100 is used to provide a process platform for subsequently forming a semiconductor structure.

[0030] Specifically, the first region I is used to form an NMOS (Negative channel Metal Oxide Semiconductor), and the second region II is used to form a PMOS (Positive Channel Metal Oxide Semiconductor).

[0031] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. An interface layer can also be formed on the surface of the substrate, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, etc.

[0032] Subsequently, an isolation material layer is formed on the substrate 100 exposed by the fin portion 101. The isolation material layer covers the sidewalls of the fin portion 101. The fin portion 101 in the first region I is removed, a groove is formed in the isolation material layer in the first region I, a second channel layer is formed in the groove, a source-drain doping layer is formed in the second channel layer. When the semiconductor structure operates, the first punch-through prevention layer 102 makes the depletion layers of the source and drain in the first region I not easily expand, reducing the probability of punch-through of the source and drain in the first region I, which is beneficial to improving the electrical performance of the semiconductor structure in the first region I.

[0033] The first region I is used to form an NMOS, and the corresponding source-drain doping layer in the first region I serves as the source and drain of the NMOS. When the semiconductor structure operates, the source-drain doping layer applies tensile stress to the channel, and stretching the channel can improve the migration rate of electrons. Specifically, the source-drain doping layer is doped with N-type ions. The N-type ions replace the positions of silicon atoms in the lattice. The more N-type ions are doped, the higher the concentration of majority carriers, and the stronger the conductivity. Specifically, the N-type ions include one or more of P, As, and Sb.

[0034] The conduction type of the first-type ions in the first punch-through prevention layer 102 is different from the conduction type of the doping ions in the source-drain doping layer in the first region I. The first punch-through prevention layer 102 is doped with P-type ions, and the P-type ions include one or more of B, Ga, and In.

[0035] In this embodiment, the material of the first punch-through prevention layer 102 includes silicon germanide doped with first-type ions. The first region I is an NMOS region. When the semiconductor structure operates, the carriers in the channel of the NMOS are electrons. Subsequently, the material of the second channel layer formed in the groove is usually silicon. Therefore, the concentration of Ge in the second channel layer is lower than the concentration of Ge in the first punch-through prevention layer 102. When the semiconductor structure operates, the first punch-through prevention layer 102 can make the depletion layers of the source and drain in the second region II not easily expand while providing sufficient stress to the second channel layer, improving the migration rate of carriers in the second channel layer.

[0036] In this embodiment, the concentration of the first-type ions at the bottom of the first punch-through prevention layer 102 is higher than the concentration of the first-type ions at the top of the first punch-through prevention layer 102.

[0037] In this embodiment, the conductivity type of the first-type ions is the same as that of the doped ions in the source-drain doping layer of the second region II. The doping concentration of the first-type ions at the bottom of the first punch-through prevention layer 102 is higher than that of the first-type ions at the top of the first punch-through prevention layer 102, so that the first-type ions in the first punch-through prevention layer 102 are not easily diffused into the second punch-through prevention layer 103. When the semiconductor structure operates, the second punch-through prevention layer 103 can prevent the depletion layers of the source and drain of the second region II from easily expanding, reducing the probability of punch-through of the source and drain in the second region II, which is beneficial to improving the electrical performance of the semiconductor structure in the second region II. Specifically, the first punch-through prevention layer 102 is a Super Steep Retrograde N well (SSRNW).

[0038] It should be noted that the first punch-through prevention layer 102 should not be too thick or too thin. If the first punch-through prevention layer 102 is too thick, it is easy to spend too much process time to form the first punch-through prevention layer 102, resulting in low formation efficiency of the first punch-through prevention layer 102. And if the first punch-through prevention layer 102 is too thick, the height of the corresponding fin 101 is too large. During the process of etching to form the fin 101, the fin 101 is easy to bend or tilt, and the formation quality of the fin 101 is poor. Correspondingly, adjacent fins 101 are easy to bridge, and the quality of the semiconductor structure formed based on the fins 101 subsequently is poor. If the first punch-through prevention layer 102 is too thin, the N-type ions in the source-drain doping layer of the second region II are easily diffused into the entire first punch-through prevention layer 102 and a part of the substrate 100 with a certain thickness. When the semiconductor structure operates, the depletion layers of the source and drain of the source-drain doping layer in the second region II are easy to expand, and the source and drain are easy to punch through, resulting in poor improvement of the electrical performance of the semiconductor structure. In this embodiment, the thickness of the first punch-through prevention layer 102 is 45 nanometers to 60 nanometers.

[0039] Subsequently, a source-drain doping layer is formed in the fin 101 of the second region II. When the semiconductor structure operates, the second punch-through prevention layer 103 can prevent the depletion layers of the source and drain of the second region II from easily expanding, reducing the probability of punch-through of the source and drain in the second region II, which is beneficial to improving the electrical performance of the semiconductor structure.

[0040] In this embodiment, the second region II is used to form a PMOS, and the source-drain doping layer of the second region II serves as the source and drain of the PMOS. When the semiconductor structure operates, the source-drain doping layer applies a compressive stress to the channel under the gate structure, and compressing the channel can improve the mobility of holes. Specifically, the source-drain doping layer of the second region II is doped with P-type ions, and the P-type ions replace the positions of silicon atoms in the lattice. The more P-type ions are doped, the higher the concentration of majority carriers, and the stronger the conductivity. Specifically, the P-type ions include one or more of B, Ga, and In.

[0041] Correspondingly, the conduction type of the second-type ions in the second punch-through prevention layer 103 is different from the conduction type of the doping ions in the source-drain doping layer of the second region II. The second punch-through prevention layer 103 is doped with N-type ions, and the N-type ions include one or more of P, As, and Sb.

[0042] Specifically, the second punch-through prevention layer 103 includes silicon germanide doped with N-type ions. The second region II is used to form a PMOS, and the carriers of the PMOS are holes. When the semiconductor structure operates, it is beneficial to improve the migration rate of carriers in the first channel layer 104.

[0043] When the semiconductor structure operates, the top of the first channel layer 104 is used as the channel region of the second region II.

[0044] In this embodiment, the material of the first channel layer 104 includes silicon germanide. When the semiconductor structure operates, the carriers in the channel of the PMOS are holes. Germanium silicon can improve the mobility of channel carriers in the PMOS more than silicon, which is beneficial to improving the electrical performance of the semiconductor structure.

[0045] It should also be noted that the fin 101 is formed by a self-aligned double patterning (SADP) process. The uniformity of the fin 101 is good, which simplifies the formation process of the fin 101 and is beneficial to improving the formation efficiency of the fin 101. In other embodiments, the fin can also be formed by a self-aligned quadruple patterning (SAQP) process or a self-aligned multiple patterning (SAMP) process.

[0046] Specifically, the step of providing the substrate includes: as Figure 6As shown, an initial substrate 200 is provided; a first punch-through prevention material layer 202 is formed on the initial substrate 200; a second punch-through prevention material layer 203 is formed on the first punch-through prevention material layer 202; a semiconductor material layer 201 is formed on the second punch-through prevention material layer 203; as Figure 7 As shown, the semiconductor material layer 201, the second punch-through prevention material layer 203, the first punch-through prevention material layer 202 and a part of the thickness of the initial substrate 200 are etched to form the substrate.

[0047] The step of forming the first punch-through prevention material layer 202 includes: forming the first epitaxial layer by using a selective epitaxy growth process (SEG); in the step of forming the first epitaxial layer, in-suit doping of the first epitaxial layer with first-type ions is performed to form the first punch-through prevention material layer 202.

[0048] The first epitaxial layer obtained by the selective epitaxy growth method has high purity and few lattice defects, which is beneficial to improving the formation quality of the first punch-through prevention material layer 202. Correspondingly, the formation quality of the first punch-through prevention layer 102 is good, so that the doping ions in the source / drain doping layer of the first region I are not easily diffused into the first punch-through prevention layer 102 through the lattice gaps, thereby being beneficial to optimizing the electrical performance of the semiconductor structure.

[0049] In-suit doping can improve the activation rate of the first-type ions in the first punch-through prevention layer 102, and is beneficial to blocking the diffusion of N-type ions in the source / drain doping layer of the first region I into the first punch-through prevention layer 102 when the semiconductor structure works.

[0050] It should be noted that in the step of forming the first anti-punchthrough material layer 202, the doping dose of the first-type ions in the first anti-punchthrough material layer 202 should neither be too large nor too small. Correspondingly, the doping dose of the first-type ions in the first anti-punchthrough layer 102 should neither be too large nor too small. If the doping dose of the first-type ions in the first anti-punchthrough layer 102 is too large, the first-type ions in the first anti-punchthrough layer 102 are likely to diffuse into the second anti-punchthrough layer 103. In this embodiment, the first-type ions have the same conduction type as the doping ions in the source-drain doping layer of the second region II. When the semiconductor structure operates, under the combined action of the first-type ions in the second anti-punchthrough layer 103, the depletion layers of the source and drain of the second region II are likely to expand, increasing the probability of punchthrough of the source and drain of the second region II and resulting in poor electrical performance of the semiconductor structure. If the doping dose of the first-type ions in the first anti-punchthrough layer 102 is too small, when the semiconductor structure operates, the first anti-punchthrough layer 102 cannot effectively prevent the expansion of the depletion layers of the source and drain of the first region I, and the source and drain of the first region I are likely to punch through, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the doping dose of the first-type ions in the first anti-punchthrough layer 102 is from 1.0E15 atoms per square centimeter to 1.0E18 atoms per square centimeter.

[0051] The step of forming the second anti-punchthrough material layer 203 includes: forming the second epitaxial layer by selective epitaxial growth process. In the step of forming the second epitaxial layer, in-situ doping of the second-type ions is performed on the second epitaxial layer to form the second anti-punchthrough material layer 203.

[0052] The second epitaxial layer obtained by selective epitaxial growth method has high purity and few lattice defects, which is beneficial to improving the formation quality of the second anti-punchthrough material layer 203. Correspondingly, the formation quality of the second anti-punchthrough layer 103 is better, making it difficult for the doping ions in the source-drain doping layer of the second region II to diffuse into the second anti-punchthrough layer 103 through lattice gaps, thereby being beneficial to optimizing the electrical performance of the semiconductor structure.

[0053] In this embodiment, in-situ doping can improve the activation rate of the doping ions in the second anti-punchthrough layer 103. When the semiconductor structure operates, it is beneficial to prevent the P-type ions in the source-drain doping layer of the second region II from diffusing into the second anti-punchthrough layer 103.

[0054] It should be noted that in the step of providing the substrate, the materials of the second epitaxial layer and the first channel layer 104 are the same. Correspondingly, subsequently, in a single etching process, the second anti-punchthrough layer 103 and the first channel layer 104 in the first region I can be removed to form a groove in the isolation material layer, which is beneficial to reducing the difficulty of forming the groove.

[0055] It should also be noted that in the step of providing the substrate, a mask layer 106 is formed on the top of the first channel layer 104. Using the mask layer 106 as a mask, the semiconductor material layer 201, the second punch-through prevention material layer 203, the first punch-through prevention material layer 202, and a part of the thickness of the initial substrate 200 are etched to form the substrate.

[0056] Specifically, the material of the mask layer 106 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, boron nitride silicon, and boron nitride carbon silicon. In this embodiment, the material of the mask layer 106 includes silicon nitride.

[0057] It should be noted that a buffer layer 105 is formed between the mask layer 106 and the fin 101. The buffer layer 105 is used to reduce the stress between the mask layer 106 and the fin 101 and improve the adhesion between the mask layer 106 and the semiconductor material layer 201.

[0058] In this embodiment, the material of the buffer layer 105 includes silicon oxide.

[0059] Reference Figure 8 , an isolation material layer 107 is formed on the substrate 100 exposed by the fin 101, and the isolation material layer 107 covers the side walls of the fin 101.

[0060] Subsequently, the second punch-through prevention layer 103 and the first channel layer 104 in the first region I are removed, and a groove is formed in the isolation material layer 107. The isolation material layer 107 prepares for the formation of the groove, and at the same time, the isolation material layer 107 prepares for the subsequent formation of the isolation layer.

[0061] In this embodiment, the material of the isolation material layer 107 includes silicon oxide. Silicon oxide is a commonly used dielectric material in the process with low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and cost of forming the isolation material layer 107, and reducing the process difficulty of forming the isolation layer by etching a part of the thickness of the isolation material layer 107 subsequently.

[0062] In this embodiment, the isolation material layer 107 is formed by plasma enhanced chemical vapor deposition process (PECVD). The PECVD process ionizes the gas containing the atoms of the thin film composition by means of microwave or radio frequency, etc., to form a plasma locally, and the plasma has strong chemical activity and is easy to react. The PECVD process allows the growth of the required thin film in a low-temperature environment, and the PECVD process also has the advantages of fast deposition rate, high productivity, good film formation quality, and high density.

[0063] Reference Figure 9 Remove the second punch-through prevention layer 103 and the first channel layer 104 in the first region I, and form a groove 108 in the isolation material layer 107.

[0064] The groove 108 prepares for the subsequent formation of the second channel layer. Specifically, in this embodiment, the groove 108 is surrounded by the first punch-through prevention layer 102 and the isolation material layer 107.

[0065] In this embodiment, a dry etching process is used to remove the second punch-through prevention layer 103 and the first channel layer 104 in the first region I. The dry etching process has anisotropic etching characteristics and good etching profile controllability, which is beneficial to making the morphology of the groove 108 meet the process requirements. During the process of using the dry etching process to remove the second punch-through prevention layer 103 and the first channel layer 104, by selecting an appropriate etching gas, the isolation material layer 107 is not easily damaged, and the formation quality of the groove 108 is better.

[0066] It should be noted that in this embodiment, the materials of the second epitaxial layer and the first channel layer 104 are the same. Correspondingly, in a single-step dry etching process, the second punch-through prevention layer 103 and the first channel layer 104 in the first region I can be removed, and the formation difficulty of the groove is relatively small.

[0067] In this embodiment, the materials of the second epitaxial layer and the first channel layer 104 include silicon germanide. Correspondingly, the dry etching gas includes hydrogen chloride.

[0068] Specifically, the steps of removing the second punch-through prevention layer 103 and the first channel layer 104 in the first region I include: forming a shielding layer 109 that covers the fin 101 in the second region II and exposes the fin 101 in the first region I; using the shielding layer 109 as a mask to remove the second punch-through prevention layer 103 and the first channel layer 104 in the first region I.

[0069] The shielding layer 109 is used to protect the fin 101 in the second region II from being accidentally etched during the process of removing the second punch-through prevention layer 103 and the first channel layer 104 in the first region I.

[0070] In this embodiment, the material of the shielding layer 109 is an organic material. The organic material is a material that is easy to remove, which reduces the damage to the fin 101 when the shielding layer 109 is removed subsequently.

[0071] Specifically, the material of the shielding layer 109 can be a BARC (bottom anti-reflective coating) material, an ODL (organic dielectric layer) material, a photoresist, a DARC (dielectric anti-reflective coating) material, a DUO (Deep UV Light Absorbing Oxide) material, or an APF (Advanced Patterning Film) material.

[0072] The method for forming the semiconductor structure further includes: after forming the groove 108, removing the shielding layer 109.

[0073] After forming the groove 108, removing the shielding layer 109 makes the organic material in the shielding layer 109 not easily contaminate the machine platform.

[0074] In this embodiment, an ashing process is used to remove the shielding layer 109.

[0075] It should be noted that the first anti-punchthrough layer 102 contains first-type ions, the material of the substrate 100 includes silicon, and the doping concentration of the first-type ions between the first anti-punchthrough layer 102 and the substrate 100 is relatively large. During the formation of the semiconductor structure, the first-type ions in the first anti-punchthrough layer 102 are likely to diffuse into the substrate 100 to form an anti-punchthrough region 111 in the substrate 100.

[0076] Reference Figures 10 to 13 , a second channel layer 110 is formed in the groove 108.

[0077] When the semiconductor structure operates, the top of the second channel layer 110 is used as the channel region of the first region I.

[0078] In this embodiment, the first region I is used to form an NMOS. The material of the first anti-punchthrough layer 102 is silicon germanide, and the material of the second channel layer 110 is silicon. When the semiconductor structure operates, the first anti-punchthrough layer 102 can prevent the depletion layers of the source and drain of the first region I from easily expanding, and at the same time, can provide sufficient stress to the second channel layer 110 to improve the migration rate of carriers in the second channel layer 110.

[0079] Specifically, the step of forming the second channel layer 110 includes:

[0080] As Figure 10 shown, a third epitaxial layer 113 is formed in the groove 108.

[0081] In this embodiment, the third epitaxial layer 113 is formed by selective epitaxy growth (SEG). The third epitaxial layer 113 obtained by selective epitaxy growth has high purity and few defects, which is beneficial to improving the formation quality of the third epitaxial layer 113, and thus is beneficial to optimizing the electrical performance of the semiconductor structure.

[0082] It should be noted that the material of the isolation material layer 107 is silicon oxide. In the step of forming the third epitaxial layer 113 by selective epitaxy growth process, the material of the third epitaxial layer 113 is not easily epitaxially grown on the isolation material layer 107.

[0083] It should be noted that the third epitaxial layer 113 is formed by selective epitaxy growth method, and usually the top of the third epitaxial layer 113 has an irregular shape.

[0084] Such as Figure 11 shown, an isolation material film 112 covering the isolation material layer 107 and the third epitaxial layer 113 is formed.

[0085] Compared with the case of directly planarizing the third epitaxial layer in this embodiment, the isolation material film 112 covers the third epitaxial layer 113, which is beneficial to improving the flatness of the top of the second channel layer formed by planarization.

[0086] In this embodiment, the material of the isolation material film 112 includes silicon oxide. Silicon oxide is a dielectric material commonly used in the process, with low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and process cost of forming the isolation material film 112.

[0087] In this embodiment, the isolation material film 112 is formed by Flowable Chemical Vapor Deposition (FCVD) process. The Flowable Chemical Vapor Deposition process has good filling ability, which is beneficial to reducing the probability of forming defects such as voids in the isolation material film 112, and correspondingly beneficial to improving the film formation quality of the isolation material film 112.

[0088] Such as Figure 12 shown, taking the top of the mask layer 106 as the planarization stop position, the isolation material film 112, a part of the thickness of the isolation material layer 107 and a part of the thickness of the third epitaxial layer 113 are planarized, and the remaining third epitaxial layer 113 serves as the second channel layer 110.

[0089] In this embodiment, chemical mechanical planarization (CMP) is used for planarization. Chemical mechanical planarization is a global surface planarization technique that can precisely and uniformly polish the third epitaxial layer 113 to the required thickness and flatness, enabling the second channel layer 110 to meet the process requirements.

[0090] Reference Figure 13 , etch a part of the thickness of the isolation material layer 107 to form an isolation layer 114, and the isolation layer 114 covers partial sidewalls of the first channel layer 104 and the second channel layer 110.

[0091] The isolation layer 114 is used for electrically isolating adjacent devices.

[0092] In this embodiment, the material of the isolation layer 114 is an insulating material.

[0093] Specifically, the material of the isolation layer 114 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 114 is silicon oxide.

[0094] In this embodiment, a dry etching process is used to etch a part of the thickness of the isolation material layer 107 to form the isolation layer 114. Using a dry etching process is beneficial for precisely controlling the removal thickness of the isolation material layer 107 and obtaining the isolation layer 114 with the required thickness.

[0095] The method for forming the semiconductor structure further includes: after forming the isolation layer 114, forming a gate structure spanning the first channel layer 104 and the second channel layer 110 and source-drain doping layers in the first channel layer 104 and the second channel layer 110 on both sides of the gate structure, and the gate structure covers partial top walls and partial sidewalls of the first channel layer 104 and the second channel layer 110.

[0096] The method for forming the semiconductor structure further includes: before etching the isolation material layer 107 to form the isolation layer 114, removing the mask layer 106 and the buffer layer 105 on the first channel layer 104.

[0097] Reference Figure 14 and Figure 15 , which shows a schematic structural diagram corresponding to the key steps in the second embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0098] The same parts of this embodiment and the first embodiment will not be elaborated here, and the differences from the first embodiment are as follows:

[0099] Such as Figure 14As shown, in the step of removing the second anti-punchthrough layer 303 and the first channel layer 304 in the first region I and forming a groove 308 in the isolation material layer 307, the first anti-punchthrough layer 302 in the first region I is also removed.

[0100] In the method for forming the semiconductor structure, after the first anti-punchthrough layer 302 is formed and before the first anti-punchthrough layer 302 is removed, generally, the first-type ions in the first anti-punchthrough layer 302 have diffused to the bottom of the first anti-punchthrough layer 302 to form a punchthrough prevention region 311, and the punchthrough prevention region 311 is doped with first-type ions.

[0101] Removing the first anti-punchthrough layer 302 makes the depth of the groove 308 larger, and correspondingly, the space for forming the second channel layer is larger, and the height of the formed second channel layer is larger. When the semiconductor structure operates, the punchthrough prevention region 311 is used to prevent the depletion layers of the source and drain of the source-drain doping layer subsequently formed in the first region I from easily expanding. The larger height of the second channel layer makes the flow region of the channel carriers in the second region II larger, reduces the confinement of the punchthrough prevention region 311 on the carrier flow region, increases the spatial region for carrier flow, and is beneficial to the carrier migration rate.

[0102] In this embodiment, the material of the first channel layer 304 includes silicon germanide, the material of the second anti-punchthrough layer 303 includes silicon germanide doped with second-type ions, and the material of the first anti-punchthrough layer 302 includes silicon germanide doped with first-type ions.

[0103] In this embodiment, a dry etching process is used to remove the first channel layer 304, the second anti-punchthrough layer 303, and the first anti-punchthrough layer 302. The dry etching process has anisotropic etching characteristics and good etching profile controllability, which is beneficial to making the morphology of the groove 308 meet the process requirements. In the process of using the dry etching process to remove the second anti-punchthrough layer 303 and the first channel layer 304, by selecting an appropriate etching gas, the isolation material layer 307 can be made less likely to be damaged, and the formation quality of the groove 308 is better.

[0104] As Figure 15 shown, a second channel layer 310 is formed in the groove 308; a part of the thickness of the isolation material layer 307 is etched to form an isolation layer 314, and the isolation layer 314 covers part of the sidewalls of the first channel layer 304 and the second channel layer 310.

[0105] Correspondingly, referring to Figure 16 , a schematic structural diagram of the first embodiment of the semiconductor structure of the present invention is shown.

[0106] The semiconductor structure includes: a substrate 501, the substrate 501 including a first region I and a second region II; a first fin 500, separated on the substrate 501 in the first region I, the first fin 500 including an anti-punchthrough region 502 and a first channel layer 503 located on the anti-punchthrough region 502, the anti-punchthrough region 502 being doped with first-type ions; a second fin 400, separated on the substrate 501 in the second region II, the second fin 400 including a first anti-punchthrough layer 401 and a second channel layer 402 located on the first anti-punchthrough layer 401, the first anti-punchthrough layer 401 being doped with second-type ions, the conductivity type of the second-type ions being different from that of the first-type ions.

[0107] In an embodiment of the present invention, when the semiconductor structure operates, the anti-punchthrough region 502 in the first region I makes the depletion layers of the source and drain of the source-drain doping layer subsequently formed in the first region I not easily expand, reducing the probability of punchthrough of the source and drain in the first region I. The first anti-punchthrough layer 401 in the second region II makes the depletion layers of the source and drain of the source-drain doping layer subsequently formed in the second region II not easily expand, reducing the probability of punchthrough of the source and drain in the second region II, which is beneficial to improving the electrical performance of the semiconductor structure.

[0108] In this embodiment, the first region I is used to form an NMOS (Negative channel Metal Oxide Semiconductor), and the second region II is used to form a PMOS (Positive Channel Metal Oxide Semiconductor).

[0109] The substrate 501 is used to provide a process platform for subsequently forming the semiconductor structure.

[0110] In this embodiment, the material of the substrate 501 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. An interface layer can also be formed on the surface of the substrate 501, and the material of the interface layer is silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0111] The first region I is used to form NMOS. Subsequently, source-drain doping layers are formed in the first fin 500, and the source-drain doping layers in the first region I serve as the source and drain of the NMOS. When the semiconductor structure operates, the source-drain doping layers apply tensile stress to the channel, and stretching the channel can improve the electron migration rate. Specifically, the source-drain doping layers are doped with N-type ions. The N-type ions replace the positions of silicon atoms in the lattice. The more N-type ions are doped, the higher the concentration of majority carriers, and the stronger the conductivity. Specifically, the N-type ions include one or more of P, As, and Sb.

[0112] In this embodiment, the material of the punch-through prevention region 502 includes silicon germanide doped with first-type ions.

[0113] Specifically, the conductivity type of the first-type ions doped in the punch-through prevention region 502 is different from the conductivity type of the doped ions in the source-drain doping layers in the first region I. The first-type ions are P-type ions. The material of the punch-through prevention region 502 includes silicon germanide doped with P-type ions. The P-type ions include one or more of B, Ga, and In.

[0114] When the semiconductor structure operates, the first channel layer 503 serves as the channel of the first region I. When the semiconductor structure operates, the carriers in the channel of the NMOS are electrons. The material of the punch-through prevention region 502 includes silicon germanide doped with first-type ions, and the material of the first channel layer 503 is silicon. When the semiconductor structure operates, the punch-through prevention region 502 can provide sufficient stress to the first channel layer 503, enabling the carriers in the second channel layer 110 to have a relatively fast migration rate.

[0115] In this embodiment, the punch-through prevention region 502 is located at the bottom of the first fin 500.

[0116] When the semiconductor structure operates, the punch-through prevention region 502 makes it difficult for the depletion layers of the source and drain of the source-drain doping layers subsequently formed in the first region I to expand. The punch-through prevention region 502 is located at the bottom of the first fin 500. Correspondingly, the distance from the punch-through prevention region 502 to the top surface of the isolation layer 504 is relatively large. Correspondingly, the height of the first channel layer 503 is relatively large, such that the flow region of the channel carriers in the second region II is relatively large, reducing the confinement of the punch-through prevention region 502 to the carrier flow region and increasing the spatial region for carrier flow, which is beneficial to the carrier migration rate.

[0117] The second region II is used to form a PMOS. Subsequently, source / drain doping layers are formed in the second fin 400, and the source / drain doping layers in the second region II serve as the source and drain of the PMOS. When the semiconductor structure operates, the source / drain doping layers apply a compressive stress to the channel under the gate structure, and compressing the channel can improve the mobility of holes. Specifically, the source / drain doping layers in the second region II are doped with P-type ions. The P-type ions replace the positions of silicon atoms in the lattice. The more P-type ions are doped, the higher the concentration of majority carriers, and the stronger the conductivity. Specifically, the P-type ions include one or more of B, Ga, and In.

[0118] In this embodiment, the material of the first punch-through prevention layer 401 includes silicon germanide doped with second-type ions.

[0119] Specifically, the conductivity type of the second-type ions doped in the first punch-through prevention layer 401 is different from the conductivity type of the doped ions in the source / drain doping layers in the second region II. The second-type ions are N-type ions. The first punch-through prevention layer 401 includes silicon germanide doped with N-type ions. The N-type ions include one or more of P, As, and Sb.

[0120] When the semiconductor structure operates, the second channel layer 402 serves as the channel of the second region II. When the semiconductor structure operates, the carriers in the channel of the PMOS are holes. Germanium silicon can improve the mobility of channel carriers in the second region II more than silicon, which is beneficial to improving the electrical performance of the semiconductor structure.

[0121] It should be noted that the semiconductor structure further includes: the second punch-through prevention layer 403, which is located between the punch-through prevention region 502 and the first punch-through prevention layer 401.

[0122] The second region II is used to form a PMOS. When the PMOS operates, the migration rate of carriers in the channel is holes. Both the second punch-through prevention layer 403 and the first punch-through prevention layer 401 include germanium silicon. When the semiconductor structure operates, the second punch-through prevention layer 403 can jointly improve the migration rate of carriers in the channel of the second region II with the first punch-through prevention layer 401.

[0123] The semiconductor structure further includes: an isolation layer 504, which is located on the substrate 501 between the first fin 500 and the second fin 400, and the isolation layer 504 covers part of the sidewalls of the first channel layer 503 and the second channel layer 402.

[0124] The isolation layer 504 is used to electrically isolate adjacent devices. The material of the isolation layer 504 is an insulating material.

[0125] Specifically, the material of the isolation layer 504 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 504 is silicon oxide.

[0126] Reference Figure 17 , showing a schematic structural diagram of the second embodiment of the semiconductor structure of the present invention.

[0127] The same parts of this embodiment and the first embodiment will not be described in detail here. The differences from the first embodiment are as follows:

[0128] The semiconductor structure further includes: a second punch-through prevention layer 603, located between the punch-through prevention region 702 and the first channel layer 703, and the second punch-through prevention layer 603 is doped with first-type ions.

[0129] The first region I is used to form an NMOS. The source-drain doping layer in the first region I is doped with N-type ions. The second punch-through prevention layer 603 is doped with first-type ions. The first-type ions include P-type ions, and the conduction type of P-type ions is different from that of N-type ions. When the semiconductor structure operates, the second punch-through prevention layer 603 makes the depletion layers of the source and drain of the first region I not easily expand, reducing the probability of punch-through of the source and drain of the first region I, which is beneficial to improving the electrical performance of the semiconductor structure.

[0130] When the semiconductor structure operates, the second punch-through prevention layer 603 and the punch-through prevention region 702 together make the depletion layers of the source and drain of the first region I not easily expand, reducing the probability of punch-through of the source and drain of the first region I.

[0131] In this embodiment, the material of the second punch-through prevention layer 603 includes silicon germanide doped with first-type ions. The first region I is an NMOS region. When the semiconductor structure operates, the carriers in the channel of the NMOS are electrons. The material of the first channel layer 703 is usually silicon. Therefore, the concentration of Ge in the first channel layer 703 is lower than the concentration of Ge in the second punch-through prevention layer 603. When the semiconductor structure operates, the second punch-through prevention layer 603 can provide sufficient stress to the first channel layer 703 while making the depletion layers of the source and drain of the second region II not easily expand, improving the migration rate of carriers in the first channel layer 703.

[0132] It should be noted that the second anti-punchthrough layer 603 should not be too thick or too thin. If the second anti-punchthrough layer 603 is too thick, it is easy to spend too much process time to form the second anti-punchthrough layer 603, resulting in low formation efficiency of the second anti-punchthrough layer 603. And if the second anti-punchthrough layer 603 is too thick, the height of the corresponding first fin 700 is too large. During the process of etching to form the first fin 700, the first fin 700 is prone to bending or tilting, and the adjacent first fins 700 are prone to bridging, and the quality of the semiconductor structure formed based on the first fin 700 is poor subsequently. If the second anti-punchthrough layer 603 is too thin, the N-type ions in the source-drain doping layer in the second region II diffuse into the entire first anti-punchthrough layer 601 and part of the thickness of the substrate 701. When the semiconductor structure works, the depletion layers of the source and drain of the source-drain doping layer in the second region II are prone to expand, and the source and drain are prone to punchthrough, resulting in the improvement of the electrical performance of the semiconductor structure. In this embodiment, the thickness of the second anti-punchthrough layer 603 is 45 nanometers to 60 nanometers.

[0133] It should be noted that the doping concentration of the first-type ions in the second anti-punchthrough layer 603 should not be too large or too small. If the doping concentration of the first-type ions in the second anti-punchthrough layer 603 is too large, the first-type ions in the second anti-punchthrough layer 603 are prone to diffuse into the first anti-punchthrough layer 601. In this embodiment, the first-type ions have the same conduction type as the doping ions in the source-drain doping layer in the second region II. When the semiconductor structure works, under the combined action of the first-type ions in the first anti-punchthrough layer 601, the depletion layers of the source and drain in the second region II are prone to expand, increasing the probability of punchthrough of the source and drain in the second region II, resulting in poor electrical performance of the semiconductor structure. If the doping concentration of the first-type ions in the second anti-punchthrough layer 603 is too small, when the semiconductor structure works, the second anti-punchthrough layer 603 cannot effectively prevent the expansion of the depletion layers of the source and drain in the first region I, and the source and drain in the first region I are prone to punchthrough, resulting in poor improvement of the electrical performance of the semiconductor structure. In this embodiment, the doping concentration of the first-type ions in the second anti-punchthrough layer 603 is 1.0E20 atoms per cubic centimeter to 1.0E23 atoms per cubic centimeter.

[0134] It should be noted that the concentration of the first-type ions at the bottom of the second anti-punchthrough layer 603 is higher than the concentration of the first-type ions at the top of the second anti-punchthrough layer 603.

[0135] In this embodiment, the conduction type of the first-type ions is the same as that of the doping ions in the source-drain doping layer of the second region II. The doping concentration of the first-type ions at the bottom of the second punch-through prevention layer 603 is higher than that of the first-type ions at the top of the second punch-through prevention layer 603, so that the first-type ions in the second punch-through prevention layer 603 are not easily diffused into the first punch-through prevention layer 601. When the semiconductor structure works, the second anti-diffusion layer 603 makes the depletion layers of the source and drain of the second region II not easily expand, reducing the probability of punch-through of the source and drain, which is beneficial to improving the electrical performance of the semiconductor structure.

[0136] Specifically, the second punch-through prevention layer 603 is a Super Steep Retrograde Nwell (SSRNW).

[0137] The semiconductor structure can be formed by the formation method described in the foregoing embodiment, or can be formed by other formation methods. For the specific description of the semiconductor structure in this embodiment, reference can be made to the corresponding description in the foregoing embodiment, and details are not repeated herein.

[0138] Although the embodiments of the present invention are disclosed as above, the embodiments of the present invention are not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a first region and a second region, the substrate including a substrate and a plurality of fins located on the substrate, the fins including a first punch-through prevention layer, a second punch-through prevention layer located on the first punch-through prevention layer, and a first channel layer located on the second punch-through prevention layer, the first punch-through prevention layer being doped with first-type ions, the second punch-through prevention layer being doped with second-type ions, the conduction types of the first-type ions and the second-type ions being different; Forming an isolation material layer on the substrate exposed by the fins, the isolation material layer covering the sidewalls of the fins; Removing the second punch-through prevention layer and the first channel layer in the first region, and forming a groove in the isolation material layer; Forming a second channel layer in the groove.

2. The method for forming a semiconductor structure as described in claim 1, wherein The method for forming the semiconductor structure further includes: in the step of removing the second punch-through prevention layer and the first channel layer in the first region and forming a groove in the isolation material layer, the first punch-through prevention layer in the first region is also removed.

3. The method for forming a semiconductor structure according to claim 1 or 2, wherein The thickness of the first punch-through prevention layer is 45 nanometers to 60 nanometers.

4. The method for forming a semiconductor structure according to claim 1 or 2, characterized in that, In the step of providing the substrate, the first region is used to form an NMOS, and the second region is used to form a PMOS; The first-type ions are P-type ions, and the second-type ions are N-type ions; The material of the first punch-through prevention layer includes silicon germanide doped with first-type ions.

5. The method for forming a semiconductor structure according to claim 1 or 2, wherein, In the step of providing the substrate, the doping concentration of the first-type ions at the bottom of the first punch-through prevention layer is higher than the doping ion concentration of the first-type ions at the top of the first punch-through prevention layer.

6. The method for forming a semiconductor structure according to claim 1, wherein, A dry etching process is used to remove the second punch-through prevention layer and the first channel layer in the first region.

7. The method for forming a semiconductor structure according to claim 1, wherein, The step of removing the second punch-through prevention layer and the first channel layer in the first region includes: forming a shielding layer covering the fins in the second region and exposing the fins in the first region; Using the shielding layer as a mask, removing the second punch-through prevention layer and the first channel layer in the first region.

8. The method for forming a semiconductor structure according to claim 1, wherein, The step of providing the substrate includes: Providing an initial substrate; Forming a first punch-through prevention material layer on the initial substrate; Forming a second punch-through prevention material layer on the first punch-through prevention material layer; Forming a semiconductor material layer on the second punch-through prevention material layer; Etching the semiconductor material layer, the second punch-through prevention material layer, the first punch-through prevention material layer, and a part of the thickness of the initial substrate to form the substrate.

9. The method for forming a semiconductor structure according to claim 8, wherein, In the step of providing the substrate, the step of forming the first punch-through prevention material layer includes: forming a first epitaxial layer by using a selective epitaxial growth process, and in the step of forming the first epitaxial layer, in-situ doping the first epitaxial layer with first-type ions to form the first punch-through prevention material layer.

10. The method for forming a semiconductor structure according to claim 8, wherein, The process parameters for forming the first punch-through prevention material layer include that the doping dose of the first-type ions in the first punch-through prevention material layer is 1.0E15 atoms per square centimeter to 1.0E18 atoms per square centimeter.

11. The method for forming a semiconductor structure according to claim 8, wherein In the step of providing the substrate, the step of forming the second anti-punchthrough material layer includes: forming a second epitaxial layer by using a selective epitaxial growth process. In the step of forming the second epitaxial layer, the second anti-punchthrough material layer is formed by in-situ doping the second epitaxial layer with second-type ions.

12. The method for forming a semiconductor structure according to claim 1, wherein, The method for forming the semiconductor structure further includes: etching a part of the thickness of the isolation material layer to form an isolation layer that covers part of the sidewalls of the first channel layer and the second channel layer.

13. A semiconductor structure, characterized in that, including: a substrate including a first region and a second region; a first fin disposed on the substrate in the first region. The first fin includes an anti-punchthrough region and a first channel layer located on the anti-punchthrough region, and the anti-punchthrough region is doped with first-type ions. a second fin disposed on the substrate in the second region. The second fin includes a first anti-punchthrough layer and a second channel layer located on the first anti-punchthrough layer. The first anti-punchthrough layer is doped with second-type ions, and the conductivity type of the second-type ions is different from that of the first-type ions.

14. The semiconductor structure according to claim 13, wherein The semiconductor structure further includes: a second anti-punchthrough layer located between the anti-punchthrough region and the first channel layer, and the second anti-punchthrough layer is doped with first-type ions.

15. The semiconductor structure according to claim 14, wherein The second anti-punchthrough layer is also located between the anti-punchthrough region and the first anti-punchthrough layer.

16. The semiconductor structure according to claim 14 or 15, characterized in that, The concentration of the first-type ions at the bottom of the second anti-punchthrough layer is higher than that at the top of the second anti-punchthrough layer.

17. The semiconductor structure according to claim 14 or 15, wherein The thickness of the second anti-punchthrough layer is 45 nanometers to 60 nanometers.

18. The semiconductor structure according to claim 14 or 15, characterized in that, The doping concentration of the first-type ions in the second anti-punchthrough layer is 1.0E20 atoms per cubic centimeter to 1.0E23 atoms per cubic centimeter.

19. The semiconductor structure according to any one of claims 13 to 15, characterized in that, The anti-punchthrough region is located at the bottom of the first fin.

20. The semiconductor structure according to claim 13, wherein, The first region is used to form an NMOS, and the second region is used to form a PMOS; The first-type ions are P-type ions, and the second-type ions are N-type ions; The material of the anti-punchthrough region includes silicon germanide doped with first-type ions.

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