Packaging structure and manufacturing method thereof

Abstract

A packaging structure and a manufacturing method thereof, comprising a chip, a redistribution wiring structure, a molding mold structure, and an electromagnetic interference shielding structure. The redistribution wiring structure is arranged on the chip and forms an electrical connection. The molding mold structure surrounds the chip and the peripheral arrangement of the redistribution wiring structure. The electromagnetic interference shielding structure surrounds the peripheral arrangement of the molding mold structure. The molding mold structure surrounds the chip and the peripheral arrangement of the redistribution wiring structure to provide multi-faceted protection and reinforcement of the structure. The electromagnetic interference shielding structure surrounds the peripheral arrangement of the molding mold structure to provide multi-faceted electromagnetic interference protection for the chip and the redistribution wiring structure. Thereby, the purpose of improving structural strength, reliability and stability in use is achieved.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method, and in particular to a packaging structure and a manufacturing method that can effectively protect the strength of the overall packaging structure and provide anti-electromagnetic interference protection. Background Art

[0002] Traditional chip packaging processes involve forming multiple dicing grooves on the back of a wafer. A molding layer is then placed on the back of the wafer and within the dicing grooves. A redistribution circuit structure is then placed on the front of the wafer. Finally, the wafer is cut into multiple chips along the dicing grooves.

[0003] In traditional chip manufacturing, the molding mold layer is first set, and then the redistribution circuit structure is set, resulting in the inability to effectively protect the outer side of the redistribution circuit structure, making the redistribution circuit structure easily damaged during the subsequent assembly process.

[0004] Furthermore, conventional chips are not designed with any structures to resist electromagnetic interference (EMI), making them susceptible to EMI during subsequent use. Minor EMI may only result in reduced chip performance. However, severe EMI may damage the chip, rendering it unusable. Summary of the Invention

[0005] In view of the above-mentioned problems with the prior art, the main purpose of the present invention is to provide a packaging structure and a manufacturing method thereof. By sequentially disposing a molding layer and an EMI shielding structure around the chip and the redistribution wiring structure disposed on the chip, the structure is protected and strengthened, and the chip and the redistribution wiring structure are shielded from EMI. This improves the structural strength, reliability, and stability of the package.

[0006] In order to achieve the above-mentioned purpose, a packaging structure is provided, which includes: a chip; a redistribution circuit structure, which is arranged on the chip and forms an electrical connection; a molding mold structure, which is arranged around the chip and the redistribution circuit structure; and an electromagnetic interference shielding structure, which is arranged around the molding mold structure.

[0007] Optionally, the molding mold structure includes: a first molding mold layer, which is arranged on multiple outer side surfaces of the chip and multiple outer side surfaces of the redistribution circuit structure; a second molding mold layer, which is arranged on the bottom surface of the chip and connected to the first molding mold layer.

[0008] Optionally, the electromagnetic interference shielding structure includes a first electromagnetic interference shielding layer, which is provided on multiple outer side surfaces of the first molding mold layer, multiple outer side surfaces and a bottom surface of the second molding mold layer.

[0009] Optionally, the molding mold structure includes a first molding mold layer, which is arranged on multiple outer side surfaces of the chip and multiple outer side surfaces of the redistribution circuit structure; the electromagnetic interference shielding structure includes a first electromagnetic interference shielding layer, which is arranged on multiple outer side surfaces of the first molding mold layer.

[0010] Optionally, a plurality of grooves are further provided on the bottom surface of the second molding mold material layer, and the plurality of grooves are filled with the first electromagnetic interference shielding layer.

[0011] Optionally, a plurality of openings penetrating the second molding mold layer are further provided on the second molding mold layer, and the first electromagnetic interference shielding layer fills the plurality of openings and is connected to the bottom surface of the chip.

[0012] Optionally, the molding mold structure includes: a first molding mold layer, which is arranged on multiple outer side surfaces of the chip and multiple outer side surfaces and a top surface of the redistribution circuit structure, and the electrical connection layer arranged on the top surface of the redistribution circuit structure partially exposes the first molding mold layer; a second molding mold layer, which is arranged on the bottom surface of the chip, and the second molding mold layer is connected to the first molding mold layer.

[0013] Optionally, the electromagnetic interference shielding structure includes a first electromagnetic interference shielding layer, which is provided on multiple outer side surfaces of the first molding mold layer, multiple outer side surfaces and a bottom surface of the second molding mold layer.

[0014] Optionally, a plurality of grooves are further provided on the second molding mold material layer, and the first electromagnetic interference shielding layer fills the plurality of grooves.

[0015] Optionally, a plurality of openings penetrating the second molding mold layer are further provided on the second molding mold layer, and the first electromagnetic interference shielding layer fills the plurality of openings and is connected to the chip.

[0016] Optionally, the electromagnetic interference shielding structure includes: a first electromagnetic interference shielding layer, which is arranged on multiple outer side surfaces of the first molding mold layer, multiple outer side surfaces and the bottom surface of the second molding mold layer; a second electromagnetic interference shielding layer, which is arranged on the first molding mold layer on the top surface of the redistribution wiring structure and is separated from the exposed electrical connection layer.

[0017] Optionally, a plurality of grooves are further provided on the second molding mold material layer, and the first electromagnetic interference shielding layer fills the plurality of grooves.

[0018] Optionally, a plurality of openings penetrating the second molding mold layer are further provided on the second molding mold layer, and the first electromagnetic interference shielding layer fills the plurality of openings and is connected to the bottom surface of the chip.

[0019] In order to achieve the above-mentioned purpose, a manufacturing method of a packaging structure is provided, which includes the following steps: providing more than one wafer; forming a redistribution wiring structure on the top surface of the wafer; forming a plurality of first cutting grooves on the wafer and the corresponding redistribution wiring structure to form a plurality of chips provided with corresponding redistribution wiring structures; forming a first molding mold layer in a molding mold structure on the wafer and the corresponding redistribution wiring structure and in the corresponding first cutting grooves; processing from the bottom surface of the wafer to expose the bottom surface of the chip of the wafer and the first molding mold layer formed in the first cutting groove of the wafer, and forming a second molding mold layer in the molding mold structure on the bottom surface of the chip of the wafer and the exposed first molding mold layer; forming a plurality of second cutting grooves along the first molding mold layer formed in the plurality of first cutting grooves in the wafer and the corresponding second molding mold layer to separate the plurality of chips; forming an electromagnetic interference shielding structure around the first molding mold layer and the second molding mold layer on the chip; exposing the redistribution wiring structure on each of the chips.

[0020] Optionally, in the step of exposing the redistribution wiring structure on each of the chips, the first molding mold layer and the corresponding part of the electromagnetic interference shielding structure located on the top surface of the redistribution wiring structure of each of the chips are removed, so that the top surface of the redistribution wiring structure on each of the chips and the electrical connection layer formed on the redistribution wiring structure are exposed.

[0021] Optionally, before the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of grooves are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of grooves to form a heat dissipation structure.

[0022] Optionally, before the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of openings penetrating the second molding mold layer are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected to the bottom surface of the chip.

[0023] Optionally, in the step of exposing the redistribution wiring structure on each of the chips, part of the first molding mold layer and the corresponding part of the electromagnetic interference shielding structure are removed, so that the remaining part of the first molding mold layer covers the top surface of the redistribution wiring structure, and the electrical connection layer formed on the redistribution wiring structure is partially exposed.

[0024] Optionally, before forming the electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of grooves are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of grooves.

[0025] Optionally, before the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of openings penetrating the second molding mold layer are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected to the bottom surface of the chip.

[0026] Optionally, in the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, the first electromagnetic interference shielding layer of the electromagnetic interference shielding structure is formed on multiple outer surfaces of the first molding mold layer on each of the chips and multiple outer side surfaces and the bottom surface of the second molding mold layer on each of the chips; and the second electromagnetic interference shielding layer of the electromagnetic interference shielding structure is formed on the first molding mold layer of the redistribution circuit structure of each of the chips, and is separated from the exposed electrical connection layer.

[0027] Optionally, before the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of grooves are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of grooves to form a heat dissipation structure.

[0028] Optionally, before the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of openings penetrating the second molding mold layer are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected to the bottom surface of the chip.

[0029] Optionally, when there are multiple wafers, the wafers are placed on a temporary carrier plate; corresponding redistribution circuit structures are placed on the top surface of the wafers and electrically connected; multiple first cutting grooves are formed on the wafers and the corresponding redistribution circuit structures to form multiple chips provided with corresponding redistribution circuit structures; the first molding mold layer in the molding mold structure is placed on the wafers and the corresponding redistribution circuit structures and in the corresponding first cutting grooves; the temporary carrier plate is removed, and the bottom surface of each wafer is processed to expose the bottom surface of the chip of each wafer. And a first molding mold layer is arranged in the first cutting groove of each of the wafers, and a second molding mold layer in the molding mold structure is arranged on the bottom surface of the chip of each wafer and the exposed first molding mold layer; a plurality of second cutting grooves are formed along the first molding mold layer and the corresponding second molding mold layer arranged in the plurality of first cutting grooves in each of the wafers to separate the plurality of chips; an electromagnetic interference shielding structure is arranged on the periphery of the first molding mold layer and the second molding mold layer on each of the chips; and the redistribution line structure on each of the chips is exposed.

[0030] According to the above content, by sequentially arranging the molding mold layer and the redistribution wiring structure on the periphery of the chip and the redistribution wiring structure, multi-faceted protection and reinforcement of the structure and multi-faceted electromagnetic interference protection are provided, thereby achieving the purpose of improving structural strength and reliability and stability in use.

[0031] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, this description and the accompanying drawings are only used to illustrate the present invention and are not intended to limit the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the known technology, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0033] Figure 1 FIG. 1 is a schematic diagram of a first embodiment of a packaging structure of the present invention.

[0034] Figure 2 FIG. 4 is a flow chart of a method for manufacturing a package structure according to a first embodiment of the present invention.

[0035] Figure 3A This is a first schematic diagram of the manufacturing process of the first embodiment of the packaging structure of the present invention.

[0036] Figure 3B This is a second schematic diagram of the manufacturing process of the first embodiment of the packaging structure of the present invention.

[0037] Figure 4 This is a third schematic diagram of the manufacturing process of the first embodiment of the packaging structure of the present invention.

[0038] Figure 5 This is a fourth schematic diagram of the manufacturing process of the first embodiment of the packaging structure of the present invention.

[0039] Figure 6 This is a fifth schematic diagram of the manufacturing process of the first embodiment of the packaging structure of the present invention.

[0040] Figure 7 This is a sixth schematic diagram of the manufacturing process of the first embodiment of the packaging structure of the present invention.

[0041] Figure 8 This is the seventh schematic diagram of the manufacturing process of the first embodiment of the packaging structure of the present invention.

[0042] Figure 9 This is an eighth schematic diagram of the manufacturing process of the first embodiment of the packaging structure of the present invention.

[0043] Figure 10 FIG. 1 is a schematic diagram of a second embodiment of a packaging structure of the present invention.

[0044] Figure 11 FIG. 1 is a schematic diagram of a third embodiment of a packaging structure of the present invention.

[0045] Figure 12 FIG. 4 is a schematic diagram of a fourth embodiment of a packaging structure of the present invention.

[0046] Figure 13 FIG. 5 is a schematic diagram of a fifth embodiment of a packaging structure of the present invention.

[0047] Figure 14 FIG. 1 is a schematic diagram of a sixth embodiment of a packaging structure of the present invention.

[0048] Figure 15 FIG. 1 is a schematic diagram of a seventh embodiment of a packaging structure of the present invention.

[0049] Figure 16 FIG. 1 is a schematic diagram of an eighth embodiment of a packaging structure of the present invention.

[0050] Figure 17 FIG. 1 is a schematic diagram of a ninth embodiment of a packaging structure of the present invention.

[0051] Figure 18 FIG. 1 is a schematic diagram of a tenth embodiment of a packaging structure of the present invention.

[0052] Reference numerals

[0053] 10 chips

[0054] 11 Third bottom surface

[0055] 12 Outer side

[0056] 100 wafers

[0057] 101 First Top Surface

[0058] 102 First bottom surface

[0059] 103 First cutting groove

[0060] 104 Second cutting groove

[0061] 20 Rewiring structure

[0062] 21 Dielectric layer

[0063] 211 Second top surface

[0064] 212 Second bottom surface

[0065] 213 outer side

[0066] 22 circuit layer

[0067] 23 Electrical connection layer

[0068] 30 Molding mold material structure

[0069] 31 First molding mold layer

[0070] 311 Fourth Top Surface

[0071] 312 outer side

[0072] 32 Second molding mold layer

[0073] 321 Fourth Bottom

[0074] 322 outer side

[0075] 323 groove

[0076] 323A opening

[0077] 40 Electromagnetic interference shielding structure

[0078] 41 First electromagnetic interference shielding layer

[0079] 42 Second electromagnetic interference shielding layer

[0080] A Temporary load plate

[0081] Steps S51 to S58 DETAILED DESCRIPTION

[0082] Regarding the first embodiment of the packaging structure of the present invention, please refer to Figure 1 As shown, it includes a chip 10, a redistribution circuit structure 20, a molding mold structure 30, and an electromagnetic interference shielding structure 40. The redistribution circuit structure 20 is arranged on the chip 10, and the redistribution circuit structure 20 forms an electrical connection with the chip 10. The molding mold structure 30 is arranged around the chip 10 and the redistribution circuit structure 20. The electromagnetic interference shielding structure 40 is arranged around the molding mold structure 30.

[0083] For the manufacturing method of the packaging structure, please refer to Figure 2 The flowchart shown will be explained in the subsequent content.

[0084] Please refer to Figure 2 、 3A , 3B, as shown Figure 2As shown in step S51 in . One or more wafers 100 are provided. In one example, to improve production efficiency, multiple wafers 100 can be provided at once and placed on a temporary carrier plate A. The temporary carrier plate A can be a printed circuit board (PCB), a glass substrate, a ceramic substrate, or a supporting fixture. In one example, the shape of the wafer 100 placed on the temporary carrier plate A is not limited and can be various shapes, such as a full circle, a semicircle, a quarter circle, etc. This allows wafers 100 of different shapes to be processed at once, significantly improving production efficiency. Furthermore, utilizing traditional PCB manufacturing methods to process subsequent circuit fabrication on the wafer 100 can effectively reduce production costs. Basically, each wafer 100 is composed of a substrate and multiple circuit structures spaced apart on the substrate. The wafer 100 has a first top surface 101 and a first bottom surface 102 opposing each other. In one example, the first top surface 101 is the active surface of the circuit structure on the wafer 100. The first bottom surface 102 is the bottom surface of the substrate of the wafer 100. For ease of explanation, in the following steps, the method of simultaneously producing multiple wafers 100 will be described. However, the production method of a single wafer 100 or multiple wafers 100 is the same. The only difference is that when executing to step S55, since multiple wafers 100 are set on the temporary carrier plate A, the temporary carrier plate A needs to be removed first for the method of simultaneously producing multiple wafers 100. As for the production method of a single wafer 100, since the single wafer 100 is not set on the temporary carrier plate A, there is no need to remove the temporary carrier plate A. In addition, in another example, if necessary, a single wafer 100 can also be set on the temporary carrier plate A to improve the reliability of production, but in the case of this example, the temporary carrier plate A needs to be removed. The specific application method can be selected according to actual needs.

[0085] Please refer to Figure 2 、 3B, as shown in step S52. Corresponding redistribution circuit structures 20 are respectively formed on the first top surfaces 101 of the multiple wafers 100. Each of the redistribution circuit structures 20 includes a plurality of dielectric layers 21 and a plurality of circuit layers 22. The redistribution circuit structure 20 includes a second top surface 211 and a second bottom surface 212 relative to each other. The second bottom surface 212 of the redistribution circuit structure 20 is arranged on the first top surface 101 of the wafer 100. The multiple circuit layers 22 are respectively arranged in the corresponding dielectric layers 21. The multiple circuit layers 22 are respectively electrically connected to the circuit structures of the wafer 100. In addition, part of the circuit layer 22 is exposed to the second top surface 211 of the redistribution circuit structure 20. In addition, an electrical connection layer 23 is provided on the second top surface 211 of the redistribution circuit structure 20. The electrical connection layer 23 is electrically connected to the circuit layer 22 of the redistribution circuit structure 20 that exposes the corresponding dielectric layer 21.

[0086] The second top surface 211 of the redistribution circuit structure 20 is the top surface of the outermost dielectric layer 21 . The second bottom surface 212 of the redistribution circuit structure 20 is the bottom surface of the dielectric layer 21 in contact with the wafer 100 .

[0087] In one example, the electrical connection layer 23 includes a plurality of solder balls, which provide a better electrical connection effect when used for subsequent electrical connection.

[0088] Typically, the contact area of the circuit structure on the wafer 100 is small and difficult to connect. By using the circuit layer 22 of the redistributed circuit structure 20 as an extended circuit, the expandability, accuracy, and reliability of the circuit connection can be improved.

[0089] After setting up the plurality of redistribution line structures 20, please refer to Figure 2 、 4 As shown in step S53, a plurality of first cutting grooves 103 are formed on the plurality of wafers 100 and the corresponding redistribution wiring structures 20. The plurality of first cutting grooves 103 are formed by extending a depth from the second top surface 211 of the redistribution wiring structure 20 toward the first bottom surface 102 of the wafer 100. In one example, the plurality of first cutting grooves 103 can be formed by a laser cutting method or a hub-type cutting method.

[0090] After forming the plurality of first cutting grooves 103, since the plurality of first cutting grooves 103 only extend to a certain depth of the wafer 100, a plurality of the above-mentioned chips 10 that have not yet been separated and a corresponding redistribution circuit structure 20 are formed on each of the wafers 100. Each of the chips 10 has a first top surface 101 that is the same as the corresponding wafer 100, a third bottom surface 11 (the passive surface of the chip 10) connected to the wafer 100, and a plurality of exposed outer side surfaces 12. Each chip 10 on the wafer 100 has a corresponding redistribution circuit structure 20, so the circuit structure of each chip 10 is electrically connected to the corresponding redistribution circuit structure 20.

[0091] The redistribution circuit structure 20 is arranged on the first top surface 101 of the wafer 100 in an entire surface manner, and the chips 10 of the wafer 100 respectively have corresponding circuit layers 22. There will be no circuit layer 22 in the area other than the multiple chips 10. In other words, there will be no circuit layer 22 in the area corresponding to where the multiple first cutting grooves 103 are to be formed. After the multiple first cutting grooves 103 are formed, the redistribution circuit structure 20 on each of the chips 10 also includes multiple exposed outer side surfaces 213, that is, the outer side surfaces of the corresponding dielectric layer 21.

[0092] The outer side surface 213 of the redistribution wiring structure 20 corresponds to the outer side surface 12 of the connected chip 10. In one example, the chip 10 may be in the shape of a rectangular parallelepiped or a cube. The redistribution wiring structure 20 disposed on the chip 10 also corresponds to a rectangular parallelepiped or a cube. In one example, the outer side surface 12 of the chip 10 includes four faces. The outer side surface 213 of the redistribution wiring structure 20 disposed on the chip 10 includes four faces.

[0093] After forming the plurality of first cutting grooves 103, please refer to Figure 2 、 4 , 5. As shown in step S54, the first molding mold layer 31 in the molding mold structure 30 is formed on each of the wafers 100 and the corresponding redistribution circuit structure 20 and in the corresponding first cutting groove 103. The first molding mold layer 31 covers the outer side surface 12 of the chip 10 of the wafer 100, the outer side surface 213, the second top surface 211 and the electrical connection layer 23 of the corresponding redistribution circuit structure 20, and fills the corresponding first cutting groove 103. In one example, the first molding mold layer 31 can be an epoxy molding mold (Epoxy molding Compound) or the like, but is not limited thereto.

[0094] Please refer to Figure 2 、 5, 6, and 7, as shown in step S55. The temporary carrier plate A is removed, and the first bottom surface 102 of each of the wafers 100 is processed to expose the third bottom surface 11 of the chip 10 of each wafer 100 and the first molding mold layer 31 formed in the first cutting groove 103 on each of the wafers 100. The second molding mold layer 32 in the molding mold structure 30 is formed on the third bottom surface 11 of each of the chips 10 and the exposed first molding mold layer 31. The first molding mold layer 31 and the second molding mold layer 32 are connected to form the molding mold structure 30.

[0095] In one example, the treatment performed on the first bottom surface 102 of the wafer 100 may be a grinding method. Through the grinding method, a portion of the substrate of the wafer 100 is removed, temporarily separating the chips 10 of each wafer 100 into individual pieces, and exposing the surface of the first molding layer 31 disposed within the plurality of first dicing grooves 103 corresponding to the third bottom surface 11 of the chips 10. Because the chips 10 are secured by the corresponding first molding layer 31 and second molding layer 32, they are not yet separated from each other.

[0096] In one example, the second molding material layer 32 of the molding material structure 30 may be an epoxy molding compound, but is not limited thereto.

[0097] Please refer to Figure 2 、 7 , 8, as shown in step S56. A plurality of second cutting grooves 104 are formed on the first molding mold layer 31 and the corresponding second molding mold layer 32 in the plurality of first cutting grooves 103 formed in each of the wafers 100 to separate the plurality of chips 10. In one example, the plurality of second cutting grooves 104 can be formed by a laser cutting method or a hub-type cutting method. When the plurality of chips 10 are separated, the first molding mold layer 31 and the second molding mold layer 32 are also separated. So that each of the chips 10 is respectively provided with a corresponding redistribution circuit structure 20, a corresponding first molding mold layer 31 and a corresponding second molding mold layer 32. In one example, a width of the second cutting groove 104 is smaller than a width of the first cutting groove 103.

[0098] In the above example, the first molding material layer 31 has an exposed fourth top surface 311 and a plurality of exposed outer side surfaces 312 . The second molding material layer 32 has an exposed fourth bottom surface 321 and a plurality of exposed outer side surfaces 322 .

[0099] Please refer to Figure 2 、 9As shown in step S57, an electromagnetic interference shielding structure 40 is formed on the periphery of the first molding mold layer 31 and the second molding mold layer 32 on each of the chips 10. For simplicity, only one chip 10 is shown and described in the drawings. Before setting the electromagnetic interference shielding structure 40, Figure 8 The separated chips 10 are placed on a temporary tape and are removed from the temporary tape after the EMI shielding structure 40 is set. This part is omitted in the figure.

[0100] The EMI shielding structure 40 includes a first EMI shielding layer 41 . The first EMI shielding layer 41 is disposed on the outer side surface 312 of the first molding material layer 31 and the fourth bottom surface 321 and outer side surface 322 of the second molding material layer 32 .

[0101] The electromagnetic interference shielding structure 40 may be made of a metal material. In one example, the metal material includes but is not limited to copper, nickel, and gold.

[0102] Please refer to Figure 1 、 2 As shown in FIG. 9 , after the electromagnetic interference shielding structure 40 is set, as shown in step S58 , the second top surface 211 of the redistribution circuit structure 20 and the electrical connection layer 23 on each of the chips 10 are exposed to the first molding mold layer 31 .

[0103] In one example, the first molding mold layer 31 and a corresponding portion of the first electromagnetic interference shielding layer 41 on the second top surface 211 of the redistribution wiring structure 20 are removed by dry etching (plasma etching) or the like, so that the first molding mold layer 31 is exposed from the second top surface 211 of the redistribution wiring structure 20 and a portion of the electrical connection layer 23.

[0104] For the structure of the first embodiment, the redistribution circuit structure 20 is arranged on the first top surface 101 of the chip 10. The molding mold structure 30 is arranged on the outer side surface 12 and the third bottom surface 11 of the chip 10, and is arranged on the outer side surface 213 of the redistribution circuit structure 20. That is, the first molding mold layer 31 of the molding mold structure 30 is arranged on the outer side surface 213 of the redistribution circuit structure 20 and the outer side surface 12 of the chip 10. The second molding mold layer 32 of the molding mold structure 30 is arranged on the third bottom surface 11 of the chip 10. The first electromagnetic interference shielding layer 41 of the electromagnetic interference shielding structure 40 is arranged on the outer side surface 312 of the first molding mold layer 31, and on the fourth bottom surface 321 and the outer side surface 322 of the second molding mold layer 32.

[0105] For the second embodiment of the package structure, please refer to Figure 10As shown, the second embodiment is substantially the same as the above embodiment. In the second embodiment, the second molding mold layer 32 is removed, as well as a portion of the first EMI shielding layer 41 disposed on the outer side surface 322 and the fourth bottom surface 321 of the second molding mold layer 32, to expose the third bottom surface 11 of the wafer 100, the surface of the first molding mold layer 31 corresponding to the third bottom surface 11 of the wafer 100, and the surface of the first EMI shielding layer 41 corresponding to the third bottom surface 11 of the wafer 100. This embodiment provides four-sided protection for the package structure.

[0106] Regarding the third embodiment of the packaging structure of the present invention, please refer to Figure 11 As shown. The third embodiment is substantially the same as the first embodiment described above. In the third embodiment, before the electromagnetic interference shielding structure 40 is provided, a plurality of grooves 323 are further formed on the fourth bottom surface 321 of the second molding mold layer 32. When the first electromagnetic interference shielding layer 41 of the electromagnetic interference shielding structure 40 is provided, the first electromagnetic interference shielding layer 41 covers and fills the plurality of grooves 323 to form a plurality of heat dissipation structures. Since the first electromagnetic interference shielding layer 41 is very close to the third bottom surface 11 of the chip 10 through the plurality of grooves 323, the heat energy of the chip 10 can also be dissipated outward through the first electromagnetic interference shielding layer 41.

[0107] Regarding the fourth embodiment of the packaging structure of the present invention, please refer to Figure 12 As shown, the fourth embodiment is substantially the same as the above embodiments. In the fourth embodiment, before the electromagnetic interference shielding structure 40 is provided, a plurality of openings 323A penetrating the second molding mold layer 32 are further formed on the fourth bottom surface 321 of the second molding mold layer 32. When the first electromagnetic interference shielding layer 41 of the electromagnetic interference shielding structure 40 is provided, the first electromagnetic interference shielding layer 41 covers and fills the plurality of openings 323A. The first electromagnetic interference shielding layer 41 is made to contact the third bottom surface 11 of the chip 10 through the plurality of openings 323A to form a plurality of heat dissipation structures. In this example, the first electromagnetic interference shielding layer 41 is not electrically connected to the chip 10. The heat energy of the chip 10 can be dissipated outward through the first electromagnetic interference shielding layer 41.

[0108] Regarding the fifth embodiment of the packaging structure of the present invention, please refer to Figure 13As shown. The fifth embodiment is substantially the same as the above embodiments. In the fifth embodiment, in step S58, part of the first molding mold layer 31 and the corresponding part of the first electromagnetic interference shielding layer 41 are removed, so that the remaining part of the first molding mold layer 31 covers the second top surface 211 of the redistribution circuit structure 20, and the multiple electrical connection layers 23 are partially exposed to the first molding mold layer 31. In addition, the first electromagnetic interference shielding layer 41 is flush with the first molding mold layer 31 provided on the second top surface 211 of the redistribution circuit structure 20 to effectively provide anti-electromagnetic interference protection. The chip 10 and the redistribution circuit structure 20 are surrounded by the molding mold structure 30 to provide six-sided protection for the structure.

[0109] In one example, the thickness of the electrical connection layer 23 exposed by the first molding material layer 31 disposed on the second top surface 211 of the redistribution wiring structure 20 is more than half the height of the electrical connection layer 23. This can provide both effective protection and effective connection.

[0110] Regarding the sixth embodiment of the packaging structure of the present invention, please refer to Figure 14 As shown. The sixth embodiment is substantially the same as the fifth embodiment. In the sixth embodiment, before providing the electromagnetic interference shielding structure 40, a plurality of grooves 323 may be further formed on the fourth bottom surface 321 of the second molding mold layer 32. When providing the first electromagnetic interference shielding layer 41 of the electromagnetic interference shielding structure 40, the first electromagnetic interference shielding layer 41 covers and fills the plurality of grooves 323 to form a plurality of heat dissipation structures. Since the first electromagnetic interference shielding layer 41 is very close to the third bottom surface 11 of the chip 10 through the plurality of grooves 323, the heat energy of the chip 10 can also be dissipated outward through the first electromagnetic interference shielding layer 41.

[0111] Regarding the seventh embodiment of the packaging structure of the present invention, please refer to Figure 15 As shown. The seventh embodiment is substantially the same as the fifth embodiment. In the seventh embodiment, before the electromagnetic interference shielding structure 40 is provided, a plurality of openings 323A penetrating the second molding mold layer 32 may be further formed on the fourth bottom surface 321 of the second molding mold layer 32. When the first electromagnetic interference shielding layer 41 of the electromagnetic interference shielding structure 40 is provided, the first electromagnetic interference shielding layer 41 covers and fills the plurality of openings 323A. The first electromagnetic interference shielding layer 41 is made to contact the third bottom surface 11 of the chip 10 through the plurality of openings 323A to form a plurality of heat dissipation structures. In this example, the first electromagnetic interference shielding layer 41 is not electrically connected to the chip 10. The heat energy of the chip 10 can be conducted outwards through the first electromagnetic interference shielding layer 41 for heat dissipation.

[0112] Regarding the eighth embodiment of the package structure of the present invention, please refer to Figure 16 As shown. The eighth embodiment is substantially the same as the fifth embodiment. In the eighth embodiment, a second electromagnetic interference shielding layer 42 of the electromagnetic interference shielding structure 40 is further provided on the first molding mold layer 31 on the second top surface 211 of the redistribution wiring structure 20 and the first electromagnetic interference shielding layer 41. The second electromagnetic interference shielding layer 42 is electrically connected to the first electromagnetic interference shielding layer 41. The second electromagnetic interference shielding layer 42 is spaced apart from the exposed multiple electrical connection layers 23, that is, there is no electrical connection between the two, to avoid signal interference and short circuit. The second electromagnetic interference shielding layer 42 can be a metal material. In one example, metal materials include but are not limited to copper, nickel, and gold. By providing the second electromagnetic interference shielding layer 42, anti-electromagnetic interference protection is provided to the second top surface 211 of the redistribution wiring structure 20, so as to achieve the effect of six-sided anti-electromagnetic interference protection.

[0113] Regarding the ninth embodiment of the packaging structure of the present invention, please refer to Figure 17 As shown. The ninth embodiment is substantially the same as the eighth embodiment. In the eighth embodiment, before providing the electromagnetic interference shielding structure 40, a plurality of grooves 323 may be further formed on the fourth bottom surface 321 of the second molding mold layer 32. When providing the first electromagnetic interference shielding layer 41 of the electromagnetic interference shielding structure 40, the first electromagnetic interference shielding layer 41 covers and fills the plurality of grooves 323 to form a plurality of heat dissipation structures. Since the first electromagnetic interference shielding layer 41 is very close to the third bottom surface 11 of the chip 10 through the plurality of grooves 323, the heat energy of the chip 10 can also be dissipated outward through the first electromagnetic interference shielding layer 41.

[0114] Regarding the tenth embodiment of the package structure of the present invention, please refer to Figure 18 As shown. The tenth embodiment is substantially the same as the eighth embodiment. In the tenth embodiment, before providing the electromagnetic interference shielding structure 40, a plurality of openings 323A penetrating the second molding mold layer 32 may be further formed on the fourth bottom surface 321 of the second molding mold layer 32. When providing the first electromagnetic interference shielding layer 41 of the electromagnetic interference shielding structure 40, the first electromagnetic interference shielding layer 41 covers and fills the plurality of openings 323A. The first electromagnetic interference shielding layer 41 is made to contact the third bottom surface 11 of the chip 10 through the plurality of openings 323A to form a plurality of heat dissipation structures. In this example, the first electromagnetic interference shielding layer 41 is not electrically connected to the chip 10. The heat energy of the chip 10 can be conducted outwards through the first electromagnetic interference shielding layer 41 for heat dissipation.

[0115] According to the above, by placing multiple wafers 100 on the temporary carrier plate A and simultaneously manufacturing the redistribution wiring structure 20 for all wafers 100, production efficiency can be improved. In addition, the molding mold structure 30 provides multi-faceted protection and reinforcement for the chip 10 and the redistribution wiring structure 20. Furthermore, by providing an electromagnetic interference shielding structure 40 on the periphery of the molding mold structure 30 and corresponding to both the chip 10 and the redistribution wiring structure 20, multi-faceted electromagnetic interference protection is provided for the structure. This achieves the purpose of improving structural strength, reliability, and stability.

[0116] In some embodiments, a corresponding heat dissipation structure is formed on the second molding mold layer 32 to enhance the heat dissipation effect and further improve performance.

[0117] In some of the above embodiments, the first molded layer 31 protects the outer side surface 12 of the chip 10, the outer side surface 213 of the redistribution wiring structure 20, and the second molded layer 32 protects the third bottom surface 11 of the chip 10, thereby achieving five-sided protection of the structure. In addition, the first electromagnetic interference shielding layer 41 is provided on the outer side surface 312 of the first molded layer 31, and the fourth bottom surface 321 and outer side surface 322 of the second molded layer 32, thereby also achieving five-sided anti-electromagnetic interference protection.

[0118] Furthermore, in some embodiments, the first molding layer 31 covering the second top surface 211 of the redistribution wiring structure 20 is retained to provide protection for the redistribution wiring structure 20, thereby improving reliability when subsequently connected to a printed circuit board. In these embodiments, six sides of the structure can be protected, namely, the top, bottom, and four outer side surfaces.

[0119] In addition, in some embodiments, a second EMI shielding layer 42 is further provided on the first molding mold layer 31 retained on the second top surface 211 of the redistribution wiring structure 20 to further enhance EMI protection of the redistribution wiring structure 20, or EMI protection during subsequent connection and operation with a corresponding printed circuit board. In these embodiments, six-sided EMI protection can be achieved, namely, the top surface, the bottom surface, and the four outer side surfaces.

[0120] The above descriptions are merely embodiments of the present invention and are not intended to limit the scope of the present invention.

Claims

1. A packaging structure, characterized in that: The packaging structure includes: A chip comprising a first bottom surface and a plurality of first outer side surfaces; a redistribution circuit structure disposed on the chip and electrically connected thereto, the redistribution circuit structure comprising a second top surface and a second bottom surface opposite to each other, and a plurality of second outer side surfaces connecting the second top surface and the second bottom surface, the plurality of first outer sides corresponding to the plurality of second outer side surfaces; A molding mold structure is arranged on the periphery of the chip and the redistribution circuit structure; An electromagnetic interference shielding structure is arranged on the periphery of the molding mold structure; Wherein said forming die material structure comprises: A first molding mold material layer is provided on the plurality of first outer side surfaces of the chip and the plurality of second outer side surfaces of the redistribution circuit structure; a second molding mold layer, disposed on the first bottom surface of the chip and connected to the first molding mold layer; In which, the electromagnetic interference shielding structure includes a first electromagnetic interference shielding layer, which is arranged on multiple outer side surfaces of the first molding mold layer, multiple outer side surfaces and the bottom surface of the second molding mold layer, and the second molding mold layer is provided with multiple grooves or multiple openings passing through the second molding mold layer, wherein the multiple grooves or the multiple openings correspond to the first bottom surface of the chip.

2. The packaging structure according to claim 1, wherein: The first electromagnetic interference shielding layer fills the plurality of grooves.

3. The packaging structure according to claim 1, wherein: The first electromagnetic interference shielding layer fills the plurality of openings and is connected to the bottom surface of the chip.

4. The packaging structure according to claim 1, wherein: The first molding mold layer is also arranged on the top surface of the redistribution circuit structure, and the electrical connection layer arranged on the top surface of the redistribution circuit structure is partially exposed outside the first molding mold layer.

5. The packaging structure according to claim 4, wherein: The first electromagnetic interference shielding layer fills the plurality of grooves.

6. The packaging structure according to claim 4, wherein: The first electromagnetic interference shielding layer fills the plurality of openings and is connected to the chip.

7. The packaging structure according to claim 4, wherein: The electromagnetic interference shielding structure comprises: The second electromagnetic interference shielding layer is arranged on the first molding mold layer on the top surface of the redistribution circuit structure and is separated from the exposed electrical connection layer.

8. The packaging structure according to claim 7, wherein: The first electromagnetic interference shielding layer fills the plurality of grooves.

9. The packaging structure according to claim 7, wherein: The first electromagnetic interference shielding layer fills the plurality of openings and is connected to the bottom surface of the chip.

10. A method for manufacturing a packaging structure, characterized in that: The manufacturing method comprises the following steps: providing more than one wafer; forming a redistribution circuit structure on a top surface of the wafer; forming a plurality of first cutting grooves on the wafer and the corresponding redistribution circuit structures to form a plurality of chips provided with corresponding redistribution circuit structures; forming a first molding mold layer in a molding mold structure on the wafer and the corresponding redistribution circuit structure and in the corresponding first cutting groove; Processing the bottom surface of the wafer to expose the bottom surface of the chip of the wafer and the first molding mold layer formed in the first cutting groove of the wafer, and forming the second molding mold layer in the molding mold structure on the bottom surface of the chip of the wafer and the exposed first molding mold layer; forming a plurality of second cutting grooves along the first molding mold layer formed in the plurality of first cutting grooves in the wafer and on the corresponding second molding mold layer to separate the plurality of chips; forming an electromagnetic interference shielding structure around the first molding mold layer and the second molding mold layer on the chip; The redistribution circuit structure on each chip is exposed.

11. The method for manufacturing a packaging structure according to claim 10, wherein: In the step of exposing the redistribution wiring structure on each of the chips, the first molding mold layer and the corresponding part of the electromagnetic interference shielding structure on the top surface of the redistribution wiring structure of each of the chips are removed, so that the top surface of the redistribution wiring structure on each of the chips and the electrical connection layer formed on the redistribution wiring structure are exposed.

12. The method for manufacturing a packaging structure according to claim 11, wherein: Before the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of grooves are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of grooves to form a heat dissipation structure.

13. The method for manufacturing a packaging structure according to claim 11, wherein: Before the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of openings penetrating the second molding mold layer are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected to the bottom surface of the chip.

14. The method for manufacturing a packaging structure according to claim 10, wherein: In the step of exposing the redistribution wiring structure on each chip, part of the first molding mold layer and the corresponding part of the electromagnetic interference shielding structure are removed, so that the remaining part of the first molding mold layer covers the top surface of the redistribution wiring structure, and the electrical connection layer formed on the redistribution wiring structure is partially exposed.

15. The method for manufacturing a packaging structure according to claim 14, wherein: Before the step of setting an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of grooves are formed on the second molding mold layer; when the electromagnetic interference shielding structure is set, the electromagnetic interference shielding structure fills the plurality of grooves.

16. The method for manufacturing a packaging structure according to claim 14, wherein: Before the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of openings penetrating the second molding mold layer are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected to the bottom surface of the chip.

17. The method for manufacturing a package structure according to claim 14, wherein: In the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, the first electromagnetic interference shielding layer of the electromagnetic interference shielding structure is formed on multiple outer surfaces of the first molding mold layer on each of the chips and multiple outer side surfaces and the bottom surface of the second molding mold layer on each of the chips; and the second electromagnetic interference shielding layer of the electromagnetic interference shielding structure is formed on the first molding mold layer of the redistribution circuit structure of each of the chips, and is separated from the exposed electrical connection layer.

18. The method for manufacturing a package structure according to claim 17, wherein: Before the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of grooves are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of grooves to form a heat dissipation structure.

19. The method for manufacturing a package structure according to claim 17, wherein: Before the step of forming an electromagnetic interference shielding structure on the periphery of the first molding mold layer and the second molding mold layer on each of the chips, a plurality of openings penetrating the second molding mold layer are formed on the second molding mold layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected to the bottom surface of the chip.

20. The method for manufacturing a package structure according to claim 10, wherein: When there are multiple wafers; placing the plurality of wafers on a temporary carrier; Disposing corresponding redistribution circuit structures on top surfaces of the plurality of wafers and forming electrical connections; forming the plurality of first cutting grooves on the plurality of wafers and the corresponding redistribution circuit structures to form a plurality of chips provided with the corresponding redistribution circuit structures; Disposing a first molding mold layer in the molding mold structure on the plurality of wafers and the corresponding redistribution circuit structures and in the corresponding first cutting grooves; Removing the temporary carrier plate and processing the bottom surface of each wafer to expose the bottom surface of the chip of each wafer and the first molding mold layer disposed in the first dicing groove of each wafer, and disposing the second molding mold layer in the molding mold structure on the bottom surface of the chip of each wafer and the exposed first molding mold layer; forming a plurality of second cutting grooves along the first molding mold layer and the corresponding second molding mold layer in each of the wafers disposed in the plurality of first cutting grooves to separate the plurality of chips; An electromagnetic interference shielding structure is provided on the periphery of the first molding mold layer and the second molding mold layer on each of the chips; The redistribution circuit structure on each chip is exposed.

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