Semiconductor device and corresponding method for manufacturing the same

Abstract

Various embodiments of the present disclosure relate to semiconductor devices and corresponding methods for manufacturing semiconductor devices. A packaged semiconductor device includes a substrate having a first surface and a second surface, the second surface being opposite the first surface. At least one semiconductor die is mounted on the first surface of the substrate. Conductive leads are arranged around the substrate, and conductive structures couple the at least one semiconductor die to selected leads of the conductive leads. An encapsulation molding material is molded onto the at least one semiconductor die, the conductive leads, and the conductive structures. The encapsulation molding material leaves the second surface of the substrate uncovered by the encapsulation molding material. The substrate is formed from a layer of electrically insulating material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102020000023122, filed on September 30, 2020, which is hereby incorporated by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] The present description relates to packaged semiconductor devices for high voltage (HV) applications.

[0004] In particular, embodiments described herein may relate to packaged semiconductor devices including flat no-lead packages, such as quad flat no-lead (QFN) packages or dual flat no-lead (DFN) packages. Background Art

[0005] Conventional flat no-lead packages for semiconductor devices include a metal leadframe. The name "leadframe" (or "leadframe") is currently used (e.g., see the USPTO's USPC Comprehensive Glossary) for a metal frame that provides support for one or more integrated circuit chips or dies (e.g., providing a so-called "die pad") and electrical leads that interconnect the integrated circuit(s) in the chip(s) or die to other electrical components or contacts (e.g., via a printed circuit board (PCB)).

[0006] In a flat no-lead package, such a metal leadframe may therefore include one or more die pads and a plurality of flat leads incorporated into a molded plastic (e.g., a resin material such as epoxy). The die pad(s) and flat leads are exposed on the back side (e.g., bottom side) of the package to provide electrical and / or thermal conductivity toward a printed circuit board.

[0007] A power converter (e.g., an AC-DC or DC-DC power converter) may use a half-bridge topology with MOS field-effect transistors for low-voltage applications and insulated gate bipolar transistors (IGBTs) or silicon carbide (SiC) transistors or gallium nitride (GaN) transistors for high-voltage applications (e.g., involving voltages greater than 200 V). Power conversion may be implemented in a switching mode using a phase wave modulation (PWM) mode.

[0008] In modern power converters, high switching frequencies may be required to improve the efficiency of the converter, but parasitic impedances between the (gate) driver integrated circuit and the control (gate) terminal of the IGBT / MOSFET may set an upper limit on the switching frequency. Therefore, the overall performance of the converter may benefit from physically placing the gate driver circuit close to (e.g., as close as possible) the IGBT / MOSFET die to reduce the corresponding parasitic inductance. Therefore, flat leadless packages can be used to package power converters (e.g., AC-DC or DC-DC converters) that include gate driver circuits (or dies) and MOS / IGBT / SiC / GaN transistor circuits (or dies) in a multi-chip (or multi-die) configuration.

[0009] As is conventional in the art, the drain terminal or collector terminal of the MOS / SiC / GaN / IGBT transistor may be provided on the silicon backside so that it can be electrically connected to the corresponding die pad of the lead frame. Therefore, providing electrical insulation between the high-side transistor and the low-side transistor of the half-bridge may involve positioning the corresponding die pads in the multi-chip package at a certain distance (e.g., a safe distance) when the multi-chip semiconductor device is mounted on a printed circuit board to match certain insulation requirements, e.g., with respect to clearance distance and / or creepage distance.

[0010] As is known in the art, the gap distance can be defined as the shortest distance between two conductive components measured through air. The gap distance helps prevent dielectric breakdown between electrodes caused by air ionization.

[0011] As is known in the art, creepage distance can be defined as the shortest path between two conductive parts on an insulator, measured along the surface of the insulator. Adequate and sufficient creepage distance can prevent tracking, a process in which a partially conductive path on the surface of an insulating material is locally degraded due to discharges on or near the insulating surface.

[0012] It should be noted that because the back side (eg, bottom side) of the flat no-leads package where the die pad and leads are exposed is substantially flat, the clearance distance and creepage distance can be substantially the same in the flat no-leads package.

[0013] For example, a power QFN multi-chip half-bridge converter operating at 48V may involve 0.65mm (1mm=10 -3m) gap distance between the different die pads, and a gap distance of 1.05 mm between different die pads. Similarly, a power QFN multi-chip half-bridge converter operating at 650 V (e.g., for industrial applications) may involve a gap distance of 2.1 mm between different die pads. A power QFN multi-chip half-bridge converter operating at 1200 V (e.g., for industrial applications) may involve a gap distance of 4 mm between different die pads.

[0014] As a result, the size of quad flat no-lead (e.g., QFN) packages used in high voltage applications (e.g., high voltage AC-DC or DC-DC converters) may become larger, resulting in associated increased cost, reduced board-level reliability, and increased parasitic inductance on the wires.

[0015] Therefore, there may be a need for an improved flat no-lead package for high voltage semiconductor devices.There is a need in the art for solutions that help provide such improvements. Summary of the Invention

[0016] Embodiments disclosed herein relate to semiconductor devices.

[0017] Embodiments disclosed herein relate to corresponding methods of fabricating semiconductor devices.

[0018] According to one or more embodiments, a semiconductor device includes: a substrate having a first surface and a second surface, the second surface opposite the first surface; at least one semiconductor die mounted on the first surface of the substrate; a plurality of conductive leads arranged around the substrate; a plurality of conductive structures coupling the at least one semiconductor die to selected ones of the plurality of conductive leads; and an encapsulation molding material molded onto the at least one semiconductor die mounted on the first surface of the substrate, the plurality of conductive leads, and the plurality of conductive structures, leaving the second surface of the substrate uncovered by the encapsulation molding material. The substrate may include a layer of electrically insulating material.

[0019] Thus, one or more embodiments may not be constrained by design requirements related to creepage and / or clearance of exposed pads of packaged semiconductor devices and may result in smaller and / or less expensive packages. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0021] Figure 1 is an example of a plan view of the back side (eg, bottom side) of a semiconductor device packaged in a QFN package,

[0022] Figure 2is a simplified circuit block diagram example of certain components of a power conversion circuit according to one or more embodiments of the present specification,

[0023] Figure 3 is an example of a front view (eg, top view) of certain components of a semiconductor device according to one or more embodiments of this specification, and

[0024] Figures 4A to 4E are examples of respective steps of a method of manufacturing a semiconductor device according to one or more embodiments of this specification. DETAILED DESCRIPTION

[0025] In the following description, one or more specific details are provided to provide a deeper understanding of the examples of the embodiments of the present disclosure. These embodiments can be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not described or illustrated in detail so as not to obscure certain aspects of the embodiments.

[0026] References to "an embodiment" or "one embodiment" in the context of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more places in this specification do not necessarily refer to one and the same embodiment. Furthermore, in one or more embodiments, the particular configurations, structures, or characteristics may be combined in any suitable manner.

[0027] The headings / references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0028] For simplicity, in all the drawings attached hereto, the same parts or elements are represented by the same reference numerals / numbers. For the sake of brevity, the corresponding description of each figure will not be repeated.

[0029] By way of introduction to a detailed description of exemplary embodiments, reference may first be made to Figure 1 .

[0030] Figure 1 FIG2 is an example plan view of the back side (e.g., bottom side) of a semiconductor device 10 including a QFN package. Specifically, the semiconductor device 10 may include a system-in-package (SiP) for power conversion that includes a half-bridge gate driver circuit and high-voltage enhancement-mode GaN transistors arranged in a half-bridge configuration.

[0031] like Figure 1As illustrated, the semiconductor device 10 may include a square QFN package, for example, having dimensions of 9 x 9 mm. The semiconductor device 10 may include a lead frame including a set of die pads P1, P2, and P3 and a set of flat leads L and L', which are encapsulated in molded plastic MC and exposed on the back side (e.g., bottom side) of the semiconductor device 10.

[0032] By way of example only, die pad P1 can be electrically coupled to a ground terminal or a reference voltage terminal of semiconductor device 10, die pad P2 can be electrically coupled to a source terminal or an emitter terminal of a low-side transistor of a half-bridge (e.g., a half-bridge sense terminal), and die pad P3 can be electrically coupled to a source terminal or an emitter terminal of a high-side transistor of the half-bridge (i.e., an intermediate node of the half-bridge arrangement that provides an output voltage of semiconductor device 10).

[0033] By way of example only, the flat lead L may provide one or more input terminals and / or output terminals (e.g., including both analog and digital input terminals and / or output terminals, such as terminals for a bootstrap supply voltage, a logic supply voltage, a high-side driver logic input, a low-side driver logic input, etc.) of the semiconductor device 10. Still by way of non-limiting example, the flat lead L′ may provide a high voltage supply applied to the drain or collector of the high-side transistor of the half-bridge.

[0034] The semiconductor device 10 can be operated as a high-voltage power converter, that is, a voltage of several hundred volts (eg, 650 V) can be applied to the lead L' coupled to the drain or collector of the high-side transistor of the half-bridge. Figure 1 As shown, the creepage distance D1 between the die pad P1 and the die pad P3, the creepage distance D2 between the die pad P2 and the die pad P3, and the creepage distance D3 between the die pad P3 and the lead L' may be subject to certain design requirements, for example, equal to or greater than 2.1 mm.

[0035] It should be noted that the die pads P1, P2, P3 can be electrically coupled (for example, by means of bonding wires arranged inside the molded plastic MC) to some of the leads L, so that electrical connection of the semiconductor device 10 to the printed circuit board can be achieved even without conductivity through the die pads P1, P2, P3.

[0036] Thus, one or more embodiments of the present disclosure may provide a semiconductor device packaged in a flat no-lead package, wherein a die pad is electrically insulated from a semiconductor die or chip encapsulated in molded plastic. As a result, the die pad may not be subject to design constraints regarding adherence to creepage and / or clearance distances.

[0037] For example, Figure 2is a simplified circuit block diagram example of certain components of the power conversion circuit 20 in which one or more embodiments may be applied.

[0038] like Figure 2 As illustrated in FIG, the power conversion circuit 20 may include a half-bridge arrangement including a high-side transistor HST and a low-side transistor LST, such as an insulated gate bipolar transistor (IGBT). The high-side transistor HST has a high voltage power supply node 200a (e.g., configured to receive a high voltage positive power supply V POS ) and the output node 200b (eg, configured to provide a half-bridge output voltage V OUT The low-side transistor LST has a current path between the output node 200b and the half-bridge sensing node 200c (eg, configured to receive a high voltage negative power supply or a reference power supply V NEG The current path between the nodes).

[0039] like Figure 2 As illustrated in , the power conversion circuit 20 may include a high-side diode HSD coupled in parallel with the high-side transistor HST, and a low-side diode LSD coupled in parallel with the low-side transistor LST. For example, the high-side diode HSD may have an anode terminal coupled to the emitter terminal or source terminal of the high-side transistor HST (e.g., at the output node 200 b), and a cathode terminal coupled to the collector terminal or drain terminal of the high-side transistor HST (e.g., at the high-voltage power supply node 200 a), and the low-side diode LSD may have an anode terminal coupled to the emitter terminal or source terminal of the low-side transistor LST (e.g., at the half-bridge sense node 200 c), and a cathode terminal coupled to the collector terminal or drain terminal of the low-side transistor LST (e.g., at the output node 200 b).

[0040] like Figure 2 As illustrated in FIG, the power conversion circuit 20 may include a high-side driver circuit 202a configured to receive one or more high-side input control signals HS at one or more input nodes 204a. in and correspondingly drives the (gate) control terminal of the high-side transistor HST; and a low-side driver circuit 202b, which is configured to receive one or more low-side input control signals LS at one or more input nodes 204b. in And correspondingly drives the (gate) control terminal of the low-side transistor LST.

[0041] In one or more embodiments, the transistors HSD, LSD, the diodes HSD, LSD and the driver circuits 202a, 202b may be implemented in (physically) separate or different semiconductor chips or dies and may be integrated in a system such as a semiconductor device. Figure 3 In the multi-chip semiconductor device exemplified in Figure 3 is a diagram illustrating various components of a semiconductor device 30 (eg, power conversion circuit 20 ) according to one or more embodiments.

[0042] By way of example only, Figure 3 The semiconductor device 30 shown may be integrated in a rectangular flat no-lead package having dimensions of 17×20 mm. The semiconductor device 30 may include a power conversion circuit 20 that operates at a voltage of 1200 V and a current of 40 A in a steady state.

[0043] In one or more embodiments, the chips or dies (eg, HST, LST, HSD, LSD, 202 a , 202 b ) of the multi-chip semiconductor device 30 may be provided on an electrically insulating substrate 300 .

[0044] like Figure 3 As illustrated in FIG, a single electrically insulating substrate 300 carrying a plurality of dies may be provided in the semiconductor device 30.

[0045] Alternatively, multiple electrically insulating substrates may be provided in the semiconductor device 30 , for example, up to a respective electrically insulating substrate for each die in the semiconductor device 30 .

[0046] In one or more embodiments, the electrically insulating substrate(s) may include a ceramic substrate. The ceramic material may include, for example, oxide and / or nitride materials, such as aluminum oxide (Al2O3) and / or silicon nitride (Si3N4).

[0047] In one or more embodiments, the thickness of the insulating substrate(s) may be in the range of 100 μm to 1.27 mm, for example about 0.25 mm.

[0048] In one or more embodiments, the conventional metal die pad(s) of the lead frame of the flat leadless package may be replaced by an electrically insulating substrate(s) 300, i.e., the metal lead frame may include only leads (e.g., 200a, 200b, 200c, 204a, 204b).

[0049] Alternatively, the leadframe of the flat no-lead package may include at least one metal die pad, and the electrically insulating substrate(s) 300 may be attached to the at least one metal die pad. For example, the at least one metal die pad may include a single metal die pad (e.g., a central die pad) or a plurality of metal die pads, up to a respective metal die pad for each die in the semiconductor device 30, wherein each of the metal die pads has a respective electrically insulating substrate attached thereto.

[0050] exist Figure 3 In one or more embodiments illustrated in , the electrically insulating substrate(s) 300 may have a patterned layer of conductive material (e.g., copper) provided on a first surface thereof (e.g., an upper surface or top surface on which the semiconductor die is arranged). Such a patterned layer of conductive material may include (separate) die attach areas configured to carry semiconductor dies (e.g., HST, LST, HSD, LSD, 202 a, 202 b) and conductive traces configured to route electrical signals (e.g., to achieve electrical connections) between different semiconductor dies and / or between a semiconductor die and leads of a leadframe.

[0051] For example, in one or more embodiments, a continuous metal region 302a extending below the high-side transistor HST and the high-side diode HSD can be patterned on the electrically insulating substrate 300, thereby providing a means for electrically coupling the drain or collector of the high-side transistor HST to the cathode of the high-side diode HSD without the use of a bond wire. In addition, the continuous metal region 302a can be electrically coupled to the lead 200a by means of a bond wire 304a to receive the high-voltage positive power supply V POS .

[0052] Similarly, in one or more embodiments, a continuous metal region 302b extending below the low-side transistor LST and the low-side diode LSD can be patterned on the electrically insulating substrate 300, thereby providing a means for electrically coupling the drain or collector of the low-side transistor LST to the cathode of the low-side diode LSD without the use of a bond wire. In addition, the continuous metal region 302b can be electrically coupled to the lead 200b by means of a bond wire 304b to provide the half-bridge output voltage V OUT .

[0053] In one or more embodiments, the patterned layer of electrically conductive material provided on the first surface (eg upper or top surface) of the electrically insulating substrate(s) 300 may include one or more traces for routing one or more signals.

[0054] For example, Figure 3As shown, a set of traces 306 a can be configured to route signals between the input lead and / or the output lead 204 a and the high-side driver circuit 202 a. In particular, each of the traces 306 a can include a first end bonded to a corresponding lead 204 a (e.g., via a bond wire) and a second end bonded to a corresponding bond pad provided on the high-side driver circuit 202 a (e.g., via a bond wire).

[0055] Similarly, if Figure 3 As shown, the set of traces 306b can be configured to route signals between the input lead and / or the output lead 204b and the low-side driver circuit 202b. In particular, each trace in the traces 306b can include a first end bonded to the corresponding lead 204b (e.g., via a bond wire) and a second end bonded to a corresponding bond pad provided on the low-side driver circuit 202b (e.g., via a bond wire).

[0056] Thus, one or more embodiments can facilitate providing electrical connections between input pads and / or output pads of a semiconductor device and a semiconductor die encapsulated therein, provided that direct wire bonds between the leads and the semiconductor die can be replaced by routing via patterned traces on (multiple) electrically insulating substrates 300, which can provide increased design flexibility and reduced parasitic inductance.

[0057] In one or more embodiments, the electrically insulating substrate(s) 300 may have a conductive material layer (e.g., a copper layer) provided on a second surface (e.g., a lower surface or bottom surface) of the electrically insulating substrate(s) 300 opposite to the first surface. For example, the conductive material layer provided at the second surface may include a single (large) pad or a plurality of pads configured for soldering the packaged semiconductor device to a printed circuit board. In one or more embodiments, the thickness of such a conductive material layer may be in the range of 10 μm to 500 μm.

[0058] In one or more embodiments, patterned layer(s) of conductive material may be provided on the first surface (e.g., upper surface) and / or the second surface (e.g., lower surface) of the electrically insulating substrate(s) 300 by means of techniques such as direct bonded copper (DBC) or direct plated copper (DPC).

[0059] Thus, one or more embodiments may provide an insulating substrate in a flat no-lead (e.g., QFN) package to provide electrical insulation between the semiconductor die and the external die pads. The insulating substrate may be completely embedded in the molded plastic, and the package may enclose various high-voltage dies and drivers. The exposed pads (multiple) may thus be electrically insulated, so that creepage / clearance regulations may apply only to high-voltage leads, such as leads 200a, 200c that provide a connection to a high-voltage power source (e.g., a high-voltage battery for an electric vehicle).

[0060] It should be understood that Figure 2 and Figure 3 Reference to the particular multi-chip arrangement shown in is purely by way of non-limiting example, and the present invention may be applied to any type of multi-chip semiconductor device in which electrical isolation of the exposed die pad may be beneficial.

[0061] Similarly, it should be understood that in one or more embodiments, not all exposed die pads may be electrically insulating. For example, one or more embodiments may include both electrically insulating exposed die pads and electrically conductive exposed die pads. For example, the electrically conductive exposed die pad may be provided by utilizing a conventional QFN leadframe arrangement.

[0062] One or more embodiments may be directed to one or more methods of manufacturing a semiconductor device as disclosed herein.

[0063] For example, Figures 4A to 4E are examples of possible manufacturing steps for a method according to one or more embodiments.

[0064] like Figure 4A As shown, one step of the method may include providing a lead frame LF. The lead frame LF may include a plurality of semiconductor device locations 40. Each of the semiconductor device locations 40 may be surrounded by a corresponding set of leads of the lead frame. For example, in the manufacture of flat leadless semiconductor devices, such leads are conventionally arranged on the four sides of a square or rectangular area. Compared to conventional lead frames used to manufacture flat leadless semiconductor devices, Figure 4A The lead frame LF illustrated in FIG. 4 may not include a metal die pad at the semiconductor device position 40 .

[0065] Depending on the package size and the strip outline size, the lead frame LF may be designed as an array including rows and columns.

[0066] like Figure 4BAs illustrated in , another step of the method may include providing (e.g., attaching) an adhesive tape A bonded to a first side (e.g., bottom side or back side) of the lead frame LF. The adhesive tape A may serve as a temporary support substrate that facilitates placement of the semiconductor device at the semiconductor device position 40, as disclosed below.

[0067] like Figure 4C As illustrated in , another step of the method may include providing an insulating substrate S having a conductive layer (e.g., a metal layer) thereon. The conductive layer may be patterned or shaped to provide conductive pads and interconnects according to a desired pattern. For example, the insulating substrate S may be a ceramic substrate having pads and interconnects patterned by direct bond copper (DBC), such as a "DBC mother card." By way of example only, the insulating substrate S may have dimensions equal to 138 x 190 mm. Thus, the insulating substrate S may be configured to accommodate semiconductor dies to provide a semiconductor device array.

[0068] like Figure 4C As illustrated in , the method may comprise attaching a semiconductor die (eg, high voltage components such as high voltage transistors, diodes and driver circuits) at the conductive pads (in a manner known per se).

[0069] like Figure 4D As illustrated in , another step of the method may include singulating the semiconductor device from the insulating substrate S. After singulation, a plurality of individual electrically insulating substrates 300 may be provided, wherein each electrically insulating substrate 300 has at least one electrically conductive die pad 400 and an electrically conductive trace 402 patterned on the electrically insulating substrate 300, and at least one semiconductor die attached to the at least one die pad 404. Figure 4D The illustrated singulated devices 42 may also be referred to herein as "bare semiconductor devices."

[0070] like Figure 4E As illustrated in , another step of the method may include attaching the singulated semiconductor devices 42 at the semiconductor device locations 40 on the adhesive tape A. In such a step, the adhesive tape A may thus support the lead frame LF and the electrically insulating substrate 300 with the semiconductor devices attached thereto.

[0071] The method may further include bonding the semiconductor device to conductive pads / traces provided on the insulating substrate S and / or bonding the semiconductor device to corresponding leads of the lead frame LF (e.g., via wire bonding), molding (e.g., filling) a molded plastic (e.g., epoxy resin) to encapsulate the semiconductor device and the lead frame, and singulating the semiconductor device by cutting the lead frame to provide packaged semiconductor devices. The supporting adhesive tape A may be removed after the encapsulation step.

[0072] As previously described, in one or more embodiments of the present specification, the electrically insulating substrate 300 may be provided on an otherwise conventional metal die pad of the lead frame, i.e., the electrically insulating substrate 300 may not replace the metal die pad of the lead frame, but may be provided in addition to the metal die pad of the lead frame.

[0073] Thus, one or more embodiments may be directed to a method of manufacturing a semiconductor device that relies on the use of a conventional flat leadless leadframe comprising an array of metal die pads surrounded by a corresponding array of leads. The method differs from conventional methods of manufacturing flat leadless packaged semiconductor devices in that the method comprises attaching a corresponding electrically insulating substrate 300 having (a plurality of) semiconductor dies attached thereto at the metal die pads.

[0074] Thus, one or more embodiments may provide one or more of the following advantages:

[0075] Reducing the length of the electrical connections between the gate driver circuit(s) 202a, 202b and the respective power transistors HST, LST by facilitating closer positioning of the die in the package (e.g., up to 5 times less length), thereby reducing parasitic inductance(s) and / or crosstalk between the connections;

[0076] Providing electrical insulation between high-side and low-side components within the package by means of inserted molded plastic MC (e.g., 0.5 mm insulation distance compared to 4 mm creepage distance);

[0077] Eliminate PCB design constraints related to thermal resistance between the semiconductor die and the environment;

[0078] Provide improved thermal performance (e.g., lower thermal resistance between the semiconductor die and the ambient due to the absence of separate pads and a large number of thermal vias in the PCB); and

[0079] Avoiding modifications to the package outline (eg providing the possibility to maintain compliance with Jedec standards).

[0080] As illustrated herein, a semiconductor device (e.g., 30) may include: a substrate (e.g., 300) having a first surface and a second surface, the second surface being opposite to the first surface; at least one semiconductor die (e.g., HST, LST, HSD, LSD, 202a, 202b) mounted on the first surface of the substrate at at least one corresponding semiconductor die mounting location; a plurality of conductive leads (e.g., 200a, 200b, 200c, 204a, 204b), a plurality of Conductive leads are arranged around the substrate; a plurality of conductive structures (e.g., 304a, 304b, 306a, 306b) coupling at least one semiconductor die to selected leads of the plurality of conductive leads; and a package molding material (e.g., MC) molded onto the at least one semiconductor die mounted at the first surface of the substrate, the plurality of conductive leads, and the plurality of conductive structures, so that the second surface of the substrate is not covered by the package molding material (e.g., exposed outside the package molding material).

[0081] As exemplified herein, the substrate may include a layer of electrically insulating material.

[0082] As illustrated herein, the plurality of conductive structures may include a first conductive pattern (e.g., a patterned metal layer, optionally including a copper layer) on the first surface of the substrate. The first conductive pattern may include: at least one die pad at the at least one semiconductor die mounting location; and / or a conductive line coupling the at least one semiconductor die to selected leads of the plurality of conductive leads.

[0083] As illustrated herein, the device may include a plurality of semiconductor dies mounted at the first surface of the substrate at a corresponding plurality of semiconductor die mounting locations, and the conductive pattern may include conductive lines coupling at least one of the plurality of semiconductor dies to at least another of the plurality of semiconductor dies.

[0084] As illustrated herein, the plurality of semiconductor dies may include a first transistor die (e.g., HST), a second transistor die (e.g., LST), a first diode die (e.g., HSD), a second diode die (e.g., LSD), a first transistor driver circuit die (e.g., 202a), and a second transistor driver circuit die (e.g., 202b). The plurality of conductive leads arranged around the substrate may include a first set of control signal leads (e.g., 204a), a second set of control signal leads (e.g., 204b), a positive voltage supply lead (e.g., 200a), a negative voltage supply lead or a reference voltage supply lead (e.g., 200c), and an output voltage lead (e.g., 200b). The conductive lines in the conductive pattern on the first surface of the substrate may include: a first conductive line (e.g., 302a) coupling a drain terminal or a collector terminal of a first transistor die to a cathode terminal of a first diode; a second conductive line (e.g., 302b) coupling a drain terminal or a collector terminal of a second transistor die to a cathode terminal of a second diode die; a first subset of conductive lines (e.g., 306a) configured to route signals from the periphery of the substrate toward the first transistor driver circuit die; and a second subset of conductive lines (e.g., 306b) configured to route signals from the periphery of the substrate toward the second transistor driver circuit die. The plurality of conductive structures may further include bonding wires coupling selected ones of the plurality of conductive leads to the conductive lines.

[0085] As exemplified herein, the layer of electrically insulating material may comprise a ceramic material, optionally an oxide material and / or a nitride material, optionally aluminum oxide and / or silicon nitride.

[0086] As exemplified herein, the thickness of the layer of electrically insulating material may be in the range of 100 μm to 1.27 mm, optionally equal to 0.25 mm.

[0087] As illustrated herein, the substrate may include a conductive material layer (e.g., a metal material layer, optionally a copper layer) exposed to an outer surface of the package molding material (e.g., configured to provide solder pads for soldering the semiconductor device to a printed circuit board).

[0088] As illustrated herein, the conductive material layer exposed to the outer surface of the package molding material may include: a second conductive pattern (e.g., a metal layer, optionally including a copper layer) on the second surface of the substrate. By way of example, the thickness of the second conductive pattern may range from a few microns (e.g., 10 μm) to thick copper (e.g., 500 μm).

[0089] As illustrated herein, the conductive material layer exposed to the outer surface of the encapsulation molding material may include a die pad of a lead frame provided in a device.

[0090] As exemplified herein, the device may include a flat no-lead package, optionally a rectangular flat no-lead package.

[0091] As illustrated herein, the at least one semiconductor die may include at least one high voltage semiconductor die, and the substrate may include a layer of electrically insulating material configured to provide high voltage insulation of the at least one high voltage semiconductor die.

[0092] As illustrated herein, a method for manufacturing a packaged semiconductor device may include: providing at least one bare semiconductor device (e.g., 42), wherein the at least one bare semiconductor device includes: a substrate comprising a layer of electrically insulating material, the substrate having a first surface and a second surface, the second surface opposite to the first surface; a conductive structure, the conductive structure being formed at the first surface of the substrate; and at least one semiconductor die, the at least one semiconductor die being mounted at the first surface of the substrate; providing a lead frame (e.g., LF), the lead frame comprising at least one conductive lead set arranged around at least one corresponding semiconductor device position (e.g., 40); positioning the at least one bare semiconductor device at the at least one corresponding semiconductor device position within the lead frame; electrically coupling (e.g., wire bonding) the at least one semiconductor die to the conductive structure and / or the at least one corresponding conductive lead set; and molding an encapsulation molding material onto the at least one bare semiconductor device so that the second surface of the substrate is not covered by the encapsulation molding material (e.g., exposed outside the encapsulation molding material).

[0093] As illustrated herein, positioning the at least one bare semiconductor device at the at least one corresponding semiconductor device position may include attaching an adhesive tape (e.g., A) to one side of the lead frame and attaching the at least one bare semiconductor device to the adhesive tape at the at least one corresponding semiconductor device position within the lead frame.

[0094] As illustrated herein, the lead frame may include at least one die pad, the at least one die pad being arranged at the at least one corresponding semiconductor device position, and positioning the at least one bare semiconductor device at the at least one corresponding semiconductor device position may include: mounting the at least one bare semiconductor device on the at least one die pad of the lead frame.

[0095] Without prejudice to the basic principle, the details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without departing from the scope of protection.

[0096] The claims are an integral part of the technical teaching provided herein with respect to the exemplary embodiments.

[0097] The scope of protection is determined by the appended claims.

Claims

1. A packaged semiconductor device, comprising: an electrically insulating substrate having a first surface and a second surface, the second surface being opposite to the first surface; at least one semiconductor die mounted on the first surface of the electrically-insulative substrate at at least one corresponding semiconductor die mounting location; a plurality of electrically conductive leads of a lead frame, the plurality of electrically conductive leads being arranged around the electrically insulating substrate; a plurality of conductive structures coupling the at least one semiconductor die to selected ones of the plurality of conductive leads, wherein the plurality of conductive structures comprises a first conductive pattern on the first surface of the electrically-insulative substrate; an encapsulation molding material molded onto the at least one semiconductor die mounted at the first surface of the electrically insulating substrate, onto the plurality of conductive leads of the leadframe, and onto the plurality of conductive structures to form a flat leadless package, leaving the second surface of the electrically insulating substrate uncovered by the encapsulation molding material and leaving bottom surfaces of the plurality of conductive leads uncovered by the encapsulation molding material; as well as a plurality of semiconductor dies mounted at the first surface of the electrically insulating substrate at a corresponding plurality of semiconductor die mounting locations, wherein the first conductive pattern includes conductive lines that couple at least one semiconductor die of the plurality of semiconductor dies to at least another semiconductor die of the plurality of semiconductor dies, in: The plurality of semiconductor dies includes a first transistor die, a second transistor die, a first diode die, a second diode die, a first transistor driver circuit die, and a second transistor driver circuit die; The plurality of electrically conductive leads arranged around the electrically insulating substrate include a first set of control signal leads, a second set of control signal leads, a positive voltage supply lead, a negative voltage supply lead or a reference voltage supply lead, and an output voltage lead; The conductive lines in the conductive pattern on the first surface of the electrically insulating substrate include: a first conductive line coupling the drain terminal or collector terminal of the first transistor die to the cathode terminal of the first diode die; a second conductive line coupling the drain terminal or collector terminal of the second transistor die to the cathode terminal of the second diode die; a first subset of electrically conductive lines configured to route signals from a periphery of the electrically insulating substrate toward the first transistor driver circuit die; and a second subset of electrically conductive lines configured to route signals from the periphery of the electrically-insulative substrate toward the second transistor driver circuit die; and The plurality of conductive structures further include a bonding wire coupling selected ones of the plurality of conductive leads to the conductive line. 2 . The packaged semiconductor device of claim 1 , wherein the first conductive pattern comprises at least one die pad at the at least one semiconductor die mounting location. 3 . The packaged semiconductor device of claim 2 , wherein the first conductive pattern comprises conductive lines that couple the at least one semiconductor die to selected ones of the plurality of conductive leads. The packaged semiconductor device of claim 1 , wherein the electrically insulating substrate comprises a ceramic substrate. 5 . The packaged semiconductor device of claim 1 , wherein the electrically insulating substrate comprises one or more layers of oxide material and nitride material. 6 . The packaged semiconductor device of claim 1 , wherein the electrically insulating substrate comprises one or more layers of aluminum oxide material and silicon nitride material. 7 . The packaged semiconductor device of claim 1 , wherein the electrically insulating substrate has a thickness in the range of 100 μm to 1.27 mm. 8 . The packaged semiconductor device of claim 1 , further comprising a layer of electrically conductive material on the second surface of the electrically insulating substrate, wherein the layer of electrically conductive material is not covered by the encapsulation molding material. 9 . The packaged semiconductor device of claim 8 , wherein the layer of electrically conductive material on the second surface of the electrically insulating substrate comprises a second conductive pattern on the second surface of the substrate. 10 . The packaged semiconductor device according to claim 9 , wherein a thickness of the second conductive pattern is in a range of 10 μm to 500 μm. 11 . The packaged semiconductor device of claim 9 , wherein the layer of conductive material on the second surface of the electrically insulating substrate comprises a die pad of the leadframe.

12. The packaged semiconductor device of claim 1, wherein the at least one semiconductor die comprises at least one high-voltage semiconductor die, and wherein the electrically insulating substrate comprises a layer of electrically insulating material that provides high-voltage insulation of the at least one high-voltage semiconductor die.

13. A method of manufacturing the packaged semiconductor device according to claim 1, comprising: At least one bare semiconductor device is provided, the at least one bare semiconductor device comprising: an electrically insulating substrate, wherein the electrically insulating substrate has a first surface and a second surface, the second surface being opposite to the first surface; a conductive structure formed at the first surface of the electrically insulating substrate; and at least one semiconductor die mounted at the first surface of the electrically insulating substrate; providing a lead frame comprising at least one set of conductive leads arranged around at least one corresponding semiconductor device location; positioning the at least one bare semiconductor device at the at least one corresponding semiconductor device location within the leadframe; electrically coupling the at least one semiconductor die to the conductive structure and the corresponding at least one set of conductive leads; and An encapsulation molding material is molded onto the at least one bare semiconductor device to form a flat no-lead package, leaving the second surface of the electrically insulating substrate uncovered by the encapsulation molding material and leaving bottom surfaces of the plurality of conductive leads uncovered by the encapsulation molding material.

14. The method of claim 13 , wherein positioning the at least one bare semiconductor device at the at least one corresponding semiconductor device location comprises: attaching an adhesive tape to one side of the lead frame; as well as The at least one bare semiconductor device is attached to the adhesive tape at the at least one corresponding semiconductor device location within the leadframe.

15. The method of claim 13 , wherein the leadframe comprises at least one die pad, the at least one die pad being arranged at the at least one corresponding semiconductor device location, and wherein positioning the at least one bare semiconductor device at the at least one corresponding semiconductor device location comprises: The at least one bare semiconductor device is mounted on the at least one die pad of the lead frame.

Images