Digital transceiver integrated microsystem and method of fabrication

Abstract

This invention discloses a digital transceiver integrated microsystem and its manufacturing method. The system includes a packaging substrate with a frame cover plate mounted on it. A first glass transition plate and a second glass transition plate are arranged inside the frame cover plate. Programmable logic devices are embedded in the substrate cavity. A micro cold plate is arranged at the bottom of the substrate. Thermally conductive silicone grease is filled between the passive surface of the programmable logic device and the micro cold plate. The active surface of the programmable logic device has an array of solder ball bumps formed by wafer-level balling and is soldered to the reverse side of the first glass transition plate. Small solder balls are distributed between the first glass transition plate and the substrate, and high solder balls are distributed between the second glass transition plate and the packaging substrate. Peripheral components are arranged on the front side of the second glass transition plate, and communication devices are arranged in the cavity between the two glass transition plates. Through holes are formed in the body of the two transition plates, and metal pillars are arranged in the through holes. Redistribution layers are arranged on the front and back sides of the two transition plates. This reduces the wiring difficulty of the redistribution layers on the transition plates and improves the overall structural stability.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, specifically to a digital transceiver integrated microsystem and its manufacturing method. Background Technology

[0002] With the rapid development of electronic technology, electronic systems are evolving towards miniaturization, high performance, multifunctionality, low cost, and high reliability, making hybrid integrated microsystems an inevitable trend. For all-digital transceiver (DBF) phased array radar systems, there are numerous transceiver units (i.e., transceiver branches), typically requiring hundreds or even tens of thousands of transceiver units per array. However, the currently used traditional digital transceiver modules result in low overall system integration, and the size, weight, power consumption, reliability, cost, and channel consistency of the system equipment fall far short of engineering requirements.

[0003] With increasing integration levels, there is an urgent need to develop highly integrated, scalable, lightweight, and highly reliable radio frequency (RF) system-on-a-chip (SoC) systems, including microwave monolithic integrated circuits (MMICs), radio frequency integrated circuits (RFICs), mixed-signal integrated circuits, and high-performance digital signal processing integrated circuits (DSPs), as well as the emerging hybrid integrated microsystems. Due to the large number of components, numerous I / O operations, nascent bare-chip supply, and complex manufacturing processes, digital transceiver modules have seen slower development in high integration and miniaturization compared to MMICs and RFICs. Currently, there is still relatively little work on the high integration of ultra-complex digital transceiver systems.

[0004] In related technologies, a paper titled "Thermal Design of a Three-Dimensional Internet Broadband Digital Transceiver Microsystem" published in the journal Mechanical and Electronic Engineering in October 2019 describes a microsystem that uses a silicon interposer to replace the PCB board as the component packaging substrate and interconnect layer. The required functional devices are directly integrated on a silicon-based wafer. Then, the integration and density of the microsystem are increased by stacking multiple silicon-based wafers. At the same time, a large number of electrical TSVs and thermal TSVs are arranged inside the silicon-based wafer, and rewiring is designed on the upper and lower surfaces to achieve efficient interconnection and heat transfer, effectively reduce inter-layer communication latency, and significantly increase signal bandwidth.

[0005] However, the three-dimensional broadband digital transceiver microsystem uses a conventional 2.5D stacked structure, where two silicon interposer boards are interconnected by copper pillars, and the FPGA on the back of the lower interposer board is on the packaging substrate, making the structure unstable. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a digital transceiver microsystem with good overall structural stability and high integration.

[0007] The present invention solves the above-mentioned technical problems through the following technical means:

[0008] In a first aspect, the first embodiment of the present invention employs a digital transceiver integrated microsystem, the system comprising: a packaging substrate, a frame cover plate mounted on the packaging substrate, a first glass transition plate and a second glass transition plate arranged within the frame cover plate, a programmable logic device embedded in a cavity of the packaging substrate, a micro cold plate arranged at the bottom of the packaging substrate, thermally conductive silicone grease filled between the passive surface of the programmable logic device and the micro cold plate, an array of solder bumps formed by wafer-level ball bonding arranged on the active surface of the programmable logic device, the solder bump array being soldered to the reverse side of the first glass transition plate, small solder balls distributed between the first glass transition plate and the packaging substrate, high solder balls distributed between the reverse side of the second glass transition plate and the packaging substrate, peripheral components arranged on the front side of the second glass transition plate, and a communication device arranged within the cavity between the first glass transition plate and the second glass transition plate;

[0009] The first glass transition plate and the second glass transition plate have through holes, and metal pillars are arranged in the through holes. Furthermore, redistribution layers are evenly distributed on the front and back sides of the first glass transition plate and the second glass transition plate.

[0010] In this embodiment, the active surface of the programmable logic device (PLD), which has the highest heat dissipation, is subjected to wafer-level ball bumping to obtain a fine-pitch solder ball bump array. The PLD is then flip-chip soldered onto the first glass adapter plate to form electrical interconnects. The passive surface of the PLD is tightly interconnected with a micro-cold plate using thermally conductive silicone grease, thereby transferring the large amount of heat generated by the PLD to the outside of the system and dissipating it. The PLD itself is embedded in the cavity structure of the packaging substrate, forming a stable and reliable structure. The communication device on the front side of the first glass adapter plate is electrically interconnected with the solder ball bump array on the back side of the first glass adapter plate through metal pillars penetrating through glass vias and a redistribution layer on the surface of the first glass adapter plate. Peripheral components include high-speed interfaces, power supplies, and other driver chips. These chips have relatively few I / Os and some heat dissipation, so they are arranged on the second glass adapter board. To reduce system complexity and improve yield and reliability, the two glass adapter boards are electrically interconnected through high solder balls located around the adapter board to achieve package stacking (POP). This reduces the wiring difficulty of the rewiring layer on the adapter board, reduces the impact of crosstalk between signals, and improves the overall structural stability.

[0011] Furthermore, the communication device includes an analog-to-digital converter, a digital-to-analog converter, and a memory;

[0012] The peripheral components include a high-speed interface, a power supply, and a driver chip;

[0013] The programmable logic device, the communication device, and the peripheral components all use bare chips.

[0014] Furthermore, the length of the second glass adapter plate is greater than the length of the first glass adapter plate.

[0015] Furthermore, the thickness of the first glass adapter plate is less than the thickness of the high-tin ball.

[0016] Furthermore, thermally conductive adhesive is filled between the active surface of the programmable logic device and the reverse side of the first glass adapter plate.

[0017] Thermally conductive adhesive is filled between the front side of the driver chip and the frame cover plate.

[0018] Furthermore, the packaging substrate is a cored packaging substrate.

[0019] Furthermore, a ball grid array is welded to the bottom of the packaging substrate.

[0020] Secondly, the second embodiment of the present invention employs a method for manufacturing a digital transceiver integrated microsystem, the method comprising:

[0021] A first glass transition plate and a second glass transition plate are prepared. Through holes are opened in the plate bodies of the first glass transition plate and the second glass transition plate. Metal pillars are arranged in the through holes. Rewire layers are evenly distributed on the front and back sides of the first glass transition plate and the second glass transition plate.

[0022] Wafer-level ball placement is performed on the active surface of the programmable logic device to form a solder ball bump array. The solder ball bump array is flip-chip mounted on the back of the first glass adapter plate. A communication device is mounted on the front of the first glass adapter plate. The programmable logic device is embedded in the cavity of the packaging substrate.

[0023] The peripheral components are mounted on the front side of the second glass adapter plate;

[0024] To achieve electrical connection between the first glass adapter plate and the packaging substrate, high solder balls are arranged between the reverse side of the second glass adapter plate and the packaging substrate to achieve electrical connection between the second glass adapter plate and the packaging substrate.

[0025] Thermally conductive silicone grease is filled between the passive surface of the programmable logic device and the micro cold plate, and a frame cover is installed on the packaging substrate for packaging and debugging.

[0026] Furthermore, the peripheral components include a high-speed interface, a power supply, and a driver chip, and the method further includes:

[0027] Thermally conductive adhesive is filled between the front side of the driver chip and the frame cover plate.

[0028] Furthermore, the method also includes:

[0029] The bottom of the packaging substrate is welded with a ball grid array for assembly and integration with the module to be integrated.

[0030] The advantages of this invention are:

[0031] (1) In this embodiment, the active surface of the programmable logic device with the highest heat dissipation is subjected to wafer-level ball bonding to obtain a fine-pitch solder bump array. The programmable logic device is then flip-chip soldered onto the first glass adapter plate to form an electrical interconnect. The passive surface of the programmable logic device is tightly interconnected with the micro cold plate through thermal grease, thereby transferring the large amount of heat generated by the programmable logic device to the outside of the system and dissipating it. The programmable logic device itself is embedded in the cavity structure of the packaging substrate to form a stable and reliable structure. The communication device on the front side of the first glass adapter plate and the solder bump array on the back side of the first glass adapter plate are electrically interconnected through metal pillars penetrating the glass through-holes and the redistribution layer on the surface of the first glass adapter plate. Peripheral components include high-speed interfaces, power supplies, and other driver chips. These chips have relatively few I / Os and some heat dissipation, so they are arranged on the second glass adapter board. To reduce system complexity and improve yield and reliability, the two glass adapter boards are electrically interconnected through high solder balls located around the adapter board to achieve package stacking (POP). This reduces the wiring difficulty of the rewiring layer on the adapter board, reduces the impact of crosstalk between signals, and improves the overall structural stability.

[0032] (2) Among all types of packaging substrates, glass has better high-frequency response characteristics, is non-hygroscopic, has good insulation, can be made thinner and more transparent, and can simplify complex processes such as depositing passivation layers in silicon substrates.

[0033] (3) After the two-layer POP structure is completed, the chip mounted on the front of the second glass adapter is thinned to the same height, and then the thermal conductive adhesive is tightly attached to the front of the driver chip. Then the metal heat dissipation frame cover is installed on the packaging substrate to achieve the function of system heat dissipation and circuit protection.

[0034] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0035] Figure 1 This is a general telecommunications block diagram of the digital transceiver integrated microsystem in the first embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the architecture of the digital transceiver integrated microsystem in the first embodiment of the present invention.

[0037] Figure 3 This is a process diagram of the digital transceiver integrated microsystem in the second embodiment of the present invention.

[0038] In the picture:

[0039] 1-Miniature cold plate, 2-Thermal grease, 3-Ball grid array, 4-Packaging substrate, 5-High solder balls, 61-First glass transition plate, 62-Second glass transition plate, 7-Thermal adhesive, 8-Frame cover plate, 9-Programmable logic device, 10-Solder ball bump array, 11-Fill adhesive, 12-Communication device, 13-First redistribution layer, 14-Through hole, 15-Second redistribution layer, 16-Power supply and driver chip, 17-Small solder balls. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] like Figures 1 to 2 As shown, the first embodiment of the present invention discloses a digital transceiver integrated microsystem. The system includes: a packaging substrate 4, a frame cover plate 8 mounted on the packaging substrate 4, a first glass transition plate 61 and a second glass transition plate 62 arranged inside the frame cover plate 8, a programmable logic device 9 embedded in the cavity of the packaging substrate 4, a micro cold plate 1 arranged at the bottom of the packaging substrate 4, thermally conductive silicone grease filled between the passive surface of the programmable logic device 9 and the micro cold plate 1, a solder ball bump array 10 formed by wafer-level ball placement arranged on the active surface of the programmable logic device 9, the solder ball bump array 10 being soldered to the reverse side of the first glass transition plate 61, small solder balls 17 distributed between the first glass transition plate 61 and the packaging substrate 4, high solder balls 5 distributed between the reverse side of the second glass transition plate 62 and the packaging substrate 4, peripheral components arranged on the front side of the second glass transition plate 62, and a communication device 12 arranged in the cavity between the first glass transition plate 61 and the second glass transition plate 62.

[0042] The first glass transition plate 61 and the second glass transition plate 62 have through holes 14, and metal pillars are arranged in the through holes 14. The first glass transition plate 61 and the second glass transition plate 62 are respectively provided with a second redistribution layer 15 and a first redistribution layer 13 on their front and back sides.

[0043] It should be noted that, as Figure 1As shown, a digital transceiver integrated microsystem integrates digital logic devices and analog devices, making it a typical mixed-signal system. Effective isolation between analog and digital signals is essential. Furthermore, the various chips have different functions, with power consumption ranging from less than 1 watt to as high as 40W. Therefore, as... Figure 2 As shown, in this embodiment, the programmable logic device 9 with the highest power consumption is placed at the bottom and embedded in the packaging substrate 4. The micro cold plate 1 is attached to the back side. The programmable logic device 9 is flipped and heat dissipation is achieved by attaching thermal grease and the micro cold plate 1 to the bottom. This achieves the shortest heat dissipation path and the most stable structure. This solution can better dissipate the heat of the FPGA with the highest heat consumption and reduce heat accumulation.

[0044] The programmable logic device 9 connects to analog-to-digital converters, digital-to-analog converters, and memory via a glass adapter board, enabling most of the I / O interconnection within the system, thus simplifying the system's external interface.

[0045] The high-speed optical port, power supply, and other driver chips are placed on the top layer, allowing the heat from the power supply to be dissipated to the outside via the shortest path. Electrical and mechanical interconnection between the two glass transition boards is achieved through high-solder balls distributed around the perimeter of the glass transition boards. Simultaneously, the high-solder balls also create a cavity between the two transition boards, facilitating chip placement on the front of the first glass transition board and improving the utilization rate of the glass transition boards.

[0046] Therefore, this embodiment is suitable for miniaturizing electronic systems with high integration density, high heat generation, and numerous I / O pins, such as complex digital transceiver systems and signal processing systems. Moreover, among all packaging substrate types, glass has superior high-frequency response characteristics, is non-hygroscopic, has good insulation, and can be made thinner and more transparent, among other advantages. It also simplifies complex processes such as depositing passivation layers in silicon substrates. This invention utilizes the superior high-frequency response characteristics, excellent dielectric loss characteristics, and unique mechanical properties of glass substrates to significantly miniaturize conventionally bulky digital transceiver circuit boards, giving them a size advantage and scalability for future smaller and lighter load spaces.

[0047] Furthermore, this embodiment of the invention is based on vertically stacked glass transition plates, with no signal interconnection structure between the two glass transition plates. The two glass transition plates are directly interconnected to the packaging substrate via solder ball arrays of varying sizes around their perimeters. Compared to the thermal design schemes of three-dimensional broadband digital transceiver microsystems in related technologies, the perimeter array is more conducive to fanning out signal traces, reduces signal interconnection path and loss, offers better electromagnetic compatibility, simplifies the manufacturing process, and embeds programmable logic devices within the packaging substrate, resulting in a stable and reliable structure.

[0048] Furthermore, this embodiment employs a two-layer glass transition plate. Structurally, the glass transition plate can be made into an ultra-large substrate, while the size of current silicon transition plates is significantly limited. In terms of performance, the glass transition plate has low electrical loss and good mechanical properties, enabling smaller, more miniaturized applications. Glass also has excellent insulation properties, so no additional insulating layer is needed during circuit fabrication, optimizing the structure and reducing process complexity.

[0049] The electrical loss of glass transition boards is significantly lower than that of silicon, especially in high-frequency applications, thus further reducing circuit heat dissipation. Glass transition boards are an indispensable substrate for future high-frequency (above 30GHz) applications, which silicon cannot replace. The thermal reliability of glass transition boards is better than that of silicon, and the heat dissipation effect of the interlayer solder ball array is obvious, with smooth path, which is significantly better than the small copper pillars between silicon transition boards. Moreover, the cost of glass can be further reduced, becoming lower than that of silicon.

[0050] It should also be noted that in this embodiment, the interconnection between the substrate, the first glass transition plate 61 and the second glass transition plate 62 is achieved through various solder ball arrays. It is necessary to control the composition of the solder balls in order to form the temperature gradient required for different reflow soldering processes.

[0051] It should be understood that the composition of solder balls depends on the solder. Currently, there are many types of commercially available and R&D solders, and they are relatively mature. In practical applications, a solder with a fixed composition ratio of Pb:Sn:Ag can be found according to the required soldering temperature, thereby ensuring the optimal composition of the solder balls and the optimal soldering temperature.

[0052] In some embodiments, the communication device includes an analog-to-digital converter, a digital-to-analog converter, and a memory;

[0053] The peripheral components include a high-speed interface, a power supply, and a driver chip 16;

[0054] The programmable logic device 9, the communication device, and the peripheral components all use bare chips.

[0055] It should be noted that the communication devices and peripheral devices in this embodiment are only illustrative examples. Those skilled in the art can deploy other devices according to actual conditions. This embodiment does not impose any specific limitations.

[0056] In some embodiments, the length of the second glass adapter plate 62 is greater than the length of the first glass adapter plate 61.

[0057] It should be noted that this embodiment uses two glass adapter boards of different sizes for assembly. This is because both adapter boards are directly interconnected to the packaging substrate via back-side ball-mounting. Therefore, a larger adapter board at the top and a smaller one at the bottom is needed to free up space for ball-mounting on the upper adapter board. Furthermore, the first glass adapter board integrates the core chip and has a compact size; the second glass adapter board contains other configuration chips, analog-to-digital converter chips, and passive components, which are more numerous and require a larger adapter board. Compared with existing technologies, this method offers superior electrical performance, simplifies the manufacturing process, and facilitates heat dissipation design.

[0058] In some embodiments, the thickness of the first glass adapter plate 61 is less than the thickness of the high tin ball 5.

[0059] It should be noted that, since the glass adapter plate used in this embodiment is relatively thin, the bare chip to be mounted also needs to be thinned so that the thickness of the first glass adapter plate 61 is less than the thickness of the high solder ball 5.

[0060] It's important to note that chip thinning is done so that the chip's height after mounting on the glass adapter board is lower than the solder ball height. Otherwise, the solder balls would be suspended in mid-air, preventing interconnection with the substrate. Generally, the thickness after thinning needs to be less than the solder ball height; for example, if the solder ball is 300μm, then the chip can be 200μm.

[0061] In some embodiments, adhesive 11 is filled between the active surface of the programmable logic device 9 and the reverse side of the first glass adapter plate 61.

[0062] Thermally conductive adhesive 7 is filled between the front side of the driver chip and the frame cover plate 8.

[0063] It should be noted that in this embodiment, the filler adhesive 11 is a resin with fluidity. After being filled to the bottom of the chip, it will cure to alleviate solder ball failure caused by thermal stress generated during thermal expansion and contraction. The thermally conductive adhesive is used to ensure thermal resistance matching between the chip surface and the heat sink.

[0064] In some embodiments, the packaging substrate 4 is a cored packaging substrate 4.

[0065] It should be noted that in this embodiment, the frame cover plate 8 is made of metal and has a certain weight. Therefore, the encapsulation substrate 4 is a core substrate, which has sufficient thickness and rigidity to support the metal frame.

[0066] In some embodiments, a ball grid array 3 is welded to the bottom of the packaging substrate 4.

[0067] It should be noted that in this embodiment, the entire digital transceiver microsystem will be integrated with the template via the ball grid array 3 through flip-chip welding to form an assembly with other systems.

[0068] like Figure 3 As shown, the second embodiment of the present invention discloses a method for manufacturing a digital transceiver integrated microsystem, the method comprising:

[0069] (1) Preparation of the adapter plate: a first glass adapter plate and a second glass adapter plate are prepared. The first glass adapter plate and the second glass adapter plate have through holes. Metal pillars are arranged in the through holes. Rewire layers are evenly distributed on the front and back sides of the first glass adapter plate and the second glass adapter plate.

[0070] (2) The chip is mounted on the active surface of the programmable logic device and the wafer-level ball bump array is formed. The ball bump array is flip-chip mounted on the back of the first glass adapter plate. The communication device is mounted on the front of the first glass adapter plate. The programmable logic device is embedded in the cavity of the packaging substrate.

[0071] The peripheral components are mounted on the front side of the second glass adapter plate.

[0072] (3) Inter-board interconnection: to realize the electrical connection between the first glass transition plate and the packaging substrate, and to realize the electrical connection between the second glass transition plate and the packaging substrate by arranging high solder balls between the reverse side of the second glass transition plate and the packaging substrate;

[0073] (4) Assembly and debugging: fill the space between the passive surface of the programmable logic device and the micro cold plate with thermal grease, install the frame cover plate on the packaging substrate, and perform packaging and debugging.

[0074] It should be noted that system packaging mainly includes various interconnections between bare chips and glass interposers, between bare chips and packaging substrates, and between glass interposers. These interconnections need to be performed in sequence, such as... Figure 3 As shown, firstly, two glass adapter boards of different sizes are fabricated. Then, chips are mounted on the front and back of the glass adapter boards. After the programmable logic devices are flip-chip mounted onto the glass adapter boards, an underfill adhesive process is required. After completing the chip-adapter board packaging interconnection, the electrical interconnection between the glass adapter boards and the packaging substrate is then performed. Specifically, the first glass adapter board is interconnected with the packaging substrate using small solder balls, vertically interconnecting some signals to the lower packaging substrate; the second glass adapter board is interconnected with the packaging substrate using tall solder balls, achieving the shortest possible interconnection for the remaining signals to the substrate.

[0075] In some embodiments, the method further includes:

[0076] Thermally conductive adhesive is filled between the front side of the driver chip and the surrounding cover plate.

[0077] In some embodiments, the peripheral components include a high-speed interface, a power supply, and a driver chip, and the method further includes:

[0078] The bottom of the packaging substrate is welded with a ball grid array for assembly and integration with the module to be integrated.

[0079] The microsystem architecture fabricated in this embodiment solves the problem of mechanical, electrical, and thermal coupling in complex digital transceiver systems, achieving numerous advantages such as simple interface, good electrical performance, high integration, and low cost. Compared to existing digital microsystem forms, this system has higher functional density and integration density, higher efficiency, and lower cost, meeting the trend of devices becoming increasingly miniaturized, scalable, and highly reliable. Therefore, it is of great significance to the development of digital transceiver systems.

[0080] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0081] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0082] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0083] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A digital transceiver integrated microsystem, characterized in that, The system includes: a packaging substrate, a frame cover plate mounted on the packaging substrate, a first glass transition plate and a second glass transition plate arranged inside the frame cover plate, a programmable logic device embedded in a cavity of the packaging substrate, a micro cold plate arranged at the bottom of the packaging substrate, thermal grease filled between the passive surface of the programmable logic device and the micro cold plate, an array of solder bumps formed by wafer-level ball bonding arranged on the active surface of the programmable logic device, the solder bump array being soldered to the reverse side of the first glass transition plate, small solder balls distributed between the first glass transition plate and the packaging substrate, high solder balls distributed between the reverse side of the second glass transition plate and the packaging substrate, peripheral components arranged on the front side of the second glass transition plate, and a communication device arranged in the cavity between the first glass transition plate and the second glass transition plate; the thickness of the first glass transition plate is less than the thickness of the high solder balls. The first glass transition plate and the second glass transition plate have through holes, and metal pillars are arranged in the through holes. Furthermore, redistribution layers are evenly distributed on the front and back sides of the first glass transition plate and the second glass transition plate.

2. The digital transceiver integrated microsystem as described in claim 1, characterized in that, The communication device includes an analog-to-digital converter, a digital-to-analog converter, and a memory; The peripheral components include a high-speed interface, a power supply, and a driver chip; The programmable logic device, the communication device, and the peripheral components all use bare chips.

3. The digital transceiver integrated microsystem as described in claim 1, characterized in that, The length of the second glass adapter plate is greater than the length of the first glass adapter plate.

4. The digital transceiver integrated microsystem as described in claim 1, characterized in that, The active surface of the programmable logic device and the reverse side of the first glass adapter plate are filled with adhesive. Thermally conductive adhesive is filled between the front side of the driver chip and the surrounding cover plate.

5. The digital transceiver integrated microsystem as described in claim 1, characterized in that, The packaging substrate is a cored packaging substrate.

6. The digital transceiver integrated microsystem as described in claim 1, characterized in that, A ball grid array is welded to the bottom of the packaging substrate.

7. A method for manufacturing a digital transceiver integrated microsystem, characterized in that, The method includes: A first glass transition plate and a second glass transition plate are prepared. Through holes are opened in the plate bodies of the first glass transition plate and the second glass transition plate. Metal pillars are arranged in the through holes. Rewire layers are evenly distributed on the front and back sides of the first glass transition plate and the second glass transition plate. Wafer-level ball placement is performed on the active surface of the programmable logic device to form a solder ball bump array. The solder ball bump array is flip-chip mounted on the back of the first glass adapter plate. A communication device is mounted on the front of the first glass adapter plate. The programmable logic device is embedded in the cavity of the packaging substrate. The peripheral components are mounted on the front side of the second glass adapter plate; Electrical connection between the first glass adapter plate and the packaging substrate is achieved by placing high solder balls between the reverse side of the second glass adapter plate and the packaging substrate to achieve electrical connection between the second glass adapter plate and the packaging substrate. The thickness of the first glass adapter plate is less than the thickness of the high solder balls. Thermally conductive silicone grease is filled between the passive surface of the programmable logic device and the micro cold plate, and a frame cover is installed on the packaging substrate for packaging and debugging.

8. The method for manufacturing a digital transceiver integrated microsystem as described in claim 7, characterized in that, The peripheral components include a high-speed interface, a power supply, and a driver chip. The method further includes: Thermally conductive adhesive is filled between the front side of the driver chip and the frame cover plate.

9. The method for manufacturing a digital transceiver integrated microsystem as described in claim 7, characterized in that, The method further includes: The bottom of the packaging substrate is welded with a ball grid array for assembly and integration with the module to be integrated.

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