Memory

Abstract

The present invention provides a memory. A node contact window is defined by a bit line and an insulating line, and a contact plug filled in the node contact window is made to protrude upward from the node contact window, and a spacing structure is further used to space adjacent contact plugs, and a first gap is formed in the spacing structure, so that the dielectric constant of the dielectric material between adjacent contact plugs is reduced, and the parasitic effect of the device is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory. Background Art

[0002] With the development of semiconductor technology, the density of semiconductor elements in integrated circuits has increased, and the spacing between adjacent semiconductor elements has also decreased, resulting in parasitic effects between adjacent conductive parts that cannot be ignored.

[0003] Specifically, for a dynamic random access memory (DRAM), it usually has a memory cell array, wherein the memory cell array includes a plurality of memory cells arranged in an array, and the memory also has a plurality of bit lines, each bit line is electrically connected to a corresponding memory cell, and the memory also includes a storage capacitor, wherein the storage capacitor is used to store charges representing stored information, and the memory cell can be electrically connected to the storage capacitor through a contact plug, thereby realizing the storage function of each memory cell. As described above, with the continuous reduction in the size of semiconductors, the density of arrangement of semiconductor elements increases, and at this time, correspondingly, there will be a large parasitic effect between, for example, adjacent bit lines and adjacent contact plugs, thereby affecting the performance of the device. Summary of the invention

[0004] The object of the present invention is to provide a memory to solve the problem of large parasitic effects in existing memories.

[0005] In order to solve the above technical problems, the present invention provides a memory, comprising:

[0006] substrate;

[0007] A plurality of bit lines and a plurality of insulating lines are formed on the substrate, and the bit lines and the insulating lines intersect to define a plurality of node contact windows;

[0008] A contact plug is filled in the node contact window, and the top of the contact plug also protrudes upward from the node contact window, and a groove is defined between the protruding tops of adjacent contact plugs;

[0009] A spacing structure fills the groove to space adjacent contact plugs, wherein the spacing structure at least covers the sidewall and the bottom of the groove, and a first gap is formed in the spacing structure at a corner where the sidewall and the bottom meet.

[0010] Optionally, the spacing structure includes a first isolation layer and a second isolation layer, the first isolation layer at least covers the side wall and the bottom of the groove, and the first gap is also formed in the first isolation layer at the corner where the side wall and the bottom meet, and the second isolation layer is formed on the first isolation layer and fills the groove.

[0011] Optionally, a second gap is formed in the second isolation layer.

[0012] Optionally, the first gap is also in direct contact with the contact plug.

[0013] Optionally, the bit line includes a bit line conductive part, a bit line shielding layer covering the top surface of the bit line conductive part, and a bit line side wall covering the side wall of the bit line conductive part; wherein the bit line side wall includes a first side wall, a second side wall, and a third gap clamped between the first side wall and the second side wall.

[0014] Optionally, the third gap in the bit line spacer on the same sidewall extends continuously along the extension direction of the bit line.

[0015] Optionally, an opening in the third gap directly below the spacing structure is covered by the first isolation layer.

[0016] Optionally, the protruding top of the contact plug further extends laterally onto the top surface of the bit line and / or the insulation line.

[0017] Optionally, the protruding top of the contact plug is translated relative to the bottom portion of the contact plug to the top surface of the bit line and / or the insulating line; wherein a dimension extended by the translation of the top relative to the bottom is greater than a dimension contracted by the translation of the top relative to the bottom.

[0018] Optionally, the grooves between the tops of adjacent contact plug protrusions further extend into the bit lines and insulation lines directly below, so that the bottom of the spacing structure extends into the bit lines and the insulation lines.

[0019] Optionally, the memory further includes a storage capacitor, and a lower electrode of the storage capacitor is electrically connected to a top of the contact plug.

[0020] In the memory provided by the present invention, the node contact window is defined by the bit line and the insulating line, and the contact plug filled in the node contact window is also protruded upward from the node contact window, which is conducive to increasing the contact area of ​​the top surface of the contact plug. In addition, the adjacent node contact plugs are further spaced by the spacing structure, and the first gap is formed in the spacing structure, so that the dielectric constant of the dielectric material between the adjacent contact plugs can be reduced, and the parasitic effect of the device can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A top view of a memory in one embodiment of the present invention mainly showing bit lines and insulating lines;

[0022] Figure 2 FIG. 1 is a top view of a memory device in an embodiment of the present invention, which mainly illustrates a contact plug;

[0023] Figure 3 A top view of a memory device in an embodiment of the present invention mainly showing contact plugs and spacer structures;

[0024] Figure 4 for Figure 3 A schematic cross-sectional view of a memory in one embodiment of the present invention in directions II-I' and II-II' is shown;

[0025] Figure 5 for Figure 4 A partial enlarged view of the cross-sectional schematic diagram shown;

[0026] Figure 6 is a cross-sectional schematic diagram of a memory in an embodiment of the present invention, which illustrates a lower electrode of a storage capacitor;

[0027] Figure 7 is a schematic flow chart of a method for forming a memory in one embodiment of the present invention;

[0028] Figure 8a to Figure 8d FIG. 1 is a schematic structural diagram of a method for forming a memory in an embodiment of the present invention during its preparation process.

[0029] The reference numerals are as follows:

[0030] 100-substrate;

[0031] 101- a first source / drain region;

[0032] 102- a second source / drain region;

[0033] 110-trench isolation structure;

[0034] 120-word line;

[0035] 130-word line shielding layer;

[0036] 200-bit line;

[0037] 210-bit line conductive portion;

[0038] 220-bit line shielding layer;

[0039] 230-bit line side wall;

[0040] 231-first side wall;

[0041] 232-second side wall;

[0042] 233-Sacrificial interlayer;

[0043] 300-insulated wire;

[0044] 400a-node contact window;

[0045] 400-contact plug;

[0046] 410 - bottom contact portion;

[0047] 420-first intermediate conductive layer;

[0048] 430 - second intermediate conductive layer;

[0049] 440 - top contact portion;

[0050] 440a-filling part;

[0051] 440b-protrusion;

[0052] 500-interval structure;

[0053] 500a-groove;

[0054] 510- first isolation layer;

[0055] 520- second isolation layer;

[0056] 600-lower electrode;

[0057] G1-first gap;

[0058] G2-second gap;

[0059] G3 - The third gap. DETAILED DESCRIPTION

[0060] The core idea of ​​the present invention is to provide a memory, including a substrate, and a plurality of bit lines and a plurality of insulating lines formed on the substrate. The bit lines and the insulating lines intersect to define a plurality of node contact windows on the substrate, and the node contact windows are filled with contact plugs. Furthermore, a spacing structure is formed between the tops of adjacent contact plugs, and a gap is formed in the spacing structure to facilitate reducing the dielectric constant of the spacing structure, thereby improving the parasitic effect between adjacent contact plugs.

[0061] The memory and the method for forming the memory provided by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0062] Figure 1 FIG. 1 is a top view of a memory in an embodiment of the present invention, which mainly illustrates bit lines and insulating lines. Figure 2 FIG. 1 is a top view of a memory device according to an embodiment of the present invention, which mainly illustrates a contact plug, and FIG. Figure 3 FIG. 1 is a top view of a memory device in an embodiment of the present invention, which mainly illustrates a contact plug and a spacer structure. Figure 4 for Figure 3 The schematic cross-sectional view of the memory in one embodiment of the present invention along the II' and II-II' directions is shown.

[0063] Combination Figure 1 and Figure 4 As shown, a plurality of active areas AA are formed in the substrate 100. For example, a first source / drain area 101 and a second source / drain area 102 are formed in the plurality of active areas AA to form a storage transistor. Adjacent active areas AA may be separated from each other by a trench isolation structure 110, and the trench isolation structure 110 specifically includes an insulating material filled in an isolation trench, and the insulating material includes, for example, silicon oxide and / or silicon nitride.

[0064] Furthermore, a plurality of word lines 120 are formed in the substrate 100, and the word lines 120 extend along the second direction (X direction) and intersect with the corresponding active area AA, and the portion of the word lines 120 intersecting with the active area AA is located between the first source / drain region 101 and the second source / drain region 102, and is used to constitute the gate structure of the storage transistor.

[0065] As shown in FIG. 4 , the word line 120 is formed in a word line groove in the substrate 100 , and the top position of the word line 120 is not higher than the top position of the word line groove. In addition, a word line shielding layer 130 is filled in the upper space of the word line groove above the word line 120 , and the word line shielding layer 130 covers the word line 120 .

[0066] Continue to refer Figure 1 and Figure 4As shown, a plurality of bit lines 200 in the memory are formed on the substrate 100. The bit lines 200 extend along a first direction (Y direction) and intersect with the corresponding active area AA space, and the portion of the bit lines 200 intersecting with the active area AA, for example, constitutes a bit line contact portion, and the bit line contact portion is electrically connected to the active area AA. In this embodiment, the bit line contact portion is electrically connected to the first source / drain region 101 of the active area AA.

[0067] Furthermore, the bit line contact portion of the bit line 200 intersecting with the active area AA is further embedded in the substrate 100. That is, the bottom of the bit line contact portion is lower than the top surface of the substrate 100. In this way, the bit line contact portion of the bit line 200 can fully contact the first source / drain region 101, thereby reducing the contact resistance between the bit line 200 and the first source / drain region 101.

[0068] Figure 5 for Figure 4 The partial enlarged view of the cross-sectional schematic diagram shown in FIG. Figure 4 and Figure 5 As shown, the bit line 200 includes a bit line conductive part 210, a bit line shielding layer 220 and a bit line spacer 230. The bit line conductive part 210 is formed on the substrate 100 and is electrically connected to the corresponding active area AA, the bit line shielding layer 220 covers the top surface of the bit line conductive part 210, and the bit line spacer 230 covers at least the sidewall of the bit line conductive part 210. That is, the bit line shielding layer 220 and the bit line spacer 230 are used to achieve electrical isolation of the bit line conductive part 210, thereby forming an externally insulated bit line 200.

[0069] In this embodiment, the bit line conductive portion 210 of the bit line 200 may include multiple conductive layers stacked in sequence. For example, the bit line conductive portion 210 includes a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence from bottom to top, wherein the material of the first conductive layer includes, for example, doped polysilicon, the material of the second conductive layer includes, for example, titanium nitride, and the material of the third conductive layer includes, for example, tungsten.

[0070] Continue to refer Figure 5 As shown, the bit line spacer 230 may be a stacked structure. For example, the bit line spacer 230 includes a first spacer 231 and a second spacer 232 arranged in sequence from the inside to the outside. In this embodiment, the bit line spacer 230 also includes a third gap G3 sandwiched between the first spacer 231 and the second spacer 232.

[0071] Combination Figure 1 and Figure 5As shown, the third gap G3 in the bit line spacer 230 on the same bit line sidewall extends continuously along the extension direction of the bit line, that is, the third gap G3 extends continuously between the first spacer 231 and the second spacer 232. In this embodiment, the bit line conductive portion 210 includes a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence from bottom to top, and the bottom position of the third gap G3 is not lower than the top surface of the first conductive layer, and the top position of the third gap G3 is higher than the third conductive layer.

[0072] Continue to refer Figure 1 and Figure 4 As shown, the insulating line 300 is formed on the surface of the substrate 100, and the extending direction of the insulating line 300 is different from the extending direction of the bit line 200, so that the insulating line 300 and the bit line 200 can intersect on the top surface of the substrate 100 to define a node contact window 400a. In this embodiment, the extending direction of the insulating line 300 is the same as the extending direction of the word line WL, both extending along the second direction (X direction), and the insulating line 300 is formed directly above the word line WL.

[0073] Furthermore, the top surfaces of the bit line 200 and the insulating line 300 are flush. For example, when the insulating line 300 is formed in combination with a planarization process, the bit line 200 can be used as a grinding stop layer. In this embodiment, the top surface of the insulating line 300 is flush with the top surface of the bit line shielding layer 220 of the bit line 200.

[0074] Key References Figure 1 As shown, in this embodiment, the insulating line 300 includes a plurality of insulating line segments which are arranged in sequence along the second direction and are disconnected from each other, the insulating line segments also extend along the extension direction of the insulating line (that is, the insulating line segments also extend along the second direction), and the insulating line segments are formed between adjacent bit lines 200 so that the two ends of the insulating line segments are respectively connected to the adjacent bit lines 200, so that the node contact window 400a can be surrounded by the insulating line segments and the adjacent bit lines 200.

[0075] In this embodiment, the bottom of the node contact window 400a further extends into the substrate 100, so that a larger area of ​​the active area AA can be exposed in the node contact window 400a (that is, at least part of the active area AA is exposed in the node contact window). In addition, by making the bottom of the node contact window 400a lower than the top surface of the substrate, it is beneficial to achieve electrical connection between the contact plug 400 filled in the node contact window 400a and the active area AA. In this embodiment, the second source / drain region 102 in the active area AA is exposed in the node contact window 400a.

[0076] Key References Figure 2 and Figure 4 As shown, the memory includes a plurality of contact plugs 400, each of which is formed in a corresponding node contact window 400a, so that the plurality of contact plugs 400 are connected to the second source / drain regions 102 corresponding to the node contact windows 400a in a one-to-one correspondence.

[0077] Furthermore, the top of the contact plug 400 also protrudes upward from the node contact window, and defines a groove between the protruding tops of adjacent contact plugs 400. That is, the top surface of the contact plug 400 is higher than the top surfaces of the bit line 200 and the insulating line 300. Furthermore, the protruding top of the contact plug 400 also extends laterally to the top surface of the bit line 200 and / or the insulating line 300, which is conducive to increasing the contact area of ​​the top surface of the contact plug 400. That is, the contact plug 400 includes a lower portion filled in the node contact window and an upper portion protruding from the node contact window, and the upper portion of the contact plug 400 constitutes the protruding top of the contact plug 400, and defines the groove between the upper portions of adjacent contact plugs 400.

[0078] In this embodiment, the focus is on Figure 4 and Figure 5 As shown, the contact plug 400 includes a bottom contact portion 410 and a top contact portion 440 , wherein the material of the bottom contact portion 410 includes, for example, polysilicon, and the material of the top contact portion 440 includes, for example, tungsten.

[0079] Specifically, the bottom contact portion 410 is filled in the node contact window to electrically contact the active area AA, and the top position of the bottom contact portion 410 is lower than the top position of the node contact window; and, the top contact portion 440 is formed above the bottom contact portion 410, and the bottom of the top contact portion 440 (i.e., the filling portion 440a) is filled in the node contact window, and the top of the top contact portion 440 (i.e., the protruding portion 440b) protrudes out of the node contact window and extends laterally to the top surface of the bit line 200 and / or the insulating line 300.

[0080] In an optional solution, the protruding top of the contact plug 400 is partially translated onto the top surface of the bit line 200 and / or the insulating line 300 relative to the bottom portion of the contact plug 400. It can be considered that in this embodiment, the protruding portion 440b of the top contact portion 440 is partially translated onto the top surface of the bit line 200 and / or the insulating line 300 relative to the filling portion 440a of the top contact portion 440 and the bottom contact portion 410.

[0081] Continue to refer Figure 5 As shown, in this embodiment, the dimension D1 of the top of the contact plug 400 extending relative to the bottom can be larger than the dimension D2 of the top shrinking relative to the bottom (D1>D2).

[0082] For example, combining Figure 2 As shown, the protrusion 440b of the top contact portion 440 is translated relative to the filling portion 440a along the first direction (Y direction) so that the protrusion 440b extends to cover the insulating line 300, and the dimension D1 of the protrusion 440b at the extension end relative to the filling portion 440a is larger than the shrinking dimension D2 of the protrusion 440b at the end away from the extension end relative to the filling portion 440a. In addition, the protrusion 440b of the top contact portion 440 can also be translated relative to the filling portion 440a along the second direction (X direction) so that the protrusion 440b also extends to cover the bit line 200, and the dimension D1 of the protrusion 440b at the extension end relative to the filling portion 440a is larger than the shrinking dimension D2 of the protrusion 440b at the end away from the extension end relative to the filling portion 440a.

[0083] In an optional solution, the contact plug 400 further includes a first intermediate conductive layer 420 and a second intermediate conductive layer 430 located between the bottom contact portion 410 and the top contact portion 440. The first intermediate conductive layer 420 is formed on the top surface of the bottom contact portion 410, and the first intermediate conductive layer 420 is, for example, a metal silicide layer (for example, the first intermediate conductive layer 420 may be specifically a cobalt metal silicide layer). By providing the metal silicide layer, the contact resistance between the bottom contact portion 410 and the conductive material above it can be effectively reduced. In addition, the second intermediate conductive layer 430 covers the top surface of the first intermediate conductive layer 420, and the second intermediate conductive layer 430 also covers the sidewalls of the node contact window that are higher than the first intermediate conductive layer 420. In this embodiment, the second intermediate conductive layer 430 covers the sidewalls of the insulating line 300 and the sidewalls of the bit line 200.

[0084] Next reference Figure 3 and Figure 4As shown, the memory further includes a spacing structure 500, and the spacing structure 500 fills the groove defined by the protruding tops of adjacent contact plugs 400 to space the adjacent contact plugs 400 (specifically, the spacing structure 500 is filled between the protruding tops of adjacent contact plugs 400). The spacing structure 500 at least covers the sidewall and bottom of the groove, and a first gap G1 is formed at the corner where the sidewall and the bottom meet. In this embodiment, the first gap G1 directly contacts the insulating line 300 and / or the bit line 200.

[0085] It should be recognized that the groove defined by the protruding top of the contact plug 400 is at least partially located above the bit line 200 and the insulating line 300. Specifically, when the protruding top of the contact plug 400 does not extend laterally, the groove defined by it corresponds to directly above the bit line 200 or the insulating line 300, and the first gap G1 located at the corner of the groove is directly in contact with the bit line 200 or the insulating line 300, and can also directly contact the contact plug 400; or, when the protruding top of the contact plug 400 extends laterally, a part of the groove defined by it corresponds to directly above the node contact window, and another part corresponds to directly above the bit line 200 or the insulating line 300, and the first gap G1 located at the corner of the groove can also directly contact the bit line 200 or the insulating line 300, and the first gap G1 located at the corner of the groove can also directly contact the contact plug 400.

[0086] Specifically, the spacing structure 500 includes a first isolation layer 510 and a second isolation layer 520, wherein the first isolation layer 510 at least covers the sidewall and the bottom of the groove, and the first gap G1 is formed in the first isolation layer 510 at the corner where the sidewall and the bottom meet. In addition, the second isolation layer 520 is formed on the first isolation layer 510 and fills the groove. In this embodiment, a second gap G2 is also formed in the second isolation layer 520, so as to further reduce the dielectric constant of the dielectric material between adjacent contact plugs 500 and improve the parasitic effect between adjacent contact plugs 500.

[0087] In addition, as described above, the groove defined by the top of the adjacent contact plug 400 is at least partially located directly above the bit line 200, based on which the top opening of the third gap G3 in the bit line spacer 230 of the bit line 200 can be extended to the bottom of the groove. In this embodiment, the first isolation layer 510 in the groove covers the third gap G3, that is, the opening of the third gap G3 directly below the spacing structure 500 is covered by the first isolation layer 510.

[0088] Continue to refer Figure 4 and Figure 5 As shown, the grooves between the protruding tops of adjacent contact plugs 400 further extend into the bit lines 200 and the insulating lines 300 directly below, so that the bottom of the spacing structure 500 can further extend into the bit lines 200 and the insulating lines 300. In this way, the electrical isolation between adjacent contact plugs 400 is ensured.

[0089] For further details, please refer to Figure 6 As shown, the memory further includes a storage capacitor, and the lower electrode 600 of the storage capacitor is electrically connected to the top of the contact plug 400. In this embodiment, the second isolation layer 520 of the spacer structure 500 fills the grooves between adjacent contact plugs 400 and also covers the contact plugs 400, and the lower electrode 600 penetrates the second isolation layer 520 to be electrically connected to the top surface of the protruding top of the contact plug 400.

[0090] Based on the memory as described above, a method for forming the memory is described in detail below in conjunction with the accompanying drawings. Figure 7 is a flow chart of a method for forming a memory in one embodiment of the present invention, Figure 8a to Figure 8d FIG. 1 is a schematic structural diagram of a method for forming a memory in an embodiment of the present invention during its preparation process.

[0091] First, execute step S100. Figure 8a As shown, a substrate 100 is provided, and a plurality of bit lines 200 and a plurality of insulating lines 300 are formed on the substrate 100 . The bit lines 200 and the insulating lines 300 intersect to define a plurality of node contact windows 400 a .

[0092] A plurality of active areas AA are formed in the substrate 100. Specifically, a plurality of trench isolation structures 110 may be formed in the substrate 100 to define the plurality of active areas AA. Also, the first source / drain region 101 and the second source / drain region 102 in the active area AA may be formed by an ion implantation process. In this embodiment, each of the second source / drain regions 102 corresponds to a node contact window 400a.

[0093] In a specific solution, the bit line 200 may be formed on the substrate 100 first, and then the insulating line 300 may be formed on the substrate 100. Furthermore, the top surface of the bit line 200 may be flush with the top surface of the insulating line 300.

[0094] The bit line 200 extends continuously along the first direction. The insulating line 300 includes a plurality of insulating line segments arranged in sequence along the second direction, and each insulating line segment also extends between adjacent bit lines 200 along the second direction to connect with the bit line 200, thereby surrounding the node contact window 400a. It can be understood that the insulating line 300 extends discontinuously along the second direction, and the bit line 200 is spaced between adjacent insulating line segments in the same insulating line 300.

[0095] In this embodiment, the substrate 100 of the second source / drain region 102 may be further etched by utilizing the pattern defined by the bit line 200 and the insulating line 300 , so that the bottom of the node contact window 400 a is further embedded in the substrate 100 .

[0096] Continue to refer Figure 8a As shown, the bit line 200 includes a bit line conductive part 210, a bit line shielding layer 220 and a bit line spacer 230. The bit line shielding layer 220 and the bit line spacer 230 cover the bit line conductive part 210 from the top surface and the sidewalls thereof respectively, so as to insulate the bit line 200 from the outside.

[0097] Furthermore, the bit line spacer 230 includes a first spacer 231 and a second spacer 232 that sequentially cover the sidewalls of the bit line conductive portion 210. In this embodiment, a sacrificial interlayer 233 is sandwiched between the first spacer 231 and the second spacer 232, and the sacrificial interlayer 233 can be removed in subsequent processes to release corresponding space.

[0098] Then, step S200 is performed. For details, refer to Figure 8b As shown, a contact plug 400 is formed, the contact plug 400 fills the node contact window 400 a , and the top of the contact plug 400 also protrudes upward from the node contact window 400 a , and recesses 500 a are defined between the protruding tops of adjacent contact plugs 400 .

[0099] Specifically, the method for forming the contact plug 400 may include the following steps.

[0100] The first step is to fill the bottom contact 410 in the node contact window 400a to electrically connect with the active area AA, wherein the top surface of the bottom contact 410 is lower than the top surface of the bit line 200 and the insulating line 300, and the material of the bottom contact 410 includes polysilicon, for example.

[0101] The second step is to form a first intermediate conductive layer 420 on the top surface of the bottom contact portion 410. The first intermediate conductive layer 420 is, for example, a metal silicide layer. Specifically, the method for forming the first intermediate conductive layer 420 includes, for example: first, depositing a metal layer on the substrate 100, the metal layer covering the top surface of the bottom contact portion 410, and covering the bit line 200 and the insulating line 300; then, performing a thermal annealing process to react the metal in the metal layer with the polysilicon in the bottom contact portion 410, thereby self-aligningly forming the metal silicide layer on the top surface of the bottom contact portion 410; then, removing the unreacted portion of the metal layer.

[0102] In a third step, a second intermediate conductive layer 430 is formed, where the second intermediate conductive layer 430 covers the first intermediate conductive layer 420 , the bit line 200 , and the insulating line 300 .

[0103] The fourth step is to form a conductive material layer, which fills the node contact window and further covers the top surface of the bit line 200 and the insulating line 300. The conductive material layer can be a planarized film layer so that the top surface of the conductive material layer is substantially flat.

[0104] In a fifth step, the conductive material layer is patterned to form a top-layer contact portion 440 .

[0105] Specifically, a mask layer may be used to perform a patterning process, including: forming a mask layer on the conductive material layer, the mask layer having a plurality of mask patterns corresponding to contact plugs (in this embodiment, the mask patterns are patterns corresponding to top-layer contacts), the mask patterns covering at least part of the node contact window and also extending to cover the adjacent bit lines and / or insulating lines. In this embodiment, the mask pattern is horizontally offset relative to the node contact window 400a, so that the mask pattern covers the node contact window and the bit line 200, and / or the mask pattern covers the node contact window and the insulating line 300. In this way, when the conductive material layer is patterned using the mask layer, the formed top-layer contact 440 can be partially translated to the bit line 200 and / or the insulating line 300.

[0106] Furthermore, the conductive material layer is etched using the mask layer, and the etching stops on the bit line 200 and the insulating line 300, thereby disconnecting the top contact portions 440 in different node contact windows from each other. That is, the bottom position of the groove 500a between the tops of adjacent contact plugs 400 stops on the bit line 200 and the insulating line 300.

[0107] In addition, specific reference Figure 8b As shown, the insulating line 300 and the bit line 200 (specifically the bit line shielding layer) exposed in the groove 500a can be further etched downward. In this way, on the one hand, the conductive material residue can be avoided to ensure that adjacent contact plugs 400 are disconnected from each other; on the other hand, the top of the sacrificial interlayer 233 in the bit line sidewall 230 can be exposed.

[0108] For further details, please refer to Figure 8c As shown, the sacrificial interlayer in the bit line spacer 230 can be removed through the groove 500a, so that a third gap G3 can be formed between the first spacer 231 and the second spacer 232, and the top opening of the third gap G3 is connected to the groove 500a above it.

[0109] Then, step S300 is performed. For details, refer to Figure 8d As shown, a spacing structure 500 is formed in the groove 500a to space adjacent contact plugs 400. The spacing structure 500 at least covers the sidewall and bottom of the groove, and a first gap G1 is formed in the spacing structure at the corner where the sidewall and the bottom meet, and the first gap G1 directly contacts the bit line 200 and / or the insulation line 300.

[0110] Specifically, the method for forming the spacing structure may include: first, forming a first isolation layer 510, the first isolation layer 510 covers the bottom and sidewalls of the groove 500a, and a first gap G1 is also formed in the first isolation layer 510 at the corner where the sidewall and the bottom meet. The first isolation layer 510 may be formed by a deposition process with poor coverage performance, so as to facilitate the formation of the first gap G1 in the first isolation layer 510. In this embodiment, the first isolation layer 510 also covers the top opening of the third gap G3 in the bit line spacer. Afterwards, a second isolation layer 520 is formed in the groove 520, and in this embodiment, a second gap G2 is also formed in the second isolation layer 520.

[0111] In a further solution, the method for forming the memory further includes: forming a storage capacitor. Specifically, it includes: forming a lower electrode of the storage capacitor, wherein the bottom of the lower electrode is electrically connected to the top surface of the contact plug 400 .

[0112] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

[0113] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0114] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A memory, characterized in that: include: substrate; A plurality of bit lines and a plurality of insulating lines are formed on the substrate, and the bit lines and the insulating lines intersect to define a plurality of node contact windows, and the bit lines include bit line spacers formed on sidewalls thereof; a contact plug filled in the node contact window, wherein the top of the contact plug further protrudes upward from the node contact window and defines a groove between the protruding tops of adjacent contact plugs; and A spacing structure fills the groove to space adjacent contact plugs, wherein the spacing structure at least covers the sidewall and the bottom of the groove, and a first gap is formed in the spacing structure at a corner where the sidewall and the bottom meet.

2. The memory according to claim 1, wherein: The spacing structure includes a first isolation layer and a second isolation layer, the first isolation layer at least covers the side wall and the bottom of the groove, and the first gap is also formed in the first isolation layer at the corner where the side wall and the bottom meet, and the second isolation layer is formed on the first isolation layer and fills the groove.

3. The memory according to claim 2, wherein: A second gap is formed in the second isolation layer.

4. The memory according to claim 1, wherein: The first void is also in direct contact with the contact plug.

5. The memory according to claim 1, wherein: The bit line comprises a bit line conductive part, a bit line shielding layer covering the top surface of the bit line conductive part, and a bit line sidewall covering the side wall of the bit line conductive part; The bit line spacer includes a first spacer, a second spacer, and a third gap sandwiched between the first spacer and the second spacer.

6. The memory according to claim 5, characterized in that The third gap in the bit line spacer on the same sidewall extends continuously along the extending direction of the bit line.

7. The memory according to claim 5, wherein: The opening of the third gap directly below the spacing structure is covered by the spacing structure.

8. The memory according to claim 1, wherein: The top of the contact plug protrusion also extends laterally to the top surface of the bit line and / or the insulation line.

9. The memory according to claim 8, characterized in that The top of the contact plug protrusion is translated onto the top surface of the bit line and / or the insulation line relative to the bottom portion of the contact plug; The dimension of the top portion extended by translation relative to the bottom portion is greater than the dimension of the top portion contracted by translation relative to the bottom portion.

10. The memory according to claim 1, wherein: The grooves between the tops of adjacent contact plug protrusions further extend into the bit lines and the insulation lines directly below, so that the bottoms of the spacer structures extend into the bit lines and the insulation lines.

11. The memory according to claim 1, wherein: The memory further includes a storage capacitor, and a lower electrode of the storage capacitor is electrically connected to a top of the contact plug.

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