Flash memory layout, flash memory and method of manufacturing the same

Abstract

The application provides a flash memory layout, a flash memory and a manufacturing method of the flash memory. In the flash memory layout, the connection pattern is in a straight strip shape. Therefore, in the flash memory, the cross section of the connection part is in a straight strip shape. Compared with the connection part in the prior art, the structure is relatively simple, the process can be simplified, and the problem of photoresist floating can be avoided in the process of forming the connection part. Further, in the flash memory layout, there is a spacing area between two word line patterns, and the connection pattern is aligned with the spacing area. Therefore, in the flash memory, there is a spacing opening between two word lines in each word line group, and the spacing opening is aligned with the connection part. Therefore, the distance between the connection part and the word line is increased, the process window is increased, and the short circuit is avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a flash memory layout, a flash memory, and a method for manufacturing the same. Background Technology

[0002] Flash memory, as a secure and fast storage medium, has become the primary carrier of data and programs in embedded systems due to its advantages such as small size, large capacity, low cost, and data retention even when power is off. In recent years, with the rapid development of the smart electronics market, the use of various MCUs (microcontroller units) and SoCs (System-on-Chip) has penetrated into all aspects of daily life, including automotive electronics, industrial control, and medical products. Figure 1 As shown, in existing flash memory, the interconnect 10 is used to connect the control gates of two adjacent bit cell arrays and provide a pickup area for the device. However, the interconnect 10 is zig-shaped. During the fabrication of the interconnect 10, due to its complex structure and increasingly smaller design rules, the process window of the interconnect 10 is small. During the formation of the interconnect 10, the problem of photoresist float is prone to occur. Furthermore, due to the small spacing between the interconnect 10 and the word line (located between two adjacent interconnects), the contact structure on the interconnect 10 is more likely to short-circuit with the word line. Summary of the Invention

[0003] The purpose of this invention is to provide a flash memory layout, a flash memory, and a method for manufacturing the same, in order to solve the problems of photoresist float and small process window in the manufacturing process of flash memory.

[0004] To address the aforementioned technical problems, the present invention provides a flash memory layout, the flash memory layout comprising:

[0005] The control gate layout includes multiple parallel control gate pattern groups, each control gate pattern group includes two spaced control gate patterns, and each control gate pattern includes a vertical connecting pattern and two vertical gate patterns, with the connecting pattern located between the two gate patterns;

[0006] The character line layout includes multiple parallel groups of character line graphics, each group of character line graphics including two vertical character line graphics with a gap between the two character line graphics;

[0007] In each of the control gate graphic groups, a word line graphic group is provided between the two control gate graphics, and in each of the control gate graphics, the connecting graphic is aligned with the interval area.

[0008] Optionally, in the flash memory layout, the plurality of control gate pattern groups are arranged in parallel along a first direction and extend along a second direction. In each control gate pattern group, two control gate patterns are spaced apart along the first direction, and the spacing between two adjacent control gate patterns is 35nm to 60nm. The first direction is perpendicular to the second direction.

[0009] Optionally, in the flash memory layout, the plurality of word line pattern groups are arranged in parallel along the first direction and extend along the second direction, wherein in the second direction, there is a gap region between the two word line patterns.

[0010] Optionally, in the flash memory layout, the flash memory layout further includes a contact hole layout, which includes multiple contact hole pattern groups. Each contact hole pattern group includes two contact hole patterns that are staggered in position. One control gate pattern group corresponds to one contact hole pattern group. In each control gate pattern group, one contact hole pattern is provided on each of the two control gate patterns. The projection of the contact hole pattern on the control gate layout is located within the connection pattern.

[0011] Based on the same inventive concept, the present invention also provides a flash memory, the flash memory comprising:

[0012] Substrate;

[0013] A plurality of parallel control gate groups are located on the substrate, each control gate group including two spaced-apart control gates, each control gate including a connecting portion and two gate portions in the shape of a straight bar, the connecting portion being located between the two gate portions;

[0014] Multiple word line groups located on the substrate, each word line group comprising two straight word lines, wherein the two word lines in each word line group have a gap opening between them;

[0015] In each of the control gate groups, a word line group is provided between the two control gates, and in each of the control gates, the connecting portion is aligned with the interval opening.

[0016] Optionally, in the flash memory, the plurality of control gate groups are arranged in parallel along a first direction and extend along a second direction. In each control gate group, two control gates are spaced apart along the first direction, and the spacing between two adjacent control gates is 35nm to 60nm. The first direction is perpendicular to the second direction.

[0017] Optionally, in the flash memory, the plurality of word line groups are arranged in parallel along the first direction and extend along the second direction, wherein the spacing opening is provided between two word lines in the second direction.

[0018] Optionally, in the flash memory, the flash memory further includes a plurality of contact structure groups located on the plurality of control gate groups, each contact structure group including two contact structures arranged in a staggered manner, wherein one control gate group corresponds to one contact structure group, and in each control gate group, one contact structure is provided on each of the two control gates.

[0019] Based on the same inventive concept, the present invention also provides a method for manufacturing a flash memory, the method comprising:

[0020] Provide substrate;

[0021] Multiple parallel control gate groups are formed on the substrate. Each control gate group includes two control gates spaced apart. Each control gate includes a connecting portion with a straight cross-section and two gate portions with straight cross-sections. The connecting portion is located between the two gate portions.

[0022] Multiple parallel character line groups are formed on the substrate, each character line group including two straight character lines with a gap between the two character lines;

[0023] In each of the control gate groups, a word line group is provided between the two control gates, and in each of the control gates, the connecting portion is aligned with the interval opening.

[0024] Optionally, in the method for manufacturing the flash memory, a first control gate opening exposing the substrate is provided between two adjacent control gate groups, and a second control gate opening exposing the substrate is provided between two control gates in each control gate group, the word line groups filling the second control gate openings; and the method for forming the plurality of word line groups includes:

[0025] A word line material layer is formed, which fills the first control gate opening and the second control gate opening and covers the plurality of control gate groups;

[0026] A patterned photoresist layer is formed on the word line material layer. The patterned photoresist layer has a first photoresist opening and a second photoresist layer opening. The first photoresist opening exposes the word line material layer on the control gate group and the word line material layer in the first control gate opening. The second photoresist opening exposes a portion of the word line material layer in the second control gate opening.

[0027] The word line material layer is etched using the patterned photoresist layer as a mask to remove the word line material layer on the control gate and the word line material layer in the first control gate opening, as well as a portion of the word line material layer in the second control gate opening, and the remaining word line material layer in the second control gate opening is used to form the word line group.

[0028] Optionally, in the manufacturing method of the flash memory, the plurality of control gate groups are arranged in parallel along a first direction and extend along a second direction. In each control gate group, two control gates are spaced apart along the first direction, and the spacing between two adjacent control gates is 35nm to 60nm, wherein the first direction is perpendicular to the second direction.

[0029] Optionally, in the method for manufacturing the flash memory, the plurality of word line groups are arranged in parallel along the first direction and extend along the second direction, wherein the spacing opening is provided between the two word lines in the second direction.

[0030] Optionally, in the method for manufacturing the flash memory, the method further includes:

[0031] Multiple contact structure groups are formed on the multiple control gate groups, each contact structure group including two contact structures arranged in a staggered manner, wherein one control gate group corresponds to one contact structure group, and in each control gate group, one contact structure is provided on each of the two control gates.

[0032] In summary, this invention provides a flash memory layout, a flash memory, and a method for manufacturing the same. In the flash memory layout, the connection pattern is in the form of straight strips. This results in a straight-strip cross-section for the connection portion in the flash memory, which is simpler in structure compared to existing connection portions, simplifying the process and avoiding photoresist float issues during connection portion formation. Furthermore, in the flash memory layout, a gap region exists between two word line patterns, and the connection pattern is aligned with this gap region. This creates a gap opening between two word lines in each word line group, aligned with the connection portion. This increases the spacing between the connection portion and the word lines, thereby increasing the process window and preventing short circuits. Attached Figure Description

[0033] Figure 1 This is the existing landscape of flash memory technology;

[0034] Figure 2 This is a schematic diagram of the flash memory layout in this embodiment;

[0035] Figure 3 This is a top view of the flash memory in this embodiment;

[0036] Figure 4 This is a three-dimensional schematic diagram of the flash memory in this embodiment;

[0037] Figure 5 This is a schematic flowchart of the manufacturing method of the flash memory in this embodiment;

[0038] Figures 6 to 9 This is a schematic diagram of the structure formed in the manufacturing method of the flash memory according to an embodiment of the present invention;

[0039] The reference numerals in the attached figures are explained as follows:

[0040] 10-Connecting part;

[0041] 110 - Control gate pattern group; 111 - Control gate pattern; 111A - Connection pattern; 111B, 111C - Gate patterns;

[0042] 120 - Character line graphic group; 120A - Interval area; 121, 122 - Character line graphics;

[0043] 130 - Contact hole pattern group; 131, 132 - Contact hole patterns;

[0044] 200 - Substrate; 201 - Isolation region; 202 - Active region;

[0045] 210 - Control gate group; 211 - Control gate; 211A - Connection part; 211B, 211C - Gate part;

[0046] 210A - First control gate opening; 210B - Second control gate opening;

[0047] 220 - Word line group; 220A - Word line material layer; 220B - Spacing opening; 221, 222 - Word line;

[0048] 230 - Patterned photoresist layer; 230A - First photoresist opening; 230B - Second photoresist opening

[0049] 240 - Contact structure group; 241, 242 - Contact structure. Detailed Implementation

[0050] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed account of the flash memory layout, flash memory, and manufacturing method thereof proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0051] Figure 2 This is a schematic diagram of the flash memory layout in this embodiment. Figure 2 As shown, the present invention provides a flash memory layout, which includes a control gate layout and a word line layout. The control gate layout includes a plurality of parallel control gate pattern groups 110, each control gate pattern group 110 including two spaced-apart control gate patterns 111, each control gate pattern 111 including a vertically shaped connection pattern 111A and two vertically shaped gate patterns 111B and 111C, wherein the connection pattern 111A is located between the gate patterns 111B and 111C.

[0052] like Figure 2 As shown, the plurality of control gate pattern groups 110 are arranged parallel to each other along a first direction Y and extend along a second direction X. In each control gate pattern group 110, two control gate patterns 111 are spaced apart along the first direction Y, wherein the first direction Y is perpendicular to the second direction X. Preferably, the spacing between two adjacent control gate patterns 111 is 35nm to 60nm to ensure that the minimum spacing between each pattern meets the DRC (desigh rule check) rule, while preventing the spacing between each pattern from being too large, thereby further reducing the area of ​​a single control gate pattern group 110 and the size of the memory layout structure.

[0053] In this embodiment, the gate patterns 111B and 111C are used to form the gate portion in the flash memory, and the gate portion is used to constitute a control gate. The connection pattern 111A is used to form the connection portion in the flash memory, and the connection portion is used to connect the gate portions of two adjacent memory cell arrays in the flash memory to realize the electrical connection between the gate portions of two adjacent memory cell arrays, and can provide a contact area for the device.

[0054] Since the connection pattern 111A in this embodiment is a straight strip, the cross-section of the connection part in the flash memory is a straight strip. Compared with the connection part in the prior art, the structure is simpler, which can simplify the process and avoid the problem of photoresist floating during the formation of the connection part.

[0055] like Figure 2As shown, the character line layout includes multiple parallel character line graphics 120. Each character line graphic 120 includes two vertical character line graphics 121 and 122, with a gap region 120A between the character line graphics 121 and 122. In each control gate graphic group 110, a character line graphic group 120 is disposed between two control gate graphics 111. In each control gate graphic 111, the connecting graphic 111A is aligned with the gap region 120A.

[0056] In this embodiment, the word line pattern 120 is used to form word line groups in the flash memory, and the word line patterns 121 and 122 are used to form word lines in the flash memory. Since the connecting pattern 111A is aligned with the spacing region 120A, in the flash memory, there is a gap between two word lines in each word line group, and the gap is aligned with the connecting portion. This increases the spacing between the connecting portion and the word line, thereby increasing the process window and preventing short circuits.

[0057] like Figure 2 As shown, in this embodiment, the flash memory layout further includes a contact hole layout, which includes multiple contact hole pattern groups 130. Each contact hole pattern group 130 includes two contact hole patterns 131 and 132 that are staggered in position. One control gate pattern group 110 corresponds to one contact hole pattern group 130. In each control gate pattern group 110, one contact hole pattern 131 or one contact hole pattern 132 is provided on each of the two control gate patterns 111. The projections of the contact hole patterns 131 and 132 on the control gate layout are located within the connection pattern 111A.

[0058] In this embodiment, the contact hole pattern group 130 is used to form the contact structure group in the flash memory, and the contact hole pattern 131 and contact hole pattern 132 are used to form the contact structure in the flash memory. In addition, since the two contact hole patterns 131 and 132 in each contact hole pattern group 130 are staggered in position, it can prevent two adjacent contact structures in the flash memory from connecting together, thereby avoiding short circuits between contact structures.

[0059] Figure 3 This is a top view of the flash memory in this embodiment; Figure 4 This is a three-dimensional schematic diagram of the flash memory in this embodiment. (As shown...) Figure 3 and Figure 4As shown, based on the same inventive concept, the present invention also provides a flash memory, the flash memory comprising: a substrate 200; a plurality of parallel-arranged control gate groups 210 located on the substrate 200, each control gate group 210 comprising two spaced-apart control gates 211, each control gate 211 comprising a connecting portion 211A with a straight cross-section and two gate portions 211B and 211C with straight cross-sections; a plurality of word line groups 220 located on the substrate 200, each word line group 220 comprising two word lines 221 and 222 with straight cross-sections, wherein in each word line group 220, a spacer opening 220B is provided between the word line 221 and the word line 222.

[0060] In this embodiment, as Figure 4 As shown, the substrate 200 has an isolation region (STI) 201 and an active region (ACT) 202, the isolation region being, for example, a shallow trench isolation structure. The substrate 200 is a silicon substrate. In other embodiments, the material of the substrate 200 may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0061] like Figure 3 and Figure 4 As shown, the plurality of control gate groups 210 are arranged parallel to each other along a first direction Y and extend along a second direction X. In each control gate group 210, two control gates 211 are spaced apart along the first direction Y, wherein the first direction Y is perpendicular to the second direction X. Preferably, the spacing between two adjacent control gates 211 is 35nm to 60nm to ensure the process windows of word lines 221 and 222.

[0062] In this embodiment, the connection portion 211A is made of the same material as the gate portions 211B and 211C, all of which are doped polysilicon. The connection portion 211A is located between the two gate portions 211B and 211C, which form the control gates of two adjacent memory cell arrays. The connection portion 211A is used to achieve electrical connection between the two adjacent memory cell arrays. Furthermore, since the cross-section (i.e., the horizontal cross-sectional shape) of the connection portion 211A is straight, its structure is simpler than that of existing connection portions, simplifying the process and avoiding the problem of photoresist float during the formation of the connection portion 211A.

[0063] In this embodiment, the plurality of word line groups 220 are arranged parallel to each other along the first direction Y and extend along the second direction X. In the second direction X, there is a spacing opening 220B between word lines 221 and 222. Because of the spacing opening 220B between word lines 221 and 222, the area of ​​the flash memory occupied by word lines 221 and 222 can be reduced, and the photolithography window can be increased. Furthermore, in each control gate group 210, a word line group 220 is disposed between two control gates 211. In each control gate 211, the connecting portion 211A is aligned with the spacing opening 220B, thereby increasing the spacing between the connecting portion 211A and the word lines 221 and 222, thus increasing the process window and preventing short circuits. In addition, because the connecting portion 211A is aligned with the spacing opening 220B, the process window of the contact structures 241 and 242 formed on the connecting portion 211A can also be increased.

[0064] like Figure 3 and Figure 4 As shown, the flash memory also includes a plurality of contact structure groups 240 located on the plurality of control gate groups 210. Each contact structure group 240 includes two contact structures 241 and 242 that are staggered in position. By staggering the positions of contact structures 241 and 242, it is beneficial to avoid short circuits between contact structures 241 and 242.

[0065] like Figure 3 As shown, one control gate group 210 corresponds to one contact structure group 240. In each control gate group 210, each of the two control gates 211 is provided with one contact structure 241 or contact structure 242. The contact structure 241 and the contact structure 242 are used to realize the electrical connection between the connection part 211A and other circuits.

[0066] In this embodiment, the materials of the contact structures 241 and 242 can be copper, aluminum, tungsten, gold, silver, or titanium. In this embodiment, the materials of the contact structures 241 and 242 are copper to improve their electrical conductivity.

[0067] Furthermore, the flash memory also includes an inter-layer dielectric (ILD) layer located on the control gate group 210. Contact structures 241 and 242 are respectively located within the inter-layer dielectric layer. It should be noted that, for better illustration of the inventive points of this embodiment, the description of the inter-layer dielectric layer is omitted in the embodiments, and its illustration is also omitted in the accompanying drawings.

[0068] Figure 5 This is a schematic flowchart illustrating the manufacturing method of the flash memory in this embodiment. Figure 5 As shown, based on the same inventive concept, the present invention also provides a method for manufacturing a flash memory, the method comprising:

[0069] Step S1: Provide a substrate;

[0070] Step S2: A plurality of parallel control gate groups are formed on the substrate. Each control gate group includes two control gates spaced apart. Each control gate includes a connecting portion with a straight cross-section and two gate portions with straight cross-sections. The connecting portion is located between the two gate portions.

[0071] Step S3: Form a plurality of parallel word line groups on the substrate, each word line group including two word lines with a straight cross-section, and the two word lines having a gap opening between them;

[0072] In each of the control gate groups, a word line group is provided between the two control gates, and in each of the control gates, the connecting portion is aligned with the interval opening.

[0073] Figures 6 to 9 This is a schematic diagram of the structure formed in the manufacturing method of the flash memory according to an embodiment of the present invention. The following will refer to the accompanying drawings. Figures 6 to 9 The manufacturing method of the flash memory provided by the present invention will be described in more detail.

[0074] like Figure 6 As shown, in step S1, a substrate 200 is provided. In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the material of the substrate 200 may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc., or other types of substrates.

[0075] Continue to refer to Figure 6 As shown, in step S2, a plurality of parallel control gate groups 210 are formed on the substrate 200. Each control gate group 210 includes two spaced-apart control gates 211. Each control gate 211 includes a connecting portion 211A with a straight cross-section and two gate portions 211B and 211C with straight cross-sections. The connecting portion 211A is located between the gate portions 211B and 211C. Because the connecting portion 211A has a straight cross-section, its structure is simpler than that of the connecting portion 211A in the prior art, which simplifies the process and avoids the problem of photoresist float during the formation of the connecting portion 211A.

[0076] Specifically, the method for forming the plurality of control gate groups 210 includes: first, forming a control gate material layer (not shown) on the substrate 200, wherein the control gate material layer is made of polycrystalline silicon and can be formed by chemical vapor deposition; after forming the control gate material layer, ion doping is performed on the control gate material layer to make the control gate material layer conductive; then, etching of the control gate material layer is performed using the control gate layout provided in this embodiment to form the plurality of control gate groups 210.

[0077] like Figure 6 As shown, the plurality of control gate groups 210 are arranged in parallel along the first direction Y and extend along the second direction X. In each control gate group 210, two control gates 211 are spaced apart along the first direction Y, and the spacing between two adjacent control gates 211 is 35nm to 60nm. The first direction Y is perpendicular to the second direction X.

[0078] like Figure 6 As shown, after the plurality of control gate groups 210 are formed, there is a first control gate opening 210A between two adjacent control gate groups 210 that exposes the substrate 200. In each control gate group 210, there is a second control gate opening 210B between two control gates 211 that exposes the substrate 200. The second control gate opening 210B can be used to define the position of word line group 220.

[0079] like Figures 7-9 As shown, in step S3, a plurality of parallel word line groups 220 are formed on the substrate 200. Each word line group 220 includes two word lines 221 and 222 with straight cross-sections, and a gap opening 220B is provided between the word lines 221 and 222. The plurality of word line groups 220 are arranged parallel to each other along the first direction Y and extend along the second direction X, where the gap opening 220B is provided between the word lines 221 and 222 in the second direction X.

[0080] like Figure 9 As shown, in each control gate group 210, a word line group 220 is provided between the two control gates 211. In each control gate 211, the connecting portion 211A is aligned with the spacing opening 220B. Since there is a spacing opening 220B between the two word lines 221 and 222 in each word line group 220, and the spacing opening 220B is aligned with the connecting portion 211A, the distance between the connecting portion 211A and the word lines 221 and 222 is increased, thereby increasing the process window and avoiding short circuits.

[0081] In this embodiment, the method for forming the plurality of word line groups 220 includes: firstly, as... Figure 7 As shown, a word line material layer 220A is formed, which fills the first control gate opening 210A and the second control gate opening 210B and covers the plurality of control gate groups 210. The word line material layer 220A is made of polycrystalline silicon and can be formed using a chemical vapor deposition process. Next, as... Figure 8 As shown, a patterned photoresist layer 230 is formed on the word line material layer 220A. The patterned photoresist layer 230 has a first photoresist opening 230A and a second photoresist opening 230B. The first photoresist opening 230A exposes the word line material layer 220A on the control gate assembly 210 and the word line material layer 220A in the first control gate opening 210A. The second photoresist opening 230B exposes a portion of the word line material layer 220A in the second control gate opening 210B. In this embodiment, the patterned photoresist layer 230 has the pattern of the word line layout provided in this embodiment.

[0082] Next, as Figure 9 As shown, the word line material layer 220A is etched using the patterned photoresist layer 230 as a mask to remove the word line material layer 220A on the control gate 211 and in the first control gate opening 210A, as well as a portion of the word line material layer 220A in the second control gate opening 210B. The remaining word line material layer 220A in the second control gate opening 210B is then used to form the word line group 220. The word line material layer 220A can be etched using a plasma etching process to form the word line group 220. After forming the word line group 220, the top surfaces of word lines 221 and 222 are higher than the top surface of the control gate 211.

[0083] like Figure 3 As shown, after forming the word line group 220, the manufacturing method of the flash memory further includes: forming a plurality of contact structure groups 240 on the plurality of control gate groups 210, each contact structure group 240 including contact structures 241 and 242 arranged in staggered positions, wherein one control gate group 210 corresponds to one contact structure group 240, and in each control gate group 210, each of the two control gates 211 is provided with one contact structure 241 or one contact structure 242.

[0084] Specifically, the method for forming the plurality of contact structure groups 240 includes: First, depositing an interlayer dielectric layer (not shown) on the global surface of the substrate 200, the interlayer dielectric layer being made of silicon oxide. Then, etching the interlayer dielectric layer using the contact hole layout provided in this embodiment to form a plurality of contact hole groups in the interlayer dielectric layer. One contact hole group corresponds to one control gate group 210, and each contact hole group includes two contact holes. The two contact holes in each contact hole group are staggered in position to increase the spacing between adjacent contact holes and avoid breakdown of the dielectric layer during contact hole formation. Each contact hole is aligned with the connection portion 211A of its corresponding control gate 211. Next, a conductive layer is filled into the plurality of contact holes to form a plurality of contact structure groups 240.

[0085] In this embodiment, the conductive layer material can be copper, aluminum, tungsten, gold, silver, or titanium, and can be formed by physical vapor deposition. In this embodiment, the conductive layer material is copper to improve the electrical conductivity of the contact structure 241 and contact structure 242.

[0086] In summary, this invention provides a flash memory layout, a flash memory, and a method for manufacturing the same. In the flash memory layout, the connection pattern is in the form of straight strips. This results in a straight-strip cross-section for the connection portion in the flash memory, which is simpler in structure compared to existing connection portions, simplifying the process and avoiding photoresist float issues during connection portion formation. Furthermore, in the flash memory layout, a gap region exists between two word line patterns, and the connection pattern is aligned with this gap region. This creates a gap opening between two word lines in each word line group, aligned with the connection portion. This increases the spacing between the connection portion and the word lines, thereby increasing the process window and preventing short circuits.

[0087] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A flash memory layout, characterized in that, The flash memory layout includes: The control gate layout includes multiple parallel control gate pattern groups, each control gate pattern group includes two spaced control gate patterns, and each control gate pattern includes a vertical connecting pattern and two vertical gate patterns, with the connecting pattern located between the two gate patterns; The character line layout includes multiple parallel character line graphic groups, each character line graphic group including two straight character line graphics, with a gap between the two character line graphics, the multiple character line graphic groups are arranged in parallel along a first direction and extend along a second direction, with the gap between the two character line graphics in the second direction, and the first direction is perpendicular to the second direction; In each of the control gate graphic groups, a word line graphic group is provided between the two control gate graphics, and in each of the control gate graphics, the connecting graphic is aligned with the interval area.

2. The flash memory layout as described in claim 1, characterized in that, The plurality of control gate pattern groups are arranged in parallel along a first direction and extend along a second direction. In each control gate pattern group, two control gate patterns are spaced apart along the first direction, and the spacing between two adjacent control gate patterns is 35nm to 60nm.

3. The flash memory layout as described in claim 1, characterized in that, The flash memory layout also includes a contact hole layout, which includes multiple contact hole pattern groups. Each contact hole pattern group includes two contact hole patterns that are staggered in position. One control gate pattern group corresponds to one contact hole pattern group. In each control gate pattern group, one contact hole pattern is provided on each of the two control gate patterns. The projection of the contact hole pattern on the control gate layout is located within the connection pattern.

4. A flash memory, characterized in that, The flash memory includes: Substrate; A plurality of parallel control gate groups are located on the substrate. Each control gate group includes two control gates spaced apart. Each control gate includes a connecting portion with a straight cross-section and two gate portions with straight cross-sections. The connecting portion is located between the two gate portions. A plurality of word line groups located on the substrate, each word line group including two word lines with a straight cross-section, wherein there is a gap opening between the two word lines in each word line group, wherein the plurality of word line groups are arranged in parallel along a first direction and extend along a second direction, wherein there is the gap opening between the two word lines in the second direction, and the first direction is perpendicular to the second direction; In each of the control gate groups, a word line group is provided between the two control gates, and in each of the control gates, the connecting portion is aligned with the interval opening.

5. The flash memory as described in claim 4, characterized in that, The plurality of control gate groups are arranged in parallel along a first direction and extend along a second direction. In each control gate group, two control gates are spaced apart along the first direction, and the spacing between two adjacent control gates is 35nm to 60nm.

6. The flash memory as claimed in claim 4, characterized in that, The flash memory also includes a plurality of contact structure groups located on the plurality of control gate groups, each contact structure group including two contact structures arranged in a staggered manner, wherein one control gate group corresponds to one contact structure group, and in each control gate group, one contact structure is provided on each of the two control gates.

7. A method for manufacturing a flash memory, characterized in that, The method for manufacturing the flash memory includes: Provide substrate; A plurality of parallel control gate groups are formed on the substrate. Each control gate group includes two spaced-apart control gates. Each control gate includes a connecting portion with a straight cross-section and two gate portions with straight cross-sections. The connecting portion is located between the two gate portions. Multiple parallel word line groups are formed on the substrate. Each word line group includes two word lines with a straight cross-section and a gap between the two word lines. The multiple word line groups are arranged in parallel along a first direction and extend along a second direction. In the second direction, the gap between the two word lines is provided. The first direction is perpendicular to the second direction. In each of the control gate groups, a word line group is provided between the two control gates, and in each of the control gates, the connecting portion is aligned with the interval opening.

8. The method for manufacturing a flash memory as described in claim 7, characterized in that, There is a first control gate opening exposing the substrate between two adjacent control gate groups, and in each control gate group there is a second control gate opening exposing the substrate between two control gates, the word line group filling the second control gate opening; The method for forming the plurality of word line groups includes: A word line material layer is formed, which fills the first control gate opening and the second control gate opening and covers the plurality of control gate groups; A patterned photoresist layer is formed on the word line material layer. The patterned photoresist layer has a first photoresist opening and a second photoresist opening. The first photoresist opening exposes the word line material layer on the control gate group and the word line material layer in the first control gate opening. The second photoresist opening exposes a portion of the word line material layer in the second control gate opening. The word line material layer is etched using the patterned photoresist layer as a mask to remove the word line material layer on the control gate and the word line material layer in the first control gate opening, as well as a portion of the word line material layer in the second control gate opening, and the remaining word line material layer in the second control gate opening is used to form the word line group.

9. The method for manufacturing a flash memory as described in claim 8, characterized in that, The plurality of control gate groups are arranged in parallel along a first direction and extend along a second direction. In each control gate group, two control gates are spaced apart along the first direction, and the spacing between two adjacent control gates is 35nm to 60nm.

10. The method for manufacturing a flash memory as described in claim 7, characterized in that, The method for manufacturing the flash memory further includes: Multiple contact structure groups are formed on the multiple control gate groups, each contact structure group including two contact structures arranged in a staggered manner, wherein one control gate group corresponds to one contact structure group, and in each control gate group, one contact structure is provided on each of the two control gates.

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