Method for improving data transmission bandwidth by FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a method for improving data transmission bandwidth through an FPGA. The method comprises the steps that a data packaging module of a detector main control board sends data to be transmitted to a multi-channel GTP sending end in parallel; the data acquisition card receives the data of the corresponding channels through the multi-channel GTP receiving end and recovers Data and KCOD of each channel; an FIFO read-write control module of the data acquisition card writes data recovered by multiple channels into asynchronous FIFOs corresponding to the channels through write logic, and data buffering is carried out; the FIFO read-write control module simultaneously reads cache data of a plurality of asynchronous FIFOs through read control logic to realize cross-clock domain synchronization of multi-channel data; performing CRC (cyclic redundancy check) and processing on the read multi-channel data to obtain synchronous effective transmission data; and a single-channel GTP is upgraded to a dual-channel GTP or a multi-channel GTP, so that the data transmission bandwidth is improved, and normal operation of the FPGA chip is ensured.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and more specifically, to a method for improving data transmission bandwidth using FPGA. Background Technology

[0002] With the upgrade of the overall CT scanner performance design, the data transmission bandwidth between the detector main control board and the data acquisition card needs to be doubled. Currently, the limitation is that the transmission bandwidth of a single-channel GTP cannot meet the requirements of the new design. Simply increasing the line rate of the single-channel GTP from 2.5Gbps to 5Gbps would double the user clock generated by the GTP IP core (from 125MHz to 250MHz). However, due to limitations of the FPGA chip model, using a 250MHz clock would affect the normal operation of the FPGA. Summary of the Invention

[0003] To address at least one of the aforementioned technical problems, this invention proposes a method for improving data transmission bandwidth using FPGA.

[0004] The first aspect of this invention provides a method for improving data transmission bandwidth using an FPGA, comprising: S1, the data packaging module of the detector main control board sends the data to be transmitted in parallel to the multi-channel GTP transmitter, and the number of channels N is greater than 1 and less than or equal to 4. S2, the data acquisition cartoon multi-channel GTP receiver receives the data of the corresponding channel respectively, and recovers the Data and KCOD of each channel; S3, the FIFO read / write control module of the data acquisition card writes the data recovered from multiple channels into the asynchronous FIFO corresponding to each channel through the write logic for data buffering; S4, the FIFO read / write control module reads the cached data of multiple asynchronous FIFOs simultaneously through read control logic to achieve cross-clock domain synchronization of multi-channel data; S5 extracts and splices the read multi-channel data, performs CRC verification and processing, and obtains synchronized and valid transmission data.

[0005] In a preferred embodiment of the present invention, in step S1, the data packing module outputs Data and KCOD at the rising edge of each clock cycle; When every bit of KCOD is 0, Data is a valid data frame; When every bit of KCOD is 1, Data represents a specific data frame.

[0006] In a preferred embodiment of the present invention, the specific data frame type includes Idle frame, Header frame, Row Data frame, and Last frame.

[0007] In a preferred embodiment of the present invention, the data packaging module transmits the data to be transmitted in parallel to the multi-channel GTP transmitter at a rate that increases by N times, where N = 2, 3, 4.

[0008] In a preferred embodiment of the present invention, the multi-channel is defined as a first channel, a second channel, a third channel, and a fourth channel. The DATA and KCOD recovered by the first channel are defined as Data1 and KCOD1, the DATA and KCOD recovered by the second channel are defined as Data2 and KCOD2, and so on.

[0009] In a preferred embodiment of the present invention, the write control logic in step S3 includes: S31 is in an idle state; S32, determine whether the current frame is a specific data frame by KCOD. If it is, proceed to S33; otherwise, proceed to S34. S33, determine whether the current frame is the last frame. If it is, write the current Data and KCOD into the corresponding asynchronous FIFO and return to S31. Otherwise, write the current Data and KCOD into the corresponding asynchronous FIFO and enter S35. S34, write the Data and KCOD of the current valid data frame into the corresponding asynchronous FIFO and then proceed to S35; S35: Determine whether the readable data volume of the asynchronous FIFO of the first channel is 0 when it reaches the set threshold T. If yes, reset all asynchronous FIFOs and return to S31; otherwise, return to S32.

[0010] In a preferred embodiment of the present invention, the read control logic in step S4 includes: S41 is in an idle state; S42, determine whether the readable data volume of all asynchronous FIFOs is greater than the set readable threshold M. If so, read the data of multiple asynchronous FIFOs at the same time; otherwise, return to S41. S43: Extract and concatenate the read multi-channel data, and perform CRC check. S44. If the CRC check passes, determine if the current frame is the last frame. If it is, return to S41; otherwise, return to S42. If the CRC check fails, record the error status and prompt the error before proceeding to S43.

[0011] In a preferred embodiment of the present invention, the data transmission protocol for a single image acquisition includes sequentially transmitted Idle frames, Header frames, Row Data frames, valid data frames, and Last frames. The data transmission protocol distinguishes between specific data frames and valid data frames using KCOD, and the specific data frames are used to identify the start and end of a single image acquisition.

[0012] The technical solution of the present invention has the following advantages compared with the prior art: The design of the detector main control board and data acquisition card requires minimal changes to the logical architecture, resulting in short code development time. It does not require upgrading the FPGA chip type and ensures the normal operation of the FPGA. The hardware modification cost is low, which meets the demand for increased data transmission rate brought about by the performance upgrade of the CT machine. The single-channel GTP can be upgraded to a dual-channel GTP or a multi-channel GTP, which improves the data transmission bandwidth while ensuring the normal operation of the FPGA chip. Attached Figure Description

[0013] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, some of the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0014] Figure 1 This is a block diagram of dual-channel GTP data transmission according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the data transmission protocol for a single image acquisition according to an embodiment of the present invention; Figure 3 This is a flowchart of the asynchronous FIFO write control logic according to an embodiment of the present invention; Figure 4 This is a flowchart of the asynchronous FIFO read logic in an embodiment of the present invention. Detailed Implementation

[0015] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0016] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0017] Example 1 See Figures 1-4 As shown, this invention proposes a method for improving data transmission bandwidth using an FPGA, comprising: S1, the data packaging module of the detector main control board sends the data to be transmitted to the multi-channel GTP transmitter in parallel; S2, the data acquisition card receives the data of the corresponding channel through the dual-channel GTP receiver and recovers the 16-bit Data and 2-bit KCOD of each channel. According to the parameter settings of GTP ip, the bit width of Data and KCOD can also be a combination of 32-bit and 4-bit. S3, the FIFO read / write control module of the data acquisition card writes the data recovered from the dual channels into the asynchronous FIFO corresponding to each channel through the write logic for data buffering. For three-channel or four-channel cases, the number of asynchronous FIFOs needs to be equal to the number of transmission channels. S4, the FIFO read / write control module reads the cached data of two asynchronous FIFOs simultaneously through the read control logic to achieve cross-clock domain synchronization of dual-channel data. For three-channel or four-channel cases, it reads three or four asynchronous FIFOs simultaneously. S5 extracts and splices the read multi-channel data, performs CRC verification and processing, and obtains synchronized and valid transmission data.

[0018] According to an embodiment of the present invention, in step S1, the data packaging module outputs Data and KCOD at the rising edge of each clock cycle; When every bit of KCOD is 0, Data is a valid data frame; When every bit of KCOD is 1, Data represents a specific data frame.

[0019] According to embodiments of the present invention, specific data frame types include Idle frames, Header frames, Row Data frames, and Last frames.

[0020] According to an embodiment of the present invention, the data packaging module sends the data to be transmitted to the dual-channel GTP transmitter in parallel at a rate that increases by N times, where N equals 2, N equals 3 for three-channel transmission, and N equals 4 for four-channel transmission.

[0021] It should be noted that the data packetization module needs to increase the data transmission rate to the GTP IP core TX end by 100% compared to single-channel GTP transmission to meet the data transmission requirements of dual-channel GTP and improve the data transmission bandwidth. For three-channel transmission, the rate is increased by 3 times, and for four-channel transmission, it is increased by 4 times.

[0022] According to an embodiment of the present invention, the multi-channel is defined as a first channel and a second channel. The DATA and KCOD recovered by the first channel are defined as Data1 and KCOD1, the DATA and KCOD recovered by the second channel are defined as Data2 and KCOD2, and so on for the remaining channels.

[0023] It should be noted that DATA1 and KCOD1 have a strict synchronization relationship, and the same applies to DATA2 and KCOD2. However, {DATA1,KCOD1} and {DATA2,KCOD2} may have differences in clock phase, so it is necessary to achieve synchronization between multi-channel data.

[0024] According to an embodiment of the present invention, the write control logic in step S3 includes: S31 is in an idle state; S32, determine whether the current frame is a specific data frame by KCOD. If it is, proceed to S33; otherwise, proceed to S34. S33, determine whether the current frame is the last frame. If it is, write the current Data and KCOD into the corresponding asynchronous FIFO and return to S31. Otherwise, write the current Data and KCOD into the corresponding asynchronous FIFO and enter S35. S34, write the Data and KCOD of the current valid data frame into the corresponding asynchronous FIFO and then proceed to S35; S35: Determine whether the readable data volume of the asynchronous FIFO of the first channel is 0 when the readable data volume of the asynchronous FIFO of the other channels reaches the set threshold T. If yes, reset all asynchronous FIFOs and return to S31; otherwise, return to S32.

[0025] According to an embodiment of the present invention, the read control logic in step S4 includes: S41 is in an idle state; S42, determine whether the readable data volume of all asynchronous FIFOs is greater than the set readable threshold M. If so, read the data of all asynchronous FIFOs at the same time; otherwise, return to S41. S43, the read dual-channel data {DATA1,KCOD1} and {DATA2,KCOD2} are truncated and concatenated into DATA1 and Data2, and CRC check is performed on {DATA1,DATA2}. If it is a three-channel transmission, CRC check is performed on {DATA1,DATA2,DATA3}, and so on for four-channel transmission. S44. If the CRC check passes, determine if the current frame is the last frame. If it is, return to S41; otherwise, return to S42. If the CRC check fails, record the error status and prompt the error before proceeding to S43.

[0026] According to an embodiment of the present invention, the data transmission protocol for a single image acquisition includes sequentially transmitted Idle frames, Header frames, Row Data frames, valid data frames, and Last frames. The data transmission protocol distinguishes between specific data frames and valid data frames through KCOD, and the specific data frames are used to identify the start and end of a single image acquisition.

[0027] Specifically, all definitions of terms used in this application are shown in the table below:

[0028] In summary, the design of the detector main control board and data acquisition card requires minimal changes to the logical architecture, has a short code development time, does not require upgrading the FPGA chip type, and ensures the normal operation of the FPGA. The hardware modification cost is low, which meets the demand for increased data transmission rate brought about by the performance upgrade of the CT machine. Upgrading from a single-channel GTP to a dual-channel or multi-channel GTP increases the data transmission bandwidth while ensuring the normal operation of the FPGA chip.

[0029] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0030] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to the above embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0031] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for improving data transmission bandwidth using FPGA, characterized in that, include: S1, the data packetization module of the detector main control board sends the data to be transmitted to the multi-channel GTP transmitter in parallel. The number of channels N is greater than 1 and less than or equal to 4. S2, the data acquisition card receives data from the corresponding channels of the multi-channel GTP receiver and recovers the Data and KCOD of each channel; S3, the FIFO read / write control module of the data acquisition card writes the data recovered from multiple channels into the asynchronous FIFO corresponding to each channel through the write logic for data buffering; S4, the FIFO read / write control module reads the cached data of multiple asynchronous FIFOs simultaneously through read control logic to achieve cross-clock domain synchronization of multi-channel data; S5 extracts and splices the read multi-channel data, performs CRC verification and processing, and obtains synchronized and valid transmission data.

2. The method for improving data transmission bandwidth using FPGA according to claim 1, characterized in that, In step S1, the data packaging module outputs Data and KCOD at the rising edge of each clock cycle; When every bit of KCOD is 0, Data is a valid data frame; When every bit of KCOD is 1, Data represents a specific data frame.

3. The method for improving data transmission bandwidth using FPGA according to claim 2, characterized in that, The specific data frame types include Idle frames, Header frames, Row Data frames, and Last frames.

4. The method for improving data transmission bandwidth using FPGA according to claim 3, characterized in that, The data packetization module sends the data to be transmitted to the multi-channel GTP transmitter in parallel at a rate that increases by N times, where N=2,3,4.

5. The method for improving data transmission bandwidth using FPGA according to claim 4, characterized in that, The multi-channel is defined as the first channel, the second channel, the third channel, and the fourth channel. The DATA and KCOD recovered by the first channel are defined as Data1 and KCOD1, the DATA and KCOD recovered by the second channel are defined as Data2 and KCOD2, and so on.

6. The method for improving data transmission bandwidth using FPGA according to claim 5, characterized in that, The write control logic in step S3 includes: S31 is in an idle state; S32, determine whether the current frame is a specific data frame by KCOD. If it is, proceed to S33; otherwise, proceed to S34. S33, determine whether the current frame is the last frame. If it is, write the current Data and KCOD into the corresponding asynchronous FIFO and return to S31. Otherwise, write the current Data and KCOD into the corresponding asynchronous FIFO and enter S35. S34, write the Data and KCOD of the current valid data frame into the corresponding asynchronous FIFO and then proceed to S35; S35: Determine whether the readable data volume of the asynchronous FIFO of the first channel is 0 when it reaches the set threshold T. If yes, reset all asynchronous FIFOs and return to S31; otherwise, return to S32.

7. The method for improving data transmission bandwidth using FPGA according to claim 6, characterized in that, The read control logic in step S4 includes: S41 is in an idle state; S42, determine whether the readable data volume of all asynchronous FIFOs is greater than the set readable threshold M. If so, read the data of multiple asynchronous FIFOs at the same time; otherwise, return to S41. S43: Extract and concatenate the read multi-channel data, and perform CRC check. S44. If the CRC check passes, determine if the current frame is the last frame. If it is, return to S41; otherwise, return to S42. If the CRC check fails, record the error status and prompt the error before proceeding to S43.

8. The method for improving data transmission bandwidth using FPGA according to claim 7, characterized in that, The data transmission protocol for a single image acquisition includes sequentially transmitted Idle frames, Header frames, Row Data frames, valid data frames, and Last frames. The data transmission protocol uses KCOD to distinguish between specific data frames and valid data frames. Specific data frames are used to identify the start and end of a single image acquisition.

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