Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel, and relates to the technical field of display, wherein the array substrate comprises a substrate and a transistor located at one side of the substrate, the transistor comprises an active layer, an insulating layer and a gate metal layer, the active layer is located at one side of the substrate and comprises a main channel region and an edge channel region, the insulating layer covers the active layer, in the gate metal layer, a region intersected with the main channel region is a first region of the gate, and a region intersected with the edge channel region is a second region of the gate, the array substrate of the application is provided with a hollow region in the second region of the gate, the hollow region blocks the channel of carriers in the edge channel region between the source and the drain to different extents, or the distance between the second region of the gate and the edge channel region is increased, the second region of the gate cannot be opened in advance, and the double-peak phenomenon is improved, and the performance reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to an array substrate and a display panel. Background Technology

[0002] Currently, display technology has permeated all aspects of people's daily lives, and correspondingly, more and more materials and technologies are being used in displays. Display panels, as an important component of display devices, are used to realize the display function of these devices. Today, the mainstream display panels mainly include liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, micro LED displays, and mini LED displays.

[0003] Liquid crystal display (LCD) panels are widely used in various fields due to their advantages such as thinness, low power consumption, and low radiation. The electric field between the pixel electrodes and the common electrode in an LCD panel causes the liquid crystal molecules to deflect. After the liquid crystal molecules deflect, the light generated by the backlight component passes through the display panel. By adjusting the magnitude of the electric field, the degree of deflection of the liquid crystal molecules can be varied. Different degrees of deflection result in different transmittance of the display panel, leading to different amounts of light transmitted through the backlight component, thus achieving image display. Organic light-emitting diodes (OLEDs), as current-driven light-emitting devices, are increasingly used in high-performance displays. OLED display panels include an anode and a cathode, as well as a hole transport layer, an organic light-emitting layer, and an electron transport layer disposed between the anode and cathode. The anode provides hole injection, and the cathode provides electron injection. Driven by an external voltage, the holes and electrons injected from the cathode and anode recombine in the organic light-emitting layer, forming electron-hole pairs (i.e., excitons) at bound energy levels. The excitons radiate and de-excite, emitting photons and producing visible light. Micro LEDs and Mini LEDs are also used in other applications. LEDs have very low energy consumption and have become a research hotspot in recent years. Micro LED and Mini LED technologies both belong to LED miniaturization and matrixing technologies, referring to high-density, tiny LED arrays integrated on a single chip. Micro LED and Mini LED consume far less power than Liquid Crystal Displays (LCDs) and, like Organic Light-Emitting Diodes (OLEDs), are self-emissive. They can reduce the distance between pixels from millimeters to micrometers, and their color saturation is close to that of OLEDs. Therefore, many manufacturers regard Micro LED and Mini LED as the next-generation display technology.

[0004] Thin-film transistors (TFTs) are the main driving components in LCD, OLED, Micro LED, and Mini LED display panels. They consist of a gate, source, drain, and active layer. The source and drain are connected to the active layer. When a voltage is applied to the gate, as the gate voltage increases, the depletion layer on the surface of the active layer transforms into an electron accumulation layer, forming an inversion layer. When strong inversion is reached (i.e., the turn-on voltage is reached), carrier movement in the active layer enables conduction between the source and drain. However, existing TFTs exhibit a double-peak effect, which affects their performance.

[0005] Therefore, providing a reliable array substrate and display panel is an urgent problem to be solved in this field. Summary of the Invention

[0006] In view of this, the present invention provides an array substrate and a display panel that improve the double-peak effect of thin-film transistors and enhance performance reliability.

[0007] On one hand, the present invention provides an array substrate comprising a substrate and a transistor located on one side of the substrate, wherein the transistor comprises:

[0008] An active layer is located on one side of the substrate, the active layer includes a main channel region and an edge channel region, the edge channel region being located on at least one side of the main channel region;

[0009] An insulating layer is located on the side of the active layer away from the substrate, and the insulating layer covers the active layer;

[0010] A gate metal layer is located on the side of the insulating layer away from the substrate. The gate metal layer extends along a first direction. At least a portion of the extension direction of the active layer intersects with the extension direction of the gate metal layer. In a direction perpendicular to the plane of the substrate, the region that overlaps with the main channel region is the first region of the gate, and the remaining region is the second region of the gate.

[0011] The second region of the gate includes a cutout region, which at least partially overlaps with the edge channel region in a direction perpendicular to the plane of the substrate.

[0012] On the other hand, the present invention also provides an array substrate, characterized in that it includes a substrate and a transistor located on one side of the substrate, wherein the transistor includes:

[0013] An active layer is located on one side of the substrate, the active layer includes a main channel region and an edge channel region, the edge channel region being located on at least one side of the main channel region;

[0014] An insulating layer is located on the side of the active layer away from the substrate, and the insulating layer covers the active layer;

[0015] The gate metal layer, at least a portion of the active layer's extension direction intersects the extension direction of the gate metal layer. In a direction perpendicular to the plane of the substrate, the region overlapping with the main channel region is the first region of the gate, and the remaining region is the second region of the gate. The second region of the gate is located on the side of the insulating layer away from the substrate.

[0016] In a direction perpendicular to the plane of the substrate, the thickness of the insulating layer corresponding to the second region of the gate is greater than the thickness of the insulating layer corresponding to the first region of the gate.

[0017] On the other hand, the present invention also provides a display panel comprising any of the array substrates described above.

[0018] Compared with the prior art, the array substrate and display panel provided by the present invention achieve at least the following beneficial effects:

[0019] On one hand, the present invention provides an array substrate, including a substrate and a transistor located on one side of the substrate. The transistor includes: an active layer located on one side of the substrate, the active layer including a main channel region and an edge channel region, the edge channel region being located on at least one side of the main channel region; an insulating layer located on the side of the active layer away from the substrate, the insulating layer covering the active layer; a gate metal layer located on the side of the insulating layer away from the substrate, the gate metal layer extending along a first direction, at least a portion of the extension direction of the active layer intersecting the extension direction of the gate metal layer, and in a direction perpendicular to the plane of the substrate, the region overlapping with the main channel region is a first region of the gate, the remaining region is a second region of the gate; the second region of the gate includes a cutout region, in a direction perpendicular to the plane of the substrate. In the direction of the cutout region and the edge channel region, the cutout region and the edge channel region overlap at least partially in the direction perpendicular to the plane of the substrate. The second region of the gate includes the cutout region and the edge channel region, which overlap at least partially. When a voltage is applied to the gate metal layer, the main channel region generates carrier migration under the action of the gate voltage. The cutout region and the edge channel region overlap at least partially in the second region of the gate. Therefore, there will be no carrier migration at the position where the cutout region overlaps with the edge channel region. Thus, the setting of the cutout region at least to some extent blocks the path of carrier migration in the edge channel region, reduces the possibility of the edge channel region turning on the source and drain, thereby slowing down the edge channel region turning on before the main channel region, improving the double peak effect, improving the reliability of the transistor, and improving the performance reliability of the array substrate.

[0020] On the other hand, the present invention also provides an array substrate, including a substrate and a transistor located on one side of the substrate. The transistor includes: an active layer located on one side of the substrate, the active layer including a main channel region and an edge channel region, the edge channel region being located on at least one side of the main channel region; an insulating layer located on the side of the active layer away from the substrate, the insulating layer covering the active layer; a gate metal layer, at least a portion of the extension direction of the active layer intersects the extension direction of the gate metal layer, and in a direction perpendicular to the plane of the substrate, the region overlapping with the main channel region is a first region of the gate, the remaining region is a second region of the gate, the second region of the gate being located on the side of the insulating layer away from the substrate; in a direction perpendicular to the plane of the substrate, the thickness of the insulating layer corresponding to the second region of the gate is greater than the thickness of the insulating layer corresponding to the first region of the gate, when the gate metal layer... When a voltage is applied, the voltage of the gate metal layer controls the movement of charge carriers in the main channel region and the edge channel region of the active layer. Since the thickness of the insulating layer corresponding to the second region of the gate is greater than the thickness of the insulating layer corresponding to the first region of the gate, the distance between the second region of the gate and the edge channel region is greater than the distance between the first region of the gate and the main channel region in the direction perpendicular to the plane of the substrate. Therefore, the capacitance between the second region of the gate and the edge channel region will be less than the capacitance between the first region of the gate and the main channel region. The ability of the second region of the gate to control the movement of charge carriers in the edge channel region will be weakened, and it will be less than the ability of the first region of the gate to control the movement of charge carriers in the main channel region. The edge channel region will not reach saturation current and turn on prematurely before the main channel region, thus improving the double-peak effect of the transistor, improving the performance reliability of the transistor, and thus improving the performance reliability of the array substrate.

[0021] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0022] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0024] Figure 1 This is a planar schematic diagram of an array substrate in the prior art;

[0025] Figure 2 This is a schematic diagram of a planar structure of an array substrate provided by the present invention;

[0026] Figure 3 yes Figure 2 A cross-sectional view along line A-A' in the middle;

[0027] Figure 4 This is a schematic diagram of a planar structure of another array substrate provided by the present invention;

[0028] Figure 5 yes Figure 4 A cross-sectional view along the B-B' direction;

[0029] Figure 6 This is a schematic diagram of a planar structure of another array substrate provided by the present invention;

[0030] Figure 7 This is a schematic diagram of a planar structure of another array substrate provided by the present invention;

[0031] Figure 8 This is a schematic diagram of a planar structure of another array substrate provided by the present invention;

[0032] Figure 9 This is a schematic diagram of a planar structure of another array substrate provided by the present invention;

[0033] Figure 10 yes Figure 9 A cross-sectional view along the C-C' direction;

[0034] Figure 11 This is a schematic diagram of a planar structure of another array substrate provided by the present invention;

[0035] Figure 12 yes Figure 11 A magnified view of a portion of region M in the middle;

[0036] Figure 13 This is a schematic diagram of a planar structure of another array substrate provided by the present invention;

[0037] Figure 14 This is a schematic diagram of a planar structure of another array substrate provided by the present invention;

[0038] Figure 15 yes Figure 14 A magnified view of a portion of region N in the middle;

[0039] Figure 16 This is a schematic diagram of a planar structure of another array substrate provided by the present invention;

[0040] Figure 17 yes Figure 16 A magnified view of a portion of region P in the middle;

[0041] Figure 18 This is a schematic diagram of a planar structure of a display panel provided by the present invention;

[0042] Figure 19 This invention provides a pixel circuit. Detailed Implementation

[0043] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0044] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0045] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0046] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0047] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0048] Given the double-peak effect and poor performance reliability of transistors in the prior art, the inventors conducted the following research on existing transistors, referring to... Figure 1 , Figure 1 This is a planar schematic diagram of an array substrate in the prior art. Figure 1The array substrate includes a substrate 01 and a transistor located on one side of the substrate 01. The transistor includes an active layer 09, a gate metal layer 03, an insulating layer 07, a source 04, and a drain 05. The active layer 09 includes a channel region 02 and an edge region 023. The channel region 02 refers to the region overlapping with the gate metal layer 03, a main channel region 021, and edge channel regions 022 located on both sides of the main channel region 021. The insulating layer 07 covers the active layer 09. In the direction perpendicular to the plane of the substrate 01, the region overlapping with the main channel region 021 is the first region 031 of the gate, and the remaining region is the second region 032 of the gate. The edge channel region 022 forms a parasitic transistor. Due to the limitations of the transistor process itself, the thickness of the edge channel region 022 will inevitably be thinner than that of the main channel region 021. Thus, the turn-on voltage of the edge channel region 022 will be less than that of the main channel region 021. When a voltage is applied to the gate metal layer 03, the voltage of the gate metal layer 03 controls the movement of carriers in the main channel region 021 and the edge channel region 022 in the active layer 09, realizing the conduction between the source 04 and the drain 05. However, the edge channel region 022 will reach the saturation current and turn on earlier than the main channel region 021, causing the transistor to produce a double peak effect, which affects the performance and reliability of the transistor.

[0049] In view of this, the present invention provides an array substrate and a display panel for improving the double-peak effect and enhancing performance reliability. Specific embodiments of the array substrate and the display panel will be described in detail below.

[0050] Reference Figures 2 to 6 , Figure 2 This is a schematic diagram of a planar structure of an array substrate provided by the present invention. Figure 3 yes Figure 2 A cross-sectional view along line A-A'. Figure 4 This is a schematic diagram of a planar structure of another array substrate provided by the present invention. Figure 5 yes Figure 4 A cross-sectional view along the B-B' direction. Figure 6 This is a schematic diagram of a planar structure of another array substrate provided by the present invention.

[0051] This embodiment provides an array substrate 100, including a substrate 1 and a transistor T located on one side of the substrate 1. The transistor T includes: an active layer 9 located on one side of the substrate 1, the active layer 9 including a main channel region 21 and an edge channel region 22, the edge channel region 22 being located on at least one side of the main channel region 21; an insulating layer 7 located on the side of the active layer 9 away from the substrate 1, the insulating layer 7 covering the active layer 9; and a gate metal layer 3 located on the side of the insulating layer 7 away from the substrate 1, the gate metal layer 3 extending along a first direction X, at least a portion of the extension direction of the active layer 9 intersecting the extension direction of the gate metal layer 3, and in a direction perpendicular to the plane of the substrate 1, the region overlapping with the main channel region 21 is the first region 31 of the gate, the remaining region is the second region 32 of the gate; the second region 32 of the gate includes a cutout region 6, and in a direction perpendicular to the plane of the substrate 1, the cutout region 6 at least partially overlaps with the edge channel region 22.

[0052] Optionally, the active layer 9 can be made of semiconductor material, and the insulating layer 7 can be made of silicon nitride and silicon oxide. Of course, no specific restrictions are placed on the materials of the active layer 9 and the insulating layer 7 here.

[0053] Figures 2 to 6 The diagram shows that there are edge channel areas 22 on both sides of the main channel area 21. Of course... Figures 2 to 6 The diagram shows only the case of a single transistor T; alternatively, multiple transistor T arrays are arranged in the array substrate 100.

[0054] Specifically, Figure 2 and Figure 3 The diagram only shows a case where a cutout region 6 is provided on one side edge of the second region 32 of the gate, and the cutout region 6 only overlaps with a portion of the edge channel region 22 along the first direction X. Of course, Figure 2 and Figure 3 The diagram only shows that the orthographic projection of the active layer 9 onto the plane of the substrate 1 is rectangular. This invention does not specifically limit the shape of the orthographic projection of the active layer 9 onto the plane of the substrate 1. Figure 4 and Figure 5 The diagram only shows the case where a cutout region 6 is provided between the two edges of the second region 32 of the gate, and the cutout region 6 covers the edge channel region 22 along the first direction X. Figure 4 and Figure 5 The diagram only shows the case where the orthographic projection of the active layer 9 onto the plane of the substrate 1 is rectangular; Figure 6 The diagram shows a case where a cutout region 6 is provided on both sides of the second region 32 of the gate, and the cutout region 6 overlaps only with a portion of the edge channel region 22 along the first direction X, and the orthographic projection of the active layer 9 onto the plane of the substrate 1 is U-shaped.

[0055] It should be noted that the cutout area 6 along the second direction Y cannot completely overlap with the edge channel area 22, otherwise the gate metal layer 3 will be broken, affecting the transmission of voltage signals on the gate metal layer 3. The first direction X and the second direction Y intersect.

[0056] It is understandable that, regardless of whether the transistor T has a large aspect ratio (the ratio of the width to the length of the channel of the active layer 9) or a small aspect ratio, due to the manufacturing process, the active layer 9 will have edge channel regions 22 to varying degrees. Here, we will not make specific limitations on the orthographic projection shape of the active layer 9 on the plane of the substrate 1.

[0057] Figure 2 , Figure 4 and Figure 6 The diagram also shows that transistor T includes a source 4 and a drain 5, which are electrically connected to the active layer 9 via a via 8. It can be understood that the active layer 9 includes a channel region 2 and an edge region 23. The edge region 23 refers to the portion that does not overlap with the gate metal layer 3, while the channel region 2 refers to the portion that overlaps with the gate metal layer 3. Specifically, the channel region 2 is divided into a main channel region 21 and an edge channel region 22.

[0058] like Figures 2 to 6 As shown, in the direction perpendicular to the plane of the substrate 1, the second region 32 of the gate includes a cutout region 6 that at least partially overlaps with the edge channel region 22. When a voltage is applied to the gate metal layer 3, the main channel region 21 generates carrier migration under the action of the gate voltage. Since the cutout region 6 of the second region 32 of the gate overlaps with the edge channel region 22, there will be no carrier migration at the position where the cutout region 6 overlaps with the edge channel region 22. Therefore, the setting of the cutout region 6 blocks the path of carrier migration in the edge channel region 22 to a certain extent, reducing the possibility of the edge channel region 22 turning on the source 4 and drain 5. This can slow down the edge channel region 22 turning on before the main channel region 21, improve the double peak effect, improve the reliability of the transistor T, and improve the performance reliability of the array substrate 100.

[0059] In some alternative embodiments, reference continues to be made to... Figures 2 to 6 The transistor T also includes a source 4 and a drain 5. The source 4 and drain 5 are located on the side of the gate metal layer 3 away from the plane of the substrate 1. The source 4 and drain 5 are insulated from the gate metal layer 3 and are electrically connected to the active layer 9. In the direction from the source 4 to the drain 5, the cutout area 6 is located between the source 4 and the drain 5.

[0060] The second region 32 of the gate includes a cutout region 6 that at least partially overlaps with the edge channel region 22. When a voltage is applied to the gate metal layer 3, the main channel region 21 generates carrier migration under the action of the gate voltage. Since the cutout region 6 of the second region 32 of the gate at least partially overlaps with the edge channel region 22, there will be no carrier migration at the position where the cutout region 6 overlaps with the edge channel region 22. Therefore, the setting of the cutout region 6 at least to some extent blocks the path of carrier migration in the edge channel region 22, reducing the possibility of the edge channel region 22 turning on the source 4 and drain 5. This can slow down the edge channel region 22 turning on before the main channel region 21, improve the double peak effect, improve the reliability of the transistor T, and improve the performance reliability of the array substrate 100.

[0061] In some alternative embodiments, refer to Figure 7 , Figure 7 This is a schematic diagram of a planar structure of another array substrate provided by the present invention. The gate metal layer 3 includes a first edge 301 and a second edge 302 disposed opposite to each other along the second direction Y, and the second direction Y intersects with the first direction X.

[0062] In a direction perpendicular to the plane of the substrate 1, the cutout area 6 is located between the first edge 301 and the second edge 302.

[0063] Reference Figure 7 In the process, the gate metal layer 3 includes a first edge 301 and a second edge 302 disposed opposite to each other along the second direction Y. Optionally, the spacing between the first edge 301 and the second edge 302 is equal everywhere, which facilitates the fabrication of the gate metal layer 3. Figure 7 The image only shows the case where the hollowed-out area 6 along the first direction X overlaps with only a portion of the edge channel area 22. Of course, Figure 7 The diagram only shows the orthographic projection of the active layer 9 onto the plane of the substrate 1 as a rectangle. In the direction perpendicular to the plane of the substrate 1, the cutout area 6 is located between the first edge 301 and the second edge 302. That is, along the second direction Y, the cutout area 6 does not penetrate the first edge 301 and the second edge 302, thereby preventing the gate metal layer 3 from being disconnected and causing the gate voltage signal to be unable to be transmitted, which would affect the signal transmission in the array substrate 100.

[0064] In some alternative embodiments, reference continues to be made to Figures 2 to 7 In the direction from the main channel to the edge channel area 22, the width of the hollow area 6 that overlaps with the edge channel area 22 is less than or equal to the width of the edge channel area 22.

[0065] Figure 2 , Figure 3 , Figure 6 and Figure 7In the direction from the main channel to the edge channel area 22, the width of the hollow area 6 that overlaps with the edge channel area 22 is smaller than the width of the edge channel area 22. Figure 4 and Figure 5 In the direction from the main channel to the edge channel area 22, the width of the hollow area 6 that overlaps with the edge channel area 22 is equal to the width of the edge channel area 22. Figure 4 and Figure 5 In the direction from the main channel to the edge channel region 22, the width of the cutout region 6 is greater than the width of the edge channel region 22. However, the width of the area overlapping with the edge channel region 22 is equal to the width of the edge channel region 22. In other words, the portion of the second region 32 of the gate that is removed is relatively large. It can be said that the width of the gate metal layer 3 removed in the direction from the main channel region 21 to the edge channel region 22 is greater than the width of the edge channel region 22. Optionally, the cutout region 6 can be formed in the second region 32 of the gate by etching the gate metal layer 3 using a mask. The larger the area of ​​the cutout region 6, the larger the etched area, which is more conducive to manufacturing.

[0066] certainly, Figure 4 and Figure 5 In the direction from the main channel to the edge channel region 22, the width of the cutout region 6 that overlaps with the edge channel region 22 is equal to the width of the edge channel region 22. At this time, the cutout region 6 can cut off the path of carrier migration in the edge channel region 22. The source 4 and drain 5 will not be turned on in the edge channel region 22, and the edge channel region 22 will not be turned on before the main channel region 21. Therefore, the double peak effect will not occur, which improves the reliability of the transistor T and the performance reliability of the array substrate 100.

[0067] In some alternative embodiments, reference continues to be made to... Figure 2 , Figure 4 , Figure 6 , Figure 7 and reference Figure 8 , Figure 8 This is a schematic diagram of a planar structure of another array substrate provided by the present invention. In the direction perpendicular to the plane of the substrate 1, the orthogonal projection shape of the cutout area 6 includes a concave shape, an arc shape, a rectangle, or an hourglass shape.

[0068] Optional, Figure 2 , Figure 4 , Figure 6 and Figure 7 In the direction perpendicular to the plane of substrate 1, the orthographic projection of the cutout area is a rectangle. Figure 8The orthographic projection of the cutout area in the direction perpendicular to the plane of the substrate 1 is concave. Of course, the orthographic projection shape of the cutout area in the direction perpendicular to the plane of the substrate 1 can also be arc-shaped or hourglass-shaped. The hourglass shape means that the width of the orthographic projection of the two ends near the source 4 and drain 5 on the plane of the substrate 1 is greater than the width of the orthographic projection of the middle part on the plane of the substrate 1. Here, the orthographic projection shape of the cutout area on the substrate 1 is not specifically limited. As long as the cutout area 6 included in the second region 32 of the gate overlaps with the edge channel region 22 at least partially, there will be no carrier migration at the position where the edge channel region 22 overlaps with the cutout area 6. The cutout area 6 blocks the carrier migration path in the edge channel region 22 to a certain extent, reducing the possibility of the edge channel region 22 turning on the source 4 and drain 5. This can slow down the edge channel region 22 turning on before the main channel region 21, improve the double peak effect, improve the reliability of the transistor T, and improve the performance reliability of the array substrate 100.

[0069] It is understandable that when the orthographic projection shape of the cutout region 6 in the direction perpendicular to the plane of the substrate 1 includes a concave shape, an arc shape, or an hourglass shape, its orthographic projection edge in the plane of the substrate 1 has a curve, which can reduce the accumulation of charge carriers at sharp corners and prevent the generation of static electricity due to charge carrier accumulation. Of course, compared with the embodiment where the cutout region 6 is set as a rectangle, the area of ​​the cutout region 6 is smaller in the direction from the main channel region 21 to the edge channel region 22, and the area of ​​the gate metal layer 3 is larger for the same width. It is understandable that the larger the area of ​​the cutout region 6 is, the greater the load on the gate metal layer 3, which will increase the power consumption. When a concave shape, an arc shape, or an hourglass shape is used, the area of ​​the gate metal can be preserved as much as possible, improving the double peak phenomenon while ensuring that the power consumption remains unchanged.

[0070] Based on the same inventive concept, the present invention also provides an array substrate 100, with reference to... Figure 9 and Figure 10 , Figure 9 This is a schematic diagram of a planar structure of another array substrate provided by the present invention. Figure 10 yes Figure 9 A cross-sectional view along the C-C' direction. Figure 9 and Figure 10The array substrate 100 includes a substrate 1 and a transistor T located on one side of the substrate 1. The transistor T includes: an active layer 9 located on one side of the substrate 1, the active layer 9 including a main channel region 21 and an edge channel region 22, the edge channel region 22 being located on at least one side of the main channel region 21; an insulating layer 7 located on the side of the active layer 9 away from the substrate 1, the insulating layer 7 covering the active layer 9; and a gate metal layer 3, at least a portion of the extension direction of the active layer 9 intersecting the extension direction of the gate metal layer 3. In a direction perpendicular to the plane of the substrate 1, the region overlapping with the main channel region 21 is the first region 31 of the gate, and the remaining region is the second region 32 of the gate. The second region 32 of the gate is located on the side of the insulating layer 7 away from the substrate 1. In a direction perpendicular to the plane of the substrate 1, the thickness of the insulating layer 7 corresponding to the second region 32 of the gate is greater than the thickness of the insulating layer 7 corresponding to the first region 31 of the gate.

[0071] Optionally, the active layer 9 can be made of semiconductor materials, and the insulating layer 7 can be made of silicon nitride and silicon oxide. Of course, the materials of the active layer 9 and the insulating layer 7 are not specifically limited here. The active layer 9 includes a channel region 2 and an edge region 23. The edge region 23 refers to the part that does not overlap with the gate metal layer 3, and the channel region 2 refers to the part that overlaps with the gate metal layer 3. Specifically, the channel region 2 is divided into a main channel region 21 and an edge channel region 22.

[0072] It should be noted that the first region 31 and the second region 32 of the gate in this invention are both structures in the gate metal layer 3, and are not simple region divisions.

[0073] In this embodiment, in the direction perpendicular to the plane of the substrate 1, the thickness of the insulating layer 7 corresponding to the second region 32 of the gate is greater than the thickness of the insulating layer 7 corresponding to the first region 31 of the gate. This means that the distance between the second region 32 of the gate and the edge channel region 22 is greater than the distance between the first region 31 of the gate and the main channel region 21.

[0074] Optionally, in order to make the thickness of the insulating layer 7 corresponding to the second region 32 of the gate greater than the thickness of the insulating layer 7 corresponding to the first region 31 of the gate, a first insulating layer 71 can be fabricated first, then the first region 31 of the gate can be fabricated on this insulating layer 7, and then a second insulating layer 72 can be fabricated. Of course, the second insulating layer 72 covers the first insulating layer 71 and the first region 31 of the gate, and then the second region 32 of the gate can be fabricated on the second insulating layer 72. The second region 32 of the gate and the first region 31 of the gate are electrically connected through the via 8 to ensure signal transmission.

[0075] Figure 9 The diagram shows that there are edge channel areas 22 on both sides of the main channel area 21. Of course... Figure 9The diagram shows only the case of a single transistor T. Optionally, multiple transistors T are arranged in an array on the array substrate 100. It is understood that, regardless of whether the transistor has a large aspect ratio (the ratio of the width to the length of the channel of the active layer 9) or a small aspect ratio, due to the manufacturing process, the active layer 9 will have edge channel regions 22 to varying degrees. The orthographic projection shape of the active layer 9 on the plane of the substrate 1 can be L-shaped, rectangular, or U-shaped. Here, no specific limitation is made on the orthographic projection shape of the active layer 9 on the plane of the substrate 1.

[0076] Combination Figure 1 As can be seen, due to the limitations of the transistor process itself in the existing technology, the thickness of the edge channel region 022 will inevitably be thinner than that of the main channel region 021. As a result, the turn-on voltage of the edge channel region 022 will be less than that of the main channel region 021. When a voltage is applied to the gate metal layer 03, the edge channel region 022 will reach the saturation current and turn on earlier than the main channel region 021, causing the transistor T to produce a double peak effect.

[0077] In this embodiment, in the direction perpendicular to the plane of the substrate 1, the thickness of the insulating layer 7 corresponding to the second region 32 of the gate is greater than the thickness of the insulating layer 7 corresponding to the first region 31 of the gate. When a voltage is applied to the gate metal layer 3, the voltage of the gate metal layer 3 controls the movement of charge carriers in the main channel region 21 and the edge channel region 22 in the active layer 9. Since the thickness of the insulating layer 7 corresponding to the second region 32 of the gate is greater than the thickness of the insulating layer 7 corresponding to the first region 31 of the gate, the distance between the second region 32 of the gate and the edge channel region 22 is greater than the distance between the first region 31 of the gate and the main channel region 21 in the direction perpendicular to the plane of the substrate 1. Therefore, the capacitance between the second region 32 of the gate and the edge channel region 22 will be less than the capacitance between the first region 31 of the gate and the main channel region 21. The ability of the second region 32 of the gate to control the movement of charge carriers in the edge channel region 22 will be weakened and will be less than the ability of the first region 31 of the gate to control the movement of charge carriers in the main channel region 21. The edge channel region 22 will not reach the saturation current and turn on prematurely before the main channel region 21, thereby improving the double-peak effect of the transistor T, improving the performance reliability of the transistor T, and thus improving the performance reliability of the array substrate 100.

[0078] In some alternative embodiments, reference continues to be made to... Figure 10 The insulating layer 7 includes a first insulating layer 71 and a second insulating layer 72 stacked together, with the second insulating layer 72 located on the side of the first insulating layer 71 away from the substrate 1.

[0079] In a direction perpendicular to the plane of the substrate 1, the first region 31 of the gate is sandwiched between the first insulating layer 71 and the second insulating layer 72; the second region 32 of the gate is located on the side of the second insulating layer 72 away from the first insulating layer 71.

[0080] Optionally, along a direction perpendicular to the plane of the substrate 1, the first insulating layer 71 covers the main channel region 21 and the edge channel region 22 of the active layer 9. Corresponding to the main channel region 21 of the active layer 9, the first region 31 of the gate is located on the side of the first insulating layer 71 away from the substrate 1. The second insulating layer 72 covers the first region 31 of the gate and the position of the first insulating layer 71 corresponding to the edge channel region 22, so that the first region 31 of the gate is sandwiched between the first insulating layer 71 and the second insulating layer 72. The second region 32 of the gate in the edge channel region 22 is located on the side of the second insulating layer 72 away from the substrate 1. This ensures that the thickness of the insulating layer 7 corresponding to the second region 32 of the gate is greater than the thickness of the insulating layer 7 corresponding to the first region 31 of the gate. When a voltage is applied to the gate metal layer 3, the voltage of the gate metal layer 3 controls the main channel region 21 and the edge channel region 22 in the active layer 9. Carrier movement occurs because the thickness of the insulating layer 7 corresponding to the second region 32 of the gate is greater than the thickness of the insulating layer 7 corresponding to the first region 31 of the gate. In the direction perpendicular to the plane of the substrate 1, the distance between the second region 32 of the gate and the edge channel region 22 is greater than the distance between the first region 31 of the gate and the main channel region 21. Therefore, the capacitance between the second region 32 of the gate and the edge channel region 22 will be less than the capacitance between the first region 31 of the gate and the main channel region 21. The ability of the second region 32 of the gate to control the movement of carriers in the edge channel region 22 will be weakened and will be less than the ability of the first region 31 of the gate to control the movement of carriers in the main channel region 21. The edge channel region 22 will not reach saturation current and turn on prematurely before the main channel region 21, thus improving the double-peak effect of the transistor T, improving the performance reliability of the transistor T, and thereby improving the performance reliability of the array substrate 100.

[0081] In some alternative embodiments, reference continues to be made to... Figure 10 , Figure 10 The diagram shows that the first region 31 and the second region 32 of the gate are connected by a via 15.

[0082] It is understandable that, in the direction perpendicular to the plane of the substrate 1, the thickness of the insulating layer 7 corresponding to the second region 32 of the gate is greater than the thickness of the insulating layer 7 corresponding to the first region 31 of the gate, and the distance between the second region 32 of the gate and the edge channel region 22 is greater than the distance between the first region 31 of the gate and the main channel region 21. Therefore, the first region 31 of the gate and the second region 32 of the gate are located on different film layers. The first region 31 of the gate and the second region 32 of the gate are electrically connected through the via 15, which can ensure the transmission of signals.

[0083] In some alternative embodiments, refer to Figure 11 , Figure 12 and Figure 13 , Figure 11 This is a schematic diagram of a planar structure of another array substrate provided by the present invention. Figure 12 yes Figure 11 A magnified view of a portion of region M. Figure 13 This is a schematic diagram of a planar structure of another array substrate provided by the present invention. In this embodiment, the array substrate 100 includes at least two transistors T, each transistor T further includes a source 4 and a drain 5. The source 4 and drain 5 are located on the side of the gate metal layer 3 away from the plane of the substrate 1. The source 4 and drain 5 are insulated from the gate 3 and electrically connected to the active layer 9. The gate 3, source 4 and drain 5 of adjacent transistors T are all connected in parallel.

[0084] In this embodiment, the array substrate 100 has a high-current transistor TD, which is formed by at least two transistors T connected in parallel. Parallel connection of transistors T refers to the parallel connection of the gate 3, source 4, and drain 5 of transistor T. The number of parallel transistors T is not specifically limited in this invention. Optionally, the source 4 and drain 5 are electrically connected to the active layer 9 through vias 8. It is understood that the high-current transistor TD can be a transistor T for driving Micro LEDs, because driving Micro LEDs requires milliampere-level current. A single transistor T is suitable for driving LCD or OLED display panels but cannot be used to drive Micro LEDs. In this embodiment, the larger transistor TD formed by connecting multiple transistors T in parallel meets the requirements for driving Micro LEDs.

[0085] Reference Figure 11 and Figure 12 and combined Figure 3The gate 3, source 4, and drain 5 of adjacent transistors T are connected in parallel to form a large-size transistor TD. Each transistor T includes an active layer 9 located on one side of the substrate 1. The active layer 9 includes a main channel region 21 and an edge channel region 22, with the edge channel region 22 located on at least one side of the main channel region 21. An insulating layer 7 is located on the side of the active layer 9 away from the substrate 1 and covers the active layer 9. A gate metal layer 3 is located on the side of the insulating layer 7 away from the substrate 1 and extends along a first direction X. In a direction perpendicular to the plane of the substrate 1, the region overlapping with the main channel region 21 is the first region 31 of the gate, and the remaining region is the second region 32 of the gate. In the second region 32 of the gate, the cutout region 6 overlaps at least partially with the edge channel region 22. When a voltage is applied to the gate metal layer 3, the main channel region 21 generates carrier migration under the action of the gate voltage. The cutout region 6 of the second region 32 of the gate overlaps at least partially with the edge channel region 22. There is no carrier migration at the position where the cutout region 6 overlaps with the edge channel region 22. Therefore, the setting of the cutout region 6 blocks the carrier migration path in the edge channel region 22 to a certain extent, reducing the possibility of the edge channel region 22 turning on the source 4 and drain 5. This can slow down the edge channel region 22 turning on before the main channel region 21, improve the double peak effect, improve the reliability of the transistor T, and improve the performance reliability of the array substrate 100.

[0086] Reference Figure 13 and combined Figure 10The gates 3, sources 4, and drains 5 of adjacent transistors T are connected in parallel to form a large-size transistor TD. Each transistor T includes an active layer 9 located on one side of the substrate 1. The active layer 9 includes a main channel region 21 and an edge channel region 22, with the edge channel region 22 located on at least one side of the main channel region 21. An insulating layer 7 is located on the side of the active layer 9 away from the substrate 1 and covers the active layer 9. A gate metal layer 3, in a direction perpendicular to the plane of the substrate 1, has a first region 31 overlapping the main channel region 21, and the remaining region is a second region 32 of the gate, located on the side of the insulating layer 7 away from the substrate 1. In a direction perpendicular to the plane of the substrate 1, the thickness of the insulating layer 7 corresponding to the second region 32 of the gate is greater than the thickness of the insulating layer 7 corresponding to the first region 31 of the gate. When a voltage is applied to the gate metal layer 3, the voltage of the gate metal layer 3 controls the active layer. The carrier movement in the main channel region 21 and the edge channel region 22 in 9 is affected by the fact that the thickness of the insulating layer 7 corresponding to the second region 32 of the gate is greater than the thickness of the insulating layer 7 corresponding to the first region 31 of the gate. In the direction perpendicular to the plane of the substrate 1, the distance between the second region 32 of the gate and the edge channel region 22 is greater than the distance between the first region 31 of the gate and the main channel region 21. Therefore, the capacitance between the second region 32 of the gate and the edge channel region 22 will be less than the capacitance between the first region 31 of the gate and the main channel region 21. The ability of the second region 32 of the gate to control the movement of carriers in the edge channel region 22 will be weakened and will be less than the ability of the first region 31 of the gate to control the movement of carriers in the main channel region 21. The edge channel region 22 will not reach the saturation current and turn on prematurely before the main channel region 21, thus improving the double-peak effect of the transistor T, improving the performance reliability of the transistor T, and thereby improving the performance reliability of the array substrate 100.

[0087] In some alternative embodiments, refer to Figure 14 , Figure 15 , Figure 16 and Figure 17 , Figure 14 This is a schematic diagram of a planar structure of another array substrate provided by the present invention. Figure 15 yes Figure 14 A magnified view of a portion of region N. Figure 16 This is a schematic diagram of a planar structure of another array substrate provided by the present invention. Figure 17 yes Figure 16 A partial enlarged view of the P region. In this embodiment, the second region 32 of the gate includes a cutout region 6, which at least partially overlaps with the edge channel region 22 in a direction perpendicular to the plane of the substrate 1; there is a gap 19 between the active layers 9 of adjacent transistors T, and the cutout region 6 extends to the gap 19 in a direction perpendicular to the plane of the substrate 1.

[0088] In this embodiment, the second region 32 of the gate includes a cutout region 6. In the direction perpendicular to the plane of the substrate 1, the cutout region 6 overlaps at least partially with the edge channel region 22. Therefore, there will be no carrier migration at the position where the cutout region 6 overlaps with the edge channel region 22. Thus, the setting of the cutout region 6 blocks the carrier migration path in the edge channel region 22 to a certain extent, reducing the possibility of the edge channel region 22 turning on the source 4 and drain 5. This can slow down the edge channel region 22 turning on before the main channel region 21, improve the double peak effect, improve the reliability of the transistor T, and improve the performance reliability of the array substrate 100.

[0089] Optionally, there is a gap 19 between the active layers 9 of adjacent transistors T, and the cutout region 6 extends to the gap 19 in a direction perpendicular to the plane of the substrate 1. This allows for a larger area to be made when fabricating the cutout region 6, making it easier to fabricate.

[0090] Figure 14 and Figure 15 In the process, the orthographic projection of the hollow area 6 on the plane perpendicular to the substrate 1 is a rectangle. On the one hand, the hollow area 6 has a relatively large area, which makes it easy to manufacture. On the other hand, the closed pattern formed by the outer edge of the hollow area 6 is completely hollowed out, that is, no structure of the same layer and material as the gate is set, which avoids the accumulation of static electricity during use. Figure 16 and Figure 17 In the process, the orthographic projection of the hollow area 6 on the plane perpendicular to the substrate 1 is a U-shape. That is, the closed pattern formed by the outer edge of the hollow area 6 is not completely hollowed out. A structure with the same layer and material as the gate is set in the hollow area 6, which can be called a virtual pattern.

[0091] In some alternative embodiments, reference continues to be made to... Figures 14 to 17 The cutout regions 6 of adjacent transistors T are connected.

[0092] Figure 14 and Figure 15 In the diagram, the orthographic projection of the cutout region 6 onto the plane perpendicular to the substrate 1 is rectangular. The cutout regions 6 of adjacent transistors T are connected. It is understood that as the resolution of the display panel increases, the spacing between the active layers of two adjacent transistors becomes very small. Therefore, connecting the cutout regions 6 of adjacent transistors T allows the area of ​​the cutout region 6 to be achieved within the current process precision. This avoids the risk of not being able to form a cutout region due to its small area when each transistor has its own corresponding cutout region, ultimately failing to reduce the driving capability of the edge channel region carriers. Simultaneously, connecting the cutout regions corresponding to two transistors forms a shape like... Figure 14 and Figure 15When patterning, the area of ​​the cutout region is doubled compared to the area of ​​a dedicated cutout region for each transistor. It also includes an additional area reserved between the two cutout regions to facilitate etching. This significantly reduces process complexity and improves product yield. Of course, this method can also be used in products with lower resolution. Figure 14 and Figure 15 The design of the central hollow area 6 further improves the yield rate.

[0093] Figure 16 and Figure 17 In the diagram, the orthographic projection of the cutout area 6 onto the plane perpendicular to the substrate 1 is a U-shape. Specifically, in some products where high resolution is not required, virtual graphics can be set inside the cutout area 6 to improve etching uniformity. (See reference...) Figure 16 and Figure 17 This setting avoids the need to create, for example Figure 14 and Figure 15 The large cutout area 6 shown in the diagram excessively prolongs the etching time, which may cause over-etching around the cutout area 6, thus cutting off the gate. It should be noted that the above "the cutout areas 6 of adjacent transistors T are connected" means that the same cutout area overlaps with the active layer 2 of two adjacent transistors T.

[0094] Based on the same inventive concept, referring to Figure 18 , Figure 18 This is a schematic diagram of a planar structure of a display panel provided by the present invention. The display panel in this embodiment includes the array substrate 100 of any of the above embodiments. Figure 18 The array substrate 100 is shown only schematically. The display panel provided in this embodiment of the invention has the beneficial effects of the array substrate 100 provided in this embodiment of the invention. For details, please refer to the specific description of the array substrate 100 in the above embodiments. This embodiment will not repeat the description here.

[0095] In some alternative embodiments, reference continues to be made to... Figure 18 The display panel in this embodiment includes a display area AA and a non-display area BB that at least partially surrounds the display area AA, and a transistor T is located in the display area AA.

[0096] Of course, this embodiment does not specifically limit the type of display panel. Figures 2 to 17 It is understandable. Figures 2 to 10 In any of the embodiments, transistor T is disposed in display area AA, suitable for driving LCD or OLED display panels; Figures 11 to 17 The large-size transistor TD in the medium is suitable for driving Micro LED display panels.

[0097] It is understood that the array substrate 100 of the present invention is applicable to any form of display panel, which can improve the double-peak effect and enhance performance reliability.

[0098] In some alternative embodiments, reference continues to be made to... Figures 2 to 17 , Figure 18 and reference Figure 19 , Figure 19 This invention provides a pixel circuit 20, wherein the display area AA includes multiple pixel circuits 20 arranged in an array, and the pixel circuit 20 can be referred to as follows. Figure 19The pixel circuit 20 includes a driving transistor M3, which is a high-current transistor TD. The pixel circuit 20 also includes a first transistor M1, a second transistor M2, a driving transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a storage capacitor Cst, and a light-emitting element OL. Specifically, the control terminal of the first transistor M1 is electrically connected to the light-emitting signal input terminal E1, the first terminal of the first transistor M1 is electrically connected to the first power supply signal terminal PVDD, and the second terminal of the first transistor M1 is electrically connected to the first terminal of the driving transistor M3. The control terminal of the second transistor M2 is connected to the second scanning signal terminal E1. The input terminal S2 is electrically connected; the first terminal of the second transistor M2 is electrically connected to the data signal input terminal Vdata; the second terminal of the second transistor M2 is electrically connected to the first terminal of the driving transistor M3; the control terminal of the driving transistor M3 is electrically connected to the second terminal of the fifth transistor M5; the first terminal of the driving transistor M3 is electrically connected to the second terminal of the first transistor M1 and the second terminal of the second transistor M2; the control terminal of the fourth transistor M4 is electrically connected to the second scan signal input terminal S2; the first terminal of the fourth transistor M4 is electrically connected to the second terminal of the fifth transistor M5 and the second terminal of the storage capacitor Cst; the second terminal of the fourth transistor M4 is electrically connected to the driving transistor M3. The second terminal of transistor M3 is electrically connected to the first terminal of transistor M6; the control terminal of transistor M5 is electrically connected to the first scan signal input terminal S1, the first terminal of transistor M5 is electrically connected to the reference voltage signal input terminal Vref, and the second terminal of transistor M5 is electrically connected to the control terminal of driving transistor M3; the control terminal of transistor M6 is electrically connected to the light emission signal input terminal E1, the first terminal of transistor M6 is electrically connected to the second terminal of driving transistor M3 and the second terminal of transistor M4, and the second terminal of transistor M6 is electrically connected to the anode of light emission element OL; the control terminal of transistor M7 is electrically connected to the second scan signal input terminal S1. Signal input terminal S2 is electrically connected; the first terminal of the seventh transistor M7 is electrically connected to the reference voltage signal input terminal Vref; the second terminal of the seventh transistor M7 is electrically connected to the first terminal of the light-emitting element OL; the first terminal of the light-emitting element OL is electrically connected to the second terminals of the sixth transistor M6 and the seventh transistor M7; the second terminal of the light-emitting element OL is electrically connected to the second power supply signal terminal PVEE; the first terminal of the storage capacitor Cst is electrically connected to the first power supply signal terminal PVDD; the second terminal of the storage capacitor Cst is electrically connected to the control terminal of the driving transistor M3, the first terminal of the fourth transistor M4, and the second terminal of the fifth transistor M5.

[0099] It is understood that the pixel circuit 20 in this embodiment can be used to drive a Micro LED display panel. The driving transistor M3 in this circuit needs to be able to withstand a relatively large current. Therefore, the driving transistor M3 in this embodiment can be... Figures 11 to 17 The transistor TD corresponding to any embodiment, Figures 11 to 17The transistor TD in the circuit is composed of multiple transistors T connected in parallel, capable of handling large currents, thus allowing the transistor TD to be driven under high current. In this embodiment, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 in the pixel circuit 20 only function as switches and cannot handle large currents. The first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be... Figures 2 to 10 An embodiment of transistor T. In this embodiment, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 in the pixel circuit 20 employ... Figures 2 to 10 In the embodiment, transistor T and driving transistor M3 are adopted Figures 11 to 17 The transistor TD in the embodiment can not only improve the double-peak phenomenon, but also adapt to display panels that require high current driving.

[0100] As can be seen from the above embodiments, the array substrate and display panel provided by the present invention achieve at least the following beneficial effects:

[0101] On one hand, the present invention provides an array substrate, including a substrate and a transistor located on one side of the substrate. The transistor includes: an active layer located on one side of the substrate, the active layer including a main channel region and an edge channel region, the edge channel region being located on at least one side of the main channel region; an insulating layer located on the side of the active layer away from the substrate, the insulating layer covering the active layer; a gate metal layer located on the side of the insulating layer away from the substrate, the gate metal layer extending along a first direction, at least a portion of the extension direction of the active layer intersecting the extension direction of the gate metal layer, and in a direction perpendicular to the plane of the substrate, the region overlapping with the main channel region is a first region of the gate, the remaining region is a second region of the gate; the second region of the gate includes a cutout region, in a direction perpendicular to the plane of the substrate... In the direction of the surface, the cutout region and the edge channel region at least partially overlap in the direction perpendicular to the plane of the substrate. The second region of the gate includes the cutout region and the edge channel region at least partially overlap. When a voltage is applied to the gate metal layer, the main channel region generates carrier migration under the action of the gate voltage. The second region of the gate includes the cutout region and the edge channel region at least partially overlap. Therefore, there will be no carrier migration at the position where the cutout region overlaps with the edge channel region. Thus, the setting of the cutout region at least to some extent cuts off the carrier migration path in the edge channel region, reduces the conduction of the source and drain in the edge channel region, thereby slowing down the edge channel region turning on before the main channel region, improving the double peak effect, improving the reliability of the transistor, and improving the performance reliability of the array substrate.

[0102] On the other hand, the present invention also provides an array substrate, including a substrate and a transistor located on one side of the substrate. The transistor includes: an active layer located on one side of the substrate, the active layer including a main channel region and an edge channel region, the edge channel region being located on at least one side of the main channel region; an insulating layer located on the side of the active layer away from the substrate, the insulating layer covering the active layer; a gate metal layer, at least a portion of the extension direction of the active layer intersects the extension direction of the gate metal layer, and in a direction perpendicular to the plane of the substrate, the region overlapping with the main channel region is a first region of the gate, the remaining region is a second region of the gate, the second region of the gate being located on the side of the insulating layer away from the substrate; in a direction perpendicular to the plane of the substrate, the thickness of the insulating layer corresponding to the second region of the gate is greater than the thickness of the insulating layer corresponding to the first region of the gate, when the gate metal layer... When a voltage is applied, the voltage of the gate metal layer controls the movement of charge carriers in the main channel region and the edge channel region of the active layer. Since the thickness of the insulating layer corresponding to the second region of the gate is greater than the thickness of the insulating layer corresponding to the first region of the gate, the distance between the second region of the gate and the edge channel region is greater than the distance between the first region of the gate and the main channel region in the direction perpendicular to the plane of the substrate. Therefore, the capacitance between the second region of the gate and the edge channel region will be less than the capacitance between the first region of the gate and the main channel region. The ability of the second region of the gate to control the movement of charge carriers in the edge channel region will be weakened, and it will be less than the ability of the first region of the gate to control the movement of charge carriers in the main channel region. The edge channel region will not reach saturation current and turn on prematurely before the main channel region, thus improving the double-peak effect of the transistor, improving the performance reliability of the transistor, and thus improving the performance reliability of the array substrate.

[0103] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. An array substrate, characterized in that, The device includes a substrate and a high-current transistor located on one side of the substrate. The high-current transistor has a driving current in the milliampere range and is used to drive a Micro LED. At least two transistors are connected in parallel to form the high-current transistor. In the same high-current transistor, the gate, source, and drain of adjacent transistors are all connected in parallel. The transistor includes: An active layer is located on one side of the substrate, the active layer includes a main channel region and an edge channel region, the edge channel region being located on at least one side of the main channel region; An insulating layer is located on the side of the active layer away from the substrate, and the insulating layer covers the active layer; A gate metal layer is located on the side of the insulating layer away from the substrate. The gate metal layer extends along a first direction. At least a portion of the extension direction of the active layer intersects with the extension direction of the gate metal layer. In a direction perpendicular to the plane of the substrate, the region that overlaps with the main channel region is the first region of the gate, and the remaining region is the second region of the gate. The second region of the gate includes a cutout region, and in a direction perpendicular to the plane of the substrate, the cutout region at least partially overlaps with the edge channel region; In the same high-current transistor, the cutout areas of adjacent transistors are connected, and the closed pattern formed by the outer edges of the cutout areas is completely cut out.

2. The array substrate according to claim 1, characterized in that, The transistor further includes a source and a drain, which are located on the side of the gate metal layer away from the plane of the substrate. The source and the drain are insulated from the gate metal layer and electrically connected to the active layer. The cutout region is located between the source and the drain in the direction from the source to the drain.

3. The array substrate according to claim 1, characterized in that, The gate metal layer includes a first edge and a second edge disposed opposite to each other along a second direction, the second direction intersecting the first direction; In a direction perpendicular to the plane of the substrate, the cutout area is located between the first edge and the second edge.

4. The array substrate according to claim 1, characterized in that, In the direction from the main channel to the edge channel area, the width of the hollow area that intersects with the edge channel area is less than or equal to the width of the edge channel area.

5. The array substrate according to claim 1, characterized in that, In a direction perpendicular to the plane of the substrate, the orthographic projection shape of the cutout area includes a concave shape, an arc shape, or an hourglass shape, and the orthographic projection edge of the plane of the substrate has a curve.

6. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 5.

7. The display panel according to claim 6, characterized in that, It includes a display area and a non-display area that at least partially surrounds the display area, wherein the transistor is located in the display area.

8. The display panel according to claim 7, characterized in that, The display area includes multiple pixel circuits arranged in an array. Each pixel circuit includes a driving transistor, and the driving transistor is the transistor itself. The pixel circuit includes: The first transistor has its control terminal electrically connected to the light-emitting signal input terminal, its first terminal electrically connected to the first power supply signal terminal, and its second terminal electrically connected to the first terminal of the driving transistor. The second transistor has its control terminal electrically connected to the second scan signal input terminal, its first terminal electrically connected to the data signal input terminal, and its second terminal electrically connected to the first terminal of the driving transistor. The driving transistor has its control terminal electrically connected to the second terminal of the fifth transistor, and its first terminal electrically connected to the second terminal of the first transistor and the second terminal of the second transistor. The fourth transistor has its control terminal electrically connected to the second scan signal input terminal, its first terminal electrically connected to the second terminal of the fifth transistor and the second terminal of the storage capacitor, and its second terminal electrically connected to the second terminal of the driving transistor and the first terminal of the sixth transistor. The fifth transistor has its control terminal electrically connected to the first scan signal input terminal, its first terminal electrically connected to the reference voltage signal input terminal, and its second terminal electrically connected to the control terminal of the driving transistor. The sixth transistor has its control terminal electrically connected to the light-emitting signal input terminal, its first terminal electrically connected to the second terminal of the driving transistor and the second terminal of the fourth transistor, and its second terminal electrically connected to the anode of the light-emitting element. The seventh transistor has its control terminal electrically connected to the second scan signal input terminal, its first terminal electrically connected to the reference voltage signal input terminal, and its second terminal electrically connected to the first terminal of the light-emitting element. The light-emitting element has its first terminal electrically connected to the second terminal of the sixth transistor and the second terminal of the seventh transistor, and its second terminal electrically connected to the second power supply signal terminal. The storage capacitor has its first end electrically connected to the first power signal terminal, and its second end electrically connected to the control terminal of the driving transistor, the first terminal of the fourth transistor, and the second terminal of the fifth transistor.

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