Display panel and display terminal

Abstract

The application provides a display panel and a display terminal, the display panel comprising a gate drive circuit, the gate drive circuit comprising a plurality of drive unit circuits connected in cascade, each drive unit circuit comprising at least one thin film transistor, the thin film transistor comprising a first metal layer, an active layer, a second metal layer and a third metal layer; a first capacitor is formed between the second metal layer and the first metal layer; a second capacitor is formed between the third metal layer and the second metal layer, and a third capacitor is formed between the third metal layer and the first metal layer; the first capacitor, the second capacitor and the third capacitor are combined to form a bootstrap capacitor of the drive unit circuit; the third metal layer of the application forms a capacitor between the first metal layer and the second metal layer respectively, and a part of the second metal layer forms a capacitor between the first metal layer, which can replace the bootstrap capacitor in the prior art, removes the large-area overlapping part of the second metal layer and the first metal layer additionally added, thereby optimizing the space and reducing the frame.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display terminal. BACKGROUND

[0002] Generally, the gate driving circuit is arranged in the frame area of the display panel, and in the gate driving circuit, the thin film transistor T21 occupies the largest space. Specifically, as shown in the top view of the prior art thin film transistor and the cross-sectional view of the prior art thin film transistor shown in FIGS. Figure 1 and Figure 2 The thin film transistor includes a first metal layer 10, an active layer 20 and a second metal layer 30, wherein the second metal layer 30 and the first metal layer 10 overlap in a large area to form a bootstrap capacitor in the gate driving circuit.

[0003] Because the second metal layer 30 and the first metal layer 10 overlap in a large area, the space occupied by the gate driving circuit is increased, which increases the left and right frame of the display panel, and is not conducive to realizing a narrow frame. Therefore, it is necessary to improve this defect. SUMMARY

[0004] The embodiment of the present application provides a display panel, which is used to solve the technical problem that the frame of the prior art display panel is increased by overlapping the second metal layer and the first metal layer in a large area to form a bootstrap capacitor in the gate driving circuit, which is not conducive to realizing a narrow frame.

[0005] The embodiment of the present application provides a display panel, which includes a gate driving circuit, the gate driving circuit includes a plurality of driving unit circuits connected in cascade, each of the driving unit circuits includes at least one thin film transistor, the thin film transistor includes a first metal layer, an active layer, a second metal layer and a third metal layer; the active layer is located on the first metal layer; the second metal layer is located on the active layer, and a first capacitor is formed between the second metal layer and the first metal layer; the third metal layer is located on the second metal layer, a second capacitor is formed between the third metal layer and the second metal layer, and a third capacitor is formed between the third metal layer and the first metal layer; wherein the first capacitor, the second capacitor and the third capacitor are combined to form a bootstrap capacitor of the driving unit circuit.

[0006] In the display panel provided by the embodiment of the present application, the first metal layer includes a patterned first gate and a first gate line, the second metal layer includes a patterned source and a drain, and the source and the drain are respectively electrically connected to two ends of the active layer; wherein the orthographic projection of the first gate, the source and the drain on the active layer is located on the active layer.

[0007] In the display panel provided by the embodiment of the present application, the display panel comprises a display area and a frame area surrounding the display area, one side of the frame area is provided with a signal source module, the gate drive circuit is located in the frame area, and the gate drive circuit is arranged adjacent to the side where the signal source module is located; wherein the drive unit circuit is electrically connected with the signal source module through a clock signal wire, and the first gate electrode is electrically connected with the signal source module through the first gate line.

[0008] In the display panel provided by the embodiment of the present application, the third metal layer is electrically connected with the signal source module through a second gate line, the clock signal wire is located on the side of the drive unit circuit away from the display area, and the second gate line is located on the side of the clock signal wire away from the drive unit circuit.

[0009] In the display panel provided by the embodiment of the present application, the third metal layer is electrically connected with the signal source module through a second gate line, the clock signal wire is located on the side of the drive unit circuit away from the display area, and the second gate line is located between the clock signal wire and the drive unit circuit.

[0010] In the display panel provided by the embodiment of the present application, the thin film transistor further comprises a fourth metal layer, the fourth metal layer is located on the third metal layer, one end of the fourth metal layer is electrically connected with the third metal layer through a first via, and the other end of the fourth metal layer is electrically connected with the first gate line through a second via.

[0011] In the display panel provided by the embodiment of the present application, the thin film transistor further comprises a fourth metal layer, the fourth metal layer is located on the third metal layer, one end of the fourth metal layer is electrically connected with the third metal layer through a first via, and the other end of the fourth metal layer is electrically connected with the first gate line through a second via.

[0012] In the display panel provided by the embodiment of the present application, the plurality of drive unit circuits are divided into at least two drive unit groups, the number of the drive unit circuits in each drive unit group is equal to the number of the clock signal wires; wherein in one drive unit group, in the direction of the top view of the display panel, the area of the third metal layer gradually decreases in the direction that the length of the clock signal wire increases.

[0013] In the display panel provided by the embodiment of the present application, the plurality of drive unit circuits are divided into at least two drive unit groups, the number of the drive unit circuits in each drive unit group is equal to the number of the clock signal wires; and in one drive unit group, the straight-line distance between the third metal layer and the second metal layer gradually increases in the direction in which the length of the clock signal wire increases.

[0014] The embodiment of the present application further provides a display terminal, comprising a terminal main body and the display panel.

[0015] Beneficial effects: the display panel provided by the embodiment of the present application comprises a gate drive circuit, the gate drive circuit comprises a plurality of drive unit circuits connected in cascade, each drive unit circuit comprises at least one thin film transistor, the thin film transistor comprises a first metal layer, an active layer, a second metal layer and a third metal layer; the active layer is located on the first metal layer; the second metal layer is located on the active layer, and a first capacitor is formed between the second metal layer and the first metal layer; the third metal layer is located on the second metal layer, a second capacitor is formed between the third metal layer and the second metal layer, and a third capacitor is formed between the third metal layer and the first metal layer; wherein the first capacitor, the second capacitor and the third capacitor combine to form a bootstrap capacitor of the drive unit circuit; by adding the third metal layer on the second metal layer of the thin film transistor, the third metal layer forms a capacitor with the first metal layer and the second metal layer respectively and part of the second metal layer forms a capacitor with the first metal layer, the bootstrap capacitor in the prior art can be replaced, the large-area overlapping part between the second metal layer and the first metal layer in the prior art is removed, and therefore the space can be optimized and the frame can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced.

[0017] Figure 1 is a top view of the thin film transistor in the prior art.

[0018] Figure 2 is a sectional view of the thin film transistor in the prior art.

[0019] Figure 3 is a top view of the thin film transistor provided by the embodiment of the present application.

[0020] Figure 4 is a sectional view of the thin film transistor provided by the embodiment of the present application.

[0021] Figure 5 is an equivalent principle diagram of the bootstrap capacitor provided by the embodiment of the present application.

[0022] Figure 6 is a basic structure schematic diagram of a gate drive circuit provided by an embodiment of the present application.

[0023] Figure 7 is a basic structure schematic diagram of a display panel provided by an embodiment of the present application.

[0024] Figure 8 is a sectional view schematic diagram of another thin film transistor provided by an embodiment of the present application.

[0025] Figure 9 is a sectional view schematic diagram of still another thin film transistor provided by an embodiment of the present application.

[0026] Figure 10 is a basic structure schematic diagram of a drive unit group provided by an embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. In the drawings, the sizes and thicknesses of the components shown in the drawings are not in proportion for the sake of clarity and convenience of understanding and description.

[0028] An embodiment of the present application provides a display panel, comprising a gate drive circuit, wherein the gate drive circuit comprises a plurality of drive unit circuits connected in cascade, each of the drive unit circuits comprises at least one thin film transistor, such as Figure 3 and Figure 4 As shown in the top view of a thin film transistor provided by an embodiment of the present application and the sectional view schematic diagram of a thin film transistor provided by an embodiment of the present application, the thin film transistor comprises a first metal layer 10, an active layer 20, a second metal layer 30 and a third metal layer 40; the active layer 20 is located on the first metal layer 10; the second metal layer 30 is located on the active layer 20, and a first capacitor C1 (as shown in Figure 5 ) is formed between the second metal layer 30 and the first metal layer 10; the third metal layer 40 is located on the second metal layer 30, a second capacitor C2 (as shown in Figure 5 ) is formed between the third metal layer 40 and the second metal layer 30, and a third capacitor C3 (as shown in Figure 5 ) is formed between the third metal layer 40 and the first metal layer 10; wherein the first capacitor C1, the second capacitor C2 and the third capacitor C3 are combined to form a bootstrap capacitor of the drive unit circuit.

[0029] It can be understood that the prior art forms the bootstrap capacitor through the position of the large-area overlap of the second metal layer and the first metal layer, which causes the space occupied by the gate drive circuit to be large, and is not conducive to realizing the narrow frame. The bootstrap capacitor of the drive unit circuit is formed by the first capacitor C1 (such as Figure 5 ) between the part of the second metal layer 30 and the first metal layer 10, the second capacitor C2 (such as Figure 5 ) between the third metal layer 40 and the second metal layer 30, and the third capacitor C3 (such as Figure 5 ) between the third metal layer 40 and the first metal layer 10. The first capacitor C1, the second capacitor C2 and the third capacitor C3 are combined to form the bootstrap capacitor of the drive unit circuit, so that the large-area overlap part of the second metal layer and the first metal layer in the prior art can be removed, and the space can be optimized and the frame can be reduced.

[0030] In an embodiment, the first metal layer 10 includes a patterned first gate 101 and a first gate line 102, and the second metal layer 30 includes a patterned source 301 and a drain 302, and the source 301 and the drain 302 are respectively electrically connected to both ends of the active layer 20; wherein the orthographic projection of the first gate 101, the source 301 and the drain 302 on the active layer 20 is located on the active layer 20.

[0031] It can be understood that the orthographic projection of the first gate 101, the source 301 and the drain 302 on the active layer 20 is located on the active layer 20 in the embodiment, so as to avoid the overlap area of the first gate 101 and the source 301 and the drain 302 being too large, and the frame can be further reduced.

[0032] It should be noted that in the top view direction of the display panel, the area of the third metal layer 40 can be smaller than the area of the first gate 101, or smaller than the area of the active layer 20, and the size of the second capacitor C2 (such as Figure 5 ) between the third metal layer 40 and the second metal layer 30 and the third capacitor C3 (such as Figure 5 ) between the third metal layer 40 and the first metal layer 10 can be adjusted by adjusting the area of the third metal layer 40.

[0033] It can be understood that the first gate 101 is the bottom gate of the thin film transistor, and the third metal layer 40 is the top gate of the thin film transistor. When the first gate 101 and the third metal layer 40 are separate film layers in the thin film transistor (i.e. the third metal layer 40 is not connected to the first gate 101), the signals corresponding to the first gate 101 and the third metal layer 40 are separately input. Therefore, the electrical properties of the thin film transistor can be adjusted by adjusting the voltage of the first gate 101 and the third metal layer 40 of the thin film transistor.

[0034] It is to be noted that Vth=Vth(initial)-ΔVth; wherein Vth refers to the actual threshold voltage after the aging test, Vth(initial) refers to the threshold voltage before the aging test, and ΔVth refers to the difference between the threshold voltage after the electrical shift and the threshold voltage before the electrical shift in the aging test.

[0035] It can be understood that a smaller V-M1 Gate signal allows the thin film transistor to open, and the thin film transistor is prone to leakage, at this time, V-M3 Gate≈ΔVth. After the aging test, the equivalent threshold voltage of the double gate is calculated as follows: V-M1 Gate=Vth+V-M3 Gate=Vth(initial)-ΔVth+V-M3 Gate≈Vth(initial)-ΔVth+ΔVth≈Vth(initial). Wherein V-M1 Gate refers to the threshold voltage of the thin film transistor with the first gate 101 as the gate, and V-M3 Gate refers to the threshold voltage of the thin film transistor with the third metal layer 40 as the gate.

[0036] Specifically, when the threshold voltage Vth of the thin film transistor is positively biased, ΔVth>0V, and V-M3 Gate is adjusted to the positive voltage corresponding to ΔVth; when the threshold voltage Vth of the thin film transistor is negatively biased, ΔVth<0V, and V-M3 Gate is adjusted to the negative voltage corresponding to ΔVth. Thus, the influence of Vth shift on the electrical properties of the thin film transistor can be reduced.

[0037] In an embodiment, the display panel further comprises a substrate layer 50, a gate insulating layer 60, a first passivation layer 70, and a second passivation layer 80, the first metal layer 10 is located on the substrate layer 50, the gate insulating layer 60 is located on the first metal layer 10, the active layer 20 is located on the gate insulating layer 60, the second metal layer 30 is located on the active layer 20 and the gate insulating layer 60, the first passivation layer 70 is located on the second metal layer 30, the third metal layer 40 is located on the first passivation layer 70, and the second passivation layer 80 is located on the third metal layer 40.

[0038] In an embodiment, the second metal layer 30 further comprises a signal line 303. It is to be noted that the signal line 303 and the first gate line 102 are located in the non-display area, and the signal lines are horizontally and vertically staggered in the non-display area, which is prone to short circuit. The present application can prevent signal short circuit by connecting the signal line 303 with the first gate line 102, i.e., by connecting different layers of metal as signal lines.

[0039] Next, please refer to Figure 5The equivalent principle diagram of the bootstrap capacitor provided by the embodiment of the present application is shown in the figure, from which it can be obviously seen that the first capacitor C1 is formed between the second metal layer 30 and the first metal layer 10, the second capacitor C2 is formed between the third metal layer 40 and the second metal layer 30, and the third capacitor C3 is formed between the third metal layer 40 and the first metal layer 10. Among them, C1 and C2 are connected in series, and then connected in parallel with C3. In the display panel provided by the present application, the bootstrap capacitor is C1*C2 / (C1+C2)+C3.

[0040] Next, refer to Figure 6 The basic structure diagram of the gate drive circuit provided by the embodiment of the present application is shown in the figure, which includes a pull-up control unit 100, a pull-up unit 200, a pull-down unit 300, a pull-down maintenance unit 400 and an inverter unit 500. In Figure 6 In the gate drive circuit shown in the figure, in the first stage, when STn-2 is H (high level), T11 is opened, H passes through T11 to enter Q point, the bootstrap capacitor Cb is charged, the gates of T22 and T21 are H, T22 and T21 are opened, CKn passes through T22 to enter STn, and CKn passes through T21 to enter Gn. In the second stage, when STn-2 is L (low level), T11 is closed, at this time Cb charges Q point, CKn continues to pass through T22 to enter STn, and passes through T21 to enter Gn. In the third stage, when STn+3 is H, T41 and T31 are opened, Q point passes through T41 to enter VSSQ (first direct current low level terminal) and becomes L, so that T22 and T21 are closed; Gn passes through T31 to enter VSSG (second direct current low level terminal) and becomes L, so that the scanning signal is L, and the corresponding row of pixels is closed.

[0041] In the gate drive circuit provided by the embodiment of the present application, T21 is a control TFT of the output signal Gn (i.e. the scanning signal), and in Figure 6 In the 18T1C gate drive circuit shown in the figure, when T21 is opened, Gn outputs the same signal as CKn, which is usually high potential, so that the Nth row of pixels is synchronously opened and the corresponding data signal is written; when T21 is closed, Gn outputs the same low potential signal as VSSG, so that the Nth row of pixels is synchronously closed. In the display time of one frame, since the display picture is scanned and displayed row by row, one row of pixels is opened only once in one frame. Correspondingly, in the gate drive circuit, the TFTs related to the inverter unit 500 (including T51, T52, T61 and T62) and the TFTs related to the pull-down maintenance unit 400 (including T32, T72, T42, T33, T73 and T43) are in the opened state for a long time, and the remaining TFTs are switched in a very short time to complete signal transmission, so that Gn outputs the corresponding scanning signal, opens the driving unit circuit corresponding to the row of pixels, i.e. the Nth row of pixels, and makes the pixel write the corresponding data signal.

[0042] It should be noted that the embodiment of the present application improves T21 in the gate drive circuit, adds a third metal layer on the second metal layer of T21, the third metal layer forms a capacitor with the first metal layer and the second metal layer respectively, and part of the second metal layer forms a capacitor with the first metal layer, which can replace the bootstrap capacitor Cb in the prior art, and the large-area overlapping part of the second metal layer and the first metal layer in the prior art is removed, so that the space can be optimized and the frame can be reduced.

[0043] It should be noted that the double-gate thin film transistor provided by the embodiment of the present application is not only suitable for the thin film transistor T21 in the gate drive circuit, but also suitable for the thin film transistor in other gate drive circuits, or the display area circuit, or the DataDemux circuit, or the Gate Demux circuit, which is prone to electrical offset due to the influence of current, voltage, light, etc.

[0044] It should be noted that the present application is suitable for oxide semiconductor, amorphous silicon and low-temperature polysilicon devices in HVA&FFS mode.

[0045] In one embodiment, the signal line for adjusting the electrical property of the third metal layer 40 (such as Figure 4 ) can be arranged outside the clock signal line 12 (such as Figure 7 ) of the bus area A21 (such as Figure 7 ) of the gate drive circuit or close to the position of the thin film transistor in the drive unit circuit 11 (such as Figure 7 ). Specifically, please refer to Figure 7 , the basic structure diagram of the display panel provided by the embodiment of the present application, the display panel includes a display area A1 and a frame area A2 surrounding the display area A1, one side of the frame area A2 is provided with a signal source module 90, the gate drive circuit is located in the frame area A2, and the gate drive circuit is arranged adjacent to the side where the signal source module 90 is located; wherein the drive unit circuit 11 is electrically connected with the signal source module 90 through the clock signal line 12, and the first gate 101 (such as Figure 4 ) is electrically connected with the signal source module 90 through the first gate line 102 (such as Figure 4 ).

[0046] In the embodiment, the third metal layer 40 (such as Figure 4 ) is electrically connected with the signal source module 90 through the second gate line 13, the clock signal line 12 is located on the side of the drive unit circuit 11 away from the display area A1, and the second gate line 13 is located on the side of the clock signal line 12 away from the drive unit circuit 11.

[0047] It can be understood that the embodiment adds a second gate line 13 parallel to the clock signal line 12, the second gate line 13 can be prepared together with the third metal layer 40 (such as Figure 4 ), the second gate line 13 is directly connected to the bus area A21 from the thin film transistor inside each row of the drive unit circuit 11, and then connected to the signal source module 90 through the fan-out area A22.

[0048] In other embodiments, the third metal layer 40 (such as Figure 4 ) is electrically connected to the signal source module 90 through the second gate line 13, the clock signal line 12 is located on the side of the drive unit circuit 11 away from the display area A1, and the second gate line 13 is located between the clock signal line 12 and the drive unit circuit 11. This embodiment is not illustrated.

[0049] It should be noted that the display panel further includes a data line 21 and a scan line 22 located in the display area A1, a drive integrated circuit 91, a flexible circuit board 92, a chip on film 93, an electrostatic protection circuit 94 and a common voltage line 95 located in the frame area A2.

[0050] In an embodiment, the third metal layer 40 (such as Figure 4 ) can also be connected to the first gate line (not shown in the figure) of the bus area A21 by setting a via in the bus area A21, and then connected to the signal source module 90 through the first gate line of the fan-out area A22. For details, please refer to Figure 8 , another cross-sectional view of a thin film transistor provided by an embodiment of the present application, the thin film transistor further includes a fourth metal layer 41, the fourth metal layer 41 is located on the third metal layer 40, one end of the fourth metal layer 41 is electrically connected to the third metal layer 40 through a first via 42, and the other end of the fourth metal layer 41 is electrically connected to the first gate line 102 through a second via 43.

[0051] It can be understood that the voltage of the third metal layer 40 of the embodiment is also transmitted through the first gate line 102. Therefore, the second gate line can be omitted, and the embodiment can further reduce the frame by reducing the number of lines.

[0052] In an embodiment, the thin film transistor further includes a planarization layer 81 located between the first passivation layer 70 and the third metal layer 40.

[0053] Next, please refer to Figure 9A schematic cross-sectional view of another thin film transistor provided by an embodiment of the present application also includes a fourth metal layer 41, which is located on the third metal layer 40, one end of the fourth metal layer 41 is electrically connected with the third metal layer 40 through a first via 42, and the other end of the fourth metal layer 41 is electrically connected with the first gate 101 through a second via 43.

[0054] It can be understood that the third metal layer 40 of the thin film transistor provided by the embodiment is connected with the first gate 101 (i.e., the third capacitance C3 is 0, and the second capacitance C2 is in parallel with the first capacitance C1), and the capacitance C2 (such as Figure 5 ) formed by the overlapping area of the newly added third metal layer 40 and the second metal layer 30 (such as Figure 5 ) can replace the bootstrap capacitance Cb (such as Figure 6 ) in parallel with T21 in the prior art, so that the space occupied by the gate drive circuit can be reduced, and the left and right borders of the display panel can be narrowed.

[0055] In an embodiment, the plurality of drive unit circuits 11 (such as Figure 7 ) are divided into at least two drive unit groups 111 (such as Figure 10 ). Specifically, please refer to Figure 10 A schematic diagram of the basic structure of a drive unit group provided by an embodiment of the present application, the number of drive unit circuits in each of the drive unit groups 111 is equal to the number of clock signal wires 12.

[0056] It should be noted that, taking an FHD product as an example, there are a total of 1080 rows of pixels, and assuming that there are 6 clock signal wires CK1-CK6, the 6 clock signal wires in the gate drive circuit are repeated for a total of 1080 / 6=180 times in a cycle. Among them, in one CK cycle (i.e., in one of the drive unit groups 111), CK1 and CK6, the length of the horizontal line from left to right is not the same, CK1 horizontal line will overlap with the other 5 CK lines, and then enter the drive unit circuit, but CK6 directly enters the drive unit circuit and does not overlap with other CK lines, so their capacitances are different. The longest line (CK1) and the shortest line (CK6) are adjacent, and the difference can be clearly seen during display, i.e., the brightness of the pixels in the row where CK1 is located is obviously lower (there is a horizontal cycle line H-line dark line).

[0057] In an embodiment, in one of the drive unit groups 111, in the direction of the top view of the display panel, the area of the third metal layer 40 (such as Figure 4 ) gradually decreases in the direction in which the length of the clock signal wire 12 increases.

[0058] It should be noted that, in addition to the display area, the T21 occupies the largest space in the gate drive circuit, so its Cgs, Cgd are also the largest, and the load effect on the clock signal line 12 is also the largest. The embodiment of the application adds a third metal layer on the second metal layer of T21, adjusts the area size of the third metal layer overlaid on T21 corresponding to the different clock signal lines 12, thereby adjusting the uniformity of the load of the clock signal line, optimizing the output of the gate drive circuit, improving the dark line defect, and improving the display effect.

[0059] Among them, due to the uniformity of the thin film transistor design, after removing the large-area overlapping part of the second metal layer and the first metal layer, the first capacitances C1 (such as Figure 5 ) of all stages of T21 / T22 are equal. Therefore, by adjusting the area size of the third metal layer, the second capacitances C2 (such as Figure 5 ), the third capacitances C3 (such as Figure 5 ) can be adjusted synchronously, thereby changing the capacitance of T21.

[0060] In one embodiment, in one of the driving unit groups 111, the straight-line distance between the third metal layer 40 (such as Figure 4 ) and the second metal layer 30 (such as Figure 4 ) gradually increases in the direction of the length of the clock signal line 12.

[0061] It can be understood that, by adjusting the straight-line distance between the third metal layer and the second metal layer, the size of the second capacitances C2 (such as Figure 5 ), the third capacitances C3 (such as Figure 5 ) can be adjusted, thereby adjusting the uniformity of the load of the clock signal line, optimizing the output of the gate drive circuit, improving the dark line defect, and improving the display effect.

[0062] The embodiment of the application also provides a display terminal, which comprises a terminal main body and the display panel described above, and the terminal main body and the display panel are combined into one. The specific structure of the display panel is described in the Figures 3 to 10 and related description, which will not be repeated here. The display terminal provided by the embodiment of the application can be: mobile phone, tablet computer, notebook computer, television, digital camera, navigator, and other products or components with display function.

[0063] In summary, the display panel provided by the embodiment of the present application comprises a gate drive circuit, the gate drive circuit comprises a plurality of drive unit circuits connected in cascade, each drive unit circuit comprises at least one thin film transistor, the thin film transistor comprises a first metal layer, an active layer, a second metal layer and a third metal layer; the active layer is located on the first metal layer; the second metal layer is located on the active layer, and a first capacitor is formed between the second metal layer and the first metal layer; the third metal layer is located on the second metal layer, a second capacitor is formed between the third metal layer and the second metal layer, and a third capacitor is formed between the third metal layer and the first metal layer; wherein the first capacitor, the second capacitor and the third capacitor are combined to form a bootstrap capacitor of the drive unit circuit; the present application adds a third metal layer on the second metal layer of the thin film transistor, the third metal layer forms a capacitor between the first metal layer and the second metal layer and a capacitor between part of the second metal layer and the first metal layer, which can replace the bootstrap capacitor in the prior art, remove the large-area overlapping part of the second metal layer and the first metal layer in the prior art, thereby optimizing the space, reducing the frame, and solving the technical problem that the frame of the display panel in the prior art is increased by making the second metal layer and the first metal layer overlap in a large area to form a bootstrap capacitor in the gate drive circuit, which is not conducive to realizing a narrow frame.

[0064] The display panel and the display terminal provided by the embodiment of the present application are described in detail above. It should be understood that the exemplary embodiments described herein should only be considered as descriptive, for helping to understand the method of the present application and its core idea, and should not be considered as limiting the present application.

Claims

1. A display panel, characterized in that, The circuit includes a gate driving circuit, which comprises a plurality of cascaded driving unit circuits, each of which includes at least one thin-film transistor, the thin-film transistor comprising: A first metal layer; the first metal layer includes a patterned first gate and a first gate line; The active layer is located on the first metal layer; A second metal layer is located on the active layer, and a first capacitor is formed between the second metal layer and the first metal layer; the second metal layer includes a patterned source and a drain, and the source and the drain are electrically connected to the two ends of the active layer, respectively. A third metal layer is located on the second metal layer, a second capacitor is formed between the third metal layer and the second metal layer, and a third capacitor is formed between the third metal layer and the first metal layer; Wherein, the orthogonal projections of the third metal layer, the first gate, the source, and the drain onto the active layer are located on the active layer; the first capacitor, the second capacitor, and the third capacitor together form the bootstrap capacitor of the driving unit circuit; The first gate and the third metal layer are separate films in the thin-film transistor.

2. The display panel as described in claim 1, characterized in that, The display panel includes a display area and a border area surrounding the display area. A signal source module is disposed on one side of the border area. The gate driving circuit is located within the border area and is disposed adjacent to the side where the signal source module is located. The driving unit circuit is electrically connected to the signal source module via a clock signal trace, and the first gate is electrically connected to the signal source module via the first gate line.

3. The display panel as described in claim 2, characterized in that, The third metal layer is electrically connected to the signal source module through the second gate line. The clock signal trace is located on the side of the driving unit circuit away from the display area, and the second gate line is located on the side of the clock signal trace away from the driving unit circuit.

4. The display panel as described in claim 2, characterized in that, The third metal layer is electrically connected to the signal source module through the second gate line. The clock signal trace is located on the side of the driving unit circuit away from the display area, and the second gate line is located between the clock signal trace and the driving unit circuit.

5. The display panel as described in claim 2, characterized in that, The thin-film transistor further includes a fourth metal layer located on the third metal layer. One end of the fourth metal layer is electrically connected to the third metal layer through a first via, and the other end of the fourth metal layer is electrically connected to the first gate line through a second via.

6. The display panel as described in claim 2, characterized in that, The thin-film transistor further includes a fourth metal layer located on the third metal layer. One end of the fourth metal layer is electrically connected to the third metal layer through a first via, and the other end of the fourth metal layer is electrically connected to the first gate through a second via.

7. The display panel as described in claim 2, characterized in that, The plurality of driving unit circuits are divided into at least two driving unit groups, and the number of driving unit circuits in each driving unit group is equal to the number of clock signal traces; In one of the driving unit groups, in the top view direction of the display panel, the area of ​​the third metal layer gradually decreases along the direction of increasing length of the clock signal trace.

8. The display panel as described in claim 2, characterized in that, The plurality of driving unit circuits are divided into at least two driving unit groups, and the number of driving unit circuits in each driving unit group is equal to the number of clock signal traces; In one of the drive unit groups, the straight-line distance between the third metal layer and the second metal layer gradually increases along the direction of increasing clock signal trace length.

9. A display terminal, characterized in that, It includes a terminal body and a display panel as described in any one of claims 1 to 8, wherein the terminal body and the display panel are integrated into one unit.

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