Display panel, method of manufacturing the same, and electronic device using the same

Abstract

A display panel, a method of manufacturing the display panel, and an electronic device using the display panel are provided, the display panel including a substrate including an opening, a plurality of light emitting elements arranged in a display area located around the opening, each of the plurality of light emitting elements including a first electrode, a second electrode, and an intermediate layer between the first electrode and the second electrode, a plurality of partition walls arranged in an intermediate area between the display area and the opening, and an encapsulation layer on the plurality of light emitting elements, the encapsulation layer including an inorganic encapsulation layer and an organic encapsulation layer. The second electrode extends from the display area toward the intermediate area. An organic layer of the intermediate layer includes a plurality of open portions arranged in an area from the opening to an edge portion of the second electrode facing the opening.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0127523, filed on September 29, 2020, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display panel, a method of manufacturing the display panel, and an electronic device using the display panel. Background Technology

[0003] Recently, the applications of display panels have become more diversified. Furthermore, as display panels have become thinner and lighter, their range of applications has gradually expanded.

[0004] As the area occupied by the display area in the display panel has increased, various functions have been added in combination with or associated with the display panel. In order to add various functions while expanding the area occupied by the display area, research has been conducted on adding various functions other than displaying images to a part of the display area. Summary of the Invention

[0005] One or more embodiments relate to a display panel including at least one opening on the inside of a display area, a method of manufacturing the display panel, and an electronic device using the display panel.

[0006] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description or may be learned by practice of the disclosed embodiments.

[0007] According to one or more embodiments, a display panel includes: a substrate including an opening; a plurality of light-emitting elements disposed in a display area surrounding the opening, each of the plurality of light-emitting elements including a first electrode, a second electrode, and an intermediate layer between the first electrode and the second electrode; a plurality of partition walls disposed in the intermediate region between the display area and the opening; and an encapsulation layer on the plurality of light-emitting elements, the encapsulation layer including an inorganic encapsulation layer and an organic encapsulation layer. The second electrode extends from the display area toward the intermediate region. The organic layer of the intermediate layer includes a plurality of opening portions disposed in a region extending from the opening to the edge portion facing the opening of the second electrode.

[0008] The organic layer may include organic portions separated from each other by the plurality of openings. The top surface of the organic portion may contact the inorganic encapsulation layer.

[0009] In the plan view, each of the plurality of openings may have a closed loop shape surrounding the opening.

[0010] At least one of the plurality of openings may be arranged between two adjacent partition walls from the plurality of partition walls.

[0011] At least one of the plurality of openings may be arranged between the opening and the partition wall closest to the opening from the plurality of partition walls.

[0012] At least one of the plurality of openings may be arranged between the display area and the partition wall closest to the display area from the plurality of partition walls.

[0013] The organic layer may include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0014] The display panel may also include an inorganic insulating layer disposed on the substrate. The inorganic encapsulation layer may contact the top surface of the inorganic insulating layer through one of the plurality of openings.

[0015] The edge of the organic encapsulation layer may be adjacent to one of the plurality of partition walls. The inorganic encapsulation layer may include: a first inorganic encapsulation layer below the organic encapsulation layer; and a second inorganic encapsulation layer on the organic encapsulation layer, the second inorganic encapsulation layer contacting the first inorganic encapsulation layer in the region between the edge of the organic encapsulation layer and the opening.

[0016] The edge portion of the second electrode may be located between the display area and one of the plurality of partition walls.

[0017] The edge portion of the second electrode can be covered by an organic encapsulation layer.

[0018] The display panel may also include multiple inorganic insulating layers on a substrate. The multiple inorganic insulating layers may include multiple grooves, each groove having a depth less than the sum of the thicknesses of the multiple inorganic insulating layers. The multiple grooves may be stacked with a cover layer comprising an organic insulating material.

[0019] The display panel may also include an auxiliary layer between the display area and one of the plurality of partition walls, the auxiliary layer being stacked with an organic encapsulation layer.

[0020] The auxiliary layer may include the same material as the first electrode.

[0021] The display panel may also include a planarization layer on the encapsulation layer, the planarization layer being stacked with a portion of the plurality of partition walls and the organic encapsulation layer.

[0022] According to one or more embodiments, an electronic device includes: a display panel including an opening region, a display region surrounding the opening region, and an intermediate region between the opening region and the display region; and an assembly stacked with the opening region, wherein the display panel includes: a substrate including an opening disposed in the opening region; a plurality of light-emitting elements disposed in the display region, each of the plurality of light-emitting elements including a first electrode, a second electrode, and an intermediate layer between the first electrode and the second electrode; a plurality of partition walls disposed in the intermediate region; and an encapsulation layer disposed on the plurality of light-emitting elements, the encapsulation layer including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. A second electrode extends from the display region toward the intermediate region, the second electrode including a first opening portion defined by an edge portion of the second electrode facing the opening. The organic layer of the intermediate layer includes: a plurality of second opening portions disposed in the region from the edge portion of the second electrode to the opening; and a plurality of organic portions separated from each other by the plurality of second opening portions, the plurality of organic portions being disposed in the first opening portions.

[0023] The top surfaces of the plurality of organic components can contact the first inorganic encapsulation layer.

[0024] In the plan view, each of the plurality of second opening portions may have a closed loop shape surrounding the opening.

[0025] At least one of the plurality of second opening portions may be arranged between two adjacent partition walls from the plurality of partition walls.

[0026] At least one of the plurality of second opening portions may be arranged between the opening and the partition wall closest to the opening from the plurality of partition walls.

[0027] At least one of the plurality of second openings may be arranged between the display area and the partition wall closest to the display area from the plurality of partition walls.

[0028] The organic layer may include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0029] The edge portion of the second electrode can be covered by an organic encapsulation layer.

[0030] The edge of the organic encapsulation layer can be positioned between the edge portion of the second electrode and the opening.

[0031] The display panel may also include multiple inorganic insulating layers on a substrate. The multiple inorganic insulating layers may include multiple grooves, each groove having a depth less than the sum of the thicknesses of the multiple inorganic insulating layers. The multiple grooves may be stacked with a cover layer comprising an organic insulating material.

[0032] The display panel may also include an auxiliary layer between the display area and one of the plurality of partition walls, the auxiliary layer comprising the same material as the first electrode.

[0033] The display panel may also include: a planarization layer, which is stacked on the encapsulation layer, along with a portion of the plurality of partition walls and the organic encapsulation layer, and includes an organic insulating material.

[0034] Components may include sensors or cameras.

[0035] According to one or more embodiments, a method of manufacturing a display panel includes: forming a pixel circuit including transistors in a display area; forming a partition wall in an intermediate region surrounded by the display area; forming a first electrode disposed in the display area, the first electrode being electrically connected to the transistors; forming a plurality of auxiliary layers in the intermediate region; forming an emitter layer on the first electrode; forming an organic layer on the first electrode and the plurality of auxiliary layers; forming a second electrode on the first electrode and the plurality of auxiliary layers; irradiating a stacked structure of the plurality of auxiliary layers, the organic layer, and the second electrode with a laser, such that the second electrode includes a single first opening portion in the intermediate region, and the organic layer includes a plurality of second opening portions disposed in the intermediate region; forming an encapsulation layer on the second electrode, the encapsulation layer including an organic encapsulation layer and an inorganic encapsulation layer; and forming an opening by removing the stacked structure in the opening region inside the intermediate region. The organic layer includes a plurality of organic portions separated from each other by the plurality of second opening portions, the plurality of organic portions being disposed in the first opening portion.

[0036] The top surfaces of the plurality of organic components can contact the inorganic encapsulation layer.

[0037] Each of the plurality of second opening portions may have a closed-loop shape in a plan view.

[0038] The partition wall includes multiple partition walls. At least one of the multiple second opening portions may be arranged between two adjacent partition walls from the multiple partition walls.

[0039] The partition wall includes a plurality of partition walls. At least one of the plurality of second opening portions may be arranged between the opening and the partition wall closest to the opening among the plurality of partition walls.

[0040] The partition wall includes multiple partition walls. At least one of the multiple second opening portions can be located between the display area and the partition wall closest to the display area among the multiple partition walls.

[0041] The plurality of auxiliary layers may include the same material as the first electrode.

[0042] The organic layer may include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0043] These and / or other aspects will become apparent and more readily understood from the detailed description of the embodiments, drawings, and claims. Attached Figure Description

[0044] The above and other aspects, features, and advantages of certain embodiments disclosed will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0045] Figure 1 This is a perspective view of an electronic device according to an embodiment;

[0046] Figure 2 It is along Figure 1 A cross-sectional view of the electronic device according to the embodiment, taken by line I-I';

[0047] Figure 3 This is a plan view of the display panel according to an embodiment;

[0048] Figure 4 It is the equivalent circuit of one of the light-emitting diodes connected to the display panel;

[0049] Figure 5 This is a plan view of a portion of the display panel according to an embodiment;

[0050] Figure 6A and Figure 6B It is along Figure 5 A cross-sectional view of the display panel according to the embodiment, taken by line V-V';

[0051] Figure 7A yes Figure 6A An enlarged sectional view of region VIIa;

[0052] Figure 7B yes Figure 6A The diagram shows the functional layers.

[0053] Figure 7C yes Figure 6A A plan view of the second electrode is shown in the figure;

[0054] Figures 8A to 8E This is a cross-sectional view illustrating the process of manufacturing a display panel according to an embodiment;

[0055] Figure 9 It is along Figure 5 A cross-sectional view of the display panel according to the embodiment, taken by line V-V';

[0056] Figure 10 It is along Figure 5A cross-sectional view of the display panel according to the embodiment, taken by line V-V';

[0057] Figure 11 It is along Figure 5 A cross-sectional view of the display panel according to the embodiment, taken by line V-V';

[0058] Figure 12 This is a cross-sectional view of a portion of the display area and a portion of the intermediate area of ​​the display panel according to an embodiment;

[0059] Figure 13 It is along Figure 5 A cross-sectional view of the display panel according to the embodiment, taken by line V-V';

[0060] Figure 14 It is along Figure 5 A cross-sectional view of the display panel according to the embodiment, taken by line V-V';

[0061] Figure 15 It is along Figure 5 A cross-sectional view of the display panel according to the embodiment, taken by line V-V';

[0062] Figure 16 It is along Figure 5 A cross-sectional view of the display panel according to the embodiment, taken by line V-V';

[0063] Figure 17 It is a cross-sectional view of a portion of the display area and a portion of the intermediate area of ​​the display panel according to an embodiment; and

[0064] Figure 18 yes Figure 17 Plan view of the protrusions and partition walls. Detailed Implementation

[0065] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, in which the same reference numerals throughout denote the same elements. In this regard, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0066] Because this disclosure allows for various variations and numerous embodiments, certain embodiments will be shown in the accompanying drawings and described in the written description. The effects and features of the disclosure, as well as methods of implementing them, will become clear from the embodiments described in more detail below with reference to the accompanying drawings. However, the disclosure is not limited to the following embodiments and can be implemented in various forms.

[0067] In the following description, embodiments will be described with reference to the accompanying drawings, in which the same reference numerals denote the same elements, and therefore their redundant descriptions will not be repeated.

[0068] While terms such as "first" and "second" can be used to describe various components, such components are not necessarily limited to these terms. These terms are used to distinguish one component from another.

[0069] Unless the context clearly indicates otherwise, the singular forms “a (kind)” and “the” as used herein are also intended to include the plural forms.

[0070] It will be understood that the terms “comprising,” “including,” and / or variations thereof, as used herein, indicate the presence of the stated feature or component, but do not preclude the addition of one or more other features or components.

[0071] It will also be understood that when a layer, region, or component is referred to as being "on" another layer, region, or component, it can be directly or indirectly on said other layer, region, or component. That is, for example, intermediate layers, regions, or components may exist.

[0072] For ease of explanation, the dimensions of elements in the accompanying drawings may be exaggerated or reduced. For example, since the dimensions and thicknesses of elements in the accompanying drawings are arbitrarily shown for ease of explanation, the disclosure is not limited thereto.

[0073] When embodiments can be implemented differently, certain process sequences may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0074] It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, that layer, region, or component may be "directly connected" to said other layer, region, or component, or may be "indirectly connected" to said other layer, region, or component with other intermediate layers, regions, or components situated between them. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, that layer, region, or component may be "directly electrically connected" to said other layer, region, or component, or may be "indirectly electrically connected" to said other layer, region, or component with other layers, regions, or components situated between them.

[0075] Furthermore, when describing embodiments of this disclosure, the use of "may" indicates "one or more embodiments of this disclosure".

[0076] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “bottom,” “top,” etc., may be used herein to describe the relationship of one element or feature as shown in the drawings to another element or feature. It will be understood that spatial relative terms are intended to include not only the orientation depicted in the drawings but also different orientations of the device in use or operation. For example, if the device in the drawings is rotated, an element described as “below” or “under” other elements or features will then be oriented “above” or “above” said other elements or features. Thus, the term “below” can encompass both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0077] As used herein, the terms “basically,” “about,” and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for inherent biases in measurements or calculations that will be recognized by one of ordinary skill in the art.

[0078] In this specification, "A and / or B" means A or B, or A and B. In this specification, "at least one of A and B" means A or B, or A and B.

[0079] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0080] Figure 1 This is a perspective view of electronic device 1 according to an embodiment.

[0081] Reference Figure 1Electronic device 1 may include a device for displaying moving or still images, and can be used as a display screen for various suitable products including televisions, laptops, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices including mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs). Additionally, electronic device 1 can be used in wearable devices including smartwatches, smartwatch phones, glasses-type displays, and head-mounted displays (HMDs). Furthermore, electronic device 1 can be used as a dashboard for automobiles, a central dashboard for automobiles, or a central information display (CID) arranged on the dashboard, an interior mirror display replacing the exterior rearview mirrors of automobiles, and a display arranged on the rear side of the front seats as an entertainment device for rear-seat occupants of automobiles. For ease of description, Figure 1 An electronic device 1 according to an embodiment is shown as, for example, a smartphone.

[0082] Electronic device 1 can have a rectangular shape in a plan view. For example, as shown... Figure 1 As shown, electronic device 1 can have a rectangular planar shape with a short side extending in the x-direction and a long side extending in the y-direction. The corner where the short side extending in the x-direction and the long side extending in the y-direction intersect can be rounded to have a certain curvature (e.g., a preset curvature), or it can be formed at a right angle. The planar shape of electronic device 1 is not limited to a rectangle, but can be formed in other polygonal, elliptical, or irregular shapes.

[0083] Electronic device 1 may include an opening region OA (or a first region) and a display region DA (or a second region) that at least partially surrounds the opening region OA. Electronic device 1 may include an intermediate region MA and a peripheral region PA (or a fourth region). The intermediate region MA may be a third region disposed between the opening region OA and the display region DA, and the peripheral region PA may be outside the display region DA. For example, the peripheral region PA may surround the display region DA.

[0084] The opening area OA can be arranged inside the display area DA. In an embodiment, as shown... Figure 1As shown, the opening region OA can be arranged on the upper left side or the upper left side of the display region DA. However, this disclosure is not limited to this, and various suitable modifications can be made. For example, the opening region OA can be arranged on or at the center of the display region DA and / or on the upper right side or the upper right side of the display region DA. In the plan view of this specification, "left," "right," "up," and "down" respectively indicate the directions when viewing the electronic device 1 from a direction perpendicular to the surface of the electronic device 1. For example, "left" indicates the (-)x direction, "right" indicates the (+)x direction, "up" indicates the (+)y direction, and "down" indicates the (-)y direction. Although in Figure 1 The illustration shows the setting of one opening region OA, but in another embodiment, multiple opening regions OA can be set.

[0085] Figure 2 It is along Figure 1 A cross-sectional view of the electronic device 1 according to the embodiment, taken by line I-I'.

[0086] Reference Figure 2 The electronic device 1 may include a display panel 10 and a component 70 disposed in an opening area 0A of the display panel 10. The display panel 10 and the component 70 may be housed in a housing HS.

[0087] The display panel 10 may include a display element layer 20, an input sensing layer 40, an optical function layer 50, and a cover window 60.

[0088] Display element layer 20 may include display elements (or light-emitting elements) that emit light to display images. The display elements may include light-emitting diodes (LEDs), such as organic light-emitting diodes (OLEDs) including an organic emitting layer. In another embodiment, the LED may be an inorganic LED comprising inorganic materials. An inorganic LED may include a PN junction diode comprising inorganic semiconductor materials. When a voltage is applied to the PN junction diode in the forward direction, holes and electrons are injected, and light of a certain color (e.g., a preset color) can be emitted by converting the energy generated due to the recombination of holes and electrons into light energy. Inorganic LEDs may have a width ranging from a few micrometers to several hundred micrometers, or a width ranging from a few micrometers to several hundred nanometers. In embodiments, the inorganic LED may be represented by a micro LED or a nanoLED. In embodiments, display element layer 20 may include a quantum dot LED. For example, the emitting layer of display element layer 20 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0089] The input sensing layer 40 can acquire external input, such as coordinate information corresponding to a touch event. The input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may be disposed on the display element layer 20. The input sensing layer 40 can sense external input using mutual capacitance and / or self-capacitance methods.

[0090] The input sensing layer 40 can be formed (e.g., directly) on the display element layer 20, or formed separately and then bonded to the display element layer 20 by an adhesive layer such as an optically clear adhesive. For example, the input sensing layer 40 can be formed sequentially after the process of forming the display element layer 20. In this case, the adhesive layer may not be arranged between the input sensing layer 40 and the display element layer 20. Although in Figure 2 The diagram shows the input sensing layer 40 disposed between the display element layer 20 and the optical functional layer 50, but in another embodiment, the input sensing layer 40 may be disposed on the optical functional layer 50.

[0091] The optical functional layer 50 may include an anti-reflective layer. The anti-reflective layer can reduce the reflectivity of light (e.g., external light) incident from the outside through the cover window 60 onto the anti-reflective layer of the display panel 10. The anti-reflective layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal-type retarder. The polarizer may include a film-type polarizer or a liquid crystal-type polarizer. The film-type polarizer may include a stretchable synthetic resin film, and the liquid crystal-type polarizer may include liquid crystal arranged in a suitable arrangement (e.g., a predetermined arrangement).

[0092] In another embodiment, the antireflective layer may include a black matrix and color filters. The color filters can be arranged to take into account the colors of segments of light emitted from the light-emitting diodes of the display element layer 20. In another embodiment, the antireflective layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, can produce destructive interference (e.g., the first reflected light and the second reflected light can destructively interfere with each other), thus reducing the reflectivity of light (e.g., external light).

[0093] The optical functional layer 50 may include a lens layer. The lens layer may improve the emission efficiency of light emitted from the display element layer 20 or reduce color deviation. The lens layer may include layers having a concave lens shape or a convex lens shape and / or include multiple layers having different refractive indices. The optical functional layer 50 may include both an anti-reflective layer and a lens layer, or may include only one of these layers.

[0094] The display panel 10 may include an opening 10H. Regarding this, in Figure 2The diagram shows that the display element layer 20, the input sensing layer 40 and the optical function layer 50 each include a first opening to a third opening (i.e., a first opening 20H, a second opening 40H and a third opening 50H), and the first opening 20H, the second opening 40H and the third opening 50H are stacked on top of each other.

[0095] The first opening 20H can pass through the top surface of the display element layer 20 to its bottom surface. The second opening 40H can pass through the top surface of the input sensing layer 40 to its bottom surface. The third opening 50H can pass through the top surface of the optical function layer 50 to its bottom surface.

[0096] The openings 10H of the display panel 10 (e.g., the first opening 20H, the second opening 40H, and the third opening 50H) can be arranged to overlap each other in the opening area OA. The dimensions (e.g., diameters) of the first opening 20H, the second opening 40H, and the third opening 50H can be the same or different from each other.

[0097] In another embodiment, at least one of the display element layer 20, the input sensing layer 40, and the optical functional layer 50 may not include an opening. For example, one or both of the display element layer 20, the input sensing layer 40, and the optical functional layer 50 may not include an opening.

[0098] Cover window 60 may be disposed on optical functional layer 50. Cover window 60 may be bonded to optical functional layer 50 by an adhesive layer (such as optically clear adhesive OCA) disposed between cover window 60 and optical functional layer 50. Cover window 60 may include glass or plastic. Plastic may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0099] Covering window 60 may include a flexible window. For example, covering window 60 may include a polyimide window or an ultra-thin glass window.

[0100] The opening area OA can be a component area (e.g., a sensor area, a camera area, a speaker area, etc.) in which components 70 for adding various suitable functions to the electronic device 1 are arranged. The components 70 can be stacked with the opening 10H of the display panel 10.

[0101] Component 70 may include electronic components. For example, component 70 may be an electronic component that uses light or sound. For example, the electronic component may include a sensor that emits and / or receives light (such as an infrared sensor), a camera that receives light to capture an image, a sensor that outputs and senses light or sound to measure distance or identify fingerprints, a small light that outputs light, and a speaker that outputs sound. Electronic components using light may use light in various suitable wavelengths such as visible light, infrared light, and ultraviolet light. The opening region OA corresponds to the transmission region through which light and / or sound output from component 70 to the outside or traveling from the outside toward component 70 can pass.

[0102] In another embodiment, where the electronic device 1 is used as a smartwatch or for a car dashboard, component 70 may be a clock hand or a needle-like component that indicates setting information (e.g., predetermined information) such as vehicle speed. In this case, with Figure 1 In contrast, the cover window 60 may include an opening arranged in the opening area OA, such that a component 70, such as a clock hand or a needle, is exposed to the outside or visible from the outside. In embodiments, even when the electronic device 1 includes a component 70 such as a speaker, the cover window 60 may include an opening corresponding to the opening area OA.

[0103] Figure 3 This is a plan view of the display panel 10 according to an embodiment. Figure 4 It is an equivalent circuit of one of the light-emitting diodes connected to the display panel 10.

[0104] Reference Figure 3 The display panel 10 may include an opening area OA, a display area DA, a central area MA, and a peripheral area PA. The display panel 10 may include a plurality of pixels P arranged in the display area DA, and displays an image by using light (e.g., red, green, or blue light) emitted from a light-emitting diode of each pixel P.

[0105] Each pixel P may include light-emitting diodes such as Figure 4 The diagram shows an organic light-emitting diode (OLED), and each OLED can be connected (e.g., electrically connected) to a pixel circuitry PC. Although in Figure 4 The diagram shows light-emitting diodes including organic light-emitting diodes (OLEDs), but in another embodiment, display panel 10 may include inorganic light-emitting diodes instead of organic light-emitting diodes (OLEDs) as described above.

[0106] The pixel circuit PC may include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst.

[0107] The second thin-film transistor T2 is a switching thin-film transistor and can be connected to the scan line SL and the data line DL. The second thin-film transistor T2 can transmit a data voltage to the first thin-film transistor T1 based on the switching voltage input through the scan line SL, which is input through the data line DL. A storage capacitor Cst is connected to the second thin-film transistor T2 and the drive voltage line PL. The storage capacitor Cst can store a voltage corresponding to the difference between the voltage transmitted from the second thin-film transistor T2 and the first power voltage ELVDD supplied to the drive voltage line PL.

[0108] The first thin-film transistor T1 is a driving thin-film transistor and can be connected to the driving voltage line PL and the storage capacitor Cst. The driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) can be controlled according to the voltage stored in the storage capacitor Cst. The OLED can emit light with a certain brightness (e.g., a preset brightness) according to the driving current. The second electrode (e.g., the cathode) of the OLED can receive a second power voltage ELVSS.

[0109] although Figure 4 The pixel circuit PC is described as including two thin-film transistors and one storage capacitor, but this disclosure is not limited thereto. The number of thin-film transistors and the number of storage capacitors can be varied in a suitable manner depending on the design of the pixel circuit PC.

[0110] Refer again Figure 3 The intermediate region MA can surround the opening region OA. The intermediate region MA is the area in which display elements such as light-emitting organic light-emitting diodes are not arranged. Signal lines that provide signals to pixels P arranged around the opening region OA can pass through the intermediate region MA. For example, as Figure 3 As shown, data lines DL and / or scan lines SL can extend across the display area DA in the y and / or x directions. Some of the data lines DL and / or scan lines SL can bypass the opening OA in the intermediate region MA along the edge of the opening 10H formed in the opening area OA of the display panel 10. For example, the data lines DL and / or scan lines SL may not overlap with the opening area OA in the plan view or in the thickness direction of the display panel 10.

[0111] Scan driver 2100, data driver 2200, first main power line, and second main power line can be arranged in the peripheral region PA. Scan driver 2100 provides a scan signal to each pixel P, data driver 2200 provides a data signal to each pixel P, and the first main power line provides a first power voltage ELVDD (e.g., see...). Figure 4 The second main power line provides a second power voltage ELVSS (e.g., see...). Figure 4Despite Figure 3 The diagram shows the data driver 2200 positioned close to one side of the substrate 100, but in another embodiment, the data driver 2200 may be positioned on a printed circuit board connected (e.g., electrically connected) to a pad (or “soldering pad”) positioned on or near one side of the display panel 10. The printed circuit board may be flexible, and a portion of the printed circuit board may be bent to be positioned below the bottom surface of the substrate 100.

[0112] Figure 5 This is a plan view of a portion of the display panel 10 according to an embodiment.

[0113] Reference Figure 5 Pixel P is arranged in the display area DA. The intermediate area MA can be arranged between the opening area OA and the display area DA. In a plan view, pixels P adjacent to the opening area OA can be separated from each other around the opening area OA (e.g., spaced apart). Figure 5 As shown in the plan view, pixels P can be vertically separated from each other (e.g., vertically spaced apart) around the opening region OA, or horizontally separated from each other (e.g., horizontally spaced apart). See reference... Figure 3 and Figure 4 As described, each pixel P uses light emitted from a light-emitting diode that is red, green, or blue; therefore, Figure 4 The positions of pixels P shown correspond to the positions of light-emitting diodes (LEDs). Therefore, when pixels P are separated from each other (e.g., spaced apart) around the opening region OA in a plan view, it can be represented that the corresponding LEDs are separated from each other (e.g., spaced apart) around the opening region OA in a plan view. For example, in a plan view, LEDs can be vertically separated from each other (e.g., vertically spaced apart) or horizontally separated from each other (e.g., horizontally spaced apart) around the opening region OA.

[0114] Signal lines from the pixel circuit supplying signals to the light-emitting diodes connected to pixel P that are adjacent to the opening region OA may bypass the opening region OA and / or the opening 10H. For example, in a plan view or in the thickness direction of the display panel 10, signal lines adjacent to the opening region OA may not overlap with the opening region OA and / or the opening 10H. Some of the data lines DL traversing the display region DA may extend in the ±y direction to provide data signals to the vertically arranged pixels P that have the opening region OA between them, and bypass the edges of the opening region OA and / or the opening 10H in the intermediate region MA. Some of the scan lines SL traversing the display region DA may extend in the ±x direction to provide scan signals to the horizontally arranged pixels P that have the opening region OA between them, and bypass the edges of the opening region OA and / or the opening 10H in the intermediate region MA.

[0115] Despite Figure 5 The diagram illustrates a scan line SL that bypasses an opening region OA and / or an opening 10H within an intermediate region MA, but this disclosure is not limited thereto. In another embodiment, the scan line SL may be separated and / or disconnected around the opening region OA and / or the opening 10H. The scan line SL to the left of the opening region OA and / or the opening 10H may be as follows: Figure 3 The scan driver 2100, which receives signals from the left side of the display area DA, can receive signals from the scan line SL, which is located to the right of the opening area OA and / or the opening 10H, and is arranged opposite to the scan driver 2100 around the display area DA.

[0116] At least one partition wall may be arranged in the intermediate region MA. At least one partition wall may be arranged closer to the opening region OA than the portion of the signal line that is bypassed. Regarding this, Figure 5 The first to third partition walls (i.e., first partition wall PW1, second partition wall PW2, and third partition wall PW3) are shown. The first partition wall PW1, second partition wall PW2, and third partition wall PW3 may be separated from each other (e.g., spaced apart) in a closed loop shape surrounding the opening region OA and / or the opening 10H.

[0117] Figure 6A and Figure 6B It is along Figure 5 A cross-sectional view of the display panel 10 according to the embodiment, taken by line V-V'. Figure 7A yes Figure 6A An enlarged sectional view of region VIIa. Figure 7B yes Figure 6A The functional layer plan shown in the figure is as follows. Figure 7C yes Figure 6A The diagram shows a plan view of the second electrode. For ease of explanation, Figure 6AThe optical functional layer 50 of the display panel 10 is omitted (for example, see...). Figure 2 ) and cover window 60 (for example, see Figure 2 The diagram shows a display element layer 20 and an input sensing layer 40 on the display element layer 20. The display element layer 20 includes light-emitting diodes disposed on the substrate 100 to correspond to the display area DA. Figure 6A and Figure 6B An example of a light-emitting diode, such as an organic light-emitting diode (OLED), is shown.

[0118] The display panel 10 may include an opening 10H in the opening region OA. The opening 10H may have the shape of a through hole (e.g., a hole penetrating through an object) that passes through the top and bottom surfaces of the display panel 10.

[0119] When the display panel 10 includes an opening 10H arranged in the opening region OA, it can be said that multiple layers of the display panel 10 include openings arranged in the opening region OA. The substrate 100 may include an opening 100H arranged in the opening region OA. The opening 100H of the substrate 100 has a through-hole shape passing through the top and bottom surfaces of the substrate 100. Similarly, the display element layer 20 and the input sensing layer 40, both layers included on the substrate 100, may each include a first opening 20H and a second opening 40H with a through-hole shape arranged in the opening region OA. For example, the first opening 20H may pass through the display element layer 20, and the second opening 40H may pass through the input sensing layer 40. In an embodiment, the first opening 20H, the second opening 40H, and the opening 100H may be stacked on top of each other in the opening region OA to form a single opening.

[0120] Reference Figure 6A and Figure 6B The display area DA, the pixel circuit PC can be arranged on the substrate 100, and the organic light-emitting diode OLED can be arranged on the pixel circuit PC.

[0121] The substrate 100 may comprise glass or a polymeric resin. For example, the polymeric resin may comprise polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 comprising the polymeric resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure comprising an organic layer and an inorganic layer, the organic layer comprising the polymeric resin.

[0122] Buffer layer 201 may be disposed on the top surface of substrate 100. Buffer layer 201 can prevent (or substantially prevent) impurities from penetrating into the semiconductor layer Act of thin-film transistor TFT. Buffer layer 201 may include inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide, and may include a single-layer structure or a multilayer structure containing inorganic insulating materials.

[0123] The pixel circuit PC can be disposed on the buffer layer 201. The pixel circuit PC includes a thin-film transistor (TFT) and a storage capacitor Cst. The thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Although Figure 6A and Figure 6B The diagram shows a top-gate thin-film transistor (TFT) in which the gate electrode GE and the gate insulating layer 203 are disposed on the semiconductor layer Act, but the thin-film transistor TFT can be a bottom-gate thin-film transistor TFT.

[0124] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, or organic semiconductor. The gate electrode GE may include a low-resistance metallic material. The gate electrode GE may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a single-layer structure or a multilayer structure comprising the above materials.

[0125] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide. The gate insulating layer 203 may include a single-layer structure or a multi-layer structure containing the above materials.

[0126] The source electrode SE and drain electrode DE can comprise materials with excellent conductivity. The source electrode SE and drain electrode DE can comprise conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can comprise single-layer or multi-layer structures comprising the above materials. In embodiments, the source electrode SE and drain electrode DE can have a multi-layer structure of titanium layers, aluminum layers, and titanium layers (Ti / Al / Ti).

[0127] The storage capacitor Cst may include a bottom electrode CE1 and a top electrode CE2 stacked on top of each other, with a first interlayer insulating layer 205 between the bottom electrode CE1 and the top electrode CE2. The storage capacitor Cst may be stacked with a thin-film transistor (TFT). Regarding this, in Figure 6A and Figure 6BThe diagram illustrates that the gate electrode GE of the thin-film transistor TFT serves as the bottom electrode CE1 of the storage capacitor Cst. In another embodiment, the storage capacitor Cst may not be stacked with the thin-film transistor TFT, and the gate electrode GE of the thin-film transistor TFT may be formed separately from the bottom electrode CE1 of the storage capacitor Cst. The storage capacitor Cst may be covered by a second interlayer insulating layer 207.

[0128] The bottom electrode CE1 and / or top electrode CE2 of the storage capacitor Cst may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may include a single-layer structure or a multi-layer structure comprising the above materials.

[0129] The first interlayer insulation layer 205 and the second interlayer insulation layer 207 may comprise inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide. Both the first interlayer insulation layer 205 and the second interlayer insulation layer 207 may comprise a single-layer structure or a multi-layer structure containing the above materials. Optionally, both the first interlayer insulation layer 205 and the second interlayer insulation layer 207 may comprise organic insulating materials. Organic insulating materials may include general-purpose polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acryloyl polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0130] The pixel circuit PC may be covered by a first intermediate insulating layer 209 (or a first via insulating layer) between the pixel circuit PC and the first electrode 221 described below. The pixel circuit PC includes a thin-film transistor (TFT) and a storage capacitor (Cst). The first intermediate insulating layer 209 may include an approximately flat top surface.

[0131] The first electrode 221 is disposed on the pixel circuit PC. The first electrode 221 can be disposed for each pixel and connected (e.g., electrically connected) to the pixel circuit PC. For example, as Figure 6A and Figure 6B As shown, a contact metal layer CM can be disposed between the thin-film transistor TFT and the first electrode 221. The contact metal layer CM can contact the thin-film transistor TFT through contact holes formed in the first intermediate insulating layer 209. The first electrode 221 can contact the contact metal layer CM through contact holes formed in the second intermediate insulating layer 211 located on the contact metal layer CM. The contact metal layer CM can include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can include a single-layer structure or a multilayer structure comprising the above materials. As an embodiment, the contact metal layer CM can include a Ti / Al / Ti multilayer structure.

[0132] The first intermediate insulating layer 209 and the second intermediate insulating layer 211 may comprise organic insulating materials containing general-purpose polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acryloyl polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. For example, the first intermediate insulating layer 209 and the second intermediate insulating layer 211 may comprise polyimide.

[0133] Despite Figure 6A and Figure 6B The diagram shows a contact metal layer CM disposed between a first intermediate insulating layer 209 and a second intermediate insulating layer 211, connecting (e.g., electrically connecting) the pixel circuit PC to the first electrode 221. However, in another embodiment, the contact metal layer CM can be omitted. In this case, the thin-film transistor (TFT) of the pixel circuit PC can be directly connected to the first electrode 221, and one of the first intermediate insulating layer 209 and the second intermediate insulating layer 211 can be omitted. For example, an interlayer insulating layer can be disposed between the pixel circuit PC and the first electrode 221, and the first electrode 221 can be connected to the thin-film transistor (TFT) of the pixel circuit PC through an interlayer insulating layer.

[0134] The first electrode 221 may be formed on the second intermediate insulating layer 211. The first electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). In another embodiment, the first electrode 221 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or mixtures thereof. In another embodiment, the first electrode 221 may also include a layer comprising ITO, IZO, ZnO, or In₂O₃ on or under the reflective layer. In embodiments, the first electrode 221 may have a three-layer structure of ITO / Ag / ITO.

[0135] An upper insulating layer 215 may be formed on the first electrode 221. The upper insulating layer 215 may include an opening exposing the top surface of the first electrode 221 and covering the edge of the first electrode 221. The upper insulating layer 215 may be a pixel defining layer defining a pixel. For example, the width of the opening exposing the top surface of the first electrode 221 may correspond to the width of the emission region through which light is emitted, or it may correspond to the width of a pixel.

[0136] The upper insulating layer 215 may include an organic insulating material. For example, the upper insulating layer 215 may include an organic insulating material comprising general polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acryloyl polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0137] Spacer 217 may be formed on upper insulating layer 215. Spacer 217 may include organic insulating material. Spacer 217 may include the same material as upper insulating layer 215 and may be formed concurrently (e.g., simultaneously) during the same masking process.

[0138] The intermediate layer 222 may include an emitting layer 222b. The emitting layer 222b may include a polymer or a low molecular weight organic material that emits light of a specific color (e.g., a preset color). The intermediate layer 222 may include a functional layer. The functional layer may include a first functional layer 222a and / or a second functional layer 222c. The first functional layer 222a may be below the emitting layer 222b, and the second functional layer 222c may be on top of the emitting layer 222b.

[0139] The first functional layer 222a may include a single-layer structure or a multi-layer structure. For example, the first functional layer 222a may include a hole injection layer (HIL) and / or a hole transport layer (HTL).

[0140] The second functional layer 222c may include a single-layer structure or a multi-layer structure. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0141] At least one organic layer 222o of the intermediate layer 222 (e.g., a first functional layer 222a and / or a second functional layer 222c) can cover the entire display area DA. Emitting layers 222b of different colors can be separated from each other (e.g., spaced apart) according to the colors of corresponding pixels in the display area DA, and the first functional layer 222a and / or the second functional layer 222c can cover the entire display area DA. The first functional layer 222a and the second functional layer 222c can be shared by multiple pixels arranged in the display area DA. Therefore, both the first functional layer 222a and the second functional layer 222c can cover multiple first electrodes 221.

[0142] The second electrode 223 may include a conductive material with low work function. For example, the second electrode 223 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Optionally, the second electrode 223 may also include a layer comprising ITO, IZO, ZnO, or In2O3 on / below the (semi-)transparent layer comprising the above materials. In an embodiment, the second electrode 223 may include Ag and Mg. The second electrode 223 may cover the entire display area DA. The second electrode 223 may be a common layer and may cover multiple first electrodes 221. The second electrode 223 and the functional layer, as the common layer covering (e.g., completely covering) the display area DA, may have different thicknesses than each other. The second electrode 223 may be thinner than the thickness of the organic layer of the intermediate layer 222 (e.g., the thickness of the stack of the first functional layer 222a and the second functional layer 222c).

[0143] An organic light-emitting diode (OLED), comprising a first electrode 221, an intermediate layer 222, and a second electrode 223, is covered by an encapsulation layer 300. The encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example... Figure 6A and Figure 6B As shown, the encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 therebetween. In another embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order can be appropriately varied.

[0144] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise at least one inorganic material such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise a single-layer structure or a multi-layer structure containing the above materials. The organic encapsulation layer 320 may comprise a polymeric material. The polymeric material may comprise acryloyl resins (such as polymethyl methacrylate and polyacrylic acid), epoxy resins, polyimides, and polyethylene. In an embodiment, the organic encapsulation layer 320 may comprise an acrylate polymer.

[0145] The material of the first inorganic encapsulation layer 310 may be different from the material of the second inorganic encapsulation layer 330. For example, the first inorganic encapsulation layer 310 may include silicon oxynitride, and the second inorganic encapsulation layer 330 may include silicon nitride. The thickness of the first inorganic encapsulation layer 310 may be different from the thickness of the second inorganic encapsulation layer 330. The thickness of the first inorganic encapsulation layer 310 may be greater than the thickness of the second inorganic encapsulation layer 330. Optionally, the thickness of the second inorganic encapsulation layer 330 may be greater than the thickness of the first inorganic encapsulation layer 310, or the same as or equal to the thickness of the first inorganic encapsulation layer 310.

[0146] The input sensing layer 40 may be disposed on the encapsulation layer 300. The input sensing layer 40 may include a first sub-insulating layer 41a and a second sub-insulating layer 41b, a first conductive layer CML1, a second insulating layer 43, a second conductive layer CML2, and a third insulating layer 45.

[0147] The first sub-insulating layer 41a and the second sub-insulating layer 41b may include inorganic insulating layers, such as inorganic insulating layers like silicon oxide, silicon nitride, and silicon oxynitride.

[0148] Both the first conductive layer CML1 and the second conductive layer CML2 may include conductive materials, such as metals. For example, both the first conductive layer CML1 and the second conductive layer CML2 may include molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a single-layer structure or a multi-layer structure containing the above materials. In an embodiment, both the first conductive layer CML1 and the second conductive layer CML2 may have a Ti / Al / Ti structure in which titanium layers, aluminum layers, and titanium layers are sequentially stacked.

[0149] Both the first conductive layer CML1 and / or the second conductive layer CML2 may include a plurality of touch electrodes configured to sense touch input. In one embodiment, the input sensing layer 40 may include touch electrodes extending in the x-direction and touch electrodes extending in the y-direction in a plan view. The touch electrodes may sense input using a mutual capacitance method and are configured as the first conductive layer CML1 and / or the second conductive layer CML2. In another embodiment, the touch electrodes may sense input using a self-capacitance method and are configured as either the first conductive layer CML1 or the second conductive layer CML2.

[0150] The second insulating layer 43 may be disposed between the first conductive layer CML1 and the second conductive layer CML2. The second insulating layer 43 may include an inorganic insulating layer such as silicon oxide, silicon nitride, and silicon oxynitride.

[0151] The third insulating layer 45 may include an organic insulating material. For example, the third insulating layer 45 may include a polymeric material. The polymeric material may be transparent. For example, the third insulating layer 45 may include silicone resins, acrylic resins, epoxy resins, polyimide, and polyethylene.

[0152] Despite Figure 6A and Figure 6B The diagram shows an input sensing layer 40 including a first conductive layer CML1 and a second conductive layer CML2, but in another embodiment, the input sensing layer 40 may include one of the first conductive layer CML1 and the second conductive layer CML2.

[0153] Next, refer to Figure 6A and Figure 6B The first intermediate insulating layer 209 and the second intermediate insulating layer 211 may extend into the intermediate region MA. For example, the first intermediate insulating layer 209 and the second intermediate insulating layer 211 may extend into the intermediate region MA and be separated from (e.g., spaced apart from) the first partition wall PW1 described below. Similarly, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 may all extend into the intermediate region MA and be separated from (e.g., spaced apart from) the first partition wall PW1. In this case, the first intermediate insulating layer 209 may extend further toward the first partition wall PW1 than the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207.

[0154] The first intermediate insulating layer 209 may cover each of the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207. The second intermediate insulating layer 211 may extend further toward the first separator wall PW1 than the first intermediate insulating layer 209.

[0155] In the intermediate region MA, the bypass portion DL-C of the data line can be arranged on the second interlayer insulation layer 207 and the first intermediate insulation layer 209. Figure 6A and Figure 6B The arrangement of the data line bypass portion DL-C on the first intermediate insulating layer 209 and the data line bypass portion DL-C on the second interlayer insulating layer 207 with the data line DL is shown above. Figure 5 The portion of the intermediate region MA described (e.g., along) Figure 5 (Corresponds to the curved portion of the opening region OA in the text).

[0156] At least one partition wall is arranged in the intermediate region MA. In the embodiment, although in Figure 6A and Figure 6BThe illustration shows three partition walls, but in another embodiment, two, four, or more partition walls may be provided. The first partition wall PW1, the second partition wall PW2, and the third partition wall PW3 may be arranged on the buffer layer 201 (e.g., directly on the buffer layer 201).

[0157] The first partition wall PW1, the second partition wall PW2, and the third partition wall PW3 can be arranged in the intermediate region MA and separated from each other (e.g., spaced apart) in the direction from the display region DA to the opening region OA. The first partition wall PW1 can be closest to the display region DA, the third partition wall PW3 can be closest to the opening region OA, and the second partition wall PW2 can be arranged between the first partition wall PW1 and the third partition wall PW3. Figure 5 As shown, the first partition wall PW1, the second partition wall PW2, and the third partition wall PW3 can all have a closed-loop shape around the opening 10H.

[0158] like Figure 6A and Figure 6B In the embodiments shown and described below, opening 100H is also formed in the substrate 100 to correspond to opening 10H of the display panel 10. Therefore, "opening area OA", "opening 10H of display panel 10" and "opening 100H of substrate 100" can be used interchangeably in this specification. For example, "opening 10H around display panel 10" can refer to opening 100H around substrate 100 and / or opening area OA.

[0159] The first partition wall PW1, the second partition wall PW2, and the third partition wall PW3 may be separated from each other (e.g., spaced apart). In embodiments, the distance between adjacent (e.g., adjacent) partition walls may be the same. For example, the distance d1 (e.g., horizontal distance) between the first partition wall PW1 and the second partition wall PW2 may be the same as or equal to the distance d2 (e.g., horizontal distance) between the second partition wall PW2 and the third partition wall PW3.

[0160] The first partition wall PW1, the second partition wall PW2, and the third partition wall PW3 may each include an insulating material. For example, the first partition wall PW1, the second partition wall PW2, and the third partition wall PW3 may include an organic insulating material, which may be formed concurrently (e.g., simultaneously) during the process of forming multiple insulating material layers arranged in the display area DA, and may include the same material as the multiple insulating material layers.

[0161] like Figure 6A and Figure 6BAs shown, the first partition wall PW1 may include a plurality of first sub-partition wall layers (or a plurality of first sub-partition walls) 1110, 1120 and 1130. The plurality of first sub-partition wall layers 1110, 1120 and 1130 may include a first-1 sub-partition wall layer 1110, a first-2 sub-partition wall layer 1120 and a first-3 sub-partition wall layer 1130 stacked (e.g., stacked sequentially).

[0162] In this embodiment, the first-1 sub-separator layer 1110 may include the same material as the second intermediate insulating layer 211. The first-2 sub-separator layer 1120 may include the same material as the upper insulating layer 215. The first-3 sub-separator layer 1130 may include the same material as the spacer 217. The first-3 sub-separator layer 1130 may include the same material as the first-2 sub-separator layer 1120, and are formed concurrently (e.g., simultaneously) during the same masking process.

[0163] like Figure 6A As shown, the second partition wall PW2 may include a plurality of second sub-partition wall layers 1210, 1220, 1230 and 1240. The plurality of second sub-partition wall layers (or a plurality of second sub-partition walls) 1210, 1220, 1230 and 1240 may include a stacked (e.g., sequentially stacked) second-1 sub-partition wall layer 1210, second-2 sub-partition wall layer 1220, second-3 sub-partition wall layer 1230 and second-4 sub-partition wall layer 1240.

[0164] In an embodiment, the second-1st sub-separator layer 1210 may include the same material as the first intermediate insulating layer 209, the second-2nd sub-separator layer 1220 may include the same material as the second intermediate insulating layer 211, the second-3rd sub-separator layer 1230 may include the same material as the upper insulating layer 215, and the second-4th sub-separator layer 1240 may include the same material as the spacer 217. The second-4th sub-separator layer 1240 and the second-3rd sub-separator layer 1230 may include the same material and are formed concurrently (e.g., simultaneously) during the same masking process.

[0165] In another embodiment, such as Figure 6BAs shown, the second partition wall PW2 may include a second-1st sub-partition wall layer 1210, a second-2nd sub-partition wall layer 1220, and a second-3rd sub-partition wall layer 1230. The second-1st sub-partition wall layer 1210 may contain the same material as the first-1st sub-partition wall layer 1110 of the first partition wall PW1 and is formed during the same masking process. The second-2nd sub-partition wall layer 1220 may contain the same material as the first-2nd sub-partition wall layer 1120 of the first partition wall PW1 and is formed during the same masking process. The second-3rd sub-partition wall layer 1230 may contain the same material as the first-3rd sub-partition wall layer 1130 of the first partition wall PW1 and is formed during the same masking process.

[0166] like Figure 6A and Figure 6B As shown, the third partition wall PW3 may include multiple sub-partition wall layers 1310 and 1320. The multiple sub-partition wall layers (or multiple sub-partition walls) 1310 and 1320 may include a third-first sub-partition wall layer 1310 and a third-second sub-partition wall layer 1320 that are stacked (e.g., stacked sequentially).

[0167] In an embodiment, the third-first sub-separator layer 1310 may include the same material as the upper insulating layer 215, and the third-second sub-separator layer 1320 may include the same material as the spacer 217. The third-second sub-separator layer 1320 may include the same material as the third-first sub-separator layer 1310 and are formed concurrently (e.g., simultaneously) during the same masking process.

[0168] The respective sublayers of the first partition wall PW1, the second partition wall PW2, and the third partition wall PW3 may be formed concurrently (e.g., simultaneously) during the same masking process that forms at least one of the first intermediate insulating layer 209, the second intermediate insulating layer 211, the upper insulating layer 215, and the spacer 217, and are not limited to the above embodiments, and may have various suitable configurations.

[0169] The height of at least one of the first partition wall PW1, the second partition wall PW2, and the third partition wall PW3 may differ from the heights of the others. For example, as Figure 6AAs shown, the height H2 of the second partition wall PW2 can be greater than the height H1 of the first partition wall PW1 and the height H3 of the third partition wall PW3. The height H1 of the first partition wall PW1 can be greater than the height H3 of the third partition wall PW3. In other words, the vertical distance from the top surface of the substrate 100 to the top surface of the second partition wall PW2 can be greater than the vertical distance from the top surface of the substrate 100 to the top surface of the first partition wall PW1. The vertical distance from the top surface of the substrate 100 to the top surface of the first partition wall PW1 can be greater than the vertical distance from the top surface of the substrate 100 to the top surface of the third partition wall PW3.

[0170] Despite Figure 6A The diagram shows that the first partition wall PW1 and the second partition wall PW2 have different heights, but in another embodiment, the first partition wall PW1 and the second partition wall PW2 may have substantially the same height. In other words, the vertical distance from the top surface of the substrate 100 to the top surface of the first partition wall PW1 may be substantially the same as or equal to the vertical distance from the top surface of the substrate 100 to the top surface of the second partition wall PW2. The vertical distance from the top surface of the substrate 100 to the top surface of the second partition wall PW2 may be equal to or less than the vertical distance from the top surface of the substrate 100 to the top surface of the spacer 217.

[0171] The one or more partitions described above (e.g., first partition PW1, second partition PW2, and third partition PW3) can control the flow of material in the organic encapsulation layer 320 during the process of forming the encapsulation layer 300. For example, the organic encapsulation layer 320 can be formed by coating a monomer in the display area DA using a process such as inkjet printing, and then curing the monomer. The partitions can control the position of the organic encapsulation layer 320 by controlling the flow of the monomer. Regarding this, in Figure 6A and Figure 6B The diagram shows that the edge 320e of the organic encapsulation layer 320 is located on or at one side of the first partition wall PW1. In another embodiment, the edge 320e of the organic encapsulation layer 320 is located on the top surface of the first partition wall PW1, so a portion of the organic encapsulation layer 320 can be superimposed on the top surface of the first partition wall PW1. In another embodiment, the edge 320e of the organic encapsulation layer 320 can be located on or at one side of the second partition wall PW2. In this case, a portion of the organic encapsulation layer 320 can be superimposed on the top surface of the first partition wall PW1. The position of the organic encapsulation layer 320 can be determined by capturing an image of the display panel 10 including the organic encapsulation layer 320. The display panel 10 according to the embodiment includes a plurality of partition walls, which can be used to monitor the position of the organic encapsulation layer 320, for example, the position of the edge 320e of the organic encapsulation layer 320.

[0172] The edge 320e of the organic encapsulation layer 320 is located on one side of a partition wall (e.g., the first partition wall PW1), so the second inorganic encapsulation layer 330 can contact (e.g., directly contact) the first inorganic encapsulation layer 310 in the intermediate region MA. For example, the first inorganic encapsulation layer 310 can contact (e.g., directly contact) the second inorganic encapsulation layer 330 in the region between the edge 320e of the organic encapsulation layer 320 and the opening 10H of the display panel 10. In the embodiment, in Figure 6A and Figure 6B The diagram shows that the first inorganic encapsulation layer 310 contacts (e.g., directly contacts) the second inorganic encapsulation layer 330 in the area between the first partition wall PW1 and the opening 10H of the display panel 10.

[0173] The insulating layers of the input sensing layer 40 (e.g., the first sub-insulating layer 41a and the second sub-insulating layer 41b, the second insulating layer 43 and the third insulating layer 45) can extend to cover the intermediate region MA.

[0174] A planarizing insulating layer 47 (or planarization layer) may cover the intermediate region MA. The planarizing insulating layer 47 may be arranged in the intermediate region MA to have a width ranging from the first edge 47E1 to the second edge 47E2. Thus, in a plan view, the planarizing insulating layer 47 may have a closed-loop shape (e.g., annular shape) surrounding the opening 10H.

[0175] The first edge 47E1 of the planarization insulating layer 47 may face the opening 10H of the display panel 10, and the second edge 47E2 of the planarization insulating layer 47 may be adjacent to the display area DA. A portion of the planarization insulating layer 47 adjacent to the display area DA may be stacked with a portion of the organic encapsulation layer 320, simultaneously covering the edge 320e of the organic encapsulation layer 320. A second inorganic encapsulation layer 330 and a first sub-insulating layer 41a may be disposed between the portion of the planarization insulating layer 47 adjacent to the display area DA and the portion of the organic encapsulation layer 320.

[0176] The first sub-insulating layer 41a may contact (e.g., directly contact) the second sub-insulating layer 41b in the display area DA. Conversely, the first sub-insulating layer 41a may be separated from the second sub-insulating layer 41b in the thickness direction (e.g., z-direction) in the intermediate area MA due to the planarization insulating layer 47 disposed between the first sub-insulating layer 41a and the second sub-insulating layer 41b.

[0177] A second electrode 223 covering (e.g., completely covering) the display area DA may extend to the intermediate area MA. An edge portion 223ep of the second electrode 223 may be disposed between the display area DA and one of the partition walls. In an embodiment, in Figure 6A and Figure 6BThe diagram shows the edge portion 223ep of the second electrode 223 disposed between the display area DA and the first partition wall PW1. Here, the edge portion 223ep of the second electrode 223 is the portion of the second electrode 223 closest to the opening 10H. In an embodiment, a layer corresponding to the second electrode 223 may not exist in the region from the edge portion 223ep of the second electrode 223 to the opening 10H. In other words, a layer having the same material and structure as the second electrode 223 may not exist in the region from the edge portion 223ep of the second electrode 223 to the opening 10H. Regarding this, in Figure 6A , Figure 6B and Figure 7C The diagram shows a second electrode 223 including a first opening 223oh surrounded / defined by an edge portion 223ep. (See diagram for reference.) Figure 7C As shown, the first opening portion 223oh of the second electrode 223 can be superimposed with the opening region OA and the portion of the intermediate region MA near the opening region OA.

[0178] The edge portion 223ep of the second electrode 223 may be covered by an organic layer (e.g., organic encapsulation layer 320). The second electrode 223 can be formed by forming a second electrode material layer and then removing a portion of the second electrode material layer disposed in the intermediate region MA, the second electrode material layer covering (e.g., completely covering) the display region DA and the intermediate region MA. A portion of the second electrode material layer can be removed by a laser lift-off process. The edge portion 223ep of the second electrode 223 may have an irregular shape due to the laser. For example, as... Figure 7A As shown, the edge portion 223ep of the second electrode 223 may include burrs formed by a laser ablation process. The edge portion 223ep of the second electrode 223 may extend in an inclined direction away from the top surface of the substrate 100. In an embodiment, the edge portion 223ep of the second electrode 223 may be inclined in the direction extending away from the substrate 100. The cross-section of the edge portion 223ep of the second electrode 223 may have irregular non-uniformity.

[0179] The thickness of the first inorganic encapsulation layer 310 on the second electrode 223 can be determined by the shape of the edge portion 223ep of the second electrode 223, rather than being constant. For example, as Figure 7A As shown, the first inorganic encapsulation layer 310 may include a top surface that protrudes upward along the shape of the edge portion 223ep of the second electrode 223.

[0180] Although the first inorganic encapsulation layer 310 has excellent step coverage, the edge portion 223ep of the second electrode 223 beneath the first inorganic encapsulation layer 310 has an irregular shape. Therefore, the first inorganic encapsulation layer 310 may locally include portions with low density and / or small thickness. In this case, cracks may appear in the first inorganic encapsulation layer 310 and propagate to the adjacent area (e.g., cracks may grow in size and / or propagate to the surrounding area). However, according to the embodiment, the organic encapsulation layer 320 covers the edge portion 223ep of the second electrode 223, thus preventing or substantially preventing the cracking problem.

[0181] At least one organic layer 222o (hereinafter referred to as an organic layer) (e.g., a first functional layer 222a and / or a second functional layer 222c) included in the intermediate layer 222 may be disconnected in the intermediate region MA. In other words, a portion of the organic layer 222o may be removed from the intermediate region MA, and therefore, the organic layer 222o may include a second opening portion 222oh disposed in the intermediate region MA. Regarding this, Figure 6A and Figure 6B A plurality of second opening portions 222oh (e.g., a plurality of second opening portions 222oh corresponding to a plurality of second openings) are shown in the intermediate region MA. The organic layer 222o may include a first functional layer 222a and a second functional layer 222c. An opening portion 222ah of the first functional layer 222a may be superimposed with an opening portion 222ch of the second functional layer 222c to form a second opening portion 222oh. The opening portions 222ah of the first functional layer 222a and 222ch of the second functional layer 222c may be formed by removing a portion of the first functional layer 222a and the second functional layer 222c. Due to the opening portions 222ah and 222ch, the first functional layer 222a and the second functional layer 222c may be discontinuous in the intermediate region MA (e.g., the continuity of the layers may be interrupted by the corresponding opening portions).

[0182] An insulating layer (e.g., buffer layer 201) disposed under the second opening 222oh can be exposed through the second opening 222oh. The first inorganic encapsulation layer 310 can contact (e.g., directly contact) the buffer layer 201 through the second opening 222oh. The buffer layer 201 may comprise an inorganic insulating material. The contact between the first inorganic encapsulation layer 310 and the buffer layer 201 can locally block or reduce the propagation of moisture.

[0183] At least one organic layer 222o of the intermediate layer 222 covers (e.g., completely covers) the display area DA, thus potentially providing a path for moisture that might be introduced into the at least one organic layer 222o of the intermediate layer 222 through the opening 10H of the display panel 10. Conversely, according to an embodiment, the organic layer 222o includes a second opening portion 222oh disposed in the intermediate area MA, thus preventing or reducing the travel of moisture through the organic layer 222o.

[0184] The second opening portions 222oh of the organic layer 222o may be separated from each other (e.g., spaced apart) in a region from the edge portion 223ep of the second electrode 223 to the opening 10H. At least one of the second opening portions 222oh may be arranged between adjacent (e.g., adjacent) partition walls, between the third partition wall PW3 and the opening 10H, and / or between the first partition wall PW1 and the display area DA.

[0185] In an embodiment, Figure 6A and Figure 6B The second opening 222oh between the first partition wall PW1 and the display area DA, the second opening 222oh between the first partition wall PW1 and the second partition wall PW2, the second opening 222oh between the second partition wall PW2 and the third partition wall PW3, and the second opening 222oh between the third partition wall PW3 and the opening 10H are shown.

[0186] Organic layer 222o may include organic portions 222op that are separated from each other through a second opening 222oh. Organic portions 222op may be separated from each other (e.g., spaced apart) in an intermediate region MA. Organic portions 222op may include, for example, portions 222ap of a first functional layer 222a and / or portions 222cp of a second functional layer 222c.

[0187] When the second opening 222oh is formed between adjacent (e.g., adjacent) partition walls, each of the first partition wall PW1, the second partition wall PW2, and the third partition wall PW3 may be stacked with or covered by the organic portion 222op. The organic portion 222op is not covered by the second electrode 223 and may be covered (e.g., directly covered) by a layer formed on the second electrode 223 (e.g., the first inorganic encapsulation layer 310). In other words, the first inorganic encapsulation layer 310 may contact (e.g., directly contact) the top surface of the organic portion 222op.

[0188] In the plan view, each of the second opening portions 222oh may surround the opening 10H. For example, each of the second opening portions 222oh may extend along the edge of the opening 10H and have a closed loop shape surrounding (e.g., completely surrounding) the opening 10H in the plan view.

[0189] The second opening 222oh can be separated from each other (e.g., spaced apart). Therefore, as Figure 7B As shown, the organic portions 222op, which are separated from each other by the second opening portion 222oh, can also have a closed loop shape in the plan view surrounding (e.g., completely surrounding) the opening region OA.

[0190] Reference Figure 6A , Figure 6B , Figure 7B and Figure 7C The organic layer 222o may include a plurality of second opening portions 222oh. Conversely, the second electrode 223 may include a single first opening portion 223oh. The single first opening portion 223oh of the second electrode 223 may be stacked with the plurality of second opening portions 222oh (e.g., in a plan view or in the thickness direction of the display panel 10). In other words, organic portions 222op, separated from each other by the second opening portions 222oh, may be arranged inside the single first opening portion 223oh.

[0191] Figures 8A to 8E This is a cross-sectional view illustrating the process of manufacturing the display panel 10 according to an embodiment.

[0192] First, refer to Figure 8A A pixel circuit PC, a first electrode 221 on the pixel circuit PC, and at least one partition wall are formed on the substrate 100. Before forming the pixel circuit PC, a buffer layer 201 may be formed to cover (e.g., completely cover) the top surface of the substrate 100. Then, (e.g., sequentially formed) a semiconductor layer of a thin-film transistor, a gate insulating layer 203, a gate electrode of the thin-film transistor, a bottom electrode of a storage capacitor, a first interlayer insulating layer 205, a top electrode of the storage capacitor, a second interlayer insulating layer 207, a source electrode, a drain electrode, a first intermediate insulating layer 209, a contact metal layer, and a second intermediate insulating layer 211 may be formed.

[0193] The buffer layer 201 may cover the entire substrate 100. Conversely, at least a portion of at least one insulating layer on the buffer layer 201 may be removed. For example, each of the gate insulating layer 203, the first interlayer insulating layer 205, the second interlayer insulating layer 207, the first intermediate insulating layer 209, and the second intermediate insulating layer 211 formed in the portion adjacent to the opening region OA of the opening region OA and the intermediate region MA may be removed. Thus, as Figure 8AAs shown, the edges 203e, 205e, and 207e of the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 facing the opening region OA and / or adjacent to the opening region OA can be separated from the first partition wall PW1 (e.g., spaced apart) and covered by the first intermediate insulating layer 209. Similarly, the edges 209e and 211e of the first intermediate insulating layer 209 and the second intermediate insulating layer 211 facing the opening region OA and / or adjacent to the opening region OA can be separated from the first partition wall PW1 (e.g., spaced apart). The edge 209e of the first intermediate insulating layer 209 can be covered by the second intermediate insulating layer 211.

[0194] A first electrode 221 may be formed on the second intermediate insulating layer 211. An upper insulating layer 215 and a spacer 217 may be formed on the first electrode 221. When the first electrode 221 is formed in the display area DA, a plurality of auxiliary layers 1200 may be formed in the intermediate area MA. When an insulating material layer including an organic insulating material is formed in the display area DA, at least one partition wall may be formed in the intermediate area MA.

[0195] The auxiliary layer 1200 may include the same material as the first electrode 221 and is formed concurrently (e.g., simultaneously) during the same process that forms the first electrode 221. For example, the auxiliary layer 1200 may include metals and transparent conductive oxides, such as ITO / Ag / ITO.

[0196] At least one partition wall (e.g., first partition wall PW1, second partition wall PW2, and third partition wall PW3) may each have a cross-sectional shape in which the bottom width is greater than the top width. First partition wall PW1, second partition wall PW2, and third partition wall PW3 may each include multiple sublayers. Each sublayer may be formed concurrently (e.g., simultaneously) during the process of forming the first intermediate insulating layer 209, the second intermediate insulating layer 211, the upper insulating layer 215, and / or the spacer 217. The materials of the sublayers of first partition wall PW1, second partition wall PW2, and third partition wall PW3 are the same as those referenced above. Figure 6A and Figure 6B The materials described are the same.

[0197] Auxiliary layers 1200 can be arranged in the intermediate region MA and / or the open region OA. For example, an auxiliary layer 1200 can be arranged between the display region DA and the first partition wall PW1, an auxiliary layer 1200 can be arranged between adjacent (e.g., adjacent) first partition walls PW1 and second partition walls PW2, and an auxiliary layer 1200 can be arranged between adjacent (e.g., adjacent) second partition walls PW2 and third partition walls PW3. The horizontal distance between the third partition wall PW3 and the open region OA can be greater than the horizontal distance between adjacent (e.g., adjacent) partition walls. Therefore, multiple auxiliary layers 1200 can be arranged between the third partition wall PW3 and the open region OA. Auxiliary layers 1200 can also be arranged in the open region OA. The widths of the auxiliary layers 1200 can be different from each other or can be the same.

[0198] Then, as Figure 8B As shown, a first functional layer 222a, an emission layer 222b, a second functional layer 222c, and a second electrode 223 can be formed on the first electrode 221. The emission layer 222b is formed to correspond to the first electrode 221, which is separated from each other (e.g., spaced apart) in the display area DA. Conversely, as... Figure 8B As shown, the organic layer 222o (e.g., the first functional layer 222a and / or the second functional layer 222c) and the second electrode 223, which serve as a common layer, can be formed to cover the entire substrate 100.

[0199] With the organic layer 222o and the second electrode 223 covering the entire top surface of the substrate 100, cracks may occur or moisture may be introduced into the light-emitting diode. Therefore, a portion of the organic layer 222o and a portion of the second electrode 223 can be removed from the intermediate region MA. For this purpose, the substrate 100 can be irradiated with a laser. The substrate 100 can be irradiated with a laser in a direction from the back side 100b of the substrate 100 to the top surface 100t of the substrate 100. The power of the laser can be set based on the band gap of the second electrode 223. Laser irradiation can be provided once or multiple times. In the case of multiple laser irradiations, the type, power, and / or irradiation range (or laser beam size) of the laser can be changed. A portion of the second electrode 223 disposed in the intermediate region MA can be removed by laser (e.g., laser ablation process).

[0200] During the laser ablation process, the auxiliary layer 1200 can absorb laser light and be heated to a certain temperature (e.g., a preset temperature). The portion of the organic layer 222o corresponding to the auxiliary layer 1200 (e.g., the portions of the first functional layer 222a and the second functional layer 222c corresponding to the auxiliary layer 1200) can be removed. The auxiliary layer 1200 is a sacrificial layer. After removing a portion of the organic layer 222o (e.g., after forming the second opening 222oh in the organic layer 222o), it can be as follows... Figure 8C The auxiliary layer 1200 is removed as shown in the figure.

[0201] exist Figure 8C The diagram illustrates the arrangement of an edge portion 223ep of a second electrode 223 between a display region DA and one of a partition wall (e.g., a first partition wall PW1) using a laser lift-off process. The organic layer 222o may include a second opening portion 222oh disposed in the intermediate region MA and the opening region OA, and includes organic portions 222op separated from each other by the second opening portion 222oh. In the case where the organic layer 222o includes a first functional layer 222a and a second functional layer 222c, the second opening portion 222oh of the organic layer 222o may include an opening portion 222ah of the first functional layer 222a and an opening portion 222ch of the second functional layer 222c. The organic portion 222op of the organic layer 222o may include a portion 222ap of the first functional layer 222a and a portion 222cp of the second functional layer 222c.

[0202] Despite Figure 8C The diagram shows the edge portion 223ep of the second electrode 223 arranged between the display area DA and the first partition wall PW1, and the second opening portion 222oh arranged in the region from the edge portion 223ep of the second electrode 223 to the opening region OA, but this disclosure is not limited thereto. The positions of the first opening portion 223oh of the second electrode 223, the second opening portion 222oh of the organic layer 222o, and the edge portion 223ep of the second electrode 223 can be varied in a suitable manner depending on the number of auxiliary layers 1200, the position of the auxiliary layers 1200, and / or the irradiation range of the laser. In another embodiment, the edge portion 223ep of the second electrode 223 can be arranged between the first partition wall PW1 and the second partition wall PW2, between the second partition wall PW2 and the third partition wall PW3, or between the third partition wall PW3 and the opening region OA. The second opening portion 222oh of the organic layer 222o can be arranged in the region from the edge portion 223ep of the second electrode 223 to the opening region OA.

[0203] Reference Figure 8D A reference can be formed on it. Figure 8CAn encapsulation layer 300 and an input sensing layer 40 are formed on a substrate 100 of the described structure.

[0204] The first inorganic encapsulation layer 310 of the encapsulation layer 300 can be formed to cover the entire substrate 100. The first inorganic encapsulation layer 310 can be formed by chemical vapor deposition. (Refer to reference...) Figure 8C The described structure removes the auxiliary layer 1200 between adjacent (e.g., adjacent) partition walls, so that the first inorganic encapsulation layer 310 can contact (e.g., directly contact) the inorganic insulating layer underneath, such as the buffer layer 201.

[0205] The first inorganic encapsulation layer 310 has relatively excellent step coverage, and therefore can cover the edge portion 223ep of the second electrode 223 that is tilted and floating in the upward direction. In an embodiment, the edge portion 223ep of the second electrode 223 may be tilted in a direction extending away from the substrate 100. The edge portion 223ep of the second electrode 223 is a burr and has an irregular shape, so even if the first inorganic encapsulation layer 310 covers the edge portion 223ep of the second electrode 223, the possibility of cracking may be relatively high. However, the edge portion 223ep of the second electrode 223 is covered by the organic encapsulation layer 320, so the above problems can be reduced, minimized, or prevented.

[0206] The organic encapsulation layer 320 can cover particles retained on the second electrode 223 from particles that appear during the laser lift-off process. As described above, the positions of the first opening portion 223oh of the second electrode 223, the second opening portion 222oh of the organic layer 222o, and the edge portion 223ep of the second electrode 223 can be varied in a suitable manner depending on the number of auxiliary layers 1200, the position of the auxiliary layers 1200, and / or the irradiation range of the laser. In another embodiment, although as... Figure 8DAs shown, the edge 320e of the organic encapsulation layer 320 is disposed on or at one side of the first partition wall PW1, but the edge portion 223ep of the second electrode 223 can be disposed between the third partition wall PW3 and the opening region OA. In this case, the edge portion 223ep of the second electrode 223 can be disposed closer to the opening region OA than the edge 320e of the organic encapsulation layer 320 is distant from the opening region OA. Particles that appear during the laser lift-off process may remain on the second electrode 223. When the edge portion 223ep of the second electrode 223 extends further toward the opening region OA than the edge 320e of the organic encapsulation layer 320 extends to the opening region OA, the particles retained on the portion of the second electrode 223 not covered by the organic encapsulation layer 320 may not only degrade the quality of the first inorganic encapsulation layer 310, but may even degrade the quality of the layer of the second inorganic encapsulation layer 330 that partially contacts (e.g., directly contacts) the first inorganic encapsulation layer 310. Therefore, as Figure 8D As shown, compared to the distance between the edge 320e of the organic encapsulation layer 320 and the display area DA, the edge portion 223ep of the second electrode 223 is arranged closer to the display area DA, and the top surface of the second electrode 223 is covered (e.g., completely covered) by the organic encapsulation layer 320 in the intermediate region MA. In other words, the edge 320e of the organic encapsulation layer 320 can be arranged between the edge portion 223ep of the second electrode 223 and the opening 10H.

[0207] The organic encapsulation layer 320 can be formed by coating the monomer using methods such as inkjet printing and then curing it. The organic encapsulation layer 320 may include a resin formed during the curing of the monomer. The material of the organic encapsulation layer 320 is the same as described above.

[0208] A second inorganic encapsulation layer 330 is formed on the organic encapsulation layer 320. Similar to the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 330 can be formed by chemical vapor deposition. The second inorganic encapsulation layer 330 can contact (e.g., directly contact) the first inorganic encapsulation layer 310 in the intermediate region MA, where a portion of the organic encapsulation layer 320 is not formed, and the opening region OA. For example, the second inorganic encapsulation layer 330 can contact (e.g., directly contact) the first inorganic encapsulation layer 310 between the edge 320e of the organic encapsulation layer 320 and the opening region OA, thus further reducing or preventing the possibility of moisture transmission.

[0209] Then, a first sub-insulating layer 41a can be formed, and a planarization insulating layer 47 can be formed on the first sub-insulating layer 41a. The planarization insulating layer 47 can be formed in the intermediate region MA and the opening region OA. The organic encapsulation layer 320 is arranged to cover the display region DA. Conversely, the planarization insulating layer 47 may not cover the display region DA. Figure 8D During the manufacturing process shown, the planarization insulation layer 47 may be present only in the intermediate region MA and the opening region OA.

[0210] Next, a second sub-insulating layer 41b is formed, and a first conductive layer CML1, a second insulating layer 43, a second conductive layer CML2, and a third insulating layer 45 can be formed (e.g., sequentially).

[0211] Then, when the opening area OA is cut along the cutting line SCL using methods such as laser cutting, as... Figure 8E As shown, the display panel 10 may include an opening 10H formed in the opening region OA.

[0212] Figure 9 It is along Figure 5 A cross-sectional view of the display panel 10 according to the embodiment, taken along line V-V'. (Refer to...) Figure 9 The specific shape of the partition wall is the same as the one mentioned above. Figures 6A to 8E The shapes of the described embodiments differ. Specific features of other constructions besides the shape of the partition walls are also referenced. Figure 6A and Figure 6B The specific features of the described structures are the same or similar.

[0213] Although at least one partition wall (e.g., first partition wall PW1, second partition wall PW2, and third partition wall PW3) has a shape in which its lower width (e.g., bottom width) is greater than its top width, however... Figure 9 As shown, a step difference may exist between the top and bottom of the partition wall. For example, as... Figure 9 As shown, the first partition wall PW1 and / or the second partition wall PW2 may include a width smaller than the top width and the bottom width (e.g., the bottom width) at the portion between the top and the bottom. In another embodiment, the first partition wall PW1, the second partition wall PW2, and the third partition wall PW3 have a width that gradually increases from the top to the bottom.

[0214] The first sub-partition wall layer 1110 and the first sub-partition wall layer 1120 of the first sub-partition wall layer PW1 form the bottom of the first partition wall PW1 with a relatively large width. The first sub-partition wall layer 1130 can form the top of the first partition wall PW1 with a relatively small width. In a cross-sectional view, the bottom and top of the first partition wall PW1 may have a step difference. For example, the first partition wall PW1 may not have a shape in which the width gradually decreases from the bottom to the top, but may have a shape in which the width significantly decreases at the step difference.

[0215] The second sub-separator layer 1210 and the second sub-separator layer 1220 of the second sub-separator layer of the second separator PW2 can form the bottom of the second separator PW2 with a relatively large width. The second sub-separator layer 1230 and the second sub-separator layer 1240 can form the top of the second separator PW2 with a relatively small width. Similar to the first separator PW1, the bottom and top of the second separator PW2 can have a step difference in cross-sectional view.

[0216] Unlike the first partition wall PW1 and the second partition wall PW2, the third-1st sub-partition wall layer 1310 and the third-2nd sub-partition wall layer 1320 in the third sub-partition wall layer of the third partition wall PW3 may not have a step difference.

[0217] Figure 10 It is along Figure 5 A cross-sectional view of the display panel 10 according to the embodiment, taken by line V-V'.

[0218] Based on the above reference Figures 6A to 9 In the described embodiment, although it is shown that the auxiliary layer 1200 is completely removed during the manufacturing process of the display panel 10, at least one auxiliary layer 1200 may remain on the substrate 100. Regarding this, in Figure 10 The diagram shows an auxiliary layer 1200 disposed between the display area DA and the first partition wall PW1. The auxiliary layer 1200 disposed between the display area DA and the first partition wall PW1 may be covered by an organic encapsulation layer 320.

[0219] The auxiliary layer 1200 can be used to track or monitor the position of the organic encapsulation layer 320. In an embodiment, the position of the monomer and / or organic encapsulation layer 320 can be determined by microscopic images (e.g., images provided by a microscope). When the auxiliary layer 1200, including the reflective metal, is positioned closer to the display area DA than the first separator wall PW1, light is reflected from the auxiliary layer 1200, thus the position of the monomer and / or organic encapsulation layer 320 can be easily tracked.

[0220] like Figure 10 As shown, the edge portion 223ep of the second electrode 223 may be separated from the auxiliary layer 1200 (e.g., spaced apart). For example, the auxiliary layer 1200 may be disposed between the edge portion 223ep of the second electrode 223 and the first partition wall PW1. In another embodiment, the edge portion 223ep of the second electrode 223 may be stacked with the auxiliary layer 1200 depending on the laser specifications and / or the number of laser irradiations. For example, the edge portion 223ep of the second electrode 223 may be disposed on the auxiliary layer 1200 and may be stacked with the auxiliary layer 1200.

[0221] Based on the above reference Figures 6A to 9 The described embodiment, although showing a second opening 222oh of the organic layer 222o arranged between the display area DA and the first partition wall PW1, in another embodiment, in Figure 10 The diagram shows a functional layer covering the entire display area DA extending into the intermediate area MA to traverse the first partition wall PW1. The organic layer 222o (e.g., the first functional layer 222a and the second functional layer 222c) may not include the opening between the display area DA and the first partition wall PW1, and the auxiliary layer 1200 may be covered by the first functional layer 222a and the second functional layer 222c.

[0222] Figure 11 It is along Figure 5 A cross-sectional view of the display panel 10 according to the embodiment, taken by line V-V'.

[0223] according to Figure 11 Examples, such as those mentioned above Figure 10 As described, the organic layer 222o arranged in the display area DA can continuously extend to the first partition wall PW1 of the intermediate area MA. Figure 10 The implementation methods differ, in Figure 11 The diagram shows that there is no auxiliary layer 1200 between the display area DA and the first partition wall PW1. When formed from the above reference... Figures 8A to 8E In the process of manufacturing the display panel 10, the auxiliary layer 1200 may not be formed between the display area DA and the first partition wall PW1. Therefore, it is possible to form a layer with... Figure 11 The structure shown is the display panel 10.

[0224] Figure 12 This is a cross-sectional view of the display panel 10 according to an embodiment. Figure 12 This shows a portion of the display area DA and a portion of the intermediate area MA.

[0225] Reference Figure 12 The second electrode 223 of the display area DA extends into the intermediate area MA, and the edge portion 223ep of the second electrode 223 can be arranged between two adjacent (e.g., adjacent) partition walls. Figure 12 As shown, the second electrode 223 can extend toward the opening 10H to pass through the first partition wall PW1, and the edge portion 223ep of the second electrode 223 can be arranged between the first partition wall PW1 and the second partition wall PW2.

[0226] The organic layer 222o (e.g., the first functional layer 222a and the second functional layer 222c) includes a second opening portion 222oh. The second opening portion 222oh may be arranged in a region extending from the edge portion 223ep of the second electrode 223 to the opening 10H.

[0227] An encapsulation layer 300 is formed on the substrate 100. As described above, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 of the encapsulation layer 300 can be formed continuously to cover the display area DA and the intermediate area MA. The organic encapsulation layer 320 can cover the edge portion 223ep of the second electrode 223. Regarding this, in Figure 12 The diagram shows an organic encapsulation layer 320 positioned close to the second partition wall PW2, while covering the first partition wall PW1. The edge 320e of the organic encapsulation layer 320 can be as follows: Figure 12 The arrangement shown is on one side or at one side of the second partition wall PW2, or in another embodiment, it is arranged on the top surface of the second partition wall PW2.

[0228] Figure 13 and Figure 14 It is along Figure 5 A cross-sectional view of the display panel 10 according to the embodiment, taken by line V-V'.

[0229] Based on the above reference Figures 6A to 12 The described embodiment shows that the edges 203e, 205e, and 207e of the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 are arranged closer to the display area DA than the distance of the first partition wall PW1 from the display area DA. In another embodiment, referring to... Figure 13 and Figure 14 Similar to the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and / or the second interlayer insulating layer 207 can cover the entire top surface of the substrate 100. For example, the edges 203e, 205e, and 207e of the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 can form the side surface of the display panel 10 that forms the opening 10H.

[0230] As described above, the organic layer 222o may include a second opening 222oh, through which the second interlayer insulating layer 207 may be exposed. The first inorganic encapsulation layer 310 may contact (e.g., directly contact) the top surface of the second interlayer insulating layer 207 through the second opening 222oh. The second interlayer insulating layer 207 may include an inorganic insulating material. In this case, the contact between the second interlayer insulating layer 207 and the first inorganic encapsulation layer 310 may block or reduce the propagation of moisture.

[0231] Despite Figure 13 and Figure 14 The diagram shows the auxiliary layer 1200 and the organic encapsulation layer 320 stacked together, but the display panel 10 can be as follows: Figure 11 The diagram does not include auxiliary layer 1200. Although in Figure 13 and Figure 14 The diagram shows the edge 320e of the organic encapsulation layer 320 disposed on or at one side of the first partition wall PW1. However, in another embodiment, the edge 320e of the organic encapsulation layer 320 may be disposed on the top surface of the first partition wall PW1, on or at one side of the second partition wall PW2, or on the top surface of the second partition wall PW2. Various suitable modifications can be made according to one or more embodiments.

[0232] In an embodiment, such as Figure 14 As shown, the groove G can be formed in the region adjacent to the opening 10H. The groove G can be formed in an inorganic insulating structure, for example, a stacked structure including a gate insulating layer 203, a first interlayer insulating layer 205, and a second interlayer insulating layer 207. In one embodiment, the depth of the groove G can be smaller than the sum of the thicknesses of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207. In another embodiment, the groove G can be smaller than the sum of the thicknesses of the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207. In this case, the bottom surface of the groove G can be disposed on the top surface of the buffer layer 201. For example, as... Figure 14 As shown, the groove can extend partially into the buffer layer 201.

[0233] Cracks are more likely to occur in inorganic insulating materials than in organic insulating materials. Therefore, as the contact area of ​​the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207, which include inorganic insulating materials, increases, there is a possibility that cracks may occur and propagate to surrounding areas. Conversely, by forming a recess G and a capping layer 1400 comprising organic insulating material within the recess G, cracking problems can be prevented or reduced. In a view perpendicular to the substrate 100 (e.g., the surface of the substrate 100) (e.g., in a plan view), the recess G and the capping layer 1400 may have a closed-loop shape surrounding the opening region OA and the opening 10H.

[0234] Figure 15 It is along Figure 5 A cross-sectional view of the display panel 10 according to the embodiment, taken by line V-V'.

[0235] Based on the above reference Figures 6A to 14 The described embodiment, although showing three partition walls, may have different partitions in another embodiment, such as... Figure 15 As shown, the display panel 10 may include more than three partition walls.

[0236] For example, the first partition wall PW1, the second partition wall PW2, and a plurality of third partition walls PW31, PW32, ..., PW3n can be arranged and separated from each other (e.g., spaced apart) in the direction from the display area DA to the opening area OA.

[0237] The first partition wall PW1, the second partition wall PW2, and the plurality of third partition walls PW31, PW32, ..., PW3n may be separated from each other (e.g., spaced apart). The distance d1 between adjacent (e.g., adjacent) first partition walls PW1 and second partition walls PW2 may be different from the distance d2 between adjacent (e.g., adjacent) second partition walls PW2 and third-first partition walls PW31. For example, the distance d1 between the first partition wall PW1 and the second partition wall PW2 may be greater than the distance d2 between the second partition wall PW2 and the third-first partition wall PW31. The distance d3 between adjacent (e.g., adjacent) partition walls among the plurality of third partition walls PW31, PW32, ..., PW3n may be the same as or equal to the distance d2 between the second partition wall PW2 and the third-first partition wall PW31.

[0238] Figure 16 It is along Figure 5 A cross-sectional view of the display panel 10 according to the embodiment, taken by line V-V'.

[0239] Based on the above reference Figures 6A to 15 The described embodiment shows that the planarization insulating layer 47 covers the area of ​​the intermediate region MA that is not covered by the organic encapsulation layer 320, and the planarization insulating layer 47 is located only in the intermediate region MA; however, this disclosure is not limited thereto.

[0240] In another embodiment, such as Figure 16 As shown, the input sensing layer 40 may include a first insulating layer 41, a first conductive layer CML1, a second insulating layer 43, a second conductive layer CML2, and a third insulating layer 45. The third insulating layer 45, comprising an organic insulating material, from the insulating layers of the input sensing layer 40 can cover the area of ​​the intermediate region MA not covered by the organic encapsulation layer 320. With the above structure, unlike the embodiment described above, the planarization insulating layer 47, which is only disposed in the intermediate region MA, can be omitted. In this case, as... Figure 16 As shown, portions of the third insulating layer 45, which serves as a planarization layer, can be respectively disposed in the recessed spaces between the partition walls, for example, the recessed space between the first partition wall PW1 and the second partition wall PW2, and the recessed space between the second partition wall PW2 and the third partition wall PW3.

[0241] Figure 17 This is a cross-sectional view of a portion of the display area DA and a portion of the intermediate area MA of the display panel 10 according to an embodiment. Figure 18 yes Figure 17 Plan view of the protrusions and partition walls.

[0242] Reference Figure 17 As described above, a light-emitting diode (e.g., an organic light-emitting diode OLED) can be arranged in the display area DA, and an insulating layer (e.g., gate insulating layer 203, first interlayer insulating layer 205 and second interlayer insulating layer 207, first intermediate insulating layer 209 and second intermediate insulating layer 211) arranged below the organic light-emitting diode OLED can extend toward the intermediate area MA. Its description can be referenced above. Figures 6A to 16 The descriptions provided are identical, therefore, redundant descriptions need not be repeated.

[0243] A structure comprising multiple protrusions PS and valleys VY between adjacent (e.g., adjacent) protrusions PS can be formed on the insulating layer in the intermediate region MA. The structure including the protrusions PS and valleys VY can be superimposed on the data line bypass portion DL-C. For example, at least one of the data line bypass portions DL-C can be superimposed on the protrusions PS and valleys VY.

[0244] like Figure 17 As shown, the protrusions PS and valleys VY can be arranged alternately in the horizontal direction (e.g., the x-direction). For example, valleys VY can be arranged between adjacent (e.g., adjacent) protrusions PS, and protrusions PS can be arranged between adjacent (e.g., adjacent) valleys VY. The structure including protrusions PS and valleys VY can be formed by at least one insulating layer ISL (e.g., a layer including upper insulating layer 215 and spacer 217 (217L)) on the second intermediate insulating layer 211.

[0245] A portion of the organic encapsulation layer 320 can be disposed in a recessed space corresponding to the valley VY, and the volume of the organic encapsulation layer 320 can be adequately ensured by the valley structure. In the comparative example, when the valley structure is not provided, it may be difficult to adequately ensure the thickness of the organic encapsulation layer 320 covering the area where the data lines are arranged, bypassing the DL-C, due to the flow of monomers injected by the inkjet method. Conversely, according to the embodiment, a structure including the valley VY is formed, thus improving the volume of monomers received in the valley VY, thereby adequately ensuring the thickness of the organic encapsulation layer 320. Figure 18 In the plan view shown, the valley VY and the protrusion PS can have a closed-loop shape surrounding the opening 10H of the display panel 10. Although Figure 17 and Figure 18A planarized insulating layer 47 is shown disposed in the intermediate region MA and has a closed-loop shape surrounding the opening 10H of the display panel 10. However, in another embodiment, a third insulating layer 45 may be disposed (e.g., see...). Figure 16 Instead of referring to Figure 17 The described planarized insulating layer 47.

[0246] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims and their equivalents.

Claims

1. A display panel, the display panel comprising: The base, including the opening; Multiple light-emitting elements are arranged in a display area surrounding the opening, each of the multiple light-emitting elements including a first electrode, a second electrode, and an intermediate layer located between the first electrode and the second electrode; Multiple partition walls are arranged in the intermediate area between the display area and the opening; as well as An encapsulation layer is located on the plurality of light-emitting elements, and the encapsulation layer includes an inorganic encapsulation layer and an organic encapsulation layer. The second electrode extends from the display area toward the central area, and The organic layer of the intermediate layer includes a plurality of openings not disposed therein, the plurality of openings being arranged in a region from the opening to the edge portion of the second electrode facing the opening.

2. The display panel according to claim 1, wherein, The organic layer comprises organic portions separated from each other by the plurality of openings, and The top surface of the organic portion contacts the inorganic encapsulation layer.

3. The display panel according to claim 1, wherein, In the plan view, each of the plurality of openings has a closed-loop shape surrounding the opening.

4. The display panel according to claim 1, wherein, At least one of the plurality of openings is arranged between two adjacent partition walls from among the plurality of partition walls.

5. The display panel according to claim 1, wherein, At least one of the plurality of openings is arranged between the opening and the partition wall closest to the opening from the plurality of partition walls.

6. The display panel according to claim 1, wherein, At least one of the plurality of openings is arranged between the display area and the partition wall closest to the display area from the plurality of partition walls.

7. The display panel according to claim 1, wherein, The organic layer includes at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

8. The display panel according to claim 1, further comprising: An inorganic insulating layer is disposed on the substrate. The inorganic encapsulation layer contacts the top surface of the inorganic insulating layer through one of the plurality of openings.

9. The display panel according to claim 1, wherein, The edge of the organic encapsulation layer is adjacent to one of the plurality of partition walls, and The inorganic encapsulation layer includes: A first inorganic encapsulation layer is located below the organic encapsulation layer; and A second inorganic encapsulation layer is located on the organic encapsulation layer, and the second inorganic encapsulation layer contacts the first inorganic encapsulation layer in the region between the edge and the opening of the organic encapsulation layer.

10. The display panel according to claim 1, wherein, The edge portion of the second electrode is located between the display area and one of the plurality of partition walls.

11. The display panel according to claim 10, wherein, The edge portion of the second electrode is covered by the organic encapsulation layer.

12. The display panel according to claim 1, further comprising: Multiple inorganic insulating layers are located on the substrate. The plurality of inorganic insulating layers includes a plurality of grooves, each groove having a depth smaller than the sum of the thicknesses of the plurality of inorganic insulating layers. The plurality of grooves are stacked with a covering layer comprising an organic insulating material.

13. The display panel according to claim 1, further comprising: An auxiliary layer is located between the display area and one of the plurality of partition walls, and the auxiliary layer is stacked with the organic encapsulation layer.

14. The display panel according to claim 13, wherein, The auxiliary layer comprises the same material as the first electrode.

15. The display panel according to claim 1, further comprising: A planarization layer is located on the encapsulation layer, and the planarization layer is superimposed on the plurality of partition walls and a portion of the organic encapsulation layer.

16. An electronic device, the electronic device comprising: The display panel includes an opening area, a display area surrounding the opening area, and an intermediate area between the opening area and the display area. as well as The component is stacked with the opening region. The display panel includes: a substrate including an opening disposed in the opening region; a plurality of light-emitting elements disposed in the display region, each of the plurality of light-emitting elements including a first electrode, a second electrode, and an intermediate layer located between the first electrode and the second electrode; a plurality of partition walls disposed in the intermediate region; and an encapsulation layer disposed on the plurality of light-emitting elements, the encapsulation layer including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The second electrode extends from the display area toward the central area, and includes a first opening portion defined by an edge portion of the second electrode facing the opening. The organic layer of the intermediate layer includes: a plurality of second opening portions not disposed therein, arranged in the region from the edge portion of the second electrode to the opening; and a plurality of organic portions separated from each other by the plurality of second opening portions, the plurality of organic portions being arranged in the first opening portion.

17. The electronic device according to claim 16, wherein, The top surfaces of the plurality of organic components contact the first inorganic encapsulation layer.

18. The electronic device according to claim 16, wherein, In the plan view, each of the plurality of second opening portions has a closed loop shape surrounding the opening.

19. The electronic device according to claim 16, wherein, At least one of the plurality of second opening portions is arranged between two adjacent partition walls from among the plurality of partition walls.

20. The electronic device according to claim 16, wherein, At least one of the plurality of second opening portions is arranged between the opening and the partition wall closest to the opening from the plurality of partition walls.

21. The electronic device according to claim 16, wherein, At least one of the plurality of second opening portions is arranged between the display area and the partition wall closest to the display area from the plurality of partition walls.

22. The electronic device according to claim 16, wherein, The organic layer includes at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

23. The electronic device according to claim 16, wherein, The edge portion of the second electrode is covered by the organic encapsulation layer.

24. The electronic device according to claim 23, wherein, The edge of the organic encapsulation layer is positioned between the edge portion of the second electrode and the opening.

25. The electronic device according to claim 16, wherein, The display panel also includes multiple inorganic insulating layers on the substrate. The plurality of inorganic insulating layers includes a plurality of grooves, each groove having a depth smaller than the sum of the thicknesses of the plurality of inorganic insulating layers. The plurality of grooves are stacked with a covering layer comprising an organic insulating material.

26. The electronic device according to claim 16, wherein, The display panel also includes: An auxiliary layer is located between the display area and one of the plurality of partition walls, and the auxiliary layer comprises the same material as the first electrode.

27. The electronic device according to claim 16, wherein, The display panel also includes: A planarization layer, located on the encapsulation layer, is superimposed on the plurality of partition walls and a portion of the organic encapsulation layer, and comprises an organic insulating material.

28. The electronic device according to claim 16, wherein, The components include sensors or cameras.

29. A method for manufacturing a display panel, the method comprising: Pixel circuits, including transistors, are formed in the display area; A partition wall is formed in the central area surrounded by the display area; A first electrode is formed in the display area, and the first electrode is electrically connected to the transistor; Multiple auxiliary layers are formed in the intermediate region; An emission layer is formed on the first electrode; An organic layer is formed on the first electrode and the plurality of auxiliary layers; A second electrode is formed on the first electrode and the plurality of auxiliary layers; The stacked structure of the plurality of auxiliary layers, the organic layer and the second electrode is irradiated with a laser, such that the second electrode includes a single first opening portion in the intermediate region, and the organic layer includes a plurality of second opening portions disposed in the intermediate region; An encapsulation layer is formed on the second electrode, the encapsulation layer comprising an organic encapsulation layer and an inorganic encapsulation layer; as well as An opening is formed by removing the stacked structure in the opening area inside the intermediate area. The organic layer includes a plurality of organic portions separated from each other by the plurality of second openings, the plurality of organic portions being arranged in the first opening.

30. The method according to claim 29, wherein, The top surfaces of the plurality of organic components contact the inorganic encapsulation layer.

31. The method according to claim 29, wherein, Each of the plurality of second opening portions has a closed-loop shape in the plan view.

32. The method according to claim 29, wherein, The partition wall includes multiple partition walls, and At least one of the plurality of second opening portions is arranged between two adjacent partition walls from among the plurality of partition walls.

33. The method according to claim 29, wherein, The partition wall includes multiple partition walls, and At least one of the plurality of second opening portions is arranged between the opening and the partition wall closest to the opening from the plurality of partition walls.

34. The method according to claim 29, wherein, The partition wall includes multiple partition walls, and At least one of the plurality of second opening portions is located between the display area and the partition wall closest to the display area from the plurality of partition walls.

35. The method according to claim 29, wherein, The plurality of auxiliary layers comprise the same material as the first electrode.

36. The method according to claim 29, wherein, The organic layer includes at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

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