A HEMT device for suppressing current collapse and its manufacturing method

Abstract

This invention relates to the field of semiconductor and semiconductor manufacturing technology, specifically to a HEMT device for suppressing current collapse and its manufacturing method. The device includes a substrate with a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The barrier layer has a source, a gate, and a drain. A P-GaN layer is disposed between the gate and the barrier layer. A storage layer is disposed between the source and the barrier layer. Passivation layers are disposed between the source and the gate, and between the gate and the drain. This invention discloses a HEMT device for suppressing current collapse. Through the storage layer configuration, when the device is off, the net negative charge in the pGaN charge storage layer below the source effectively accelerates the depletion of the 2DEG, reducing the turn-off time and lowering the device turn-off loss. When the device is on, the net negative charge in the storage layer decreases, which helps the 2DEG recover, reducing the turn-on time and lowering the turn-on loss.

Description

Technical Field

[0001] This invention relates to the field of semiconductor and semiconductor manufacturing technology, specifically to a HEMT device that suppresses current collapse and its manufacturing method. Background Technology

[0002] In wide-bandgap compound semiconductor electronic devices, GaN-based HEMTs are one of the main devices used in high-frequency, high-power applications and are currently a research hotspot.

[0003] GaN materials have advantages such as wide bandgap, high critical breakdown electric field, high electron saturation velocity, high thermal conductivity, and strong radiation resistance. Therefore, GaN-based HEMT devices have excellent characteristics such as high electron mobility, high critical breakdown electric field strength, and high electron saturation velocity.

[0004] Moreover, nitride materials have strong spontaneous and piezoelectric polarization effects, which can significantly improve the density and mobility of two-dimensional electron gas (2DEG) in the HEMT material structure, giving GaN HEMTs very strong current handling capabilities, making them an excellent solution for high-frequency and high-power switching applications.

[0005] Despite continuous breakthroughs in the performance of GaN-based HEMTs as technology advances, their large-scale application remains limited by electrical reliability issues. Electrical stress degradation is a particularly significant problem. The main advantage of GaN-based HEMTs lies in their high frequency and high power; therefore, the existence of current collapse effects has severely hampered their application.

[0006] In conventional GaN HEMTs, the channel 2DEG gains energy under the influence of the peak electric field near the drain side under the gate, jumps out of the channel potential well and enters the buffer layer, is trapped by the buffer layer trap and cannot be released in time, resulting in a significant current collapse effect.

[0007] Although GaN-based power HEMT devices inherently possess low power consumption, their switching losses still need to be reduced to meet the demands of higher efficiency applications. This is especially true in high-frequency operating environments, where switching losses still constitute a significant portion of the overall power consumption.

[0008] When GaN HEMT devices operate under high-frequency, large-signal conditions, the output current of the device will decrease significantly, which will lead to a reduction in output power, also known as the current collapse effect.

[0009] There are two main reasons for the current collapse effect: ① the "virtual gate" effect caused by surface traps; ② the trapping of hot electrons in the channel by buffer layer traps.

[0010] Compared to GaN buffer layer traps, the effects of surface traps can be mitigated through processing. By growing a passivation layer on the device surface to alter the surface state energy levels, the impact of surface traps on the electron concentration in the GaN HEMT channel can be reduced, thereby suppressing current collapse.

[0011] However, the impact of buffer layer traps on current collapse is difficult to solve effectively from a technological perspective.

[0012] Therefore, in order to avoid the above problems, it is necessary to optimize the design of existing HEMT devices and the manufacturing process. Summary of the Invention

[0013] The purpose of this invention is to overcome the shortcomings of the prior art and provide a HEMT device that can suppress current collapse.

[0014] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0015] A HEMT device for suppressing current collapse includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, a channel layer on the buffer layer, a barrier layer on the channel layer, a source, a gate, and a drain on the barrier layer, a P-GaN layer between the gate and the barrier layer, a storage layer between the source and the barrier layer, and passivation layers between the source and the gate, and between the gate and the drain.

[0016] The barrier layer is provided with a groove group; the groove group is arranged near the drain end of the barrier layer; the groove group is arranged below the region between the gate and the drain; the groove group includes a plurality of groove bodies disposed on the barrier layer; the passivation layer extends into each groove body.

[0017] The plurality of grooves are spaced apart.

[0018] Adjacent grooves are distributed at equal intervals.

[0019] There is a height difference between adjacent grooves; the grooves near the gate have the greatest depth, and the depth of each groove in the groove group gradually decreases from the gate to the drain side.

[0020] The vertical cross-section of the groove is rectangular or semi-circular.

[0021] A method for manufacturing the HEMT device, the method comprising the following steps:

[0022] Step 1: Provide a base substrate and grow a nucleation layer on the substrate;

[0023] Step 2: Epitaxially extend a buffer layer onto the nucleation layer;

[0024] Step 3: Grow a channel layer on the buffer layer; grow a barrier layer on the channel layer; grow a P-type charge storage layer on the barrier layer;

[0025] Step 4: After step 3 is completed, the P-type charge storage layer is etched. During etching, the region where the source is arranged on the barrier layer is required to form the storage layer; the region where the gate is arranged on the barrier layer is required to form the cap layer.

[0026] Step 5: After completing Step 4, fabricate the source and drain on the barrier layer; the source and drain must form an ohmic contact with the barrier layer.

[0027] Step 6: After step 5 is completed, etch a group of grooves on the barrier layer; the groove group is required to be arranged near the drain end of the barrier layer; the groove group is arranged below the region between the gate and the drain.

[0028] Step 7: After step 6 is completed, a passivation layer is grown on the barrier layer;

[0029] Step 8: Fabricate the gate on the cap layer;

[0030] Step 9: After completing step 8, the production of one HEMT device is complete. If HEMT devices need to be produced repeatedly, repeat steps 1-8.

[0031] In step 6, it is required that the groove depth is the largest at the end near the gate and the groove depth is the smallest at the end near the drain.

[0032] The groove body is etched into an arc-shaped groove or a rectangular groove.

[0033] The side of the groove body near the gate in the groove group is flush with the side of the cap layer.

[0034] The advantages of this invention are:

[0035] This invention discloses a HEMT device that suppresses current collapse. By setting up a storage layer, when the device is turned off, the net negative charge in the pGaN charge storage layer below the source effectively accelerates the depletion of 2DEG, reduces the turn-off time, and lowers the device turn-off loss. When the device is turned on, the net negative charge in the storage layer is reduced, which helps 2DEG recovery, reduces the turn-on time, and lowers the turn-on loss.

[0036] Furthermore, the presence of the groove bodies in the groove group can modulate the barrier layer thickness to a certain extent, reducing the probability of channel electrons jumping out of the potential well and being trapped by the buffer layer trap, thus enhancing the device's control over the channel. The multiple rectangular (or semi-circular) blocking regions between the gate and drain can prevent the electric field from concentrating at the gate edge and the groove edge. The blocking regions reduce the path for gate electrode electrons to migrate laterally from the barrier layer surface to the drain when the GaN HEMT is turned off, thus slightly increasing the static on-resistance. In addition, compared with the prior art, this invention does not use a field plate structure, avoiding the introduction of gate-source parasitic capacitance and parasitic resistance, and the process is simple and easy to implement. Attached Figure Description

[0037] The following is a brief explanation of the contents of each of the accompanying drawings and the markings in the drawings:

[0038] Figure 1 This is a schematic diagram of the structure of the first embodiment of the present invention.

[0039] Figure 2 This is a schematic diagram of the structure of the second embodiment of the present invention.

[0040] The markings in the above figures are all:

[0041] 1. Substrate, 2. Nucleation layer, 3. Buffer layer, 4. Channel layer, 5. Barrier layer, 6. Passivation layer, 7. Trench group, 8. Storage layer, 9. Source, 10. Gate, 11. Drain, 12. Cap layer. Detailed Implementation

[0042] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and the description of the preferred embodiments.

[0043] A HEMT device for suppressing current collapse includes a substrate 1, a nucleation layer 2 on the substrate 1, a buffer layer 3 on the nucleation layer 2, a channel layer 4 on the buffer layer 3, a barrier layer 5 on the channel layer 4, a source 9, a gate 10, and a drain 11 on the barrier layer 5, a P-GaN layer (cap layer 12) between the gate 10 and the barrier layer 5, a storage layer 8 between the source 9 and the barrier layer 5, and passivation layers 6 between the source 9 and the gate 10 and between the gate 10 and the drain 11. This invention discloses a HEMT device for suppressing current collapse. Through the storage layer 8, when the device is turned off, the net negative charge in the pGaN charge storage layer 8 below the source 9 effectively accelerates the depletion of the 2DEG, reducing the turn-off time and lowering the device turn-off loss. When the device is turned on, the net negative charge in the storage layer 8 decreases, which helps the 2DEG recover, reducing the turn-on time and lowering the turn-on loss.

[0044] In addition, in this invention, the barrier layer 5 is provided with a groove group 7; the groove group 7 is arranged near one end of the barrier layer 5 near the drain 11; the groove group 7 is arranged below the region between the gate 10 and the drain 11; the groove group 7 includes a plurality of groove bodies 71 disposed on the barrier layer 5; the passivation layer 6 extends into each groove body 71; in this invention, the presence of the groove body 71 can modulate the thickness of the barrier layer 5 to a certain extent, reduce the probability of channel electrons jumping out of the potential well and being trapped by the buffer layer 3, and enhance the device's control capability over the channel; the multiple rectangular (or semi-circular) blocking regions between the gate and drain 11 can prevent the electric field from concentrating at the edge of the gate 10 and the edge of the groove; the blocking regions reduce the path for gate electrode electrons to migrate laterally from the surface of the barrier layer 5 to the drain 11 when the GaN HEMT is turned off, and slightly increase the static on-resistance.

[0045] Furthermore, in this invention, the plurality of groove bodies 71 are spaced apart; the presence of multiple groove bodies here can prevent the electric field from concentrating on the sidewall of a single groove, thereby enhancing the channel control capability; in addition, in this invention, the spacing between adjacent groove bodies from the gate to the drain can be equidistant, or it can be distributed in an arithmetic or geometrical manner (increasing sequentially), which provides better control over the electric field distribution.

[0046] Furthermore, in this invention, adjacent groove bodies 71 are equidistantly distributed; this equidistant distribution method provides better control over the electric field distribution.

[0047] Furthermore, in this invention, there is a height difference between adjacent groove bodies 71; the groove body 71 near the gate 10 has the greatest depth, and the depth of each groove body 71 in the groove group 7 gradually decreases from the gate 10 to the drain 11; through the disclosure of the above structure, this invention enables the passivation layer 6 to form multiple stepped blocking regions between the source and drain 11; the blocking regions can slowly weaken the electric field between the gate 10 and the drain 11, and while ensuring sufficient two-dimensional electron gas to provide current, enhance the device's control over the channel, avoid electric field concentration, and effectively alleviate the current collapse effect.

[0048] Furthermore, in this invention, the vertical cross-section of the groove body 71 is rectangular or semi-circular; the advantage of using a rectangular cross-section for the groove body is that the manufacturing process is simple; while the semi-circular cross-section of the groove body improves the electric field concentration effect; through such a structural setting, this invention can avoid the electric field from concentrating at the edge of the gate 10 and the edge of the groove.

[0049] A method for manufacturing the HEMT device, the method comprising the following steps:

[0050] Step 1: Provide a base substrate 1, and grow a nucleation layer 2 on the substrate 1;

[0051] Step 2: Epitaxially extend buffer layer 3 onto nucleation layer 2;

[0052] Step 3: Grow a channel layer 4 on the buffer layer 3; grow a barrier layer 5 on the channel layer 4; grow a P-type charge storage layer on the barrier layer 5;

[0053] Step 4: After step 3 is completed, the P-type charge storage layer is etched. During etching, the storage layer 8 is formed in the region where the source 9 is arranged on the barrier layer 5; and the cap layer 12 is formed in the region where the gate 10 is arranged on the barrier layer 5.

[0054] Step 5: After step 4 is completed, the source 9 and drain 11 are fabricated on the barrier layer 5; it is required that the source 9 and drain 11 form an ohmic contact with the barrier layer 5.

[0055] Step 6: After step 5 is completed, etch a groove group 7 on the barrier layer 5; the groove group 7 is required to be arranged near the drain 11 end of the barrier layer 5; the groove group 7 is arranged below the region between the gate 10 and the drain 11.

[0056] Step 7: After step 6 is completed, a passivation layer 6 is grown on the barrier layer 5;

[0057] Step 8: Fabricate gate 10 on cap layer 12;

[0058] Step 9: After completing step 8, the production of one HEMT device is complete. If HEMT devices need to be produced repeatedly, repeat steps 1-8.

[0059] specific;

[0060] Substrate 1 is typically silicon or silicon carbide, and materials capable of growing group III nitrides (including but not limited to gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, diamond, sapphire, germanium) are also grown.

[0061] Nucleation layer 2 is grown on substrate 1; Function of nucleation layer: Direct epitaxial growth of GaN material on substrate often results in poor quality. Therefore, a nucleation layer is inserted between the substrate and the epitaxial structure to promote the lateral growth of GaN, improve the growth quality of the epitaxial layer, and also serve as an isolation layer to prevent interdiffusion between the substrate and GaN material; Matching substrate 1 material and heterojunction material layer; Thickness: ≤200nm; Growth method: MOCVD, MBE, ALD; Growth temperature: 750℃~1150℃;

[0062] The epitaxial buffer layer 3 on the nucleation layer 2 serves to protect the substrate 1 from metal ion intrusion and to bond other semiconductor material layers that need to be grown on it; it can be a group III nitride material such as AlGaN, GaN or AlGaInN; thickness: 1-2 μm, growth method: MOCVD, MBE, HVPE, temperature: 800-1200℃.

[0063] A channel layer 4 is grown on the buffer layer 3, and a barrier layer 5 is grown on the channel layer 4. The channel layer 4 and the barrier layer 5 form a heterojunction. A 2DEG is generated at the interface between the channel layer 4 and the barrier layer 5 near the end of the channel layer 4. Thickness: <250nm; Growth method: MOCVD, MBE, ALD.

[0064] A pGaN and / or P-type charge storage layer is grown on the barrier layer 5. The charge storage layer 8 is made of GaN or AlGaN. The p-type doping concentration and the thickness of the pGaN film need to be optimized based on their impact on the concentration of 2DEG. Growth methods: MOCVD, MBE, ALD.

[0065] Etch pGaN while retaining the cap layer 12 under the gate 10 and the memory layer 8 under the source 9;

[0066] Source 9 and drain 11 are fabricated on barrier layer 5. Source 9 and drain 11 are to form ohmic contacts with the semiconductor material of barrier layer 5; fabrication method: electroplating, metal evaporation, sputtering or combination thereof; metal includes but is not limited to: Ti, Al, Ni, Au, Ta or a combination of several of these metals;

[0067] Multiple grooves 71 are etched on the drain side of the gate of the barrier layer 5. The groove 71 closest to the gate 10 is etched the deepest, and the groove near the drain is etched the shallowest.

[0068] A passivation layer 6 is grown in the region between the source and drain electrodes 11. The passivation layer 6 protects the device from the influence of the ambient atmosphere and fills the groove 71, effectively suppressing the current collapse effect. Growth method: PECVD, LPCVD, etc. Material: silicon dioxide, silicon nitride, etc.

[0069] A window for the gate 10 is photolithographically formed on the passivation layer 6, the passivation layer 6 under the gate 10 is etched, and then metal is deposited to prepare the gate 10. The gate 10 forms a Schottky contact with the semiconductor material of the barrier layer 5. Specifically, the gate 10 forms a Schottky contact with the cap layer 12. The preparation method is electroplating, metal evaporation, sputtering, or a combination thereof. The metals include, but are not limited to, Ni, Au, Pd, Pt, and other metal systems or combinations thereof.

[0070] Furthermore, in step 6 of this invention, the groove 71 near the gate 10 is required to have the greatest depth, and the groove 71 near the drain 11 is required to have the smallest depth. In actual processing, because the depths of each groove are different, each groove must be etched sequentially during actual etching. Theoretically, there is little difference between etching the groove with the greater depth first and etching the groove with the smaller depth first during actual etching. However, in actual operation, the groove with the greater depth can be etched first, followed by the groove with the smaller depth. This etching method is convenient for actual etching because the groove with the greater depth is arranged close to the gate, which also serves as a good calibration.

[0071] Furthermore, in this invention, the groove 71 is etched into an arc-shaped groove or a rectangular groove; the rectangular groove structure can be etched using a normal etching method, while the arc-shaped groove requires the addition of ion milling to the instrument for etching.

[0072] Furthermore, in the groove group 7 described in this invention, the side of the groove body 71 near the gate 10 is flush with the side of the cap layer 12; the largest groove body needs to be arranged everywhere along the edge of the gate, and the spacing between the groove bodies can be equidistant / proportional / arithmetic distribution; here, equidistant means equidistant along the longitudinal direction, as shown in the view; because the electric field is the largest near the drain end under the gate, arranging the groove bodies along the gate edge can improve the electric field distribution, and the advantage of the distribution setting between the groove groups is also to optimize the electric field distribution; at the same time, such a setting can play a good calibration role and facilitate the control of the etching start point; the spacing between adjacent groove bodies from the gate to the drain can be equidistant, or it can be arithmetic or proportional distribution (the spacing increases sequentially), such a distribution has a better effect on the control of the electric field distribution.

[0073] Obviously, the specific implementation of this invention is not limited to the above-described methods. Any non-substantial improvements made using the inventive concept and technical solution of this invention are within the protection scope of this invention.

Claims

1. A HEMT device for suppressing current collapse, characterized in that, The device includes a substrate, on which a nucleation layer is disposed; a buffer layer is disposed on the nucleation layer; a channel layer is disposed on the buffer layer; a barrier layer is disposed on the channel layer; a source, a gate, and a drain are disposed on the barrier layer; a P-GaN layer is disposed between the gate and the barrier layer; a storage layer is disposed between the source and the barrier layer; and passivation layers are disposed between the source and the gate, and between the gate and the drain. The barrier layer is provided with a groove group; the groove group is arranged near the drain end of the barrier layer; the groove group is arranged below the region between the gate and the drain; the groove group includes a plurality of groove bodies disposed on the barrier layer; the passivation layer extends into each groove body; There is a height difference between adjacent grooves; the grooves near the gate have the greatest depth, and the depth of each groove in the groove group gradually decreases from the gate to the drain side.

2. The HEMT device for suppressing current collapse according to claim 1, characterized in that, The plurality of grooves are spaced apart.

3. The HEMT device for suppressing current collapse according to claim 2, characterized in that, Adjacent grooves are distributed at equal intervals.

4. The HEMT device for suppressing current collapse according to claim 1, characterized in that, The vertical cross-section of the groove is rectangular or semi-circular.

5. A method for manufacturing a HEMT device as described in any one of claims 1-4, characterized in that, The production method includes the following steps: Step 1: Provide a base substrate and grow a nucleation layer on the substrate; Step 2: Epitaxially extend a buffer layer onto the nucleation layer; Step 3: Grow a channel layer on the buffer layer; grow a barrier layer on the channel layer; grow a P-type charge storage layer on the barrier layer; Step 4: After step 3 is completed, the P-type charge storage layer is etched. During etching, the region where the source is arranged on the barrier layer is required to form the storage layer; the region where the gate is arranged on the barrier layer is required to form the cap layer. Step 5: After completing Step 4, fabricate the source and drain on the barrier layer; the source and drain must form an ohmic contact with the barrier layer. Step 6: After step 5 is completed, etch a group of grooves on the barrier layer; the groove group is required to be arranged near the drain end of the barrier layer; the groove group is arranged below the region between the gate and the drain. Step 7: After step 6 is completed, a passivation layer is grown on the barrier layer; Step 8: Fabricate the gate on the cap layer; Step 9: After completing step 8, the production of one HEMT device is complete. If HEMT devices need to be produced repeatedly, repeat steps 1-8.

6. A method for manufacturing a HEMT device according to claim 5, characterized in that, In step 6, it is required that the groove depth is the largest at the end near the gate and the groove depth is the smallest at the end near the drain.

7. A method for manufacturing a HEMT device according to claim 6, characterized in that, The groove body is etched into an arc-shaped groove or a rectangular groove.

8. A method for manufacturing a HEMT device according to claim 6, characterized in that, The side of the groove body near the gate in the groove group is flush with the side of the cap layer.

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