A small-sized memory device structure and a method for manufacturing the same

Abstract

The present invention discloses a small-sized memory device structure and a manufacturing method thereof. The small-sized memory device structure includes: a substrate, which is formed with a P-well region, an N-well region, and a U-shaped groove, wherein the N-well region is located above the P-well region, and the U-shaped groove penetrates through the N-well region; a semi-floating gate dielectric layer, which is formed on the surface of the U-shaped groove and extends to cover part of the surface of the N-well region, and a window is formed on the surface of the N-well region; a semi-floating gate, which covers the semi-floating gate dielectric layer and completely fills the U-shaped groove, and is in contact with the surface of the N-well region at the window; a control gate dielectric layer, which is formed on the upper surface of the semi-floating gate; a control gate, which covers the control gate dielectric layer; a source region and a drain region, which are respectively formed in the N-well regions on both sides of the control gate. The semi-floating gate region is programmed by a PMOS transistor parasitic on the side wall of the U-shaped groove of the semi-floating gate transistor, which greatly simplifies the structure of the semi-floating gate transistor and miniaturizes the device cell size.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a small-sized memory device structure and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor memories, the device size thereof is continuously decreasing, and its operating speed is also continuously increasing. As a new type of capacitorless memory device, the semi-floating gate transistor (SFGT) has the advantages of fast write operation speed, small cell area, high chip density, low operating voltage during data storage, and strong data retention ability.

[0003] For a semi-floating gate transistor with a general structure, the size of one unit thereof is 8-12F2. However, this unit size does not have an obvious advantage compared with the unit sizes of DRAM and FBC. For example, in the current 2Xnm process, the area of a DRAM unit is 0.0036μm 2 , and the area of an SFGT unit is 0.0090 / 0.0064μm 2 . Therefore, from the perspectives of device working principles and structures, etc., on the premise of ensuring the basic performance of the device, how to further miniaturize the SFGT unit size, reduce the SFGT unit area to be equivalent to or even smaller than the area of the mainstream memory units in the market, and further reflect the advantage of the small cell area of the semi-floating gate transistor to achieve a higher chip integration density has very important scientific research value and practical application significance. Summary of the Invention

[0004] To solve the above problems, the present invention discloses a small-sized memory device structure, including: a substrate, which is formed with a P-well region, an N-well region, and a U-shaped groove, wherein the N-well region is located above the P-well region, and the U-shaped groove penetrates through the N-well region; a semi-floating gate dielectric layer, formed on the surface of the U-shaped groove and extending to cover a part of the surface of the N-well region, and a window is formed on the surface of the N-well region; a semi-floating gate, covering the semi-floating gate dielectric layer and completely filling the U-shaped groove, and contacting the surface of the N-well region at the window; a control gate dielectric layer, formed on the upper surface of the semi-floating gate; a control gate, covering the control gate dielectric layer; a source region and a drain region, respectively formed in the N-well regions on both sides of the control gate.

[0005] In the small-sized memory device structure of the present invention, preferably, the semi-floating gate is made of P-type polysilicon, and the control gate is made of N-type polysilicon.

[0006] In the small-sized memory device structure of the present invention, preferably, it further includes an N-type heavily doped region, formed in the N-well regions on both sides of the control gate, for regulating the reverse bias leakage current magnitude of the PN junction at the window.

[0007] The present invention also discloses a method for fabricating a small-sized memory device structure, comprising the following steps: forming a P-well region and an N-well region in a device fabrication region of a substrate, wherein the N-well region is located above the P-well region; etching to form a U-shaped groove, such that the U-shaped groove penetrates through the N-well region; forming a semi-floating gate dielectric layer, and then performing etching to form a window on the surface of the N-well region; forming a semi-floating gate, such that it covers the semi-floating gate dielectric layer and completely fills the U-shaped groove, and is in contact with the surface of the N-well region at the window; forming a control gate dielectric layer on the semi-floating gate; forming a control gate, such that it covers the control gate dielectric layer; performing edge etching to expose the surfaces of a part of the N-well region on both sides of the control gate, and performing N-type ion implantation to form a source region and a drain region.

[0008] In the method for fabricating a small-sized memory device structure of the present invention, preferably, dry oxidation is used to form silicon oxide as the semi-floating gate dielectric layer.

[0009] In the method for fabricating a small-sized memory device structure of the present invention, preferably, the semi-floating gate is P-type polysilicon and the control gate is N-type polysilicon.

[0010] In the method for fabricating a small-sized memory device structure of the present invention, preferably, before forming the source and drain regions, N-type ion implantation with heavy doping is performed in the N-well regions on both sides of the control gate to form N-type heavily doped regions for regulating the reverse bias leakage current magnitude of the PN junction at the window. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a flowchart of the method for fabricating a small-sized memory device structure.

[0012] Figures 2 to 8 are schematic structural diagrams of each stage of the method for fabricating a small-sized memory device structure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0014] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0015] In addition, many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of the device, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details. Unless specifically pointed out below, each part of the device can be composed of materials well-known to those skilled in the art, or materials with similar functions developed in the future can be used.

[0016] Figure 1 is a flowchart of a method for fabricating a small-sized memory device structure. As Figure 1 shown, the method for fabricating a small-sized memory device structure includes the following steps:

[0017] Step S1, deposit a first silicon oxide layer 103 and a first silicon nitride layer 104 with a certain thickness on a silicon substrate to form a hard mask layer. The forming method can be chemical vapor deposition, atomic layer deposition, electron beam evaporation, sputtering, etc. Perform P-type ion implantation (the doping ion is, for example, boron) and light-doped N-type ion implantation with a dose range of 8e 12 cm -2 ~4e 13 cm -2 successively on the silicon substrate (the doping ion is, for example, arsenic), and then perform the corresponding annealing process to form a P-well region 100 and an N-well region 102. The N-well region 102 is located above the P-well region 100. The obtained structure is as Figure 2 shown.

[0018] Step S2, spin-coat a photoresist on the above structure, expose and develop to define the position of the U-groove, and remove part of the hard mask layer and the silicon substrate through dry etching, such as plasma etching, reactive ion etching, ion milling etching, etc. to form a U-shaped groove, so that the U-shaped groove penetrates through the N-well region 102. Then remove the photoresist by dissolving or ashing in a solvent. Inject BF2 ions and perform the relevant annealing process to adjust the channel threshold, and then remove the hard mask layer. The obtained structure is as Figure 3 shown.

[0019] Step S3: A second silicon oxide layer is formed as the semi-floating gate dielectric layer 105 through dry oxidation. Then, photoresist is spin-coated and a window pattern is formed through photolithography processes such as exposure and development. Subsequently, part of the second silicon oxide layer is removed by dry etching, such as plasma etching, reactive ion etching, ion milling etching, etc., to form a window for the semi-floating gate. The resulting structure is as shown in Figure 4 shown.

[0020] Next, a first polysilicon layer with a certain thickness is deposited to completely fill the U-shaped groove. Then, ion implantation of P-type impurity boron and corresponding annealing are carried out to form a P-type polysilicon layer, which is chemically mechanically polished to a certain height as the semi-floating gate 106. The semi-floating gate 106 is in contact with the surface of the N-well region 102 at the window.

[0021] Step S4: A third silicon oxide layer 107 and a third silicon nitride layer 108 between the control gate and the semi-floating gate are deposited as the control gate dielectric layer. Then, a second polysilicon layer 109 with a certain thickness is deposited. The resulting structure is as shown in Figure 5 shown. The deposition method can be chemical vapor deposition, atomic layer deposition, electron beam evaporation, sputtering, etc.

[0022] Photoresist is spin-coated and an edge etching pattern is formed through photolithography processes such as exposure and development. Then, part of the second polysilicon and the gate dielectric are removed by dry etching, such as plasma etching, reactive ion etching, ion milling etching, etc. The dry etching removes part of the second polysilicon layer 109, the third silicon nitride layer 108, the third silicon oxide layer 107, and the second silicon oxide layer 105 at the edge, exposing part of the surface of the N-well region 102. The resulting structure is as shown in Figure 6 shown.

[0023] Step S5: Heavy-doped N-type ion implantation with a dose range of 7e 13 cm -2 ~3e 14 cm -2 is carried out in the N-well regions 102 on both sides of the control gate to form N-type heavily doped regions 110, 111 for regulating the reverse bias leakage current magnitude of the PN junction at the window. The resulting structure is as shown in Figure 7 shown.

[0024] Step S6: Subsequently, an isotropic deposition of a fourth silicon oxide layer and a fourth silicon nitride layer and an anisotropic etching are carried out to form the gate sidewall 112. Finally, source-drain ion implantation of N-type impurities such as arsenic (As) is carried out to form the source region 113 and the drain region 114. At the same time, the second polysilicon layer 109 is doped to form an N-type polysilicon layer as the control gate 115, finally forming a small-sized memory device structure. The resulting structure is as shown in Figure 8 shown.

[0025] As shown in Figure 8As shown in the figure, the small-sized storage device structure of the present invention includes: a substrate, which is formed with a P-well region 100, an N-well region 102 and a U-shaped groove. Among them, the N-well region 102 is located above the P-well region 100, and the U-shaped groove penetrates through the N-well region 102; a semi-floating gate dielectric layer 105 is formed on the surface of the U-shaped groove and extends to cover part of the surface of the N-well region 102, and a window is formed on the surface of the N-well region 102; a semi-floating gate 106 covers the semi-floating gate dielectric layer 105 and completely fills the U-shaped groove, and is in contact with the surface of the N-well region 102 at the window; the control gate dielectric layer includes a third silicon oxide layer 107 and a third silicon nitride layer 108, which are formed on the upper surface of the semi-floating gate 106; a control gate 115 covers the control gate dielectric layer; a source region 113 and a drain region 114 are respectively formed in the N-well region 102 on both sides of the control gate 115. Preferably, it also includes N-type heavily doped regions 110, 111, which are formed in the N-well regions on both sides of the control gate and are used to regulate the reverse bias leakage current magnitude of the PN junction at the window.

[0026] The working principle of this structure is different from that of the traditional semi-floating gate transistor. The traditional semi-floating gate transistor mainly relies on the band-to-band tunneling embedded in the TFET, and its tunneling efficiency is relatively sensitive to the NWELL concentration, which means that it has relatively high requirements for process conditions. While this structure, under appropriate bias voltages, uses the turn-on of the PMOS transistor parasitic on the sidewall of the U-groove type semi-floating gate transistor for programming operations, eliminating the sensitivity of the band-to-band tunneling efficiency of the traditional semi-floating gate transistor to the N-well region concentration. In addition, this structure is overall similar to a MOS transistor, greatly simplifying the device structure, facilitating the further miniaturization of the device size, and achieving a smaller cell size.

[0027] As described above, the above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A small-sized memory device structure, characterized in that, Comprising: A substrate, which is formed with a P-well region, an N-well region, and a U-shaped groove, wherein the N-well region is located above the P-well region, and the U-shaped groove penetrates the N-well region; A semi-floating gate dielectric layer, formed on the surface of the U-shaped groove and extending to cover part of the surface of the N-well region, and a window is formed on the surface of the N-well region; A semi-floating gate, covering the semi-floating gate dielectric layer and completely filling the U-shaped groove, and contacting the surface of the N-well region at the window; A control gate dielectric layer, formed on the upper surface of the semi-floating gate; A control gate, covering the control gate dielectric layer; A source region and a drain region, respectively formed in the N-well regions on both sides of the control gate, Programming is performed through the turn-on of the PMOS transistor parasitic on the sidewall of the U-shaped groove, Among them, the N-well region is a lightly doped region with a doping dose of 8e 12 cm -2 ~4e 13 cm -2 。 2. The small-sized memory device structure according to claim 1, characterized in that, The semi-floating gate is made of P-type polysilicon, and the control gate is made of N-type polysilicon.

3. The small-sized memory device structure according to claim 1, characterized in that, It further includes an N-type heavily doped region, formed in the N-well regions on both sides of the control gate, for regulating the reverse bias leakage current magnitude of the PN junction at the window.

4. A method for fabricating a small-sized memory device structure, characterized in that, Including the following steps: Forming a P-well region and an N-well region in the device fabrication area of the substrate, the N-well region being located above the P-well region; Etching to form a U-shaped groove, so that the U-shaped groove penetrates the N-well region; Forming a semi-floating gate dielectric layer, and then etching to form a window on the surface of the N-well region; Forming a semi-floating gate, so that it covers the semi-floating gate dielectric layer and completely fills the U-shaped groove, and contacts the surface of the N-well region at the window; Forming a control gate dielectric layer on the semi-floating gate; Forming a control gate, so that it covers the control gate dielectric layer; Performing edge etching to expose the surfaces of part of the N-well regions on both sides of the control gate, and performing N-type ion implantation to form a source region and a drain region, Programming is performed through the turn-on of the PMOS transistor parasitic on the sidewall of the U-shaped groove, Among them, the N-well region is a lightly doped region with a doping dose of 8e 12 cm -2 ~4e 13 cm -2 .

5. The method for fabricating a small-sized memory device structure according to claim 4, characterized in that, Dry oxidation is used to form silicon oxide as the semi-floating gate dielectric layer.

6. The method for fabricating a small-sized memory device structure according to claim 4, characterized in that, The semi-floating gate is made of P-type polysilicon, and the control gate is made of N-type polysilicon.

7. The method for fabricating a small-sized memory device structure according to claim 4, characterized in that, Before forming the source and drain regions, N-type ion implantation with heavy doping is performed in the N-well regions on both sides of the control gate to form an N-type heavily doped region for regulating the reverse bias leakage current magnitude of the PN junction at the window.

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