A vertical gate storage device structure and a method for manufacturing the same

Abstract

The present invention discloses a vertical gate memory device structure and a manufacturing method thereof. The vertical gate memory device structure includes: a substrate, which is formed with a P-well region, an N-well region and a U-shaped groove, wherein the N-well region is located above the P-well region, and the U-shaped groove penetrates through the N-well region; a first gate oxide layer, formed on the surface of the U-shaped groove and extending to cover part of the surface of the N-well region, and windows are formed at the sidewalls of the U-shaped groove and the surface of the N-well region; a semi-floating gate, formed in the U-shaped groove, covering the first gate oxide layer, and contacting the N-well region at the windows; a control gate dielectric layer, formed in the U-shaped groove, covering the semi-floating gate and extending to cover part of the first gate oxide layer; a control gate, covering the control gate dielectric layer and completely filling the U-shaped groove; a source region and a drain region, respectively formed on both sides of the control gate in the N-well region.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor memories, and particularly relates to a storage device structure with a vertical gate and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor memories, the device size thereof is continuously decreasing, and the operating speed is also continuously increasing. As a new type of capacitorless storage device, the semi-floating gate transistor (SFGT) has the advantages of fast write operation speed, small cell area, high chip density, low operating voltage during data storage, and strong data retention ability.

[0003] From the working principle of the semi-floating gate transistor, it can be seen that the gate dielectric capacitance between the control gate and the semi-floating gate has a crucial impact on the gate voltage utilization efficiency and the overall performance of the device. Under certain conditions, the larger the gate dielectric capacitance, the relatively higher the voltage coupling efficiency of the control gate to the semi-floating gate region, that is, the higher the control gate voltage utilization rate. This is beneficial to reducing the control gate operating voltage, improving the programming efficiency and retention characteristics of the device, and also helps the peripheral circuit design of the semi-floating gate transistor, which is of great significance for the scientific research and practical application of the semi-floating gate transistor. Summary of the Invention

[0004] In order to solve the above problems, the present invention discloses a storage device structure with a vertical gate, including: a substrate, which is formed with a P-well region, an N-well region, and a U-shaped groove, wherein the N-well region is located above the P-well region, and the U-shaped groove penetrates through the N-well region; a first gate oxide layer, formed on the surface of the U-shaped groove and extending to cover a part of the surface of the N-well region, and windows are formed at the sidewalls of the U-shaped groove and the surface of the N-well region; a semi-floating gate, formed in the U-shaped groove, covering the first gate oxide layer, and contacting the N-well region at the windows; a control gate dielectric layer, formed in the U-shaped groove, covering the semi-floating gate and extending to cover a part of the first gate oxide layer; a control gate, covering the control gate dielectric layer and completely filling the U-shaped groove; a source region and a drain region, respectively formed on both sides of the control gate and in the N-well region.

[0005] In the storage device structure with a vertical gate of the present invention, preferably, the semi-floating gate is made of P-type polysilicon, and the control gate is made of N-type polysilicon.

[0006] The present invention also discloses a method for preparing a vertical gate memory device structure, comprising the following steps: forming a P-well region and an N-well region in a device fabrication region of a substrate, wherein the N-well region is located above the P-well region; etching to form a U-shaped groove, such that the U-shaped groove penetrates through the N-well region; forming a first gate oxide layer, and then etching to form a window on sidewalls of the U-shaped groove and on a surface of the N-well region; forming a P-type polysilicon layer in the U-shaped groove, such that the P-type polysilicon layer covers the first gate oxide layer and completely fills the U-shaped groove, and is in contact with the N-well region at the window; performing photolithography and etching on the P-type polysilicon layer to form a semi-floating gate and a fabrication region of a control gate; forming a control gate dielectric layer in the U-shaped groove, covering the semi-floating gate and extending to cover a part of the first gate oxide layer; forming a polysilicon layer, such that the polysilicon layer covers the control gate dielectric layer and completely fills the U-shaped groove; performing edge etching to expose surfaces of parts of the N-well region on both sides of the control gate, and performing N-type ion implantation to form a control gate, a source region and a drain region.

[0007] In the method for preparing a vertical gate memory device structure of the present invention, preferably, the specific steps for forming a window include: depositing a silicon nitride layer on the first gate oxide layer, such that the silicon nitride layer fills the U-shaped groove; dry etching to remove a part of the silicon nitride layer, such that the first gate oxide layer on a sidewall and an upper surface on one side of the U-shaped groove is exposed; wet etching to remove the exposed first gate oxide layer to form a window, and then isotropically etching to remove the silicon nitride layer.

[0008] In the method for preparing a vertical gate memory device structure of the present invention, preferably, dry oxidation is used to form silicon oxide as the first layer of gate oxide layer.

[0009] The present invention effectively increases the gate dielectric capacitance coupling area between the control gate and the semi-floating gate, improves the coupling efficiency of the control gate voltage, is beneficial to reducing the working voltage of the control gate, improving the programming efficiency and retention characteristics of the device, and at the same time, this structure also helps to reduce the cell size of the device and increase the chip integration density of the device. Description of the Drawings

[0010] Figure 1 is a flowchart of a method for preparing a vertical gate memory device structure.

[0011] Figures 2 to 12 is a schematic structural diagram of each stage of a method for preparing a vertical gate memory device structure. Detailed Embodiments

[0012] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the following will describe the technical solutions in the embodiments of the present invention clearly and completely in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts belong to the scope of protection of the present invention.

[0013] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0014] In addition, many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of the device, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details. Unless specifically stated below, each part of the device can be made of materials well known to those skilled in the art, or materials with similar functions developed in the future can be used.

[0015] Figure 1 is a flowchart of a method for fabricating a vertical gate memory device structure. As Figure 1 shown, the method for fabricating a vertical gate memory device structure includes the following steps:

[0016] Step S1, deposit a first silicon oxide layer 103 and a first silicon nitride layer 104 with a certain thickness on a silicon substrate to form a hard mask layer. The forming method can be chemical vapor deposition, atomic layer deposition, electron beam evaporation, sputtering, etc. Perform P-type ion implantation (the doping ion is boron, for example) and N-type ion implantation (the doping ion is arsenic, for example) on the silicon substrate in sequence, and then perform the corresponding annealing process to form a P-well region 100 and an N-well region 102. The N-well region 102 is located above the P-well region 100. The obtained structure is as Figure 2 shown.

[0017] Step S2, on the basis of the above structure, spin-coat photoresist, expose and develop to define the position of the U-groove. Through dry etching, such as plasma etching, reactive ion etching, ion milling etching, etc., remove part of the hard mask layer and the silicon substrate to form a U-shaped groove, so that the U-shaped groove penetrates the N-well region 102. Then remove the photoresist by dissolving it in a solvent or ashing. Inject BF2 by ion implantation and perform related annealing processes for channel threshold adjustment, and then remove the hard mask layer. The obtained structure is as Figure 3 shown.

[0018] Step S3, form a second silicon oxide layer as the first gate oxide layer 105 by dry oxidation, and then deposit a certain thickness of second silicon nitride layer 106 to fill the U-shaped groove and chemically mechanically polish it to a certain height. The obtained structure is as Figure 4 shown. After that, spin-coat photoresist, define the position where the second silicon nitride layer needs to be etched, and remove part of the second silicon nitride layer by dry etching, so that part of the side wall and the upper surface of the first gate oxide layer 105 on one side of the U-shaped groove are exposed. The obtained structure is as Figure 5 shown.

[0019] After that, wet-etch the first gate oxide layer 105 exposed to the air to etch out the window of the semi-floating gate region. Then isotropically etch to remove the second silicon nitride layer 106. The obtained structure is as Figure 6 shown. Then deposit a certain thickness of the first polysilicon layer to completely fill the U-shaped groove, and then perform ion implantation of P-type impurity boron and corresponding annealing to form a P-type polysilicon layer 107 and make part of the P-type impurity diffuse outside the window, and perform chemical mechanical polishing to make the upper surface of the P-type polysilicon layer 107 flush with the upper surface of the first gate oxide layer 105. The obtained structure is as Figure 7 shown.

[0020] Step S4, on the basis of the above structure, spin-coat photoresist, expose and develop to define the position of the control gate. Subsequently, remove a certain thickness of the P-type polysilicon in the U-shaped groove by dry etching to obtain a semi-floating gate and form a control gate fabrication area. The obtained structure is as Figure 8 shown. Then deposit a third silicon oxide layer 108 and a third silicon nitride layer 109 between the control gate and the semi-floating gate as the control gate dielectric layer. The obtained structure is as Figure 9 shown.

[0021] Then deposit a certain thickness of the second polysilicon layer 110 to fill the U-shaped groove and chemically mechanically polish it to a certain height. The obtained structure is as Figure 10 shown. After that, dry-etch to remove part of the second polysilicon layer 110, the third silicon nitride layer 109, the third silicon oxide layer 108 and the second silicon oxide layer 105 at the edge, so that part of the surface of the N-well region 102 is exposed. The obtained structure is as Figure 11 shown.

[0022] Step S5. Subsequently, an isotropic deposition of a fourth silicon oxide layer and a fourth silicon nitride layer is performed, and then an anisotropic etching is carried out to form the gate sidewall 111. Finally, a source / drain ion implantation of an N-type impurity such as arsenic (As) is performed to form the source region 112 and the drain region 113. At the same time, the second polysilicon layer 110 is doped to form an N-type polysilicon layer as the control gate 114, and finally a vertical-gate structure semi-floating gate transistor is formed. The obtained structure is as shown in Figure 12 shown.

[0023] As Figure 12 shown, a vertical-gate storage device structure of the present invention includes: a substrate, which is formed with a P-well region 100, an N-well region 102, and a U-shaped groove. Among them, the N-well region 102 is located above the P-well region 100, and the U-shaped groove penetrates through the N-well region 102; a first gate oxide layer 105, which is formed on the surface of the U-shaped groove and extends to cover a part of the surface of the N-well region 102, and windows are formed at the sidewalls of the U-shaped groove and the surface of the N-well region 102; a semi-floating gate 107, which is formed in the U-shaped groove, covers the first gate oxide layer 105, and is in contact with the N-well region 102 at the windows; a control gate dielectric layer includes a third silicon oxide layer 108 and a third silicon nitride layer 109, which are formed in the U-shaped groove, cover the semi-floating gate 107 and extend to cover the first gate oxide layer 105; a control gate 114, which covers the control gate dielectric layer and completely fills the U-shaped groove; a source region 112 and a drain region 113, which are respectively formed in the N-well region 102 on both sides of the control gate 114.

[0024] Different from the planar gate structure of the traditional semi-floating gate transistor, the vertical-gate storage device structure of the present invention uses the PMOS transistor parasitic on the sidewall of the U-shaped groove for programming. Both the control gate and the semi-floating gate of the device are placed in the U-shaped groove, increasing the gate dielectric capacitance coupling area between the control gate and the semi-floating gate, improving the utilization efficiency of the control gate voltage, helping to reduce the gate operating voltage, and improving the programming efficiency and retention characteristics of the device. At the same time, it is also beneficial to miniaturize the cell size of the device and increase the integration density of the device.

[0025] The above is only the specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A vertical gate memory device structure, characterized in that, It includes: A substrate, which is formed with a P-well region, an N-well region and a U-shaped groove, wherein the N-well region is located above the P-well region, and the U-shaped groove penetrates the N-well region; A first gate oxide layer is formed on the surface of the U-shaped groove and extends to cover part of the surface of the N-well region, and windows are formed on the side wall of the U-shaped groove and the surface of the N-well region; A semi-floating gate is formed in the U-shaped groove, covering the first gate oxide layer, and is in contact with the N-well region at the window; A control gate dielectric layer is formed in the U-shaped groove, covering the semi-floating gate and extending to cover part of the first gate oxide layer; A control gate covers the control gate dielectric layer and completely fills the U-shaped groove; Source regions and drain regions are respectively formed on both sides of the control gate, in the N-well region, Programming is performed using the PMOS transistor parasitic on the side wall of the U-shaped groove.

2. The vertical gate memory device structure according to claim 1, characterized in that, The semi-floating gate is made of P-type polysilicon, and the control gate is made of N-type polysilicon.

3. A method for manufacturing a vertical gate memory device structure, characterized in that, It includes the following steps: Form a P-well region and an N-well region in the device manufacturing region of the substrate, and the N-well region is located above the P-well region; Etch to form a U-shaped groove so that the U-shaped groove penetrates the N-well region; Form a first gate oxide layer, and then perform etching to form windows on the side wall of the U-shaped groove and the surface of the N-well region; Form a P-type polysilicon layer in the U-shaped groove, so that it covers the first gate oxide layer and completely fills the U-shaped groove, and is in contact with the N-well region at the window; Perform photolithography and etching on the P-type polysilicon layer to form the semi-floating gate and the manufacturing region of the control gate; Form a control gate dielectric layer in the U-shaped groove, covering the semi-floating gate and extending to cover part of the first gate oxide layer; Form a polysilicon layer, so that it covers the control gate dielectric layer and completely fills the U-shaped groove; Perform edge etching to expose the surfaces of part of the N-well region on both sides of the control gate, and perform N-type ion implantation to form the control gate, source regions and drain regions, Programming is performed using the PMOS transistor parasitic on the side wall of the U-shaped groove.

4. The method for manufacturing a vertical gate memory device structure according to claim 3, characterized in that, The specific steps for forming the window include: Deposit a silicon nitride layer on the first gate oxide layer to fill the U-shaped groove; Dry etch to remove part of the silicon nitride layer to expose the first gate oxide layer on the side wall and the upper surface on one side of the U-shaped groove; Wet etch to remove the exposed first gate oxide layer to form a window, and then isotropically etch to remove the silicon nitride layer.

5. The method for manufacturing a vertical gate memory device structure according to claim 3, characterized in that, Dry oxidation method is used to form silicon oxide as the first layer of gate oxide layer.

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