Rs485 protection component, transmitting driver and transceiver

Abstract

The application discloses an RS485 protection assembly, a sending driver and a transceiver, wherein the RS485 protection assembly is provided with a detection circuit and a protection signal generation circuit, detects RS485 voltage through the detection circuit, and outputs a first voltage signal when the voltage is higher than a preset first voltage and outputs a second voltage signal when the voltage is lower than a preset second voltage, so that the protection signal generation circuit can output a protection signal according to the first voltage signal or the second voltage signal, so that the A / B pin driving circuit is turned off after receiving the protection signal, thereby effectively protecting the A / B pin driving circuit, and enabling the A / B pin driving circuit adopting a low-voltage gate process to withstand high voltage.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit design, and particularly relates to an RS485 protection assembly, a sending driver and a transceiver. BACKGROUND

[0002] RS485 is a low-cost and reliable communication specification, which can be used in application fields such as networking of electric meter systems, and the RS485 interface defines the electrical characteristics of the corresponding interface. In the existing RS485 transceiver, the input voltage range of the A port and the B port of the transmitter circuit is usually + / -13V, and it is necessary to consider whether the gate of the MOS tube in the driving circuit can directly withstand high voltage.

[0003] The MOS tube of the current driving circuit is usually designed by using an HVCMOS (High-Voltage CMOS) process, and the gate thereof can directly withstand a relatively high voltage. However, in view of the chip manufacturing cost, a high-voltage process with a smaller line width needs to be used. With the evolution of the high-voltage process to a smaller line width, especially to 0.18um process and below, the high-voltage gate no longer supports thick gate oxide, but is changed to a low-voltage gate process with thin gate oxide. For example, in the commonly used 0.18um HVBCD (a kind of monolithic integrated process technology) process, the VDS (drain-source voltage) of the high-voltage MOS tube can withstand high voltage, but the VGS (gate-source voltage) can only withstand a maximum working voltage of 5.5V. Therefore, it is necessary to design a driving circuit suitable for a low-voltage gate process. SUMMARY

[0004] The present application aims to solve the technical problem that the MOS tube in the driving circuit of the RS485 in the prior art cannot withstand high voltage, and provides an RS485 protection assembly, a sending driver and a transceiver.

[0005] The present application solves the above technical problem by the following technical scheme:

[0006] The present application provides an RS485 protection assembly for protecting the A / B pin driving circuit of an RS485 chip. The RS485 protection assembly comprises a detection circuit and a protection signal generation circuit. The RS485 chip comprises an A pin and a B pin, and the A pin and the B pin are used to connect an RS485 bus.

[0007] One end of the detection circuit is used to connect the RS485 bus, and the other end of the detection circuit is connected with one end of the protection signal generation circuit. The other end of the protection signal generation circuit is used to connect the A / B pin driving circuit.

[0008] The detection circuit is configured to detect the voltage of the RS485 bus, output a first voltage signal when the voltage of the RS485 bus is higher than a preset first voltage, and output a second voltage signal when the voltage of the RS485 bus is lower than a preset second voltage.

[0009] The protection signal generation circuit is configured to receive the first voltage signal or the second voltage signal, and output a protection signal according to the first voltage signal or the second voltage signal, so that the A / B pin driving circuit is turned off after receiving the protection signal.

[0010] Preferably, the detection circuit comprises a first comparison voltage generation sub-circuit, a first reference voltage generation sub-circuit, and a first comparison sub-circuit.

[0011] The input end of the first comparison voltage generation sub-circuit is connected with the RS485 bus, the output end of the first comparison voltage generation sub-circuit is connected with the positive input end of the first comparison sub-circuit, the input end of the first reference voltage sub-circuit is connected with a power supply, and the output end of the first reference voltage sub-circuit is connected with the negative input end of the first comparison sub-circuit.

[0012] The first comparison voltage generation sub-circuit is configured to output a first comparison voltage when the voltage of the RS485 bus is higher than the preset first voltage.

[0013] The first reference voltage generation sub-circuit is configured to output a first reference voltage.

[0014] The first comparison sub-circuit is configured to compare the first comparison voltage and the first reference voltage, and output the first voltage signal when the first comparison voltage is greater than the first reference voltage.

[0015] The detection circuit further comprises a second comparison voltage generation sub-circuit, a second reference voltage generation sub-circuit, and a second comparison sub-circuit.

[0016] The input end of the second comparison voltage generation sub-circuit is connected with the RS485 bus, the output end of the second comparison voltage generation sub-circuit is connected with the negative input end of the second comparison sub-circuit, the input end of the second reference voltage generation sub-circuit is connected with a power supply, and the output end of the second reference voltage generation sub-circuit is connected with the positive input end of the second comparison sub-circuit.

[0017] The second comparison voltage generation sub-circuit is configured to output a second comparison voltage when the voltage of the RS485 bus is lower than the preset second voltage.

[0018] The second reference voltage generation sub-circuit is configured to output a second reference voltage.

[0019] The second comparison sub-circuit is configured to compare the second comparison voltage and the second reference voltage, and output the second voltage signal when the second comparison voltage is less than the second reference voltage.

[0020] Preferably, the first comparison voltage generating sub-circuit comprises a first PMOS transistor, a second PMOS transistor, a sixth NMOS transistor, a first resistor and a first current source.

[0021] The first reference voltage generating sub-circuit comprises a third PMOS transistor, a fourth PMOS transistor and a second current source.

[0022] The first comparison sub-circuit comprises a first comparator.

[0023] One end of the first current source is connected to the drain and gate of the first PMOS transistor, the gate of the second PMOS transistor and the drain of the sixth NMOS transistor, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the RS485 bus through the first resistor, the source of the sixth NMOS transistor is connected to the positive input terminal of the first comparator, one end of the second current source is connected to the drain and gate of the third PMOS transistor, the gate of the fourth PMOS transistor and the negative input terminal of the first comparator, the source of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the fourth PMOS transistor and the gate of the sixth NMOS transistor are connected to a power supply, the other end of the first current source and the other end of the second current source are grounded, and the output terminal of the first comparator outputs a first voltage signal.

[0024] The second comparison voltage generating sub-circuit comprises a first NMOS transistor, a second NMOS transistor, a fifth NMOS transistor, a second resistor and a third current source.

[0025] The second reference voltage generating sub-circuit comprises a third NMOS transistor, a fourth NMOS transistor and a fourth current source, and the second comparison sub-circuit comprises a second comparator.

[0026] One end of the third current source is connected with the drain and gate of the first NMOS tube, the gate of the second NMOS tube and the drain of the fifth NMOS tube respectively, the source of the first NMOS tube is connected with the source of the second NMOS tube, the drain of the second NMOS tube is connected with the RS485 bus through the second resistance, the source of the fifth NMOS tube is connected with the negative input end of the second comparator, one end of the third current source is connected with the drain and gate of the third NMOS tube, the gate of the fourth NMOS tube and the positive input end of the second comparator respectively, the source of the third NMOS tube is connected with the source of the fourth NMOS tube, the drain of the fourth NMOS tube and the gate of the fifth NMOS tube are grounded, the other end of the third current source and the other end of the fourth current source are connected with the power supply respectively, and the output end of the second comparator outputs the second voltage signal.

[0027] Preferably, the protection signal generating circuit comprises a first protection signal generating sub-circuit and a second protection signal generating sub-circuit.

[0028] The input end of the first protection signal generating sub-circuit and the input end of the second protection signal generating sub-circuit are connected with the other end of the detection circuit respectively, and the output end of the first protection signal generating sub-circuit and the output end of the second protection signal generating sub-circuit are connected with the A / B foot driving circuit respectively.

[0029] The first protection signal generating sub-circuit comprises a first level conversion unit, which is used for detecting the level state of the first voltage signal, outputting a low level signal when the first voltage signal is a low level, and outputting a high level signal when the first voltage signal is a high level.

[0030] The second protection signal generating sub-circuit comprises a second level conversion unit, which is used for detecting the level state of the second voltage signal, outputting a high level signal when the second voltage signal is a low level, and outputting a low level signal when the second voltage signal is a high level.

[0031] Preferably, the first protection signal generating sub-circuit further comprises a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a third resistance, a first inverter, a second inverter and a fifth current source.

[0032] The other end of the detection circuit is connected with the gate of the fifth PMOS, the input end of the first inverter, the gate of the seventh NMOS, the input end of the second inverter respectively, the output end of the first inverter is connected with the input end of the first level conversion unit, the output end of the first level conversion unit is connected with the gate of the sixth PMOS, the source of the fifth PMOS is connected with the power supply, the drain of the fifth PMOS is connected with the drain of the sixth PMOS, the source of the sixth PMOS is connected with the drain of the seventh NMOS, one end of the third resistance, the drain of the eighth PMOS, the drain of the ninth NMOS respectively, the source of the seventh NMOS and the other end of the third resistance are grounded;

[0033] The drain of the seventh PMOS is connected with the RS485 bus, the source of the seventh PMOS is connected with the source of the eighth PMOS, the gate of the seventh PMOS is connected with the gate and the drain of the eighth PMOS, the source of the eighth PMOS outputs the first protection signal to the A / B foot driving circuit to make the A / B foot driving circuit off;

[0034] One end of the fifth current source is connected with the drain and the gate of the eighth NMOS, the gate of the ninth NMOS, the drain of the tenth NMOS respectively, the output end of the second inverter is connected with the gate of the tenth NMOS, the source of the eighth NMOS, the source of the ninth NMOS and the source of the tenth NMOS are grounded, the other end of the fifth current source is connected with the power supply.

[0035] Preferably, the first protection signal generating sub-circuit further comprises a first capacitor and a fourth resistance;

[0036] One end of the first capacitor is connected with the first output end of the detection circuit, the other end of the first capacitor is connected with one end of the fourth resistance and the gate of the seventh NMOS, the other end of the fourth resistance is grounded.

[0037] Preferably, the second protection signal generating sub-circuit further comprises a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS, a fifteenth NMOS, an eleventh PMOS, a twelfth PMOS, a thirteenth PMOS, a fourteenth PMOS, a fifth resistance, a third inverter, a fourth inverter, a sixth current source;

[0038] Another end of the detection circuit is connected with the gate of the eleventh PMOS, the input end of the third inverter, the input end of the second level conversion unit, the input end of the fourth inverter respectively, the output end of the fourth inverter is connected with the gate of the thirteenth NMOS, the source of the thirteenth NMOS is grounded, the drain of the thirteenth NMOS is connected with the drain of the twelfth NMOS, the gate of the twelfth NMOS is connected with the output end of the second level conversion unit, the source of the twelfth NMOS is connected with the drain of the twelfth PMOS, one end of the fifth resistor, the drain of the fourteenth PMOS and the drain of the fourteenth NMOS respectively, the gate of the twelfth PMOS is connected with the output end of the third inverter, the source of the twelfth PMOS and the other end of the fifth resistor are connected with the power supply;

[0039] The drain of the fifteenth NMOS is connected with the RS485 bus, the source of the fifteenth NMOS is connected with the source of the fourteenth NMOS, the gate of the fifteenth NMOS is connected with the gate and the drain of the fourteenth NMOS, and the drain of the fourteenth NMOS outputs the second protection signal to the A / B foot driving circuit to make the A / B foot driving circuit off;

[0040] One end of the sixth current source is connected with the drain and the gate of the thirteenth PMOS, the gate of the fourteenth PMOS and the drain of the eleventh PMOS respectively, the source of the eleventh PMOS, the source of the thirteenth PMOS and the source of the fourteenth PMOS are connected with the power supply, and the other end of the sixth current source is grounded.

[0041] Preferably, the second protection signal generation sub-circuit further comprises a second capacitor and a sixth resistor;

[0042] One end of the second capacitor is connected with the output end of the third inverter, the other end of the second capacitor is connected with one end of the sixth resistor and the gate of the twelfth PMOS, and the other end of the sixth resistor is grounded.

[0043] Preferably, the first level conversion unit comprises a ninth PMOS, a tenth PMOS and an eleventh NMOS;

[0044] The output end of the first inverter is connected with the gate of the ninth PMOS and the gate of the eleventh NMOS respectively, the source of the ninth PMOS is connected with a power supply, the drain of the ninth PMOS is connected with the drain of the tenth PMOS, the drain of the eleventh NMOS is connected with the gate and the source of the tenth PMOS and the gate of the sixth PMOS respectively, and the source of the eleventh NMOS is grounded.

[0045] Preferably, the second level conversion unit comprises a fifteenth PMOS, a sixteenth PMOS and a sixteenth NMOS.

[0046] The second output end of the detection circuit is connected with the gate of the fifteenth PMOS and the gate of the sixteenth NMOS respectively, the source of the fifteenth PMOS is connected with a power supply, the drain of the fifteenth PMOS is connected with the drain of the sixteenth PMOS and the gate of the twelfth NMOS respectively, the drain of the sixteenth NMOS is connected with the gate and the source of the sixteenth PMOS respectively, and the source of the sixteenth NMOS is grounded.

[0047] The application further provides an RS485 sending driver, wherein the RS485 driving module comprises a driving circuit and an RS485 protection assembly as described above.

[0048] The RS485 protection assembly is connected with the input end of the driving circuit, and the output end of the driving circuit is connected with the RS485 bus.

[0049] The driving circuit is used for being turned off when the first voltage signal or the second voltage signal sent by the RS485 protection assembly is received.

[0050] Preferably, the driving circuit comprises a P channel and an N channel.

[0051] The P channel comprises a seventeenth PMOS, an eighteenth PMOS, a nineteenth PMOS and a twentieth PMOS.

[0052] The N channel comprises a seventeenth NMOS, an eighteenth NMOS, a nineteenth NMOS and a twentieth NMOS.

[0053] The drain of the seventeenth PMOS is connected with a power supply, the gate of the seventeenth PMOS is connected with the drain of the eighteenth PMOS, the source of the seventeenth PMOS is connected with the source of the eighteenth PMOS, the source of the nineteenth PMOS and the source of the twentieth PMOS respectively, the gate of the nineteenth PMOS is connected with the drain of the twentieth PMOS.

[0054] The gate of the eighteenth PMOS tube and the gate of the twentieth PMOS tube are connected with the RS485 protection component, the gate of the nineteenth PMOS tube is also connected with the data end of the RS485 chip, the source of the nineteenth PMOS tube is also connected with the RS485 bus, and the gate of the seventeenth PMOS tube is also connected with the RS485 protection component.

[0055] The drain of the nineteenth NMOS tube is grounded, the gate of the nineteenth NMOS tube is connected with the drain of the twentieth NMOS tube, the source of the nineteenth NMOS tube is connected with the source of the twentieth NMOS tube, the source of the seventeenth NMOS tube and the source of the eighteenth NMOS tube respectively, and the gate of the seventeenth NMOS tube is connected with the drain of the eighteenth NMOS tube.

[0056] The gate of the twentieth NMOS tube and the gate of the eighteenth NMOS tube are connected with the RS485 protection component, the gate of the seventeenth NMOS tube is also connected with the data end of the RS485 chip, the source of the seventeenth NMOS tube is also connected with the RS485 bus, and the gate of the nineteenth NMOS tube is also connected with the RS485 protection component.

[0057] The application further provides an RS485 transceiver, which comprises:

[0058] The RS485 sending driver as described above; and,

[0059] The RS485 transceiver.

[0060] The positive progress effect of the application is that: by setting the detection circuit and the protection signal generating circuit, the RS485 voltage is detected by the detection circuit, the first voltage signal is outputted when being higher than the preset first voltage, and the second voltage signal is outputted when being lower than the preset second voltage, so that the protection signal generating circuit can output the protection signal according to the first voltage signal or the second voltage signal, so that the A / B foot driving circuit is turned off after receiving the protection signal, thereby effectively protecting the A / B foot driving circuit, and the A / B foot driving circuit adopting the low-voltage gate process can also withstand high voltage. BRIEF DESCRIPTION OF DRAWINGS

[0061] Figure 1 It is a schematic block diagram of the RS485 protection component of the embodiment 1 of the application.

[0062] Figure 2 It is a schematic block diagram of the detection circuit of the RS485 protection component of the embodiment 1 of the application.

[0063] Figure 3A schematic block diagram of a protection signal generation circuit of the RS485 protection assembly of embodiment 1 of the present application.

[0064] Figure 4 A circuit connection diagram of a detection circuit of the RS485 protection assembly of embodiment 1 of the present application.

[0065] Figure 5 A circuit connection diagram of a first protection signal generation sub-circuit of the RS485 protection assembly of embodiment 1 of the present application.

[0066] Figure 6 A circuit connection diagram of a second protection signal generation sub-circuit of the RS485 protection assembly of embodiment 1 of the present application.

[0067] Figure 7 A schematic block diagram of the RS485 sending driver of embodiment 2 of the present application.

[0068] Figure 8 A circuit connection diagram of a driving circuit of the RS485 sending driver of embodiment 2 of the present application. DETAILED DESCRIPTION

[0069] The present application will be further described below by way of examples, but the present application is not limited in scope to the examples described.

[0070] Embodiment 1

[0071] The present embodiment provides a RS485 protection assembly for protecting an A / B pin driving circuit of a RS485 chip, the RS485 chip comprising an A pin and a B pin, the A pin and the B pin being used for connecting a RS485 bus, as shown in Figure 1 The RS485 protection assembly of the present embodiment comprises a detection circuit 1 and a protection signal generation circuit 2. One end of the detection circuit 1 is used for connecting the RS485 bus (i.e. A / B line), the other end of the detection circuit 1 is connected with one end of the protection signal generation circuit 2, and the other end of the protection signal generation circuit 2 is used for connecting the A / B pin driving circuit.

[0072] In the present embodiment, the detection circuit 1 is used for detecting the voltage of the RS485 bus, and outputs a first voltage signal when the voltage of the RS485 bus is higher than a preset first voltage, and outputs a second voltage signal when the voltage of the RS485 bus is lower than a preset second voltage; the protection signal generation circuit 2 is used for receiving the first voltage signal or the second voltage signal, and outputs a protection signal according to the first voltage signal or the second voltage signal, so as to turn off the A / B pin driving circuit after receiving the protection signal.

[0073] In an alternative embodiment, referring to Figure 2The detection circuit 1 comprises a first comparison voltage generating sub-circuit 101, a first reference voltage generating sub-circuit 102 and a first comparison sub-circuit 103.

[0074] Specifically, the input end of the first comparison voltage generating sub-circuit 101 is connected with the RS485 bus, the output end of the first comparison voltage generating sub-circuit 101 is connected with the positive input end of the first comparison sub-circuit 103, the input end of the first reference voltage sub-circuit 102 is connected with the power supply, and the output end of the first reference voltage sub-circuit 102 is connected with the negative input end of the first comparison sub-circuit 103.

[0075] The first comparison voltage generating sub-circuit 101 is configured to output a first comparison voltage when the voltage of the RS485 bus is higher than a preset first voltage, the first reference voltage generating sub-circuit 102 is configured to output a first reference voltage, and the first comparison sub-circuit 103 is configured to compare the first comparison voltage and the first reference voltage, and output a first voltage signal when the first comparison voltage is greater than the first reference voltage. The first voltage signal is low by default, and the first voltage signal output by the detection circuit 1 is a high signal when the voltage of the RS485 bus is higher than the preset first voltage. Of course, the state of the first voltage is not limited to this, and other level states are also possible.

[0076] In an alternative embodiment, the detection circuit 1 further comprises a second comparison voltage generating sub-circuit 104, a second reference voltage generating sub-circuit 105 and a second comparison sub-circuit 106.

[0077] Specifically, the input end of the second comparison voltage generating sub-circuit 104 is connected with the RS485 bus, the output end of the second comparison voltage generating sub-circuit 104 is connected with the negative input end of the second comparison sub-circuit 106, the input end of the second reference voltage generating sub-circuit 105 is connected with the power supply, and the output end of the second reference voltage generating sub-circuit 105 is connected with the positive input end of the second comparison sub-circuit 106.

[0078] The second comparison voltage generating sub-circuit 104 is configured to output a second comparison voltage when the voltage of the RS485 bus is lower than a preset second voltage, the second reference voltage generating sub-circuit 105 is configured to output a second reference voltage, and the second comparison sub-circuit 106 is configured to compare the second comparison voltage and the second reference voltage, and output a second voltage signal when the second comparison voltage is less than the second reference voltage. The second voltage signal is low by default, and the first voltage signal output by the detection circuit 1 is a high signal when the voltage of the RS485 bus is less than the preset second voltage. Of course, the state of the first voltage is not limited to this, and other level states are also possible.

[0079] In an alternative embodiment, referring to Figure 3The protection signal generating circuit 2 comprises a first protection signal generating sub-circuit 201 and a second protection signal generating sub-circuit 202.

[0080] Specifically, the input end of the first protection signal generating sub-circuit 201 and the input end of the second protection signal generating sub-circuit 202 are connected with the other end of the detection circuit 1 respectively, and the output end of the first protection signal generating sub-circuit 201 and the output end of the second protection signal generating sub-circuit 202 are connected with the A / B foot driving circuit and output protection signals respectively. The protection signals comprise a first protection signal PD_SD and a second protection signal ND_SD. When the first voltage signal is at a low level, the first protection signal PD_SD output by the first protection signal generating sub-circuit 201 is at a high level, and when the first voltage signal is at a high level, the first protection signal ND_SD output by the first protection signal generating sub-circuit 201 is at a low level. When the second voltage signal is at a low level, the first protection signal ND_SD output by the second protection signal generating sub-circuit 202 is at a low level, and when the second voltage signal is at a high level, the second protection signal ND_SD output by the second protection signal generating sub-circuit 202 is at a high level.

[0081] The first protection signal generating sub-circuit 201 comprises a first level conversion unit 2011, which is used for detecting the level state of the first voltage signal and outputting a low level signal when the first voltage signal is at a low level and outputting a high level signal when the first voltage signal is at a high level. The second protection signal generating sub-circuit 202 comprises a second level conversion unit 2021, which is used for detecting the level state of the second voltage signal and outputting a high level signal when the second voltage signal is at a low level and outputting a low level signal when the second voltage signal is at a high level.

[0082] In the embodiment, for convenience of description, the preset first voltage is set to 5.5V and the preset second voltage is set to -1V. Of course, the preset first voltage and the preset second voltage are not limited to this. For example, the preset first voltage is set to 6V and the preset second voltage is set to -2V. 0-5V or 0-3.3V is the normal working range of the A / B foot driving circuit, and other voltage ranges are also available, which are not limited.

[0083] The port voltage of the A / B foot driving circuit is within the range of 0-5V, and the GP_T node in the A / B foot driving circuit is at a low level and the GN_L node is at a high level.

[0084] The circuit connection of the detection circuit 1 is described in detail as follows.

[0085] For example, the detection circuit 1 comprises a first detection sub-circuit 101 and a second detection sub-circuit 102. Figure 4As shown, the first comparison voltage generating sub-circuit 201 comprises a first PMOS M10, a second PMOS M9, a sixth NMOS M14, a first resistor R2 and a first current source I1, the first reference voltage generating sub-circuit 102 comprises a third PMOS M12, a fourth PMOS M11 and a second current source I2, and the first comparison sub-circuit 103 comprises a first comparator 302.

[0086] One end of the first current source I1 is connected to the drain and gate of the first PMOS M10, the gate of the second PMOS M9 and the drain of the sixth NMOS M14, the source of the first PMOS M10 is connected to the source of the second PMOS M9, the drain of the second PMOS M9 is connected to the RS485 bus through the first resistor R2, the source of the sixth NMOS M14 is connected to the positive input terminal of the first comparator 302, one end of the second current source I2 is connected to the drain and gate of the third PMOS M12, the gate of the fourth PMOS M11 and the negative input terminal of the first comparator 302, the source of the third PMOS M12 is connected to the source of the fourth PMOS M11, the drain of the fourth PMOS M11 and the gate of the sixth NMOS M14 are connected to the power supply, the other end of the first current source I1 and the other end of the second current source I2 are grounded, and the output terminal of the first comparator 302 outputs the first voltage signal.

[0087] The second comparison voltage generating sub-circuit 104 comprises a first NMOS M5, a second NMOS M6, a fifth NMOS M13, a second resistor R1 and a third current source I3, the second reference voltage generating sub-circuit 105 comprises a third NMOS M7, a fourth NMOS M8 and a fourth current source I4, and the second comparison sub-circuit 106 comprises a second comparator 301.

[0088] One end of the third current source I3 is connected to the drain and gate of the first NMOS M5, the gate of the second NMOS M6 and the drain of the fifth NMOS M13, the source of the first NMOS M5 is connected to the source of the second NMOS M6, the drain of the second NMOS M6 is connected to the RS485 bus through the second resistor R1, the source of the fifth NMOS M13 is connected to the negative input terminal of the second comparator 301, one end of the third current source I3 is connected to the drain and gate of the third NMOS M7, the gate of the fourth NMOS M8 and the positive input terminal of the second comparator 301, the source of the third NMOS M7 is connected to the source of the fourth NMOS M8, the drain of the fourth NMOS M8 and the gate of the fifth NMOS M13 are grounded, the other end of the third current source I3 and the other end of the fourth current source I4 are connected to the power supply, and the output terminal of the second comparator 301 outputs the second voltage signal.

[0089] The following describes three working conditions of the detection circuit 1 in combination with Figure 4

[0090] (1) When the voltage of the A / B pin of the RS485 chip is in the range of 0-5V, the voltage of node F is higher than that of node E, so the second comparator 301 outputs a low level; the first NMOS tube M5, the second NMOS tube M6, the third NMOS tube M7 and the fourth NMOS tube M8 are in a mirror size relationship, and the first NMOS tube M5 and the second NMOS tube M6 are in a back-to-back diode connection, so when the A / B pin is at a high voltage, the second comparison voltage generating sub-circuit will not be turned on, and the gate of the fifth NMOS tube M13 is grounded to clamp the voltage of node F.

[0091] (2) When the voltage of the A / B pin of the RS485 chip is lower than the preset second voltage, the voltage of node F is lower than that of node E, so the second voltage signal BELOW_0V output by the second comparator 301 becomes high.

[0092] (3) When the voltage of the A / B pin of the RS485 chip is higher than the preset first voltage, the voltage of node G is higher than that of node H, so the first voltage signal OVER_5V output by the first comparator 302 becomes high.

[0093] The following specifically describes the circuit connection of the first protection signal generating sub-circuit 201 in the protection signal generating circuit 2:

[0094] As shown in Figure 5 , the first protection signal generating sub-circuit 201 further includes a fifth PMOS tube M19, a sixth PMOS tube M20, a seventh PMOS tube M21, an eighth PMOS tube M22, a seventh NMOS tube M18, an eighth NMOS tube M27, a ninth NMOS tube M28, a tenth NMOS tube M29, a third resistor R4, a first inverter 401, a second inverter 402 and a fifth current source I5.

[0095] ​The other end of the detection circuit 1 is connected with the gate of the fifth PMOS M19, the input of the first inverter, the gate of the seventh NMOS M18, and the input of the second inverter 402, respectively. The output of the first inverter is connected with the input of the first level conversion unit 2011. The output of the first level conversion unit 2011 is connected with the gate of the sixth PMOS M20. The source of the fifth PMOS M19 is connected with the power supply. The drain of the fifth PMOS M19 is connected with the drain of the sixth PMOS M20. The source of the sixth PMOS M20 is connected with the drain of the seventh NMOS M18, one end of the third resistor R4, the drain of the eighth PMOS M22, and the drain of the ninth NMOS M28, respectively. The source of the seventh NMOS M18 and the other end of the third resistor R4 are grounded.

[0096] The drain of the seventh PMOS M21 is connected with the RS485 bus. The source of the seventh PMOS M21 is connected with the source of the eighth PMOS M22. The gate of the seventh PMOS M21 is connected with the gate and the drain of the eighth PMOS M22. The source of the eighth PMOS M22 outputs the first protection signal to the A / B foot driving circuit to make the A / B foot driving circuit off.

[0097] One end of the fifth current source I5 is connected with the drain and the gate of the eighth NMOS M27, the gate of the ninth NMOS M28, and the drain of the tenth NMOS M29, respectively. The output of the second inverter 402 is connected with the gate of the tenth NMOS M29. The source of the eighth NMOS M27, the source of the ninth NMOS M28, and the source of the tenth NMOS M29 are grounded. The other end of the fifth current source I5 is connected with the power supply.

[0098] Optionally, the first level conversion unit 2011 comprises the ninth PMOS M15, the tenth PMOS M16, and the eleventh NMOS M17.

[0099] The output of the first inverter 401 is connected with the gate of the ninth PMOS M15 and the gate of the eleventh NMOS M17, respectively. The source of the ninth PMOS M15 is connected with the power supply. The drain of the ninth PMOS M15 is connected with the drain of the tenth PMOS M16. The drain of the eleventh NMOS M17 is connected with the gate and the source of the tenth PMOS M16 and the gate of the sixth PMOS M20, respectively. The source of the eleventh NMOS M17 is grounded. The drain of the eleventh NMOS M17 and the source of the tenth PMOS M16 form a node GP_T.

[0100] In a preferred embodiment, in order to enable the first protection signal generating sub-circuit 201 to respond quickly when the A / B pin sees a high voltage, a fast pull-down path is provided, i.e. the first protection signal generating sub-circuit 201 further comprises a first capacitor C1 and a fourth resistor R3. Specifically, one end of the first capacitor C1 is connected to the first output end of the detection circuit 1, the other end of the first capacitor C1 is connected to one end of the fourth resistor R3 and the gate of the seventh NMOS transistor M18, and the other end of the fourth resistor R3 is grounded.

[0101] The following describes three working conditions of the first protection signal generating sub-circuit 201 in combination with Figure 5

[0102] (1) When the voltage of the A / B pin of the RS485 chip is a negative voltage (less than 0V), the circuit composed of the seventh PMOS transistor M21 and the eighth PMOS transistor M22 will not be turned on, and the back-to-back connection of the substrate parasitic diodes of the seventh PMOS transistor M21 and the eighth PMOS transistor M22 has no path, and the gate is diode-connected, which ensures that the seventh PMOS transistor M21 and the eighth PMOS transistor M22 will not be damaged by a high voltage signal, and finally the A / B pin can be disconnected from the first protection signal generating sub-circuit 201.

[0103] (2) When the voltage of the A / B pin of the RS485 chip is lower than the preset first voltage in the detection circuit 1, the first voltage signal OVER_5V is a low-level logic, so that the node GP_T is also low, and then the fifth PMOS transistor M19 and the sixth PMOS transistor M20 are turned on, at this time the node I is low, and the seventh NMOS transistor M18 is turned off; when the third resistor R4 is set to a large resistance, the first protection signal PD_SD output by the node O is pulled up to VDD, at this time, part of the PMOS transistors in the A / B pin driving circuit are disconnected, and the PMOS transistors used for output can work normally.

[0104] (3) When the voltage of the A / B pin of the RS485 chip is higher than the preset first voltage in the detection circuit 1, the first voltage signal OVER_5V is flipped to a high-level logic, so that the node GP_T is also flipped to high, and then the fifth PMOS transistor M19 and the sixth PMOS transistor M20 are disconnected, and the tenth NMOS transistor M29 is disconnected, so that the current source composed of the eighth NMOS transistor M27 and the ninth NMOS transistor M28 works normally, and together with the seventh PMOS transistor M21 and the eighth PMOS transistor M22, it sets the first protection signal PD_SD to reduce the voltage of the A / B pin by one voltage value, ensuring that the PMOS transistor used for output is turned on, and at the same time ensuring that the gate voltage VGS is within a safe range.

[0105] ​The circuit connection of the second protection signal generating sub-circuit 202 in the protection signal generating circuit 2 is described in detail below:

[0106] like Figure 6 As shown, the second protection signal generating sub-circuit 202 further includes a twelfth NMOS transistor M37, a thirteenth NMOS transistor M38, a fourteenth NMOS transistor M39, a fifteenth NMOS transistor M40, an eleventh PMOS transistor M30, a twelfth PMOS transistor M33, a thirteenth PMOS transistor M31, a fourteenth PMOS transistor M32, a fifth resistor R6, a third inverter 501, a fourth inverter 502, and a sixth current source I6.

[0107] The other end of the detection circuit 1 is respectively connected to the gate of the eleventh PMOS transistor M30, the input end of the third inverter 501, the input end of the second level conversion unit 2021, and the input end of the fourth inverter 502. The output end of the fourth inverter 502 is connected to the gate of the thirteenth NMOS transistor M38. The source of the thirteenth NMOS transistor M38 is grounded. The drain of the thirteenth NMOS transistor M38 is connected to the drain of the twelfth NMOS transistor M37. The gate of the twelfth NMOS transistor M37 is connected to the output end of the second level conversion unit 2021. The source of the twelfth NMOS transistor M37 is respectively connected to the drain of the twelfth PMOS transistor M33, one end of the fifth resistor R6, the drain of the fourteenth PMOS transistor M32, and the drain of the fourteenth NMOS transistor M39. The gate of the twelfth PMOS transistor M33 is connected to the output end of the third inverter 501. The source of the twelfth PMOS transistor M33 and the other end of the fifth resistor R6 are connected to the power supply.

[0108] The drain of the fifteenth NMOS transistor M40 is connected to the RS485 bus, the source of the fifteenth NMOS transistor M40 is connected to the source of the fourteenth NMOS transistor M39, the gate of the fifteenth NMOS transistor M40 is connected to the gate and drain of the fourteenth NMOS transistor M39, and the drain of the fourteenth NMOS transistor M39 outputs a second protection signal to the A / B pin drive circuit to shut down the A / B pin drive circuit.

[0109] One end of the sixth current source I6 is respectively connected to the drain and gate of the thirteenth PMOS transistor M31, the gate of the fourteenth PMOS transistor M32, and the drain of the eleventh PMOS transistor. The source of the eleventh PMOS transistor M30, the source of the thirteenth PMOS transistor M31, and the source of the fourteenth PMOS transistor M32 are connected to the power supply. The other end of the sixth current source I6 is grounded.

[0110] Optionally, the second level conversion unit 2021 includes a fifteenth PMOS transistor M34, a sixteenth PMOS transistor M35, and a sixteenth NMOS transistor M36.

[0111] The second output end of the detection circuit 1 is connected with the gate of the fifteenth PMOS M34 and the gate of the sixteenth NMOS M36 respectively, the source of the fifteenth PMOS M34 is connected with a power supply, the drain of the fifteenth PMOS M34 is connected with the drain of the sixteenth PMOS M35 and the gate of the twelfth NMOS M37 respectively, the drain of the sixteenth NMOS M36 is connected with the gate and the source of the sixteenth PMOS respectively, and the source of the sixteenth NMOS M36 is grounded. The drain of the fifteenth PMOS M34 and the drain of the sixteenth PMOS M35 form a node GN_L.

[0112] In a preferred embodiment, in order to enable the second protection signal generation sub-circuit 202 to respond quickly when a high voltage is seen at the A / B pin, a fast pull-up path is provided, that is, the second protection signal generation sub-circuit 202 further includes a second capacitor C2 and a sixth resistor R5. Specifically, one end of the second capacitor C2 is connected with the output end of the third inverter 501, the other end of the second capacitor C2 is connected with the gate of the twelfth PMOS M33 and one end of the sixth resistor R5, and the other end of the sixth resistor R5 is grounded.

[0113] The three working conditions of the second protection signal generation sub-circuit 202 will be introduced below in combination with Figure 6 .

[0114] (1) When the voltage of the A / B pin of the RS485 chip is a positive voltage (greater than 0V), the circuit composed of the fourteenth NMOS M39 and the fifteenth NMOS M40 will not be turned on, and the back-to-back connection of the substrate parasitic diodes of the fourteenth NMOS M39 and the fifteenth NMOS M40 has no path, and the gate is diode-connected, which ensures that the fourteenth NMOS M39 and the fifteenth NMOS M40 will not be damaged by the high voltage signal, and finally the A / B pin can be disconnected from the second protection signal generation sub-circuit 202.

[0115] (2) When the voltage of the A / B pin of the RS485 chip is higher than the preset second voltage in the detection circuit 1, the second voltage signal BELOW_0V is a low-level logic, so that the node GN_L is also high, then the twelfth NMOS M37 and the thirteenth NMOS M38 are turned on, at this time the node J is high, and the twelfth PMOS M33 is turned off; when the fifth resistor R6 is set to a large resistance, the second protection signal ND_SD output by the node P is pulled down to GND, at this time, part of the NMOS in the A / B pin driving circuit is disconnected, and the NMOS used for output can work normally.

[0116] (3) When the voltage of the A / B pin of the RS485 chip is lower than the preset second voltage in the detection circuit 1, the second voltage signal BELOW_0V is flipped to a high-level logic, so that the node GN_L is also flipped to a low level, then the twelfth NMOS transistor M37 and the thirteenth NMOS transistor M38 are disconnected, and the eleventh PMOS transistor M30 is also disconnected, so that the current source composed of the thirteenth PMOS transistor M31 and the fourteenth PMOS transistor M32 works normally, and together with the fourteenth NMOS transistor M39 and the fifteenth NMOS transistor M40, the second protection signal ND_SD is set, and a voltage value is added to the A / B pin to ensure that the NMOS transistor used for output can work normally and its gate voltage VGS is within a safe range.

[0117] This embodiment provides a detection circuit and a protection signal generating circuit, wherein the detection circuit detects the RS485 voltage and outputs a first voltage signal when it is higher than a preset first voltage, and outputs a second voltage signal when it is lower than a preset second voltage, so that the protection signal generating circuit can output a protection signal according to the first voltage signal or the second voltage signal, so that the A / B pin drive circuit is shut down after receiving the protection signal, thereby effectively protecting the A / B pin drive circuit, so that the A / B pin drive circuit using a low-voltage gate process can also withstand high voltage.

[0118] Example 2

[0119] This embodiment provides an RS485 transmission driver, such as Figure 7 As shown, the RS485 driver module includes a driver circuit 3 and the RS485 protection component 4 of Example 1.

[0120] The RS485 protection component 4 is connected to the input end of the drive circuit 3, and the output end of the drive circuit 3 is connected to the RS485 bus. The drive circuit is used to shut down when receiving the protection signal sent by the RS485 protection component.

[0121] In this embodiment, if Figure 8 As shown, the driving circuit 3 includes a P path and an N path. The P path includes the seventeenth PMOS transistor M1, the eighteenth PMOS transistor M23, the nineteenth PMOS transistor M2 and the twentieth PMOS transistor M24; the N path includes the seventeenth NMOS transistor M3, the eighteenth NMOS transistor M25, the nineteenth NMOS transistor M4 and the twentieth NMOS transistor M26.

[0122] The drain of the seventeenth PMOS transistor M1 is connected with the power supply, the gate of the seventeenth PMOS transistor M1 is connected with the drain of the eighteenth PMOS transistor M23, the source of the seventeenth PMOS transistor M1 is connected with the source of the eighteenth PMOS transistor M23, the source of the nineteenth PMOS transistor M2 and the source of the twentieth PMOS transistor M24 respectively, the gate of the nineteenth PMOS transistor M2 is connected with the drain of the twentieth PMOS transistor M24. The gate of the eighteenth PMOS transistor M23 and the gate of the twentieth PMOS transistor M24 are connected with the RS485 protection component, the gate of the nineteenth PMOS transistor M2 is also connected with the data end of the RS485 chip, the source of the nineteenth PMOS transistor M2 is also connected with the RS485 bus, and the gate of the seventeenth PMOS transistor M1 is also connected with the RS485 protection component 4.

[0123] The drain of the nineteenth NMOS transistor M4 is grounded, the gate of the nineteenth NMOS transistor M4 is connected with the drain of the twentieth NMOS transistor M26, the source of the nineteenth NMOS transistor M4 is connected with the source of the twentieth NMOS transistor M26, the source of the seventeenth NMOS transistor M3 and the source of the eighteenth NMOS transistor M25 respectively, the gate of the seventeenth NMOS transistor M3 is connected with the drain of the eighteenth NMOS transistor M25. The gate of the twentieth NMOS transistor M26 and the gate of the eighteenth NMOS transistor M25 are connected with the RS485 protection component, the gate of the seventeenth NMOS transistor M3 is also connected with the data end of the RS485 chip, the source of the seventeenth NMOS transistor M3 is also connected with the RS485 bus, and the gate of the nineteenth NMOS transistor M4 is also connected with the RS485 protection component 4.

[0124] Specifically, the gate of the seventeenth PMOS transistor M1 in the P path is connected with the node GP_T, the gate of the nineteenth PMOS transistor M2 is connected with the data end GP_M of the RS485 chip, and the gate of the eighteenth PMOS transistor M23 and the gate of the twentieth PMOS transistor M24 are connected with the node O; the gate of the nineteenth NMOS transistor M4 in the N path is connected with the node GN_L, the gate of the seventeenth NMOS transistor M3 is connected with the data end GN_M of the RS485 chip, and the gate of the eighteenth NMOS transistor M25 and the gate of the twentieth NMOS transistor M26 are connected with the node P.

[0125] It should be noted that, as long as the A / B pin voltage is in the range of 0-5V, the node GP_T is low, the node GN_L is high, the seventeenth PMOS tube M1 and the nineteenth NMOS tube M4 remain in the on state; the data transfer of the RS485 chip to the data end GP_M / GN_M, respectively control the power output tube the nineteenth PMOS tube M2 and the seventeenth NMOS tube M3, thereby driving the logic of A / B port flip; the BULK parasitic diode of P tube path (the seventeenth PMOS tube M1, the nineteenth PMOS tube M2) and N tube path (the seventeenth NMOS tube M3, the nineteenth NMOS tube M4) are connected in back-to-back form to prevent high voltage from being seen by A / B pin when off state, wherein all internal devices and current paths seen by A / B port have to withstand a wide range of positive and negative voltage.

[0126] The following will be combined Figure 4 , Figure 5 , Figure 6 and Figure 8 , the control logic of the RS485 sending driver of the embodiment is introduced:

[0127] The detection circuit in the RS485 protection component detects the voltage of the RS485 bus (the voltage borne by the A / B pin of the RS485 chip);

[0128] (1) When the RS485 bus voltage is greater than the preset first voltage, the first voltage signal OVER_5V is logically flipped high, and then the first protection signal PD_SD is generated through the first protection signal generating sub-circuit; at this time, the node GP_T is set to high level, and the first protection signal PD_SD is pulled low, so that the seventeenth PMOS tube M1 is turned off, the eighteenth PMOS tube M23 and the twentieth PMOS tube M24 controlled by the first protection signal PD_SD are turned on, and the VGS of the nineteenth PMOS tube M2 is kept off to ensure that the VGS of the seventeenth PMOS tube M1 and the nineteenth PMOS tube M2 is in a safe range. In addition, the VGS of the eighteenth PMOS tube M23 and the twentieth PMOS tube M24 can also be ensured to be in a normal range through the first protection signal generating sub-circuit.

[0129] (2) When the RS485 bus voltage is lower than the preset second voltage, the second voltage signal BELOW_0V is logically flipped high, and then the second protection signal generating sub-circuit generates the second protection signal ND_SD; at this time, the node GN_L is set to low level, and the second protection signal ND_SD is pulled high, so that the nineteenth NMOS tube M4 is turned off, the eighteenth NMOS tube M25 and the twentieth NMOS tube M26 controlled by the second protection signal ND_SD are turned on, and the VGS of the seventeenth NMOS tube M3 = 0 remains in the off state, thereby ensuring the VGS safety range of the seventeenth NMOS tube M3 and the nineteenth NMOS tube M4. In addition, the VGS of the eighteenth NMOS tube M25 and the twentieth NMOS tube M26 can also be ensured to be in the normal range through the first protection signal generating sub-circuit.

[0130] The RS485 sending driver of the embodiment includes the protection assembly of embodiment 1, so the effects of embodiment 1 are specifically implemented, and details are not described herein.

[0131] Embodiment 3

[0132] The embodiment provides an RS485 transceiver, and the RS485 transceiver of the embodiment includes the RS485 sending driver of embodiment 2 and the RS485 transceiver.

[0133] Although the specific embodiments of the present application are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present application is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present application, and these changes and modifications all fall within the protection scope of the present application.

Claims

1. An RS485 protection assembly, characterized by The application discloses an A / B pin driving circuit for protecting an RS485 chip, and relates to the technical field of RS485 protection components. The RS485 protection component comprises a detection circuit and a protection signal generation circuit. One end of the detection circuit is used for connecting the RS485 bus, and the other end of the detection circuit is connected with one end of the protection signal generation circuit. The detection circuit is used for detecting the voltage of the RS485 bus, and outputs a first voltage signal when the voltage of the RS485 bus is higher than a preset first voltage and outputs a second voltage signal when the voltage of the RS485 bus is lower than a preset second voltage. The protection signal generation circuit is used for receiving the first voltage signal or the second voltage signal and outputting a protection signal according to the first voltage signal or the second voltage signal, so that the A / B pin driving circuit is turned off after receiving the protection signal. The protection signal generation circuit comprises a first protection signal generation sub-circuit and a second protection signal generation sub-circuit. The input end of the first protection signal generation sub-circuit and the input end of the second protection signal generation sub-circuit are respectively connected with the other end of the detection circuit, and the output end of the first protection signal generation sub-circuit and the output end of the second protection signal generation sub-circuit are respectively connected with the A / B pin driving circuit. The first protection signal generation sub-circuit is used for outputting a first protection signal according to the first voltage signal. The second protection signal generation sub-circuit is used for outputting a second protection signal according to the second voltage signal. The first protection signal is a voltage value which is reduced on the basis of the voltage of the RS485 bus, and the second protection signal is a voltage value which is increased on the basis of the voltage of the RS485 bus.

2. The RS485 protection component of claim 1, wherein The detection circuit comprises a first comparison voltage generation sub-circuit, a first reference voltage generation sub-circuit and a first comparison sub-circuit. The input end of the first comparison voltage generation sub-circuit is connected with the RS485 bus, the output end of the first comparison voltage generation sub-circuit is connected with the positive input end of the first comparison sub-circuit, the input end of the first reference voltage generation sub-circuit is connected with a power supply, and the output end of the first reference voltage generation sub-circuit is connected with the negative input end of the first comparison sub-circuit. The first comparison voltage generation sub-circuit is used for outputting a first comparison voltage when the voltage of the RS485 bus is higher than the preset first voltage. The first reference voltage generation sub-circuit is used for outputting a first reference voltage. The first comparison sub-circuit is used for comparing the sizes of the first comparison voltage and the first reference voltage and outputting the first voltage signal when the first comparison voltage is greater than the first reference voltage. The detection circuit further comprises a second comparison voltage generation sub-circuit, a second reference voltage generation sub-circuit and a second comparison sub-circuit. An input end of the second comparison voltage generating sub-circuit is connected with the RS485 bus, an output end of the second comparison voltage generating sub-circuit is connected with a negative input end of the second comparison sub-circuit, an input end of the second reference voltage generating sub-circuit is connected with a power supply, and an output end of the second reference voltage generating sub-circuit is connected with a positive input end of the second comparison sub-circuit; The second comparison voltage generating sub-circuit is configured to output a second comparison voltage when a voltage of the RS485 bus is lower than a preset second voltage; The second reference voltage generating sub-circuit is configured to output a second reference voltage; The second comparison sub-circuit is configured to compare the second comparison voltage and the second reference voltage, and output the second voltage signal when the second comparison voltage is lower than the second reference voltage.

3. The RS485 protection assembly of claim 2, wherein The first comparison voltage generating sub-circuit comprises a first PMOS tube, a second PMOS tube, a sixth NMOS tube, a first resistor and a first current source; The first reference voltage generating sub-circuit comprises a third PMOS tube, a fourth PMOS tube and a second current source; The first comparison sub-circuit comprises a first comparator; One end of the first current source is connected with a drain and a gate of the first PMOS tube, a gate of the second PMOS tube and a drain of the sixth NMOS tube respectively, a source of the first PMOS tube is connected with a source of the second PMOS tube, a drain of the second PMOS tube is connected with the RS485 bus through the first resistor, a source of the sixth NMOS tube is connected with a positive input end of the first comparator, one end of the second current source is connected with a drain and a gate of the third PMOS tube, a gate of the fourth PMOS tube and a negative input end of the first comparator respectively, a source of the third PMOS tube is connected with a source of the fourth PMOS tube, a drain of the fourth PMOS tube and a gate of the sixth NMOS tube are connected with the power supply, the other end of the first current source and the other end of the second current source are grounded, and an output end of the first comparator outputs a first voltage signal; The second comparison voltage generating sub-circuit comprises a first NMOS tube, a second NMOS tube, a fifth NMOS tube, a second resistor and a third current source; The second reference voltage generating sub-circuit comprises a third NMOS tube, a fourth NMOS tube and a fourth current source; and the second comparison sub-circuit comprises a second comparator; One end of the third current source is connected with the drain and gate of the first NMOS tube, the gate of the second NMOS tube, and the drain of the fifth NMOS tube respectively, the source of the first NMOS tube is connected with the source of the second NMOS tube, the drain of the second NMOS tube is connected with the RS485 bus through the second resistance, the source of the fifth NMOS tube is connected with the negative input end of the second comparator, one end of the third current source is connected with the drain and gate of the third NMOS tube, the gate of the fourth NMOS tube, and the positive input end of the second comparator respectively, the source of the third NMOS tube is connected with the source of the fourth NMOS tube, the drain of the fourth NMOS tube and the gate of the fifth NMOS tube are grounded, the other end of the third current source and the other end of the fourth current source are connected with the power supply respectively, and the output end of the second comparator outputs the second voltage signal.

4. The RS485 protection component of claim 1, wherein, the first protection signal generation sub-circuit comprises a first level conversion unit, the first level conversion unit is used for detecting the level state of the first voltage signal, and outputs a low level signal when the first voltage signal is a low level and outputs a high level signal when the first voltage signal is a high level; the second protection signal generation sub-circuit comprises a second level conversion unit, the second level conversion unit is used for detecting the level state of the second voltage signal, and outputs a high level signal when the second voltage signal is a low level and outputs a low level signal when the second voltage signal is a high level.

5. The RS485 protection component of claim 4, wherein, the first protection signal generation sub-circuit further comprises a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a third resistance, a first inverter, a second inverter, and a fifth current source; the other end of the detection circuit is connected with the gate of the fifth PMOS tube, the input end of the first inverter, the gate of the seventh NMOS tube, and the input end of the second inverter respectively, the output end of the first inverter is connected with the input end of the first level conversion unit, the output end of the first level conversion unit is connected with the gate of the sixth PMOS tube, the source of the fifth PMOS tube is connected with the power supply, the drain of the fifth PMOS tube is connected with the drain of the sixth PMOS tube, the source of the sixth PMOS tube is connected with the drain of the seventh NMOS tube, one end of the third resistance, the drain of the eighth PMOS tube, and the drain of the ninth NMOS tube respectively, the source of the seventh NMOS tube and the other end of the third resistance are grounded; The drain of the seventh PMOS tube is connected with the RS485 bus, the source of the seventh PMOS tube is connected with the source of the eighth PMOS tube, the gate of the seventh PMOS tube is connected with the gate and the drain of the eighth PMOS tube, and the source of the eighth PMOS tube outputs the first protection signal to the A / B foot driving circuit to make the A / B foot driving circuit turn off; One end of the fifth current source is connected with the drain and the gate of the eighth NMOS tube, the gate of the ninth NMOS tube and the drain of the tenth NMOS tube respectively, the output end of the second inverter is connected with the gate of the tenth NMOS tube, the source of the eighth NMOS tube, the source of the ninth NMOS tube and the source of the tenth NMOS tube are grounded, and the other end of the fifth current source is connected with the power supply.

6. The RS485 protection assembly of claim 5, wherein, The first protection signal generation sub-circuit further comprises a first capacitor and a fourth resistor; One end of the first capacitor is connected with the first output end of the detection circuit, the other end of the first capacitor is connected with the gate of the seventh NMOS tube and one end of the fourth resistor, and the other end of the fourth resistor is grounded.

7. The RS485 protection assembly of claim 4, wherein, The second protection signal generation sub-circuit further comprises a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifth resistor, a third inverter, a fourth inverter and a sixth current source; The other end of the detection circuit is connected with the gate of the eleventh PMOS tube, the input end of the third inverter, the input end of the second level conversion unit and the input end of the fourth inverter respectively, the output end of the fourth inverter is connected with the gate of the thirteenth NMOS tube, the source of the thirteenth NMOS tube is grounded, the drain of the thirteenth NMOS tube is connected with the drain of the twelfth NMOS tube, the gate of the twelfth NMOS tube is connected with the output end of the second level conversion unit, the source of the twelfth NMOS tube is connected with the drain of the twelfth PMOS tube, one end of the fifth resistor, the drain of the fourteenth PMOS tube and the drain of the fourteenth NMOS tube respectively, the gate of the twelfth PMOS tube is connected with the output end of the third inverter, and the source of the twelfth PMOS tube and the other end of the fifth resistor are connected with the power supply; The drain of the fifteenth NMOS tube is connected with the RS485 bus, the source of the fifteenth NMOS tube is connected with the source of the fourteenth NMOS tube, the gate of the fifteenth NMOS tube is connected with the gate and the drain of the fourteenth NMOS tube, and the drain of the fourteenth NMOS tube outputs the second protection signal to the A / B foot driving circuit to make the A / B foot driving circuit turn off; One end of the sixth current source is connected with the drain and gate of the thirteenth PMOS, the gate of the fourteenth PMOS and the drain of the eleventh PMOS, the source of the eleventh PMOS, the source of the thirteenth PMOS and the source of the fourteenth PMOS are connected with a power supply, and the other end of the sixth current source is grounded.

8. The RS485 protection assembly of claim 7, wherein, The second protection signal generating sub-circuit further comprises a second capacitor and a sixth resistor; One end of the second capacitor is connected with the output end of the third inverter, the other end of the second capacitor is connected with the gate of the twelfth PMOS and one end of the sixth resistor, and the other end of the sixth resistor is grounded.

9. The RS485 protection assembly of claim 5, wherein, The first level converting unit comprises a ninth PMOS, a tenth PMOS and an eleventh NMOS; The output end of the first inverter is connected with the gate of the ninth PMOS and the gate of the eleventh NMOS, the source of the ninth PMOS is connected with a power supply, the drain of the ninth PMOS is connected with the drain of the tenth PMOS, the drain of the eleventh NMOS is connected with the gate and the source of the tenth PMOS and the gate of the sixth PMOS, and the source of the eleventh NMOS is grounded.

10. The RS485 protection assembly of claim 7, wherein, The second level converting unit comprises a fifteenth PMOS, a sixteenth PMOS and a sixteenth NMOS; The second output end of the detection circuit is connected with the gate of the fifteenth PMOS and the gate of the sixteenth NMOS, the source of the fifteenth PMOS is connected with a power supply, the drain of the fifteenth PMOS is connected with the drain of the sixteenth PMOS and the gate of the twelfth NMOS, the drain of the sixteenth NMOS is connected with the gate and the source of the sixteenth PMOS, and the source of the sixteenth NMOS is grounded.

11. An RS485 transmit driver, characterized by The RS485 sending driver comprises a driving circuit and the RS485 protection assembly of any one of claims 1-10; The RS485 protection assembly is connected with the input end of the driving circuit, and the output end of the driving circuit is connected with the RS485 bus; The driving circuit is used for being turned off when the first voltage signal or the second voltage signal sent by the RS485 protection assembly is received.

12. The RS485 transmit driver of claim 11, wherein, The driving circuit comprises a P path and an N path; The P path comprises a seventeenth PMOS, an eighteenth PMOS, a nineteenth PMOS and a twentieth PMOS; The N path comprises a seventeenth NMOS, an eighteenth NMOS, a nineteenth NMOS and a twentieth NMOS; The drain of the seventeenth PMOS tube is connected with a power supply, the gate of the seventeenth PMOS tube is connected with the drain of the eighteenth PMOS tube, the source of the seventeenth PMOS tube is connected with the source of the eighteenth PMOS tube, the source of the nineteenth PMOS tube and the source of the twentieth PMOS tube respectively, the gate of the nineteenth PMOS tube is connected with the drain of the twentieth PMOS tube; The gate of the eighteenth PMOS tube and the gate of the twentieth PMOS tube are connected with the RS485 protection component, the gate of the nineteenth PMOS tube is also connected with the data end of the RS485 chip, the source of the nineteenth PMOS tube is also connected with the RS485 bus, and the gate of the seventeenth PMOS tube is also connected with the RS485 protection component; The drain of the nineteenth NMOS tube is grounded, the gate of the nineteenth NMOS tube is connected with the drain of the twentieth NMOS tube, the source of the nineteenth NMOS tube is connected with the source of the twentieth NMOS tube, the source of the seventeenth NMOS tube and the source of the eighteenth NMOS tube respectively, the gate of the seventeenth NMOS tube is connected with the drain of the eighteenth NMOS tube; The gate of the twentieth NMOS tube and the gate of the eighteenth NMOS tube are connected with the RS485 protection component, the gate of the seventeenth NMOS tube is also connected with the data end of the RS485 chip, the source of the seventeenth NMOS tube is also connected with the RS485 bus, and the gate of the nineteenth NMOS tube is also connected with the RS485 protection component.

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