A fine-grained two-parallel Systolic FxLMS filter design method based on FPGA
By designing fine-grained two parallel Systolic FxLMS filters on FPGAs, the problem that adaptive filters in the prior art are difficult to ensure convergence, reduce power consumption and improve throughput at the same time in hardware implementation, and efficient broadband noise processing and noise reduction effects are achieved.
Patent Information
- Application Number
- CN202111623826.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-28
- Publication Date
- 2025-04-25
- Estimated Expiration
- 2041-12-28
AI Technical Summary
In hardware implementation, existing active noise control algorithms are difficult to ensure the convergence of adaptive filters, reduce power consumption and improve throughput at the same time. Especially when broadband noise processing, there is a problem of "water bed effect" and the problem of noise not falling and rising in the middle and high frequency bands without decreasing.
A fine-grained two-parallel Systolic FxLMS filter design method based on FPGA is proposed. Through the pipeline design of the Systolic FxLMS algorithm, two parallel fast FIR filter modules and fine-grained two-parallel Systolic FxLMS filter structure, the active audio noise reduction with low power consumption and high throughput is achieved.
It achieves higher throughput and faster convergence speed, while reducing system power consumption, improving the processing capacity of broadband noise, and avoiding the problem of "water bed effect" and the problem of increasing noise without decreasing and instead increasing in the middle and high frequency bands.
Smart Images
Figure CN114337604B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of digital signal processing, and in particular relates to a fine-grained two-parallel SystolicFxLMS filter design method based on FPGA. Background Art
[0002] With the rapid development of economy and the advancement of urbanization, noise seriously threatens people's physical and mental health. Therefore, controlling noise pollution is an urgent problem to be solved. Noise control methods can be divided into passive noise control (PNC) and active noise control (ANC). ANC can effectively reduce low-frequency noise and is widely used in active noise reduction headphones. The core of the ANC system is the adaptive algorithm and adaptive filter. The most widely used adaptive algorithm in the ANC system is the Filtered-X Least Mean Square (FxLMS) algorithm. The FxLMS algorithm has become the "benchmark" algorithm in the ANC system due to its clear physical mechanism, small amount of calculation and simple implementation.
[0003] In the existing active noise control algorithm, the MATLAB simulation stage is the main focus. The present invention focuses on the research on the characteristics and structural improvement of the active noise control algorithm, and considers the adaptive filter structure analysis and hardware implementation of power consumption, algorithm convergence, and throughput. In practical applications, reducing power consumption and improving throughput while ensuring the convergence of the adaptive filter are important factors for hardware implementation. In the application of noise reduction headphones, due to its compact structure, the feedback ANC system is used to place the reference microphone close to the secondary sound source, which will cause the feedback ANC system to have a narrow noise reduction frequency band and the "water bed effect" of the mid-high frequency band noise rising instead of falling during noise reduction, and the ability to handle broadband noise is poor. Therefore, the feedforward ANC system places a reference microphone at the target noise source to obtain a reference signal, which is not only suitable for processing narrowband noise signals, but also suitable for processing broadband noise signals, and has strong robustness. Therefore, the present invention studies the possibility of implementing the feedforward FxLMS algorithm in active noise reduction headphones, and proposes a fine-grained two-parallel Systolic FxLMS filter design method based on FPGA. Summary of the invention
[0004] The present invention aims to solve the above problems of the prior art. A fine-grained two-parallel Systolic FxLMS filter design method based on FPGA is proposed. The technical solution of the present invention is as follows:
[0005] A fine-grained two-parallel Systolic FxLMS filter design method based on FPGA comprises the following steps: firstly, Systolic FxLMS (pulsating filter-x least mean square algorithm) filter design is performed (Systolic FxLMS filter is used for audio active noise reduction); then, two parallel Systolic FxLMS filters are designed, and the two parallel Systolic FxLMS filters are used to realize audio active noise reduction with low power consumption; finally, fine-grained two parallel Systolic FxLMS filters are designed, and the fine-grained two parallel Systolic FxLMS filters are used to realize audio active noise reduction with high throughput.
[0006] Furthermore, the Systolic FxLMS filter specifically includes:
[0007] The adaptive filtering module is used to implement the multiplication operation of N weight coefficients W(n) and N input signals X(n). The iterative operation formula of the Systolic FxLMS algorithm adaptive filtering is y(n) = W T (n)X(n);
[0008] The first error calculation module is used to implement the subtraction operation of the output signal y(n) and the noise signal d(n). The error calculation iterative operation formula of the SystolicFxLMS algorithm is e(n)=d(n)-W T (n)X'(n);
[0009] The first weight update module is composed of N carry adders, which are used to update N weight coefficients. The weight update iteration calculation formula of the SystolicFxLMS algorithm is W(n+1)=W(n)+μe(n)X'(n);
[0010] The first secondary path module uses the LMS algorithm FIR filter to perform adaptive identification of the model to correct the error gradient estimate of the LMS algorithm. The secondary path iterative operation formula of the Systolic FxLMS algorithm is X'(n) = s(n)*X(n), where s(n) represents the secondary signal, * represents the convolution operation, and X'(n) represents the filtered input signal.
[0011] Furthermore, the Systolic FxLMS filter designs multiple data processing modules PM to transmit data, and the data stream is transmitted from PM(0) to PM(N-1) in sequence; when the filter tap length is long enough, the constraint on the step factor is specifically:
[0012]
[0013] Where: μ is the step size factor of the Systolic FxLMS algorithm; λ max is the largest eigenvalue of the autocorrelation matrix of the filtered-X signal.
[0014] Furthermore, the two parallel Systolic FxLMS filters include:
[0015] Two parallel fast FIR filter modules, including three sub-filters of length N / 2, a pre-processing unit and a post-processing unit. The sub-filters represent W0, W0+W1, and W1. The pre-processing unit represents an adder, and the post-processing unit represents three adders and a delay unit. The iterative operation formula is
[0016] Y=Y0+z -1 Y1
[0017] Y0=W0X0+z -2 W1X1
[0018] Y1=(W0+W1)(X0+X1)-W0X0-W1X1
[0019] Where: Y is the output of two parallel fast FIR filters; Y0 is the output of channel 0 filter; Y1 is the output of channel 1 filter; W0 is the weight coefficient of channel 0 filter; W1 is the weight coefficient of channel 1 filter; X0 is the input signal of channel 0 filter; X1 is the input signal of channel 1 filter; z represents delay.
[0020] The second error calculation module is used to realize the output signal Subtracting the noise signal d0(n), the error calculation iterative calculation formula of the two parallel Systolic FxLMS algorithms is:
[0021]
[0022] s0(n) represents the channel 0 secondary path signal.
[0023] The second weight update module consists of N carry adders, which are used to update N weight coefficients. The weight update iterative calculation formula of the two parallel Systolic FxLMS algorithms is
[0024] The second secondary path module uses the LMS algorithm FIR filter to perform adaptive identification of the model to correct the error gradient estimate of the LMS algorithm. The iterative calculation formula of the secondary path of the two parallel Systolic FxLMS algorithms is
[0025] Where: s0(n) represents the secondary path signal of channel 0; * represents the convolution operation; X0'(n) represents the input signal after channel 0 filtering; X1'(n) represents the input signal after channel 1 filtering;
[0026] Furthermore, for the two parallel Systolic FxLMS filters, when N=8, W={w0, w1, w2, w3, w4, w5, w6, w7}, the two parallel fast FIR filter module sub-filters are:
[0027] W0={w0,w2,w4,w6}
[0028] W1={w1,w3,w5,w7}
[0029] W0+W1={w0+w1,w2+w3,w4+w5,w6+w7}
[0030] The two parallel Systolic FxLMS filter framework, the two parallel input signals are:
[0031]
[0032] Furthermore, the fine-grained two-parallel Systolic FxLMS filter includes:
[0033] The multiplication-accumulation operation module uses the Radix-4 Booth coding algorithm to design 16×16 parallel fixed-point operations combined with the Wallace tree algorithm;
[0034] The fused multiply-add unit module is implemented by combining partial product generation and Wallace tree to reduce the critical path;
[0035] 4:2 compression tree modules are connected in a carry-saving way, changing the previous standard partial product compression method based on full adders, introducing the idea of horizontal data paths, and reducing the number of compression tree levels and critical path delay;
[0036] The carry propagation adder module is designed with the Han-Carlson adder structure. The Han-Carlson adder structure is a parallel prefix addition structure, and the total number of stages required is Where N represents the number of operations.
[0037] Furthermore, the Radix-4 Booth encoding algorithm specifically includes:
[0038] Radix-4 Booth encoding is divided into three stages. The first stage is to perform Booth encoding to generate partial products. The second stage is to input the partial products into the Wallace compression tree and compress them in parallel to two operands. The third stage is to use an adder to add the two operands to obtain the final product result.
[0039] Furthermore, the Wallace tree algorithm is used to optimize multiplication and accumulation operations, compressing the accumulation operation of multiple data into the addition of two operands through a tree structure, and shortening the delay of the critical path by reducing the number of accumulation operations;
[0040] The Wallace tree is divided into four stages. In the first stage, the 4:2 compression tree is used to compress the partial products generated by Booth coding. In the second stage, the 3:2 compression tree is used to further compress the generated partial products. In the third stage, the 4:2 compression tree is used to compress the partial products generated in the previous level. In the fourth stage, the final partial products are summed.
[0041] Furthermore, the 4:2 compression tree module has 4 inputs X1, X2, X3 and X4, 2 outputs Carry and Sum, and 2 carries Cin and Cout. The 4:2 compression tree receives a carry Cin at a low position and generates a carry output Cout at a high position. In order to avoid serial carry and speed up the generation of the sum represented by the partial product carry storage table, the output Cout must be independent of the input Cin. The 3:2 compression tree module has 3 inputs X1, X2 and X3, 2 outputs Carry and Sum, and 2 carries Cin and Cout.
[0042] Furthermore, the Han-Carlson adder is designed based on the parallel prefix adder PPA principle, and is a combination of a Kogge-Stone adder and a Brent-Kung adder, and the Kogge-Stone adder and the Brent-Kung adder are parallel prefix adders.
[0043] The advantages and beneficial effects of the present invention are as follows:
[0044] (1) The Systolic FxLMS filter described above adopts pipeline technology and designs multiple data processing modules (PM) to transmit data. The data stream is transmitted from PM(0) to PM(N-1) in sequence. Through the "pulsation" operation, the Systolic FxLMS algorithm has a higher throughput and a faster convergence speed than the FxLMS algorithm.
[0045] (2) The two parallel Systolic FxLMS filters described above, wherein the two parallel fast FIR filter modules use algorithm strength reduction transformation to implement two parallel FIR filters. When the order N = 8 and the parallelism L = 2, the traditional two parallel FIR filters require 16 multiplications and 14 additions, while the two parallel fast FIR filters only require 12 multiplications and 13 additions. The two parallel fast FIR algorithm greatly reduces the number of multiplications and reduces system power consumption.
[0046] (3) The fine-grained two-parallel Systolic FxLMS filter adopts two parallel fast FIR filter structures to improve system throughput, and introduces multi-operand addition, multiplication-accumulation unit and fused multiplication-accumulation unit to compress the number of operations, so as to reduce the critical path delay. The proposed 8-tap fine-grained two-parallel Systolic FxLMS filter structure has a throughput twice that of the traditional structure at the same frequency, and the algorithm convergence is close to the Systolic FxLMS algorithm. Compared with the existing best structure, its power consumption is reduced by 9.28%. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] Figure 1 It is a design diagram of two parallel Systolic FxLMS filters provided by a preferred embodiment of the present invention.
[0048] Figure 2 It is the design diagram of the Systolic FxLMS algorithm provided by the present invention.
[0049] Figure 3 This is a design diagram of a fine-grained two-parallel Systolic FxLMS filter provided by the present invention.
[0050] Figure 4 It is a comparison of the convergence of the two parallel Systolic FxLMS algorithms provided by the present invention. DETAILED DESCRIPTION
[0051] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.
[0052] The technical solution of the present invention to solve the above technical problems is:
[0053] The present invention discloses a fine-grained two-parallel Systolic FxLMS filter design method based on FPGA, which mainly includes three parts: (1) Systolic FxLMS filter design (2) two-parallel Systolic FxLMS filter design (3) fine-grained two-parallel Systolic FxLMS filter design.
[0054] As attached Figure 1 As shown, the present invention proposes a fine-grained two-parallel Systolic FxLMS filter design method based on FPGA, characterized in that the Systolic FxLMS filter includes:
[0055] The adaptive filtering module is used to implement the multiplication operation of N weight coefficients W(n) and N input signals X(n). The iterative operation formula of the Systolic FxLMS algorithm adaptive filtering is y(n) = W T (n)X(n);
[0056] The error calculation module is used to implement the subtraction operation between the output signal y(n) and the noise signal d(n). The error calculation iterative operation formula of the SystolicFxLMS algorithm is e(n) = d(n) - W T (n)X'(n);
[0057] The weight update module consists of N carry adders, which are used to update N weight coefficients. The weight update iteration calculation formula of the Systolic FxLMS algorithm is W(n+1)=W(n)+μe(n)X'(n);
[0058] The secondary path module uses the LMS algorithm FIR filter to perform adaptive identification of the model to correct the error gradient estimate of the LMS algorithm. The secondary path iteration operation formula of the Systolic FxLMS algorithm is X'(n) = s(n)*X(n), where s(n) represents the secondary signal, * represents the convolution operation, and X'(n) represents the filtered input signal;
[0059] Furthermore, the present invention proposes a fine-grained two-parallel Systolic FxLMS filter design method based on FPGA, characterized in that the Systolic FxLMS filter designs multiple data processing modules (Processing Module, PM) to transmit data, and the data stream is transmitted from PM (0) to PM (N-1) in sequence; when the filter tap length is long enough, the constraint on the step factor is specifically:
[0060]
[0061] Where: μ is the step size factor of the Systolic FxLMS algorithm; λ max is the largest eigenvalue of the autocorrelation matrix of the filtered-X signal.
[0062] As attached Figure 2As shown, the present invention proposes a fine-grained two-parallel Systolic FxLMS filter design method based on FPGA, characterized in that the two-parallel Systolic FxLMS filter includes:
[0063] Two parallel fast FIR filter modules, including three sub-filters of length N / 2, a pre-processing unit, and a post-processing unit. The sub-filters represent W0, W0+W1, and W1. The pre-processing unit represents an adder, and the post-processing unit represents three adders and a delay unit. The iterative operation formula is
[0064] Y=Y0+z -1 Y1
[0065] Y0=W0X0+z -2 W1X1
[0066] Y1=(W0+W1)(X0+X1)-W0X0-W1X1
[0067] Wherein: Y represents the output of two parallel fast FIR filters; Y0 represents the output of channel 0 filter; Y1 represents the output of channel 1 filter; W0 represents the weight coefficient of channel 0 filter; W1 represents the weight coefficient of channel 1 filter; X0 represents the input signal of channel 0 filter; X1 represents the input signal of channel 1 filter; z represents delay.
[0068] Error calculation module, used to realize output signal Subtract the noise signal d0(n), and the error calculation iterative calculation formula of the two parallel Systolic FxLMS algorithms is
[0069]
[0070] s0(n) represents the signal of the secondary path of channel 0.
[0071] The weight update module consists of N carry adders, which are used to update N weight coefficients. The weight update iterative calculation formula of the two parallel SystolicFxLMS algorithms is
[0072] The secondary path module uses the LMS algorithm FIR filter to perform adaptive identification of the model to correct the error gradient estimate of the LMS algorithm. The secondary path iteration formula of the two parallel Systolic FxLMS algorithms is
[0073] Where: s0(n) represents the secondary signal of channel 0; * represents the convolution operation; X0'(n) represents the input signal after channel 0 filtering; X1'(n) represents the input signal after channel 1 filtering;
[0074] Furthermore, the present invention proposes a fine-grained two-parallel Systolic FxLMS filter structure design method based on FPGA, characterized in that, for the two parallel Systolic FxLMS filters, when N=8, W={w0, w1, w2, w3, w4, w5, w6, w7}, the two parallel fast FIR filter module sub-filters are:
[0075] W0={w0,w2,w4,w6}
[0076] W1={w1,w3,w5,w7}
[0077] W0+W1={w0+w1,w2+w3,w4+w5,w6+w7}
[0078] The two parallel Systolic FxLMS filters have two parallel input signals:
[0079]
[0080] As attached Figure 3 As shown, the present invention proposes a fine-grained two-parallel Systolic FxLMS filter design method based on FPGA, characterized in that the fine-grained two-parallel Systolic FxLMS filter includes:
[0081] The multiplication-accumulation module uses the Radix-4 Booth coding algorithm to design 16×16 parallel fixed-point operations combined with the Wallace tree algorithm to reduce the number of accumulation operations to shorten the critical path delay and improve the overall throughput of the MAC unit in the circuit;
[0082] The fused multiply-add unit module is implemented by combining partial product generation and Wallace tree to reduce the critical path;
[0083] 4:2 compression tree modules are connected in a carry-saving way, changing the previous standard partial product compression method based on full adders and introducing the idea of horizontal data paths, while reducing the number of compression tree levels and critical path delays, and improving the operation speed;
[0084] The carry propagation adder module adopts the Han-Carlson adder design. The Han-Carlson adder structure is a parallel prefix addition structure, and the total number of stages required is Where N represents the number of operations;
[0085] Furthermore, the fine-grained two-parallel Systolic FxLMS filter proposed in the present invention is characterized in that the Radix-4 Booth coding algorithm can reduce the number of summed partial products to achieve high parallelization and deep pipelining;
[0086] Radix-4 Booth encoding is divided into three stages. The first stage is to perform Booth encoding to generate partial products. The second stage is to input the partial products into the Wallace compression tree and compress them in parallel to two operands. The third stage is to use an adder to add the two operands to obtain the final product result.
[0087] Furthermore, the fine-grained two-parallel Systolic FxLMS filter proposed in the present invention is characterized in that the Wallace tree algorithm is used to optimize the multiplication and accumulation operations, and the accumulation operation of multiple data is compressed into the addition of two operands through a tree structure, thereby shortening the delay of the critical path by reducing the number of accumulation operations;
[0088] The Wallace tree is divided into four stages. In the first stage, the 4:2 compression tree is used to compress the partial products generated by Booth coding. In the second stage, the 3:2 compression tree is used to further compress the generated partial products. In the third stage, the 4:2 compression tree is used to compress the partial products generated in the previous level. In the fourth stage, the final partial products are summed.
[0089] Furthermore, the fine-grained two-parallel Systolic FxLMS filter proposed in the present invention is characterized in that the 4:2 compression tree module has 4 inputs X1, X2, X3 and X4, 2 outputs (Carry and Sum) and 2 carries (Cin and Cout), the 4:2 compression tree accepts a carry Cin at a low position and generates a carry output Cout to a high position, and in order to avoid serial carry and speed up the generation of the partial product carry storage table representing the sum, the output Cout must be independent of the input Cin; the 3:2 compression tree module has 3 inputs X1, X2 and X3, 2 outputs Carry and Sum, and 2 carries Cin and Cout.
[0090] Furthermore, the fine-grained two-parallel Systolic FxLMS filter proposed in the present invention is characterized in that the Han-Carlson adder is designed based on the parallel prefix adder (PPA) principle, which is a combination of a Kogge-Stone adder and a Brent-Kung adder, which reduces the critical path delay of the adding circuit and improves the operating speed of the adder to a certain extent.
[0091] As attached Figure 4, which represents the convergence comparison of fine-grained two parallel Systolic FxLMS algorithms.
[0092] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.
[0093] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.
Claims
1. A fine-grained two-parallel Systolic FxLMS filter design method based on FPGA, characterized in that: The method comprises the following steps: firstly, a Systolic FxLMS pulsating filter-X least mean square algorithm filter is designed, and the Systolic FxLMS filter is used for audio active noise reduction; then, two parallel Systolic FxLMS filters are designed, and the two parallel Systolic FxLMS filters are used for low power consumption to realize audio active noise reduction; finally, a fine-grained two parallel Systolic FxLMS filter is designed, and the fine-grained two parallel Systolic FxLMS filters are used for high throughput to realize audio active noise reduction; The Systolic FxLMS filter specifically includes: The adaptive filtering module is used to realize the multiplication operation of N weight coefficients W(n) and N input signals X(n). The iterative operation formula of the SystolicFxLMS algorithm adaptive filtering is y(n)=W T (n)X(n); The first error calculation module is used to implement the subtraction operation of the output signal y(n) and the noise signal d(n). The error calculation iterative operation formula of the SystolicFxLMS algorithm is e(n)=d(n)-W T (n)X'(n); The first weight update module is composed of N carry adders, which are used to update N weight coefficients. The weight update iteration calculation formula of the Systolic FxLMS algorithm is W(n+1)=W(n)+μe(n)X'(n); μ is the step size factor of the Systolic FxLMS algorithm; The first secondary path module uses the LMS algorithm FIR filter to perform adaptive identification of the model to correct the error gradient estimation value of the LMS algorithm. The secondary path iteration operation formula of the Systolic FxLMS algorithm is X'(n) = s(n)*X(n), where s(n) represents the secondary signal, * represents the convolution operation, and X'(n) represents the input signal after filtering; The two parallel Systolic FxLMS filters include: Two parallel fast FIR filter modules, including three sub-filters of length N / 2, a pre-processing unit and a post-processing unit. The sub-filters represent W0, W0+W1, and W1. The pre-processing unit represents an adder, and the post-processing unit represents three adders and a delay unit. The iterative operation formula is Y=Y0+z -1 Y1 Y0=W0X0+z -2 W1X1 Y1=(W0+W1)(X0+X1)-W0X0-W1X1 Where: Y represents the output of two parallel fast FIR filters; Y0 represents the output of channel 0 filter; Y1 represents the output of channel 1 filter; W0 represents the weight coefficient of channel 0 filter; W1 represents the weight coefficient of channel 1 filter; X0 represents the input signal of channel 0 filter; X1 represents the input signal of channel 1 filter; z represents delay; The second error calculation module is used to realize the output signal Subtracting the noise signal d0(n), the error calculation iterative calculation formula of the two parallel Systolic FxLMS algorithms is: s0(n) represents the signal of the secondary path of channel 0; The second weight update module consists of N carry adders, which are used to update N weight coefficients. The weight update iterative calculation formula of the two parallel SystolicFxLMS algorithms is The second secondary path module uses the LMS algorithm FIR filter to perform adaptive identification of the model to correct the error gradient estimate of the LMS algorithm. The iterative calculation formula of the secondary path of the two parallel Systolic FxLMS algorithms is Where: s0(n) represents the secondary signal of channel 0; * represents the convolution operation; X0'(n) represents the input signal after channel 0 filtering; X1'(n) represents the input signal after channel 1 filtering; The fine-grained two-parallel Systolic FxLMS filter includes: The multiplication-accumulation module uses Radix-4 Booth coding to design 16×16 parallel fixed-point operations combined with Wallace tree; The fused multiply-add unit module is implemented by combining partial product generation and Wallace tree to reduce the critical path; 4:2 compression tree modules are connected in a carry-saving way, changing the previous standard partial product compression method based on full adders, introducing the idea of horizontal data paths, and reducing the number of compression tree levels and critical path delay; The carry propagation adder module is designed using the Han-Carlson adder structure. The Han-Carlson adder structure is a parallel prefix addition structure, and the total number of stages required is Where N1 represents the number of operation bits.
2. The method for designing fine-grained two-parallel Systolic FxLMS filters based on FPGA according to claim 1, characterized in that: The Systolic FxLMS filter designs multiple data processing modules PM to transmit data, and the data stream is transmitted from PM(0) to PM(N-1) in sequence; when the filter tap length is long enough, the constraint on the step factor is specifically: Where: μ is the step size factor of the Systolic FxLMS algorithm; λ max is the largest eigenvalue of the autocorrelation matrix of the filtered-X signal.
3. The method for designing fine-grained two-parallel Systolic FxLMS filters based on FPGA according to claim 1, characterized in that: The two parallel Systolic FxLMS filters, when N = 8, W = {w0, w1, w2, w3, w4, w5, w6, w7}, the two parallel fast FIR filter module sub-filters are: W0={w0,w2,w4,w6} W1={w1,w3,w5,w7} W0+W1={w0+w1,w2+w3,w4+w5,w6+w7} Two parallel Systolic FxLMS filter frameworks, two parallel input signals are:
4. The method for designing fine-grained two-parallel Systolic FxLMS filters based on FPGA according to claim 1, characterized in that: The Radix-4 Booth encoding specifically includes: Radix-4 Booth encoding is divided into three stages. The first stage is to perform Booth encoding to generate partial products. The second stage is to input the partial products into the Wallace compression tree and compress them in parallel to two operands. The third stage is to use an adder to add the two operands to obtain the final product result.
5. The method for designing fine-grained two-parallel Systolic FxLMS filters based on FPGA according to claim 4, characterized in that: The Wallace tree is used to optimize multiplication and accumulation operations, compressing the accumulation operation of multiple data into the addition of two operands through a tree structure, and shortening the delay of the critical path by reducing the number of accumulation operations; The Wallace tree is divided into four stages. In the first stage, the 4:2 compression tree is used to compress the partial products generated by Booth coding. In the second stage, the 3:2 compression tree is used to further compress the generated partial products. In the third stage, the 4:2 compression tree is used to compress the partial products generated in the previous level. In the fourth stage, the final partial products are summed.