Chip pin architecture, method and chip for multiplexing Vcore and Boot pins

Abstract

The present application provides a chip pin architecture, method and chip for multiplexing Vcore and Boot pins. The pin architecture includes a PMU module, a voltage comparison module and a Boot pin; the PMU module has a Vcore voltage terminal. The multiplexing method is: the input signal of the Boot pin is sent to the voltage comparison module, and the hysteresis voltage comparator of the voltage comparison module compares the input signal of the Boot pin with the first reference voltage and outputs a startup mode selection signal of the chip when it is powered on; the Boot pin is also connected to the Vcore voltage terminal, and the Boot pin is also used for an external Vcore capacitor to constitute pin multiplexing. The level range of the Boot pin is the range of the Vcore voltage. The voltage comparison module also includes a clock cycle filter to filter out interference signals with a frequency of the startup clock frequency. The chip includes the above-mentioned pin architecture. The present application can save pin resources, is easy to use, and works reliably.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a chip pin architecture, method and chip for multiplexing Vcore and Boot pins. Background Art

[0002] Vcore is generally the core voltage generated by the PMU (power management module) inside the SOC / MCU. A large capacitor is required to provide power to the core devices. The Boot pin is generally used when the SOC / MCU is powered on to choose whether to re-burn a new program or execute the MCU internal program by identifying its level. Recently, the more popular MCUs, such as Figure 1 The MCU shown, Pin 1

[0003] The (Vcap / Vcore) pin and Pin28 (BOOT0) pin, especially the Boot0 pin, are only used to select whether to re-burn a new program or execute the MCU internal program at startup; that is, they cannot be used in the customer's normal system application, which is a waste of customer available resources.

[0004] Limitations of the prior art: In the pin architecture of general MCUs, multiplexing digital functions and analog functions together is a common technical means that is very easy to implement through design. However, multiplexing the core power pin Vcore with the digital function pin is not a common means of the prior art. Therefore, in some Low Pin Count (few pins) MCUs, multiplexing the core voltage Vcore with the boot pin Boot0 can greatly enhance the competitiveness of the MCU. The biggest risk is that if the design is not handled well, the voltage of the external port (DVCC) will be introduced into the core device, and the core device will burn out. Therefore, multiplexing the core power pin Vcore with the digital function pin to achieve the multiplexing of power and port pins while ensuring the reliability of related functions is a problem that technicians in this field hope to solve. Summary of the invention

[0005] In view of the above problems existing in the prior art, the purpose of this application is to provide a chip pin architecture for multiplexing Vcore and Boot pins, a method for multiplexing Vcore and Boot pins, and a chip based on the chip pin architecture. In order to achieve the above purpose, this application provides the following technical solutions.

[0006] A chip pin architecture for multiplexing Vcore and Boot pins, comprising a PMU module, a voltage comparison module and a Boot pin; the PMU module has a Vcore voltage terminal for providing a Vcore voltage to an internal circuit of the chip; an input signal of the Boot pin is sent to the voltage comparison module, the voltage comparison module comprises a first voltage comparator, the first voltage comparator compares the input signal of the Boot pin with a first reference voltage and outputs a startup mode selection signal for the chip when powered on; the Boot pin is also connected to the Vcore voltage terminal and is used to externally connect a Vcore capacitor to form a multiplexed pin.

[0007] In some implementations, the input level range of the Boot pin is an allowable voltage range of the Vcore voltage.

[0008] In some implementations, the voltage comparator is a hysteresis voltage comparator, one input terminal of the hysteresis voltage comparator inputs the first reference voltage, and the other input terminal inputs a level signal from the Boot pin; the first reference voltage is equal to the Vcore voltage.

[0009] In some embodiments, the voltage comparison module also includes a second voltage comparator, which compares the input signal of the Boot pin with a second reference voltage, and then outputs the startup mode selection signal together with the first voltage comparator, the second reference voltage is greater than the first reference voltage, when the input signal level of the Boot pin is lower than the first reference voltage, the first voltage comparator and the second voltage comparator both output a low level, when the input signal level of the Boot pin is higher than the second reference voltage, the first voltage comparator and the second voltage comparator both output a high level, when the input signal level of the Boot pin is between the first reference voltage and the second reference voltage, the first voltage comparator outputs a high level and the second voltage comparator outputs a low level, so that the startup mode selection signal includes three states.

[0010] In some implementations, the Boot pin inputs a level signal including the boot mode selection signal through a set Boot protocol, and the Boot protocol supports at least two boot modes.

[0011] In some implementations, the voltage comparison module further includes a digital filter, which filters the output of the voltage comparator, and the digital filter is suitable for filtering out interference signals having a frequency equal to the startup clock frequency.

[0012] In some implementations, the digital filter is a clock cycle filter, and a filtering reference clock frequency of the clock cycle filter is less than a startup clock frequency of the chip, so that the clock cycle filter can filter out interference signals with a frequency of the startup clock frequency.

[0013] In some embodiments, the voltage comparison module also includes a low-pass analog filter arranged between the Boot pin and the first voltage comparator, and the filtering parameters of the low-pass analog filter are matched with the startup clock frequency of the chip, so that the low-pass analog filter can filter out interference signals with a frequency of the startup clock frequency.

[0014] The present application also provides a Vcore and Boot pin multiplexing method for setting the pin architecture of a chip, wherein the chip includes a PMU module and a Boot pin, the Vcore voltage terminal of the PMU module provides a Vcore voltage for an internal circuit of the chip, and a voltage comparison module is set in the chip, and an input signal of the Boot pin is compared with a first reference voltage to output a startup mode selection signal of the chip when it is powered on; the Boot pin is simultaneously connected to the Vcore voltage terminal, and the Boot pin is simultaneously used for an external Vcore capacitor to form a multiplexed pin.

[0015] The present application also provides a chip, comprising any of the aforementioned chip pin architectures for multiplexing Vcore and Boot pins.

[0016] Each embodiment of the present application has at least one of the following technical effects:

[0017] 1. By setting the voltage comparison module to extract the carrier information on the Vcore voltage, the carrier information is used to control the startup mode of the chip, so as to realize the multiplexing of the Vcore and Boot pins and save limited pin resources.

[0018] 2. By limiting the signal level with carrier information input to the Boot pin within the allowable range of the Vcore voltage, the chip core can be guaranteed to work normally without risk.

[0019] 3. By setting an analog filter before the voltage comparator, or setting a digital filter after the voltage comparator, the noise outside the frequency domain of the Boot signal, especially the noise with the frequency of the chip startup clock, is filtered out to prevent the Vcore voltage noise caused by the operation of the core device from falsely triggering the Boot signal.

[0020] 4. By setting multiple voltage comparators and multiple reference voltages, multiple boot modes can be controlled by one Boot pin on some chips with a wide Vcore voltage allowable range; or multiple boot modes can be controlled by setting the Boot protocol.

[0021] 5. The noise signal with smaller amplitude is filtered out by setting the hysteresis voltage comparator, and the noise signal related to the chip startup clock frequency is effectively filtered out by reasonably setting the clock cycle filter and its filtering reference clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The preferred implementation modes will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present invention.

[0023] Figure 1 This is a schematic diagram of the pin arrangement of an existing MCU chip;

[0024] Figure 2 The chip architecture and chip schematic diagram of Vcore and Boot pin multiplexing in one embodiment;

[0025] Figure 3 yes Figure 2 The connection diagram of the chip and the programmer is shown;

[0026] Figure 4 is a schematic diagram of a chip according to another embodiment;

[0027] Figure 5 is a schematic diagram of a voltage comparison module of an embodiment;

[0028] Figure 6 It is a schematic diagram of the Boot signal and the startup mode signal with noise;

[0029] Figure 7 is a schematic diagram of a Boot signal and a startup mode signal of an embodiment;

[0030] Figure 8 is a schematic diagram of a Boot signal and a startup mode signal of another embodiment;

[0031] Description of Figure Numbers:

[0032] U0. Chip, U1. First voltage comparator, U2. Second voltage comparator, U3. Burner, U5. Digital filter, M1. Voltage comparison module, C1. Vcore capacitor, DVCC. Chip main power supply voltage, DVSS. Chip ground terminal, Vref1. First reference voltage, Vref2. Second reference voltage, Vth. Threshold voltage, Boot_Out. Startup mode selection signal. DETAILED DESCRIPTION

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0034] In order to make the drawings concise, only the parts related to the present application are schematically shown in each figure, and they do not represent the actual structure of the product. In some figures, only one of the parts with the same structure or function is schematically drawn, or only one of them is marked. In this article, "one" not only means "only one", but also means "more than one". The term "and / or" used in the specification of this application and the attached claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. The terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0035] Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0036] like Figure 2 As shown, in one embodiment of a chip pin architecture for multiplexing Vcore and Boot pins of the present application, a PMU module, a voltage comparison module M1 and a Boot pin are included; the PMU module has a Vcore voltage terminal for providing a Vcore voltage to the internal circuit of the chip U0; the voltage comparison module M1 includes a first voltage comparator U1, the input signal of the Boot pin is sent to the voltage comparison module M1, and the first voltage comparator U1 compares the input signal of the Boot pin with the first reference voltage Vref1 and outputs a startup mode selection signal Boot_Out of the chip U0 when it is powered on. The Boot pin is also connected to the Vcore voltage terminal of the PMU module, and the Boot pin is also used to externally connect the Vcore capacitor C1 to form a Vcore / Boot multiplexing pin.

[0037] In integrated circuits such as IoT SOC or general MCU, in order to reduce power consumption, the power supply voltage Vcore of the core is usually lower than the I / O voltage or the chip main power supply voltage DVCC. Its distribution is generally determined by the process of the core voltage. For example, the Vcore voltage of the TSMC 180nm process core is 1.8V, the Vcore voltage of the Grace 110nm process core is 1.5V, and the Vcore voltage of the UMC 55nm process core is 1.2V. In order to ensure the stability of the Vcore voltage when the power is turned on and the core is working, it is necessary to connect a large capacity Vcore capacitor C1 that is difficult to integrate to the chip U0, or to set multiple capacitors in combination. This application uses a Vcore capacitor C1 as an example. When the actual working voltage of the core is higher than 10% of the Vcore voltage or lower than 10% of the Vcore voltage, the working timing of the internal digital circuit will be at risk; when the core working voltage is as high as about 2 times the Vcore voltage, the internal digital circuit may even be damaged. Therefore, in order to ensure that the core devices work properly and eliminate the risk of device damage, the core operating voltage must be within an allowable range, typically 0.9 to 1.1 times the Vcore voltage. For example, under TSMC 180nm process, the Vcore voltage is between 1.8*0.9 and 1.8*1.1 (V), that is, between 1.62V and 1.98V, which can allow chip U0 to work normally without risk. Of course, in some occasions where risk control requirements are not high, the core operating voltage can also be allowed to slightly exceed this range for a short time.

[0038] In some embodiments, the input level range of the Boot pin is the allowable voltage range of the Vcore voltage. Typically, it can be always controlled between 0.9 and 1.1 Vcore voltages. A voltage clamping circuit can be set in the relevant circuit to achieve this. At the same time, the first voltage comparator U1 is powered by the chip main power supply voltage DVCC (not shown in the figure) so that it is not affected by Vcore voltage fluctuations. The specific connection method of the first voltage comparator U1 is that the in-phase input terminal is connected to the Boot pin, and the inverting input terminal is connected to the first reference voltage Vref1. According to the logic setting inside the chip U0, the opposite connection method can also be used. At the same time, the first reference voltage Vref1 can be set to a level value within the range of 0.9 to 1.1 times the Vcore voltage.

[0039] In the drawings of the present application, the pins of different integrated circuits and some of the signals connected thereto use the same labels, such as the chip main power voltage DVCC, the chip ground terminal DVSS, the Boot signal, etc. Since those skilled in the art can undoubtedly understand their meanings, they are no longer distinguished for the sake of simplicity.

[0040] Figure 3The figure shows a typical application scenario, where the programmer U3 sends a level signal of 1.1 times the Vcore voltage to the Boot pin of the chip U0, requesting the chip U0 to switch the boot mode to the burning mode. At this time, the first reference voltage Vref1 can be set to be equal to the Vcore voltage, so that the boot mode selection signal Boot_Out output by the first voltage comparator U1 is at a high level. Through the internal logic setting of the chip U0, the request intention of the programmer U3 can be identified, the boot mode is switched to the burning mode, and the corresponding Boot code is run.

[0041] In some embodiments, Figure 5 As shown, the first voltage comparator U1 is a hysteresis voltage comparator, the inverting input terminal of the hysteresis voltage comparator inputs the first reference voltage Vref1, and the non-inverting input terminal inputs the level signal from the Boot pin; the first reference voltage Vref1 is equal to the Vcore voltage. The hysteresis voltage comparator can filter out smaller voltage fluctuations, for example, the upper and lower thresholds of the hysteresis voltage comparator are set to 0.95 times the Vcore voltage and 1.05 times the Vcore voltage, as shown in FIG. Figure 6 and Figure 7 As shown, the Boot signal from the Boot pin has a similar Figure 6 When the noise signal with a small fluctuation amplitude is shown at A in the middle, the hysteresis characteristic of the hysteresis voltage comparator can be used to filter it out. When the core of the chip U0 is working, especially when it is powered on and started, if only a small amplitude Vcore voltage fluctuation is generated, it is only necessary to set the first voltage comparator U1 as a hysteresis voltage comparator and reasonably set the value of the threshold voltage Vth, which can achieve a good effect of filtering out noise.

[0042] In some embodiments, Figure 5 As shown, the voltage comparison module M1 also includes a digital filter U5, which filters the output of the first voltage comparator U1. The digital filter U5 is suitable for filtering out interference signals with a frequency equal to the startup clock frequency of the chip U0. The digital filter U5 can be a FIR filter, an IIR filter, a clock cycle filter, etc. The filtering parameters are set according to the chip startup clock frequency matching, and the digital filter U5 is also powered by the chip main power supply voltage DVCC. Generally, when powered on, the chip U0 in the form of MCU / SOC, etc., starts at a low speed, such as starting with a 4MHz / 8MHz startup clock frequency, so the noise frequency is basically at 4MHz / 8MHz. The protocol used by the Boot signal needs to avoid this noise frequency. At the same time, by setting the digital filter U5 as a low-pass filter, and its cut-off frequency is lower than the above-mentioned typical noise frequency, the recognition reliability of the correct boot mode selection signal Boot_Out from the Boot signal can be improved. For example Figure 6The noise signal with a large voltage fluctuation amplitude at B in the middle cannot be filtered out by the hysteresis voltage comparator alone because its fluctuation amplitude is greater than the hysteresis voltage threshold range of the hysteresis voltage comparator. However, due to its obvious frequency characteristics, it can be effectively filtered out by the digital filter U5. In addition to setting the cutoff frequency of the digital filter U5, other settings can also be used, such as the word length and order of the FIR filter for optimization design.

[0043] In some embodiments, Figure 5 As shown, the digital filter U5 is a clock cycle filter, and the filtering reference clock frequency of the clock cycle filter is less than the startup clock frequency of the chip U0, so that the clock cycle filter can filter out interference signals with a frequency of the startup clock frequency. Figure 8 As shown, when the Boot signal carries a signal similar to Figure 6 When the noise signal with large fluctuation amplitude is shown at B in the figure ( Figure 8 The noise signal is not shown in the Boot signal curve in FIG. 1 ), and the filtering reference clock frequency of the clock cycle filter can be determined by analyzing the distribution of its continuous width. Figure 6 and Figure 8 As shown in the figure, due to the large fluctuation amplitude of the noise at B, the noise still exists after passing through the hysteresis voltage comparator, and each occurrence lasts for 3 chip U0 startup clock cycles; at this time, the filter reference clock frequency can be set to 1 / 8 of the chip U0 startup clock frequency, that is, the filter reference clock period is set to 8 chip U0 startup clock widths, and the noise can be reliably filtered out. Of course, the filter reference clock frequency can be flexibly set according to actual conditions. Since the clock cycle filter usually generates a delay corresponding to the filter reference clock period, Figure 8 It can be seen that when the width N of the noise signal with a large fluctuation amplitude is smaller than the filtering delay T of the clock cycle filter, it can be filtered out by the clock cycle filter to obtain a reliable startup mode selection signal Boot_Out.

[0044] In some embodiments, Figure 4As shown, the voltage comparison module M1 also includes a second voltage comparator U2. The second voltage comparator U2 compares the input signal of the Boot pin with the second reference voltage Vref2, and then outputs the startup mode selection signal Boot_Out together with the first voltage comparator U1. The second reference voltage Vref2 is greater than the first reference voltage Vref1. When the input signal level of the Boot pin is lower than the first reference voltage Vref1, the first voltage comparator U1 and the second voltage comparator U2 both output a low level. When the input signal level of the Boot pin is higher than the second reference voltage Vref2, the first voltage comparator U1 and the second voltage comparator U2 both output a high level. When the input signal level of the Boot pin is between the first reference voltage Vref1 and the second reference voltage Vref2, the first voltage comparator U1 outputs a high level and the second voltage comparator U2 outputs a low level, so that the startup mode selection signal Boot_Out includes three states. At this time, the startup mode selection signal Boot_Out is equivalent to including a 2-bit digital signal, and therefore includes three states of 00, 01, and 11. The chip U0 sets the corresponding internal logic to achieve the selection of multiple startup modes. This embodiment can be used for application scenarios where the Vcore voltage is relatively high and its allowable range is relatively large. In this case, the first reference voltage Vref1 and the second reference voltage Vref2 can be set to 0.97 times the Vcore voltage and 1.03 times the Vcore voltage, respectively. The functions of the Boot0 and Boot1 pins of some integrated circuits can be implemented through one Boot pin.

[0045] In some embodiments, the Boot pin inputs a level signal including the boot mode selection signal Boot_Out through a set Boot protocol, and the Boot protocol supports at least two boot modes. For example, when the chip U0 detects that the boot mode selection signal Boot_Out changes from a low level to a high level, it enters the Boot protocol reading state, and determines which boot mode to adopt according to the subsequent change of the boot mode selection signal Boot_Out read.

[0046] In some embodiments, the voltage comparison module M1 further includes a low-pass analog filter disposed between the Boot pin and the first voltage comparator U1. The filtering parameters of the low-pass analog filter are matched with the startup clock frequency of the chip U0, so that the low-pass analog filter can filter out interference signals with a frequency equal to the startup clock frequency. The low-pass analog filter can adopt existing technology, for example, a large resistor can be simulated by a MOS tube, and a low-pass filter can be formed by combining a MOS tube section capacitor with a small capacitance value, so as to filter out interference signals with a frequency equal to the startup clock frequency, that is, Figure 6The noise signal shown at B in FIG. At this time, the first voltage comparator U1 uses a hysteresis voltage comparator to effectively filter out other noise signals with lower frequencies and smaller voltage fluctuations.

[0047] In one embodiment of a Vcore and Boot pin multiplexing method provided in the present application, as shown in FIG. Figure 1 As shown, the pin architecture of chip U0 is set. Chip U0 includes a PMU module and a Boot pin. The Vcore voltage terminal of the PMU module provides a Vcore voltage for the internal circuit of chip U0. The pin multiplexing method is: by setting a voltage comparison module M1 in chip U0, and comparing the input signal of the Boot pin with the first reference voltage Vref1, the boot mode selection signal Boot_Out of chip U0 when powered on is output; and connecting the Boot pin to the Vcore voltage terminal at the same time, and using the Boot pin for an external Vcore capacitor C1, so as to realize the multiplexing of Vcore and Boot pins.

[0048] In one embodiment of a chip provided in the present application, chip U0 includes a chip pin architecture for multiplexing Vcore and Boot pins provided in any of the above embodiments, and chip U0 can be various integrated circuits such as MCU, SOC, ASIC (special chip), MPU, etc. that need to connect Vcore capacitor C1 for core voltage and need to select the startup mode through Boot signal. The present invention solves the problem of how to reuse the core voltage Vcore and the startup pin Boot in the pin architecture design of IoT SOC and general MCU, especially Low Pin Count (few pins) chips, enhances the competitiveness of the product, and at the same time avoids the introduction of external port high voltage (such as the chip main power supply voltage DVCC of the external circuit) into the core device, eliminating the risk of burning the core device.

[0049] The above are only preferred embodiments of the present application and the technical principles used. Various obvious changes, readjustments and substitutions can be made without departing from the concept of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. In the absence of conflict, the above embodiments and the features in the embodiments can be combined with each other.

Claims

1. A chip pin architecture for multiplexing Vcore and Boot pins, characterized in that: Includes PMU module, voltage comparison module and Boot pin; The PMU module has a Vcore voltage terminal for providing a Vcore voltage to an internal circuit of the chip; The voltage comparison module includes a first voltage comparator, the input signal of the Boot pin is sent to the voltage comparison module, and the first voltage comparator compares the input signal of the Boot pin with a first reference voltage and then outputs a startup mode selection signal of the chip when it is powered on; The Boot pin is also connected to the Vcore voltage terminal and is used to externally connect a Vcore capacitor to form a multiplexed pin.

2. The chip pin architecture for multiplexing Vcore and Boot pins according to claim 1, characterized in that: The input level range of the Boot pin is the allowable voltage range of the Vcore voltage.

3. The chip pin architecture for multiplexing Vcore and Boot pins according to claim 1, characterized in that: The first voltage comparator is a hysteresis voltage comparator, one input terminal of the hysteresis voltage comparator inputs the first reference voltage, and the other input terminal inputs a level signal from the Boot pin; The first reference voltage is equal to the Vcore voltage.

4. The chip pin architecture for multiplexing Vcore and Boot pins according to claim 1, characterized in that: The voltage comparison module further includes a second voltage comparator, which compares the input signal of the Boot pin with a second reference voltage and then outputs the startup mode selection signal together with the first voltage comparator; The second reference voltage is greater than the first reference voltage. When the input signal level of the Boot pin is lower than the first reference voltage, the first voltage comparator and the second voltage comparator both output a low level. When the input signal level of the Boot pin is higher than the second reference voltage, the first voltage comparator and the second voltage comparator both output a high level. When the input signal level of the Boot pin is between the first reference voltage and the second reference voltage, the first voltage comparator outputs a high level and the second voltage comparator outputs a low level, so that the startup mode selection signal includes three states.

5. The chip pin architecture for multiplexing Vcore and Boot pins according to claim 1, characterized in that: The Boot pin inputs a level signal including the boot mode selection signal through a set Boot protocol, and the Boot protocol supports at least two boot modes.

6. The chip pin architecture for multiplexing Vcore and Boot pins according to any one of claims 1 to 5, characterized in that: The voltage comparison module further includes a digital filter, which filters the output of the first voltage comparator. The digital filter is suitable for filtering out interference signals having a frequency equal to the startup clock frequency.

7. The chip pin architecture for multiplexing Vcore and Boot pins according to claim 6, characterized in that: The digital filter is a clock cycle filter, and the filtering reference clock frequency of the clock cycle filter is less than the startup clock frequency of the chip, so that the clock cycle filter can filter out interference signals with a frequency of the startup clock frequency.

8. The chip pin architecture for multiplexing Vcore and Boot pins according to any one of claims 1 to 5, characterized in that: The voltage comparison module also includes a low-pass analog filter arranged between the Boot pin and the voltage comparator. The filtering parameters of the low-pass analog filter are matched with the startup clock frequency of the chip, so that the low-pass analog filter can filter out interference signals with a frequency of the startup clock frequency.

9. A Vcore and Boot pin multiplexing method for setting the pin architecture of a chip, wherein the chip includes a PMU module and a Boot pin, and the Vcore voltage terminal of the PMU module provides a Vcore voltage for an internal circuit of the chip, characterized in that: By setting a voltage comparison module in the chip, and comparing the input signal of the Boot pin with a first reference voltage, the startup mode selection signal of the chip is output when the chip is powered on and started; The Boot pin is connected to the Vcore voltage terminal at the same time, and the Boot pin is used to externally connect a Vcore capacitor to form a multiplexed pin.

10. A chip, characterized in that: A chip pin architecture comprising Vcore and Boot pin multiplexing according to any one of claims 1 to 8.

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