A successive approximation analog-to-digital converter and comparison method

Abstract

This invention relates to the field of integrated circuit technology and provides a successive approximation analog-to-digital converter (ADC) and a comparison method. The comparison method includes: providing a successive approximation ADC comprising n-1 weighted capacitors, a charge transfer capacitor, and a comparator; sampling an input differential signal through the first weighted capacitor and the charge transfer capacitor; importing the input differential signal stored on the charge transfer capacitor, transferring and redistributing the input differential signal across the other n-2 weighted capacitors and the charge transfer capacitor (excluding the first weighted capacitor), completing the first comparison; importing the input differential signal stored on the first weighted capacitor and the input differential signal stored on the charge transfer capacitor, and importing a reference voltage through the second to j-th weighted capacitors, transferring and redistributing the input differential signal and the reference voltage across the capacitor array, completing the j-th comparison, thus solving the bandwidth mismatch problem.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a successive approximation analog-to-digital converter and a comparison method. Background Technology

[0002] In recent years, with the continuous development of industrial control technology, the requirements for high-precision analog-to-digital converters (ADCs) have become increasingly higher. In industrial fields that require high-precision control, the accuracy requirement for ADCs has been raised to 18 bits, while the power consumption requirement has been further reduced. In the field of industrial control, due to the advantages of successive approximation analog-to-digital converters (SAR ADCs) such as low power consumption, digital process compatibility and relatively simple structure, SAR ADCs are still the main structure of 16-bit and above ADCs. In the traditional SAR ADC structure, the capacitor array is used as a sampling capacitor at the same time. The advantage of this structure is that no additional sampling capacitor is needed, saving chip area. However, the disadvantage is that multiple weighted capacitors are sampled at the same time. Because the voltage sampled by each weighted capacitor is actually different, the sampling accuracy is reduced, which directly causes the performance of the entire SAR ADC to decline. As the frequency of the input signal increases, this performance decline becomes more and more obvious. Therefore, the problems of the traditional SAR ADC structure are: (1) The sampling network is a multi-capacitor network, and the resistors and capacitors on each capacitor sampling path are different, which causes bandwidth mismatch on each sampling capacitor path. (2) In order to ensure the reliability of the comparator, the amplitude of the input differential signal is up to twice the voltage difference between the power supply and ground of the comparator, which increases the noise requirements of the comparator. Summary of the Invention

[0003] This invention provides a successive approximation analog-to-digital converter and a comparison method to solve the problems of bandwidth mismatch and high comparator noise requirements in existing successive approximation analog-to-digital converters.

[0004] To achieve the above and other related objectives, the present invention provides a successive approximation analog-to-digital converter, comprising:

[0005] Comparator;

[0006] The capacitor array includes a first capacitor array and a second capacitor array. Both the first capacitor array and the second capacitor array include n-1 weighted capacitors and charge transfer capacitors. The first plate of the first capacitor array is connected to the non-inverting input terminal of the comparator, and the first plate of the second capacitor array is connected to the inverting input terminal of the comparator. Here, n is an integer greater than or equal to 3, and the n-1 weighted capacitors are arranged in descending order of capacitance, with the first weighted capacitor having the largest capacitance and the last weighted capacitor having the smallest capacitance.

[0007] The system includes a first channel switch, a second channel switch, a third channel switch, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first switch array, and a second switch array. A first common-mode voltage, after passing through the first channel switch connected in series, is connected to the non-inverting input of the comparator. The first common-mode voltage, after passing through the second channel switch connected in series, is connected to the inverting input of the comparator. The third channel switch is connected in series between the non-inverting and inverting inputs of the comparator. The second plate of the first weighted capacitor in the first capacitor array is also connected to the first output of the input differential signal via the first switch connected in series. The second plate of the first weighted capacitor in the second capacitor array is also connected to the second output of the input differential signal via the second switch connected in series. The first charge transfer capacitor in the first capacitor array... The second plate of the charge transfer capacitor in the second capacitor array is also connected to the first output terminal of the input differential signal via the third switch connected in series. The second plate of the first weighted capacitor in the capacitor array is connected to the second common-mode voltage via the fifth switch. The second plate of the charge transfer capacitor in the capacitor array is connected to the second common-mode voltage via the sixth switch. The second plate of the last weighted capacitor in the capacitor array is grounded. The second plate of the m-th weighted capacitor in the capacitor array is connected to the second common-mode voltage via the corresponding switch in the first switch array. The second plate of the m-th weighted capacitor in the capacitor array is also connected to the reference voltage via the corresponding switch in the second switch array, where m = 2, 3, ..., n-2.

[0008] The logic control module has its input terminal connected to the output terminal of the comparator and its output terminal connected to the second switch array. It controls each switch in the second switch array according to the output signal of the comparator, so that the m-th weighted capacitor is repeatedly superimposed with the reference voltage to successively approximate the conversion, and performs successive approximation comparison based on the comparator to achieve analog-to-digital conversion.

[0009] Optionally, the capacitance of the charge transfer capacitor is smaller than the capacitance of the last weighted capacitor.

[0010] Optionally, the capacitor array further includes: a redundant bit capacitor array, wherein the second plate of the redundant bit capacitor array is connected to the second common-mode voltage through a corresponding switch in the first switch array, and the second plate of the redundant bit capacitor array is also connected to the reference voltage through a corresponding switch in the second switch array.

[0011] Optionally, the weight values ​​of the weighted capacitor from the high bit to the low bit are respectively: 2 n-2 C,2n-3 C, ..., 2C, C.

[0012] Optionally, when in sampling state, the first channel switch, the second channel switch, the third channel switch, the first switch, the second switch, the third switch, and the fourth switch are turned on, and the first switch array is controlled so that the second plate of the m-th weighted capacitor in the capacitor array is connected to the second common-mode voltage, and the first weighted capacitor and the charge transfer capacitor sample the input differential signal.

[0013] Optionally, after sampling, the first weighted capacitor is controlled to be in an off state, the sixth switch is turned on, and the first switch array is controlled so that the second plate of the m-th weighted capacitor in the capacitor array is connected to the second common-mode voltage. The input differential signal stored on the charge transfer capacitor is transferred and redistributed on the other n-2 weighted capacitors and the charge transfer capacitor to reduce the amplitude of the input differential signal. The reduced input differential signal is received by the comparator and the first comparison is completed to obtain the polarity of the input differential signal and output the highest bit digital code.

[0014] Optionally, after the first comparison, the fifth and sixth switches are turned on, controlling the first switch array so that the second plate of the m-th weighted capacitor in the capacitor array is connected to the second common-mode voltage, importing the input differential signal stored on the first weighted capacitor and the input differential signal stored on the charge transfer capacitor, and controlling the second switch array through the logic control module so that the other n-3 weighted capacitors are successively superimposed to import the reference voltage for successive approximation conversion. After n-3 comparisons, the n-3-bit output code of the successive approximation analog-to-digital converter is obtained sequentially, completing the comparison process.

[0015] To achieve the above and other related objectives, the present invention also provides a comparison method for a successive approximation analog-to-digital converter, comprising:

[0016] A successive approximation analog-to-digital converter is provided, the successive approximation analog-to-digital converter including a capacitor array and a comparator, the capacitor array including at least n-1 weight capacitors and charge transfer capacitors, where n is an integer greater than or equal to 3, the n-1 weight capacitors are arranged in descending order of capacitance, the first weight capacitor has the largest capacitance and the last weight capacitor has the smallest capacitance;

[0017] The input differential signal is sampled using the first weighted capacitor and the charge transfer capacitor;

[0018] The input differential signal stored on the charge transfer capacitor is imported, and the input differential signal is transferred and redistributed on the other n-2 weight capacitors and the charge transfer capacitors except for the first weight capacitor to form a first differential signal. The first differential signal is received by the comparator and the first comparison is completed to obtain the polarity of the input differential signal and output the highest bit digital code.

[0019] The input differential signal stored on the first weighted capacitor and the input differential signal stored on the charge transfer capacitor are imported, and the reference voltage is imported through the second to j-th weighted capacitors. The input differential signal and the reference voltage are transferred and redistributed on the capacitor array to form the j-th differential signal. The comparator receives the j-th differential signal and completes the j-th comparison, and outputs the corresponding digital code, where j is an integer from 2 to n-2.

[0020] Optionally, the capacitance of the charge transfer capacitor is smaller than the capacitance of the last weighted capacitor.

[0021] Optionally, the capacitor array further includes a redundant bit capacitor array, and the comparison method of the successive approximation analog-to-digital converter further includes:

[0022] During the j-th comparison, a reference voltage is introduced through the redundant bit capacitor array to correct the j-th differential signal.

[0023] The beneficial effects of this invention are as follows: The successive approximation analog-to-digital converter (ADC) of this invention significantly reduces the input differential signal by introducing a charge transfer capacitor. During the first comparison, the polarity of the input differential signal is directly compared, allowing the amplitude of the input differential signal to be greater than twice the voltage difference between the comparator's power supply and ground. This reduces the noise requirements of the comparator without affecting its reliability, thereby improving the signal-to-noise ratio of the successive approximation ADC. By using a first weighted capacitor and a charge transfer capacitor for sampling, the capacitor array can be approximated as a single capacitor sampling network. This eliminates the bandwidth mismatch problem of the sampling network caused by multiple capacitors and multiple sampling paths in traditional successive approximation ADCs, significantly improving the sampling accuracy of the successive approximation ADC and thus significantly enhancing the overall performance of the successive approximation ADC. Attached Figure Description

[0024] Figure 1 The diagram shows the schematic and timing sequence of a traditional SAR ADC.

[0025] Figure 2 The diagram shows the schematic and timing sequence of the improved SAR ADC structure.

[0026] Figure 3The diagram shows the sampling equivalent principle of the improved SAR ADC.

[0027] Figure 4 The diagram shows the principle of capacitor array technology in the successive approximation analog-to-digital converter of this invention.

[0028] Figure 5 The diagram shows the sampling state principle in this invention.

[0029] Figure 6 The diagram shown is an equivalent schematic diagram under the sampling state in this invention.

[0030] Figure 7 The diagram shows the equivalent principle under the charge transfer state in this invention.

[0031] Figure 8 The diagram shown is the equivalent principle diagram after the first comparison in this invention.

[0032] Figure 9 The diagram shows the transient waveforms of VP and VN in this invention.

[0033] Figure 10 The diagram shows a comparison of the SNR of the two structures under varying input signal frequencies in this invention.

[0034] Figure 11 The diagram shows a comparison of two SFDR structures under varying input signal frequency conditions in this invention. Detailed Implementation

[0035] As mentioned in the background section, traditional SAR ADCs suffer from bandwidth mismatch and high comparator noise requirements. To describe these two issues in more detail, we will take a traditional SAR ADC as an example and analyze its working principle, advantages, and disadvantages.

[0036] Figure 1 The diagram shows the schematic and timing diagram of a traditional successive approximation analog-to-digital converter, such as... Figure 1As shown, when the SARADC is in sampling mode, switches S1 and S2 are turned on. One plate of the sampling capacitor array is connected to the input signals VIP and VIN, and simultaneously to the input of the comparator. The other plate of the sampling capacitor array is connected to the common-mode voltage VCM. At this time, the sampling capacitor array tracks the input signal. When the SAR ADC completes sampling, switch S1 is turned off first, and the comparator performs the first comparison. Subsequently, switch S2 is turned off, and the other plate of the capacitor array is connected to the positive reference voltage VRP or the negative reference voltage VRN sequentially through the switch array SRN(n-1) / SRP(n-1), ..., SRN2 / SRP2, until one successive approximation process is completed. The advantage of this structure is its simple circuitry and timing. However, as the sampling frequency increases, the on-resistance of switch S1 needs to be reduced. Therefore, the area of ​​switch S1 increases with the sampling frequency, which leads to severe charge injection and clock feedthrough phenomena in switch S1, affecting the sampling accuracy of the SAR ADC and thus its overall performance. In summary, the problems of traditional SAR ADC structures are: (1) The sampling network is a multi-capacitor network, and the resistors and capacitors on each capacitor sampling path are different. Therefore, bandwidth mismatch will occur on each sampling capacitor path. (2) In order to ensure the reliability of the comparator, the amplitude of the input differential signal is up to twice the voltage difference between the comparator power supply and ground, which increases the noise requirements of the comparator.

[0037] Based on the above problems, a new sampling structure is proposed, and the schematic and timing diagram of the improved SAR ADC are as follows: Figure 2As shown, one plate of the sampling capacitor array is connected to the common-mode voltage VCM1 via switch S, and simultaneously to the differential input of the comparator COMP. The other plate of the sampling capacitor array is connected to the differential input signals VIP and VIN via switch S1, and to the common-mode voltage VCM2 via switch S2. The switch array SRN(n-1) / SRP(n-1), ..., SRN2 / SRP2 are connected to the positive and negative reference voltages VRP or VRN. When the SAR ADC is in sampling mode, switches S and S1 are turned on, and the sampling capacitor array samples the input signals VIP and VIN. After sampling is complete, switch S is first turned off. Since switch S is connected to the common-mode voltage VCM1, the error caused by charge injection and clock feedthrough when switch S is turned off is a common-mode error and will not affect the differential sampling result. Therefore, it will not affect the overall performance of the SAR ADC. This structure is also the common sampling structure of current SAR ADCs. However, this structure also has a significant problem, which will be explained below. Since each weighted capacitor C(n-1), ..., C2 in the capacitor array is connected to the input signal switch S1 as an independent switch, during the sampling process, it is equivalent to multiple capacitors sampling the input signal. The improved SAR ADC sampling equivalent principle diagram is shown below. Figure 3 As shown, the sampling switch network can be equivalently represented as a resistor network composed of resistors Rm_n-1, ..., Rm_2 and Rs2_n-1, ..., Rs2_2. Therefore, the actual sampling voltages of the sampling plates of the sampling capacitor array are VIP_n-1 / VIN_n-1, ..., VIP_2 / VIN_2, respectively. This indicates that the actual voltage sampled by each weighted capacitor in the sampling resistor array is different, and this error can be equivalent to a bandwidth mismatch. When the output signal frequency is low, the difference in actual sampling voltage caused by the above problem is not significant. However, as the input signal frequency increases, the difference in actual voltage sampled by each weighted capacitor increases significantly. The increased sampling error caused by the bandwidth mismatch will seriously affect the overall performance of the SAR ADC. This problem is also a performance bottleneck currently encountered by SAR ADCs, causing a significant decrease in the performance of SAR ADCs at high-frequency inputs. If one or more weighted capacitors are used for sampling, the bandwidth mismatch problem of the sampling network can be suppressed, but the actual sampling voltage amplitude will decrease after charge transfer, thus placing higher demands on the noise of the comparator.

[0038] Therefore, the inventors proposed a novel concept: a successive approximation analog-to-digital converter (ADC). By introducing a charge transfer capacitor, the input differential signal is significantly reduced. During the first comparison, the polarity of the input differential signal is directly compared, allowing the amplitude of the input differential signal to be greater than twice the voltage difference between the comparator's power supply and ground. This reduces the noise requirements of the comparator without affecting its reliability, thereby improving the signal-to-noise ratio (SNR) of the successive approximation ADC. By using a first weighted capacitor and a charge transfer capacitor for sampling, the capacitor array can be approximated as a single capacitor sampling network. This eliminates the bandwidth mismatch problem in traditional successive approximation ADCs caused by multiple capacitors and multiple sampling paths, significantly improving the sampling accuracy and overall performance of the successive approximation ADC.

[0039] Specifically, this invention provides a successive approximation analog-to-digital converter, comprising: a comparator; and a capacitor array, including a first capacitor array and a second capacitor array, each including n-1 weighted capacitors and charge transfer capacitors. The first plate of the first capacitor array is connected to the non-inverting input of the comparator, and the first plate of the second capacitor array is connected to the inverting input of the comparator. The n-1 weighted capacitors are arranged in descending order of capacitance. In the sampling state, the first weighted capacitor and the charge transfer capacitor sample the input differential signal. After sampling, the first weighted capacitor is deactivated, and the input differential signal stored on the charge transfer capacitor is transferred and redistributed on the other n-2 weighted capacitors and the charge transfer capacitor to reduce the amplitude of the input differential signal. The comparator receives the reduced input differential signal and completes the first comparison to obtain the polarity of the input differential signal, and outputs the highest-order digit code.

[0040] Optionally, the capacitance of the charge transfer capacitor is smaller than the capacitance of the least significant bit weighted capacitor. Optionally, the capacitor array further includes a redundant bit capacitor array. Optionally, the weight values ​​of the weighted capacitors from the most significant bit to the least significant bit are 2. n-2 C,2 n -3 C, ..., 2C, C.

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0042] Please see Figures 4 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0043] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0044] Please see Figure 4The successive approximation analog-to-digital converter includes: a comparator, the input of which is connected to the control signal CLK; a capacitor array, including a first capacitor array, a second capacitor array, and a redundant capacitor array RDAC, wherein both the first and second capacitor arrays include n-1 weighted capacitors (C1, C2, ..., Cn-1) and a charge transfer capacitor Cc, the first plate of the first capacitor array is connected to the non-inverting input (+) of the comparator, and the first plate of the second capacitor array is connected to the inverting input (-) of the comparator, where n is an integer greater than or equal to 3, and the n-1 weighted capacitors are arranged in descending order of capacitance, with the first weighted capacitor Cn-1 having the largest capacitance and the last weighted capacitor C1 having the smallest capacitance; and a switch, including... The circuit consists of a first channel switch S3, a second channel switch S4, a third channel switch S5, a first switch S6, a second switch S7, a third switch S8, a fourth switch S9, a fifth switch S10, a sixth switch S11, a first switch array S12, and a second switch array S13. The first common-mode voltage VCM1, after passing through the first channel switch S3 in series, is connected to the non-inverting input (+) of the comparator. The first common-mode voltage VCM1, after passing through the second channel switch S4 in series, is connected to the inverting input (-) of the comparator. A third channel switch S5 is connected in series between the non-inverting input (+) and the inverting input (-) of the comparator. The second plate of the first weighted capacitor Cn-1 in the first capacitor array is also connected to the first switch S6 in series. The first output terminal VIP of the input differential signal is connected to the second output terminal VIN of the input differential signal via a second switch S7 connected in series. The second plate of the charge transfer capacitor Cc in the first capacitor array is also connected to the first output terminal VIP of the input differential signal via a third switch S8 connected in series. The second plate of the charge transfer capacitor Cc in the second capacitor array is also connected to the second output terminal VIN of the input differential signal via a fourth switch S9 connected in series. The second plate of the first weight capacitor Cn-1 in the capacitor array is connected to the second common-mode voltage VCM2 via a fifth switch S10. The second plate of the charge transfer capacitor Cc in the capacitor array is connected to the second common-mode voltage VC via a sixth switch S11. M2 connection, the second plate of the last weighted capacitor C1 in the capacitor array is grounded, the second plate of the m-th weighted capacitor (C2, C3, ..., Cn-2) in the capacitor array is connected to the second common-mode voltage VCM2 through the corresponding switch in the first switch array S12, the second plate of the redundant bit capacitor array RDAC is connected to the second common-mode voltage VCM2 through the corresponding switch in the first switch array S12, the second plate of the m-th weighted capacitor in the capacitor array is also connected to the reference voltage VRP / VRN through the corresponding switch in the second switch array S13, and the second plate of the redundant bit capacitor array RDAC in the capacitor array is also connected to the reference voltage VRP / VRN through the corresponding switch in the second switch array S13.Where m = 2, 3, ..., n-2; the logic control module has its input connected to the output of the comparator, and its output connected to the second switch array S13. Based on the comparator's output signal, it controls each switch in the second switch array S13, causing the m-th weighted capacitor and the redundant bit capacitor array RDAC to be successively superimposed with a reference voltage for successive approximation conversion. Successive approximation comparisons are then performed based on the comparator to achieve analog-to-digital conversion. Specifically, the capacitance of the charge transfer capacitor Cc is less than the capacitance of the last weighted capacitor C1.

[0045] Please see Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the sampling state. Figure 4 When the successive approximation analog-to-digital converter is in sampling mode, the first channel switch S3, the second channel switch S4, the third channel switch S5, the first switch S6, the second switch S7, the third switch S8, and the fourth switch S9 are turned on. This controls the first switch array S12 so that the second plate of the m-th weighted capacitor in the capacitor array is connected to the second common-mode voltage VCM2. The first weighted capacitor Cn-1 and the charge transfer capacitor Cc sample the input differential signals VIP and VIN. The equivalent sampling circuit at this time is as follows: Figure 6 As shown, the actual sampling voltages of the second plate of capacitor C(n-1) are VIP_n-1 and VIN_n-1, respectively, and the actual sampling voltages of the second plate of capacitor Cc are VIP_n-2 and VIN_n-2, respectively. Since the capacitor Cc is set to be very small (less than the last weighted capacitor C1), the actual differential sampling voltage can be approximated as (VIP_n-1)-(VIN_n-1). This eliminates the bandwidth mismatch problem caused by the different weighted capacitors in the traditional structure.

[0046] Please see Figure 7 , Figure 7 This is the equivalent schematic diagram under charge transfer conditions. After sampling, when Figure 4When the successive approximation analog-to-digital converter is in charge transfer mode, the first weighted capacitor C(n-1) is turned off, the sixth switch S11 is turned on, and the first switch array S12 is controlled so that the second plate of the m-th weighted capacitor in the capacitor array is connected to the second common-mode voltage VCM2. The input differential signal stored on the charge transfer capacitor Cc is transferred and redistributed on the other n-2 weighted capacitors (C1, C2, ..., Cn-2), the redundant bit capacitor array RDAC, and the charge transfer capacitor Cc to reduce the amplitude of the input differential signal. The reduced input differential signal is received by the comparator and the first comparison is completed to obtain the polarity of the input differential signal and output the highest bit digital code. At this point, the mathematical expression for the input differential signals VP and VN of the comparator is VP-VN=(Cc / (C(n-2)+C(n-3)+…+C3+C2+Cc+CRDAC))(VIN-VIP), which is equivalent to the input differential signal (VIN-VIP) being multiplied by a very small coefficient and then transferred to the input of the comparator. This allows the amplitude of the input differential signal to be greater than twice the voltage difference between the comparator's power supply and ground. Without affecting the reliability of the comparator, the amplitude of the input differential signal is increased to the maximum extent, thereby improving the signal-to-noise ratio, while not increasing the noise requirements of the comparator.

[0047] Please see Figure 8 and Figure 9 ,like Figure 8 As shown, after the first comparison, the fifth switch S10 and the sixth switch S11 are turned on, controlling the first switch array S12 to connect the second plate of the m-th weighted capacitor in the capacitor array to the second common-mode voltage VCM2. The input differential signal stored on the first weighted capacitor C(n-1) and the input differential signal stored on the charge transfer capacitor Cc are then input. The logic control module controls the second switch array S13 to successively superimpose the reference voltage onto the other n-3 weighted capacitors and the redundant capacitor array for successive approximation conversion. After n-3 comparisons, the n-2-bit output code of the successive approximation analog-to-digital converter is obtained sequentially, completing the comparison process. The successive approximation waveforms of the comparator's differential input signals VP and VN are shown in the diagram below. Figure 9 As shown, when in sampling mode, the differential input signals VP and VN of the comparator are both equal to VCM1. From VP-VN=(Cc / (C(n-2)+C(n-3)+…+C3+C2+Cc+CRDAC))(VIN-VIP), we know that after Cc transfers the sampled charge, when VIP is less than VIN, the differential input signals VP and VN of the comparator successively approximate each other. (See the schematic diagram below.) Figure 9 As shown in (a); when VIP is greater than VIN, the successive approximation diagram of the differential input signals VP and VN of the comparator is as follows. Figure 9 As shown in (b). Figure 9It can be seen that the above successive approximation will produce an error of 2ΔV. Therefore, in the subsequent successive approximation process, a redundant bit capacitor array RDAC can be added to correct the above error.

[0048] Please see Figure 10 and Figure 11 In one specific embodiment, using a 180nm CMOS process, Figure 2 The improved SAR ADC structure shown and the present invention Figure 4 The SAR ADC structure shown is designed as an 18-bit 2MHz SAR ADC. The power supply voltage is 1.8V, and the sampling frequency is 2MHz. Figure 2 The improved SAR ADC structure shown has an input differential signal amplitude of 3.6V, while the SAR ADC structure using the present invention has an input differential signal amplitude of 7.2V. At a sampling frequency of 2MHz, Figure 2 The simulation results of the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) of the improved SAR ADC structure shown in the figure and the SAR ADC structure shown in this invention are compared as follows: Figure 10 and Figure 11 As shown in the simulation results above, the high-precision SARADC sampling technology proposed in this invention can significantly improve the accuracy of the SAR ADC. The performance advantages of the structure shown in this invention become even more pronounced as the input signal frequency increases.

[0049] Therefore, the successive approximation analog-to-digital converter (ADC) described above significantly reduces the input differential signal by introducing a charge transfer capacitor. During the first comparison, the polarity of the input differential signal is directly compared, allowing the input differential signal amplitude to be greater than twice the comparator power-to-ground voltage difference. This reduces the comparator noise requirements without affecting comparator reliability, thereby improving the signal-to-noise ratio (SNR) of the successive approximation ADC. By using the first weighted capacitor and the charge transfer capacitor for sampling, the capacitor array can be approximated as a single capacitor sampling network, eliminating the bandwidth mismatch problem caused by multiple capacitors and sampling paths in traditional successive approximation ADCs. This significantly improves the sampling accuracy of the successive approximation ADC, resulting in a significant performance improvement. The introduction of a redundant bit capacitor array (RDAC) corrects for errors generated during the connection of the second plate of charge transfer Cc and C(n-1) to VCM2, ensuring the accuracy of the entire successive approximation ADC during the successive approximation process.

[0050] The present invention also provides an electronic device comprising the above-described successive approximation analog-to-digital converter.

[0051] Based on the same inventive concept as the successive approximation analog-to-digital converters described above, this embodiment also provides a comparison method for successive approximation analog-to-digital converters. In this embodiment, the method is implemented on the successive approximation analog-to-digital converter described in any of the above embodiments. The specific functions and technical effects are the same as those in the above embodiments and will not be repeated here.

[0052] In one embodiment, the comparison method of a successive approximation analog-to-digital converter includes: providing a successive approximation analog-to-digital converter, the successive approximation analog-to-digital converter including a capacitor array and a comparator, the capacitor array including at least n-1 weighted capacitors and charge transfer capacitors, where n is an integer greater than or equal to 3, the n-1 weighted capacitors are arranged in descending order of capacitance, the first weighted capacitor has the largest capacitance, and the last weighted capacitor has the smallest capacitance; sampling an input differential signal through the first weighted capacitor and the charge transfer capacitor; importing the input differential signal stored on the charge transfer capacitor, the input differential signal being sampled by the other n-2 weighted capacitors excluding the first weighted capacitor. The input differential signal is transferred and redistributed on the weighted capacitors and charge transfer capacitors to form a first differential signal. The comparator receives the first differential signal and completes the first comparison to obtain the polarity of the input differential signal and output the highest bit digital code. The input differential signal stored on the first weighted capacitor and the input differential signal stored on the charge transfer capacitor are imported, and a reference voltage is introduced through the second to j-th weighted capacitors. The input differential signal and the reference voltage are transferred and redistributed on the capacitor array to form a j-th differential signal. The comparator receives the j-th differential signal and completes the j-th comparison to output the corresponding digital code, where j is an integer from 2 to n-2. Optionally, the capacitance of the charge transfer capacitor is less than the capacitance of the last weighted capacitor. Optionally, the capacitor array further includes a redundant bit capacitor array, and the comparison method of the successive approximation analog-to-digital converter further includes: during the j-th comparison, introducing the reference voltage through the redundant bit capacitor array to correct the j-th differential signal.

[0053] In summary, the successive approximation analog-to-digital converter (ADC) of this invention significantly reduces the input differential signal by introducing a charge transfer capacitor. During the first comparison, the polarity of the input differential signal is directly compared, allowing the input differential signal amplitude to be greater than twice the comparator power-to-ground voltage difference. This reduces the noise requirements of the comparator without affecting its reliability, thereby improving the signal-to-noise ratio of the successive approximation ADC. By using a first weighted capacitor and a charge transfer capacitor for sampling, the capacitor array can be approximated as a single capacitor sampling network, eliminating the bandwidth mismatch problem caused by multiple capacitors and sampling paths in traditional successive approximation ADCs. This significantly improves the sampling accuracy of the successive approximation ADC, resulting in a significant performance improvement. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A successive approximation analog-to-digital converter, characterized in that, include: Comparator; The capacitor array includes a first capacitor array and a second capacitor array. Both the first capacitor array and the second capacitor array include n-1 weighted capacitors and charge transfer capacitors. The first plate of the first capacitor array is connected to the non-inverting input terminal of the comparator, and the first plate of the second capacitor array is connected to the inverting input terminal of the comparator. Here, n is an integer greater than or equal to 3, and the n-1 weighted capacitors are arranged in descending order of capacitance, with the first weighted capacitor having the largest capacitance and the last weighted capacitor having the smallest capacitance. The system includes a first channel switch, a second channel switch, a third channel switch, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first switch array, and a second switch array. A first common-mode voltage, after passing through the first channel switch connected in series, is connected to the non-inverting input of the comparator. The first common-mode voltage, after passing through the second channel switch connected in series, is connected to the inverting input of the comparator. The third channel switch is connected in series between the non-inverting and inverting inputs of the comparator. The second plate of the first weighted capacitor in the first capacitor array is also connected to the first output of the input differential signal via the first switch connected in series. The second plate of the first weighted capacitor in the second capacitor array is also connected to the second output of the input differential signal via the second switch connected in series. The first charge transfer capacitor in the first capacitor array... The second plate of the charge transfer capacitor in the second capacitor array is also connected to the first output terminal of the input differential signal via the third switch connected in series. The second plate of the first weighted capacitor in the capacitor array is connected to the second common-mode voltage via the fifth switch. The second plate of the charge transfer capacitor in the capacitor array is connected to the second common-mode voltage via the sixth switch. The second plate of the last weighted capacitor in the capacitor array is grounded. The second plate of the m-th weighted capacitor in the capacitor array is connected to the second common-mode voltage via the corresponding switch in the first switch array. The second plate of the m-th weighted capacitor in the capacitor array is also connected to the reference voltage via the corresponding switch in the second switch array, where m = 2, 3, ..., n-2. The logic control module has its input terminal connected to the output terminal of the comparator and its output terminal connected to the second switch array. It controls each switch in the second switch array according to the output signal of the comparator, so that the m-th weighted capacitor is repeatedly superimposed with the reference voltage to successively approximate the conversion, and performs successive approximation comparison based on the comparator to realize analog-to-digital conversion. When in sampling state, the first channel switch, the second channel switch, the third channel switch, the first switch, the second switch, the third switch and the fourth switch are turned on, and the first switch array is controlled so that the second plate of the m-th weighted capacitor in the capacitor array is connected to the second common-mode voltage. The first weighted capacitor and the charge transfer capacitor sample the input differential signal. After sampling, the first weighted capacitor is turned off, the sixth switch is turned on, and the first switch array is controlled so that the second plate of the m-th weighted capacitor in the capacitor array is connected to the second common-mode voltage. The input differential signal stored on the charge transfer capacitor is transferred and redistributed on the other n-2 weighted capacitors and the charge transfer capacitor to reduce the amplitude of the input differential signal. The reduced input differential signal is received by the comparator and the first comparison is completed to obtain the polarity of the input differential signal and output the highest bit digital code.

2. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The capacitance of the charge transfer capacitor is less than the capacitance of the last weighted capacitor.

3. The successive approximation analog-to-digital converter according to claim 2, characterized in that, The capacitor array further includes: A redundant bit capacitor array, wherein the second plate of the redundant bit capacitor array is connected to the second common-mode voltage through a corresponding switch in the first switch array, and the second plate of the redundant bit capacitor array is also connected to the reference voltage through a corresponding switch in the second switch array.

4. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The weight values ​​of the weighted capacitors from high to low are: 2 n-2 C,2 n-3 C, ..., 2C, C.

5. The successive approximation analog-to-digital converter according to claim 1, characterized in that, After the first comparison, the fifth and sixth switches are turned on, controlling the first switch array so that the second plate of the m-th weighted capacitor in the capacitor array is connected to the second common-mode voltage. The input differential signal stored on the first weighted capacitor and the input differential signal stored on the charge transfer capacitor are imported. The logic control module controls the second switch array so that the other n-3 weighted capacitors are successively superimposed to import the reference voltage for successive approximation conversion. After n-3 comparisons, the n-3-bit output code of the successive approximation analog-to-digital converter is obtained sequentially, completing the comparison process.

6. A comparison method for a successive approximation analog-to-digital converter, characterized in that, include: A successive approximation analog-to-digital converter as described in any one of claims 1 to 5 is provided, the successive approximation analog-to-digital converter comprising a capacitor array and a comparator, the capacitor array comprising at least n-1 weight capacitors and charge transfer capacitors, wherein n is an integer greater than or equal to 3, the n-1 weight capacitors are arranged in descending order of capacitance, the first weight capacitor has the largest capacitance, and the last weight capacitor has the smallest capacitance; The input differential signal is sampled using the first weighted capacitor and the charge transfer capacitor; The input differential signal stored on the charge transfer capacitor is imported, and the input differential signal is transferred and redistributed on the other n-2 weight capacitors and the charge transfer capacitors except for the first weight capacitor to form a first differential signal. The first differential signal is received by the comparator and the first comparison is completed to obtain the polarity of the input differential signal and output the highest bit digital code. The input differential signal stored on the first weighted capacitor and the input differential signal stored on the charge transfer capacitor are imported, and the reference voltage is imported through the second to j-th weighted capacitors. The input differential signal and the reference voltage are transferred and redistributed on the capacitor array to form the j-th differential signal. The comparator receives the j-th differential signal and completes the j-th comparison, and outputs the corresponding digital code, where j is an integer from 2 to n-2.

7. The comparison method for a successive approximation analog-to-digital converter according to claim 6, characterized in that, The capacitance of the charge transfer capacitor is less than the capacitance of the last weighted capacitor.

8. The comparison method for a successive approximation analog-to-digital converter according to claim 7, characterized in that, The capacitor array further includes a redundant bit capacitor array, and the comparison method of the successive approximation analog-to-digital converter further includes: During the j-th comparison, a reference voltage is introduced through the redundant bit capacitor array to correct the j-th differential signal.

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