Semiconductor device

Abstract

The semiconductor device (1) includes a semiconductor substrate (10), which has an active region (10A) where a main switch element structure is formed, a current sensing region (10B) where a sense switch element structure is formed, and a peripheral region (10C) located around the active region and the current sensing region. The semiconductor substrate is a 4H-SiC substrate having an off-angle in the <11-20> direction. The current sensing region is arranged in a range where the active region does not exist when observed along the <1-100> direction.

Description

[0001] (Cross - reference to related applications)

[0002] This application is a related application of Japanese Patent Application No. 2019 - 154890 filed on August 27, 2019. Priority is claimed based on this Japanese application, and the entire contents thereof are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor device. Background Art

[0004] The development of semiconductor devices manufactured using a SiC substrate is in progress. The SiC substrate of such a semiconductor device has an active region in which a main switching element structure is formed, a current sensing region in which a sensing switching element structure is formed, and a peripheral region located around the active region and the current sensing region. The current sensing region constitutes, for example, 1 / 1000 of the area ratio of the active region. In such a semiconductor device, it is configured to detect the current flowing through the current sensing region and convert the detected current using a sensing ratio based on the area ratio, thereby monitoring the current flowing through the active region. An example of such a semiconductor device is disclosed in Japanese Unexamined Patent Application Publication No. 2017 - 79324. Summary of the Invention

[0005] Problems to be Solved by the Invention

[0006] When operating such a semiconductor device, there is a case where strip - like defects, which are a type of stacking defect, grow in the SiC substrate. If such strip - like defects grow in the active region or the current sensing region, the on - resistance of that region increases. As described above, the current sensing region is formed with a relatively small area. Therefore, if strip - like defects grow in the current sensing region, the on - resistance of the current sensing region changes greatly, and the current flowing through the current sensing region changes greatly. As a result, the sensing ratio between the current flowing through the active region and the current flowing through the current sensing region changes greatly, and it is no longer possible to correctly monitor the current flowing through the active region.

[0007] Regarding a semiconductor device manufactured using a SiC substrate, this specification provides a semiconductor device capable of maintaining a correct current monitoring function.

[0008] Means for Solving the Problems

[0009] The semiconductor device disclosed in this specification can include a semiconductor substrate having an active region where a main switch element structure is formed, a current sensing region where a sense switch element structure is formed, and a peripheral region surrounding the active region and the current sensing region. The semiconductor substrate is a 4H-SiC substrate having an off-angle in the <11-20> direction. The current sensing region is arranged in a range where the active region does not exist when observed along the <1-100> direction.

[0010] When the semiconductor device operates, a strip defect is formed starting from a part in the active region, and the strip defect grows along the <1-100> direction. In the semiconductor device, the current sensing region is arranged in a range where the active region does not exist when observed along the <1-100> direction. Therefore, the growth of the strip defect growing along the <1-100> direction from within the active region into the current sensing region is suppressed. Thus, in the semiconductor device, even if strip defects grow in the semiconductor substrate, the variation in the sensing ratio of the current flowing through the active region to the current flowing through the current sensing region can be suppressed. The semiconductor device can maintain a correct current monitoring function. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A plan view schematically showing the semiconductor device of this embodiment.

[0012] Figure 2 A cross-sectional view schematically showing the main part of the semiconductor device of this embodiment, which is a cross-section corresponding to the II-II line of Figure 1

[0013] Figure 3 A cross-sectional view schematically showing the main part of the semiconductor device of this embodiment, which is a cross-section corresponding to the III-III line of Figure 1

[0014] Figure 4 A plan view schematically showing the semiconductor device of this embodiment, which is a view showing the formed strip defects superimposed.

[0015] Figure 5 A plan view schematically showing a modified example of the semiconductor device of this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] Hereinafter, the semiconductor device of this embodiment will be described with reference to the drawings. The drawings referred to below have been scaled relative to the actual semiconductor device for clarity of illustration. In addition, it should be noted that the scales between the drawings have also been changed as needed.

[0017] InFigure 1 FIG. 1 schematically shows a plan view of the semiconductor device 1 of the present embodiment. The semiconductor device 1 is manufactured using a semiconductor substrate 10. The semiconductor substrate 10 is a 4H-SiC substrate having a (0001) plane surface and having an off-angle in the <11-20> direction.

[0018] The semiconductor substrate 10 has an active region 10A, a current sensing region 10B, and a peripheral region 10C located around the active region 10A and the current sensing region 10B. In this example, the active region 10A has a pair of rectangular partial regions. One partial region (the left partial region in the drawing) is referred to as the first active region 10Aa, and the other partial region (the right partial region in the drawing) is referred to as the second active region 10Ab.

[0019] In the active region 10A of the semiconductor substrate 10, as will be described later, a main switching element structure constituting a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is formed. A sensing switching element structure constituting a MOSFET is also formed in the current sensing region 10B of the semiconductor substrate 10. The unit cells of the main switching element structure and the sensing switching element structure are common. In the peripheral region 10C of the semiconductor substrate 10, a peripheral breakdown voltage structure such as a guard ring is formed. Further, on the peripheral region 10C of the semiconductor substrate 10, a temperature sensing element 40 and a plurality of small signal pads 50 are provided.

[0020] In Figure 2 FIG. 2 schematically shows a cross-sectional view corresponding to the II-II line of Figure 1 . In Figure 3 FIG. 3 schematically shows a cross-sectional view corresponding to the III-III line of Figure 1 . As shown in Figure 2 and Figure 3 , the MOSFETs respectively formed in the active region 10A and the current sensing region 10B include a drain electrode 22, a source electrode 24, and a trench gate portion 30.

[0021] The drain electrode 22 is provided on the back surface of the semiconductor substrate 10. The source electrode 24 is provided on the active region 10A and the current sensing region 10B in the semiconductor substrate 10. The trench gate portion 30 is provided in the surface layer portion of the active region 10A and the current sensing region 10B in the semiconductor substrate 10 and has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the semiconductor substrate 10 by the gate insulating film 34.

[0022] In the semiconductor substrate 10, an n +The drain region 11 of the n-type, the drift region 12 of the n-type, the body region 13 of the p-type, the p + -type body contact region 14, the n + -type source region 15 and the deep region 16 of the p-type.

[0023] The drain region 11 is provided in the back layer portion of the semiconductor substrate 10 and is disposed at a position exposed on the back surface of the semiconductor substrate 10. The drain region 11 is a base substrate for epitaxially growing the drift region 12. The drain region 11 is in ohmic contact with the drain electrode 22 covering the back surface of the semiconductor substrate 10.

[0024] The drift region 12 is provided on the drain region 11 and separates the drain region 11 and the body region 13. The drift region 12 is formed by crystal growth from the surface of the drain region 11 using an epitaxial growth technique.

[0025] The body region 13 is provided on the drift region 12 at a position corresponding to the active region 10A and the current sensing region 10B and is disposed in the surface layer portion of the semiconductor substrate 10. The body region 13 is formed in the surface layer portion of the semiconductor substrate 10 by ion-implanting aluminum toward the surface of the semiconductor substrate 10 using an ion implantation technique.

[0026] The body contact region 14 is provided on the body region 13, is located in the surface layer portion of the semiconductor substrate 10, and is disposed at a position exposed on the surface of the semiconductor substrate 10. The body contact region 14 is a region having a higher concentration of p-type impurities than the body region 13 and is in ohmic contact with the source electrode 24. Thus, the body region 13 is electrically connected to the source electrode 24 via the body contact region 14. The body contact region 14 is formed in the surface layer portion of the semiconductor substrate 10 by ion-implanting aluminum toward the surface of the semiconductor substrate 10 using an ion implantation technique.

[0027] The source region 15 is provided on the body region 13, is located in the surface layer portion of the semiconductor substrate 10, and is disposed at a position exposed on the surface of the semiconductor substrate 10. The source region 15 is separated from the drift region 12 by the body region 13 and is in contact with the side surface of the trench gate portion 30. The source region 15 is in ohmic contact with the source electrode 24. The source region 15 is formed in the surface layer portion of the semiconductor substrate 10 by ion-implanting nitrogen toward the surface of the semiconductor substrate 10 using an ion implantation technique.

[0028] The deep region 16 is disposed adjacent to the body region 13, located in the surface layer portion of the semiconductor substrate 10, and arranged at a position exposed on the surface of the semiconductor substrate 10. The deep region 16 is formed along the boundaries of the active region 10A and the peripheral region 10C, and the current sensing region 10B and the peripheral region 10C. The deep region 16 is formed deeper than the body region 13. The deep region 16 is formed in the surface layer portion of the semiconductor substrate 10 by ion-implanting boron toward the surface of the semiconductor substrate 10 using ion implantation technology.

[0029] In this way, MOSFETs common to the unit cells are respectively formed in the active region 10A and the current sensing region 10B. The current sensing region 10B is formed with an area ratio, for example, one-thousandth of that of the active region 10A. In the semiconductor device 1, it is configured to detect the current flowing through the current sensing region 10B, and convert the detected current using the sensing ratio based on the area ratio, thereby monitoring the current flowing through the active region 10A.

[0030] Here, in the surface layer portion of the peripheral region 10C of the semiconductor substrate 10, a peripheral breakdown voltage structure such as a guard ring structure or a reduced surface field (RESURF) structure is formed, but in Figure 2 and Figure 3 for the sake of clear illustration, such a peripheral breakdown voltage structure is omitted from the illustration.

[0031] As Figure 3 shown, the temperature sensing element 40 is provided on the peripheral region 10C of the semiconductor substrate, and is formed of a polysilicon layer formed on the interlayer insulating film on the semiconductor substrate 10. The temperature sensing element 40 has a p-type anode region 42 and an n-type cathode region 44, and is a diode element formed by the anode region 42 and the cathode region 44 being adjacent to each other. The temperature sensing element 40 is formed by ion-implanting p-type impurities and n-type impurities into the polysilicon layer using ion implantation technology. The temperature sensing element 40 detects the temperature using the characteristic that the forward voltage changes depending on the temperature change. In addition, in this example, the temperature sensing element 40 is provided on the semiconductor substrate 10, but it may be provided inside the semiconductor substrate 10 instead of this example.

[0032] Returning to Figure 1 . In the semiconductor device 1, the current sensing region 10B is arranged in a range where there is no active region 10A when observed along the <1 - 100> direction. More specifically, the current sensing region 10B is arranged between the first active region 10Aa and the second active region 10Ab when observed along the <1 - 100> direction. In addition, the current sensing region 10B is arranged between the small signal pads 50. More specifically, the current sensing region 10B is arranged between the small signal pads 50 in the <11 - 20> direction.

[0033] In addition, in the semiconductor device 1, the temperature sensing element 40 is disposed in the peripheral region 10C located between the first active region 10Aa and the second active region 10Ab. In this way, the temperature sensing element 40 and the current sensing region 10B are disposed so as to face each other in the <1-100> direction.

[0034] Next, refer to Figure 4 to describe the features of the semiconductor device 1. As described above, the semiconductor device 1 is formed by epitaxially growing the drift region 12 from the surface of the drain region 11 which is a base substrate. Therefore, as is well known, near the interface between the drain region 11 and the drift region 12, there are basal plane dislocations (BPD) and threading edge dislocations (TED) transformed from the basal plane dislocations.

[0035] In the switching operation of the semiconductor device 1, an inverse bias mode occurs in which the potential of the source electrode 24 becomes higher than the potential of the drain electrode 22. In such an inverse bias mode, since the built-in pn diode composed of the body region 13 and the drift region 12 is forward biased, the built-in pn diode can operate as a freewheeling diode. As a result, in the inverse bias mode, holes are injected from the body region 13 into the drift region 12. At this time, if the injected holes reach the basal plane dislocations or the threading edge dislocations, stacking faults starting from these dislocations expand, and strip defects 100 appear in the semiconductor substrate 10. Such strip defects 100 grow along the <1-100> direction, and their width can reach about 200 μm.

[0036] As described above, such strip defects 100 are formed because the holes injected through the operation of the built-in pn diode reach the basal plane dislocations or the threading edge dislocations. Therefore, such strip defects 100 are formed starting from the basal plane dislocations or the threading edge dislocations existing in the active region 10A and grow along the <1-100> direction.

[0037] In the semiconductor device 1, the current sensing region 10B is disposed in a range where the active region 10A does not exist when observed along the <1-100> direction. Therefore, in the semiconductor device 1, the situation where the strip defects 100 growing from the active region 10A pass through the current sensing region 10B is suppressed.

[0038] If a strip defect 100 grows within the current sensing region 10B, the on-resistance of the current sensing region 10B will increase. As described above, the current sensing region 10B is formed with a relatively small area. Therefore, if the strip defect 100 grows within the current sensing region 10B, the on-resistance of the current sensing region 10B will vary greatly, and the current flowing through the current sensing region 10B will vary greatly. As a result, the sensing of the current flowing through the active region 10A and the current flowing through the current sensing region 10B will vary greatly, and the current flowing through the active region 10A can no longer be correctly monitored.

[0039] On the other hand, in the semiconductor device 1, as described above, the growth of the strip defect 100 within the current sensing region 10B is suppressed. Although the strip defect 100 is formed within the active region 10A, since the active region 10A is formed with a relatively large area, the variation of the on-resistance is small. Therefore, in the semiconductor device 1, even if the strip defect 100 is formed within the semiconductor substrate 10, the variation of the sensing ratio of the current flowing through the active region 10A and the current flowing through the current sensing region 10B is suppressed. Thus, the semiconductor device 1 can maintain the correct current monitoring function.

[0040] In addition, in the semiconductor device 1, when viewed along the <1-100> direction, the current sensing region 10B is disposed between the first active region 10Aa and the second active region 10Ab. The peripheral region 10C between the first active region 10Aa and the second active region 10Ab is a region that should be ensured for disposing wirings connected to the gate electrode 32 and wirings connected to the temperature sensing element 40, etc. Further, in the semiconductor device 1, the temperature sensing element 40 is provided in the peripheral region 10C between the first active region 10Aa and the second active region 10Ab. That is, for the purpose of disposing various wirings and the temperature sensing element 40, the current sensing region 10B is disposed corresponding to the region where the active region 10A is not formed. Thus, in the semiconductor device 1, the current sensing region 10B can be disposed along the <1-100> direction in a positional relationship where there is no active region 10A without reducing the area of the active region 10A.

[0041] In addition, in the above embodiment, the case where the active region 10A is composed of a pair of partial regions, i.e., the first active region 10Aa and the second active region 10Ab, is illustrated. As Figure 5As shown, the number of partial regions constituting the active region 10A may also be three. In this case, the current sensing region 10B is also disposed between the partial regions of the active region 10A when viewed along the <1-100> direction. The same applies when the number of partial regions constituting the active region 10A is four or more. In addition, the current sensing region 10B and the temperature sensing element 40 may or may not be disposed so as to face each other in the <1-100> direction.

[0042] As described above, the embodiments have been described in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes variously modified and changed forms of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility through individual or various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or the drawings achieves multiple objects at the same time, and achieving one of these objects itself has technical utility.

Claims

1. A semiconductor device (1), characterized in that, it includes a semiconductor substrate (10) having an active region (10A) where a main switching element structure is formed, a current sensing region (10B) where a sense switching element structure is formed, and a peripheral region (10C) surrounding the above-mentioned active region and the above-mentioned current sensing region; the above-mentioned semiconductor substrate is a 4H-SiC substrate having an off-angle in the <11-20> direction; the above-mentioned current sensing region is arranged in a range where the above-mentioned active region does not exist when observed along the <1-100> direction; in the operating state, strip-shaped defects grow in the <1-100> direction in the above-mentioned active region; by arranging the above-mentioned current sensing region in the above-mentioned range, the growth of the above-mentioned strip-shaped defects in the above-mentioned current sensing region is suppressed.

2. The semiconductor device according to claim 1, characterized in that, the above-mentioned active region has a first active region (10Aa) and a second active region (10Ab); the above-mentioned first active region and the above-mentioned second active region are arranged separately within the above-mentioned semiconductor substrate; the above-mentioned current sensing region is arranged between the above-mentioned first active region and the above-mentioned second active region when observed along the <1-100> direction.

3. The semiconductor device according to claim 2, characterized in that, it further includes a temperature sensing element (40); the above-mentioned temperature sensing element is arranged in the above-mentioned peripheral region located between the above-mentioned first active region and the above-mentioned second active region.

4. The semiconductor device according to claim 2 or 3, characterized in that, the above-mentioned first active region and the above-mentioned second active region are arranged separately in the <11-20> direction; the above-mentioned current sensing region is located between the above-mentioned first active region and the above-mentioned second active region in the <11-20> direction, and is arranged at a position separated from the above-mentioned first active region and the above-mentioned second active region in the <1-100> direction.

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