Measurement method of WAT

Abstract

The present invention provides a WAT measurement method, which includes a test machine, a PSMU instrument, and a device formed on a wafer to be tested. The wafer is further formed with multiple test keys, and each test key is formed with multiple pads corresponding to different devices; pad arrangement data is obtained based on the arrangement of the pads, and pads that can be tested in parallel are selected based on the pad arrangement data to define multiple groups to be tested; multiple groups of address group data are obtained based on the positions of the multiple groups to be tested on the wafer; each group of address group data is input into a different PSMU in the PSMU instrument; and the multiple groups to be tested are tested simultaneously. The WAT measurement method of the present invention can effectively improve production while maintaining good performance, increase test parameters per unit time, and improve WAT machine utilization.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a WAT measurement method. Background Art

[0002] Wafer Acceptance Test (WAT) is a measurement performed on test keys at the wafer stage using specialized test equipment (including automated testers and manual testers). To ensure test consistency and test hardware reuse, test keys have a uniform number of pads and pad spacing. Test patterns are placed between the pads. WAT can reflect process fluctuations during wafer tapeout and detect anomalies on the production line. WAT serves as a control standard for wafer shipment.

[0003] WAT (wafer acceptance test) is based on the need for a corresponding test calculation program to support each test parameter. With the continuous advancement of new structures and new technology nodes, the chip die size is getting smaller and the structural design is becoming more complex, which in turn requires additional parameters to ensure higher quality.

[0004] Traditional test calculation programs use serial tests to run one by one. For complex equipment designs, the large number of test parameters required leads to long test times and slow test speeds, and the WAT machine utilization rate is relatively low.

[0005] A new testing method is needed that can effectively improve production while maintaining good performance, increase test parameters per unit time, and improve WAT machine utilization. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a WAT measurement method to solve the problem that the traditional test calculation program in the prior art adopts serial test to run one by one, which results in long test time and slow test speed for complex equipment design due to the need for numerous test parameters, and the WAT machine utilization rate is relatively low.

[0007] To achieve the above and other related objectives, the present invention provides a method for measuring WAT, comprising:

[0008] Step 1: Provide a test machine, a PSMU instrument, and a device formed on a wafer to be tested, wherein the device is formed on the wafer, and a plurality of test keys are formed on the wafer, and each of the test keys has a plurality of pads formed thereon, each of the pads corresponding to a different device;

[0009] Step 2: obtaining pad arrangement data according to the arrangement of the pads, and determining a plurality of groups to be tested according to the pad arrangement data, wherein the groups to be tested are used for parallel testing;

[0010] Step 3, obtaining multiple groups of address group data according to the positions of the multiple groups of the test groups on the wafer;

[0011] Step 4: input each set of the address group data into different PSMUs in the PSMU instrument;

[0012] Step 5: Testing multiple groups of the test groups simultaneously.

[0013] Preferably, the arrangement of the plurality of pads in step 2 includes the arrangement spacing of the pads.

[0014] Preferably, each of the test keys includes twelve pads.

[0015] Preferably, the device in step 1 is a resistor.

[0016] Preferably, the device in step 1 is a source, a drain and a gate of a metal oxide transistor.

[0017] Preferably, the device in step 1 is a capacitor.

[0018] Preferably, the method of simultaneously detecting multiple groups of the groups to be tested in step five includes: using the address grouping data in step four to connect the probe to the pad in each group of the groups to be tested; simultaneously applying voltage to the pad in each group of the groups to be tested for testing; and obtaining data on the resistance of multiple groups of the groups to be tested.

[0019] Preferably, each of the multiple groups to be tested is located on the same test key; and different groups to be tested do not share the common pad.

[0020] As described above, the WAT measurement method of the present invention has the following beneficial effects:

[0021] The WAT measurement method of the present invention can effectively improve production output while maintaining good performance, increase test parameters per unit time, and improve WAT machine utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Shown is a schematic flow chart of the method of the present invention;

[0023] Figure 2 Shown is a parallel schematic diagram of the judgment algorithm according to an embodiment of the present invention;

[0024] Figure 3It shows a comparison diagram of parallel testing and continuous testing according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] See also Figure 1 The present invention provides a method for measuring WAT, comprising:

[0027] Step 1: Provide a test machine, a PSMU instrument, and a device formed on a wafer to be tested. The device is formed on the wafer, and multiple test keys are formed on the wafer. Each test key has multiple pads, and each pad corresponds to a different device.

[0028] The test machine is required for WAT automatic testing and can be a Keysight or Agilent test machine. The test machine is divided into a test cabinet and a test head.

[0029] After wafers are produced, they must undergo an electrical test called the wafer acceptance test (WAT) before leaving the wafer fab. This test tests the electrical performance of the test keys on the scribe line. Test keys are usually designed with various components, such as NMOS, PMOS, resistors, capacitors of different sizes, and other process-related characteristics. This step can be considered a preliminary selection. Wafers with serious production problems that cause the electrical performance of the test keys to exceed specifications will be screened out and scrapped at this step. After the WAT test is completed, the wafer process is considered complete.

[0030] An SMU (Source Measure Unit) is a precision power supply device that can provide not only a voltage source with a measurement resolution of less than 1mV, but also a current source with a measurement resolution of less than 1uA. A PSMU (Parallel Source Measure Unit) is a source measure unit that can be used for parallel testing.

[0031] In a possible implementation, the device in step 1 is a resistor, which may be a well resistor, a silicon resistor, a non-silicon resistor, a contact window resistor, a metal resistor, an interconnection line through-hole resistor, etc.

[0032] In a possible implementation manner, the device in step 1 is a capacitor, which may be a MIM capacitor or a MOM capacitor.

[0033] In a possible implementation, the device in step 1 is a source, a drain, and a gate of a metal oxide transistor.

[0034] Step 2: obtaining pad arrangement data according to the arrangement of the pads, and determining multiple groups to be tested according to the pad arrangement data, wherein the groups to be tested are used for parallel testing;

[0035] In a possible implementation manner, the arrangement of the plurality of pads in step 2 includes an arrangement spacing of the pads, and the arrangement spacing may be equidistant or non-equidistant.

[0036] In one possible implementation, each test key generally includes twelve pads. The test keys can be arranged in rows or columns, and the arrangement spacing of the pads is equal. It should be understood that according to different production requirements, the test key can also include more or fewer pads. The specific number of pads is not limited here.

[0037] In one possible implementation, see Figure 2 , each group of the multiple groups to be tested is located on the same test key; different groups to be tested have no shared pads.

[0038] For example, in Figure 2 Among the pads 1 to 12 shown, pads 1 to 4 are defined as structure 1, pads 5 to 8 are defined as structure 2, pads 9 to 11 are defined as structure 3, and pads 10 to 12 are defined as structure 4. Structure 1 and structure 2 have no common pads and are a group that can be tested in parallel. In structures 3 and 4, pads 10 and 11 are common pads, which are prone to test errors or errors and cannot be a group to be tested in parallel.

[0039] In one possible implementation, the structure in step 2 is the source, drain, and gate of a metal oxide transistor, and its test parameters in the WAT test include the breakdown voltage of the source and drain, the breakdown voltage of the gate, and the electrical thickness of the gate.

[0040] Step 3: Multiple groups of address group data are obtained based on the address positions of the multiple groups of test groups on the wafer. Compared with the prior art of testing each structure separately, which takes a long time, the same type of structure is divided into multiple groups of test groups and tested in parallel, which improves the detection efficiency;

[0041] Step 4: Connect each set of address group data to different PSMUs in the PSMU instrument;

[0042] Step 5: Testing multiple groups to be tested simultaneously, so that test data can be obtained at the same time, thereby improving the test efficiency.

[0043] In one possible embodiment, the method of simultaneously testing multiple groups to be tested in step five includes: connecting the probe to the pads in each group to be tested using the address grouping data in step four; simultaneously applying voltage to the pads in each group to be tested for testing; and obtaining data of multiple groups to be tested.

[0044] In one possible embodiment, the method of simultaneously testing multiple groups to be tested in step five includes: connecting different probes to the pads corresponding to the source, drain and gate in each group to be tested; simultaneously applying voltage to the source, drain and gate in each group to be tested for testing; and obtaining resistance data of multiple groups to be tested.

[0045] Threshold voltage: The input voltage corresponding to the midpoint of the transition region in the transfer characteristic curve where the output current changes sharply with input voltage is usually called the threshold voltage. Different parameters are used to describe different devices. For example, when describing field emission characteristics, the voltage at which the current reaches 10mA is called the threshold voltage. Testing the source, drain, and gate is called threshold voltage testing.

[0046] In a possible embodiment, the method of simultaneously testing multiple groups to be tested in step five also includes: connecting different probes to the high-voltage end and the low-voltage end corresponding to the pads of the capacitors in each group to be tested; simultaneously applying voltage to the capacitors in each group to be tested for testing; and obtaining multiple groups of test group capacitance data.

[0047] In one possible implementation, see Figure 3 In the three groups of bar charts in the figure, the bar chart on the left is the time required for parallel testing, and the bar chart on the right is the time required for continuous testing in the existing technology. By comparison, it can be seen that the time required for parallel testing is less. The horizontal axis refers to a list of some product platforms, which does not involve units; the bar-marked value refers to the single-chip wafer run-time (unit min / Pcs); the percentage refers to the efficiency improvement percentage calculated between the time required for continuous testing and the time required for parallel testing. For example: the bar chart of 90CIS is (12-7) / 12≈0.4167, and this number converted into a percentage is 41.67%, and so on.

[0048] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0049] In summary, the WAT measurement method of the present invention can effectively improve production throughput, increase test parameters per unit time, and enhance WAT machine utilization while maintaining excellent performance. Therefore, the present invention effectively overcomes the shortcomings of the existing technology and has high industrial application value.

[0050] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for measuring WAT, characterized in that: At least: Step 1: Provide a test machine, a PSMU instrument, and a device to be tested, wherein the device is formed on a wafer, and a plurality of test keys are formed on the wafer, and each test key is formed with a plurality of pads, each pad corresponding to a different device; Step 2: obtaining pad arrangement data according to the arrangement of the pads, the arrangement of the plurality of pads including the arrangement spacing of the pads; dividing the pads of the same test key into a plurality of groups to be tested based on the pad arrangement data, wherein no pads are shared between different groups to be tested, and the groups to be tested are used for parallel testing; Step 3, obtaining multiple groups of address group data according to the positions of the multiple groups of the test groups on the wafer; Step 4, each group of the address packet data are input into the PSMU instrument different PSMU; Step 5: Detect multiple groups of the test groups simultaneously: connect the probe to the pads in each group of the test groups using the address grouping data in step 4; apply voltage to the pads in each group of the test groups for testing; and obtain data of multiple groups of the test groups.

2. The WAT measurement method according to claim 1, characterized in that: Each of the test keys includes twelve pads.

3. The WAT measurement method according to claim 1, characterized in that: The device in step 1 is a resistor.

4. The WAT measurement method according to claim 1, characterized in that: The devices in step 1 are the source, drain and gate of a metal oxide transistor.

5. The WAT measurement method according to claim 1, characterized in that: The device in step 1 is a capacitor.

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