A comprehensive photoelectric signal processing computing resource management method

Abstract

The present invention belongs to the field of embedded signal processing technology, and in particular, relates to a method for managing integrated optoelectronic signal processing computing resources. The method uses a RapidIO network to construct a signal processing computing resource pool and a front-end sensor interface resource pool, and realizes the elastic supply of integrated signal processing resources through a registry-based resource scheduling method. At the same time, a corresponding computing platform is designed based on an open computing architecture, and by abstracting two computing resources, namely, interfaces and processing, an interconnection architecture of fully connected mapping of signal processing resources and front-end sensor devices is adopted to provide heterogeneous computing resources of multi-core CPU+multi-core DSP+large-scale FPGA. The present invention adopts a dual-host solution and computing resource pooling technology to realize the elastic supply of embedded signal processing computing resources. The method is simple and easy to use, and the computing platform has high availability.

Description

Technical Field

[0001] The invention belongs to the technical field of embedded signal processing, and in particular relates to a comprehensive photoelectric signal processing computing resource management method. Background Art

[0002] Airborne embedded signal processing technology is an important part of avionics systems, providing signal processing computing resources for optoelectronic systems such as radar, IRST and DAS. The specific application environment of optoelectronic signal processing systems requires embedded signal processing computers to have high performance, strong real-time, high reliability, and low power consumption. In addition, signal processing computer technology also involves standardization, generalization, modularization and other engineering technologies such as environmental adaptability.

[0003] The development of avionics integration technology and the advancement of optoelectronic system sensor fusion technology have put forward higher requirements for embedded optoelectronic signal processing computer systems. Computer systems for integrated optoelectronic applications require the use of a unified interconnection bus, the ability to transmit massive data, the ability to tailor and expand processing resources, and the ability to provide information processing capabilities for both logical operations and intensive computing. Summary of the invention

[0004] Purpose of the present invention:

[0005] The present invention provides an integrated optoelectronic signal processing computing resource management method to solve the problems of dedicated computer resources and system scalability in traditional signal processing, meet the heterogeneous computing needs of massive signal processing in airborne optoelectronic integrated application scenarios, and provide customizable embedded signal processing computing resources.

[0006] The technical solution of the present invention:

[0007] A comprehensive optoelectronic signal processing computing resource management method, comprising:

[0008] Step 1: After the computing platform is started, the two HSOT hosts A and B serve as each other's redundant backups. The priority assigned to host B through the hardware slot identification number is higher than that of host A. After the computing platform is started, hosts A and B simultaneously start RapidIO switching network enumeration and start to establish a resource registration table. The computing nodes and device interfaces connected to hosts A and B are identified through the capability register CAR of each port device, and the ID lock register CSR of the corresponding computing node and device interface is locked and identified. The ID lock register CSR of the corresponding computing node and device interface can only be identified by one host, and is counted as the first resource after identification;

[0009] Step 2: When host B finds that a certain first resource has been locked and identified by host A, host B stops enumeration and waits, repeatedly obtaining the ID number of the first resource until host A releases the first resource; when host A finds that a certain first resource has been locked and identified by host B, host A retreats, and the retreat is to stop enumeration and release the locked resource according to the local resource registry;

[0010] Step 3: Host B completes the establishment of the resource registry of the computing platform, and reports a Ready message to the upper-level system through the system network interface of Host B, indicating that it can accept system tasks; at the same time, Host B broadcasts a system message to all computing nodes and device interfaces as the first message, confirming the master host identity of Host B and Host A as the backup host;

[0011] Step 4: After the computing platform is started, each computing node and device interface completes local initialization; after receiving the first message, each computing node and device interface reports its operating status to the HOST and enables the main HOST to update the resource registry of the main HOST to form a first system resource registry, wherein the operating status includes: computing power, storage capacity, communication capacity and operating load;

[0012] When a new computing node or device interface is added to the system, the newly added computing node and device interface report their running status to the host and make the host update the first system resource registry to form a second system resource registry.

[0013] When a computing node and a device interface fail or are removed, the RapidIO switching network connecting the computing node and the device interface to the host A and the host B generates an offline interruption, so that the master HOST updates the first system resource registry to form a third system resource registry;

[0014] Step 5: The main HOST forms a device interface resource pool and a computing node resource pool based on the registry, and the system application task runs on the computing platform in a service manner: After the main HOST obtains the system task from the system network interface, it queries the system resource registry, allocates the corresponding device interface and computing node according to the current system operation load, and dynamically adjusts the routing table of the RapidIO switching network. After completing the resource allocation, the main HOST sends a task command to the device interface and computing node;

[0015] Step 6: The task agent program is run on both the computing node and the device interface. The agent program is responsible for initializing local resources, parsing the task command, and loading the APP corresponding to the task command;

[0016] Step 7: The main HOST flexibly allocates device interfaces and computing nodes according to the request of the upper-level system to the APP.

[0017] Furthermore, in step 3, host B broadcasts a system message to all computing nodes and device interfaces to determine the master host identity of host B and host A as a backup host, and also includes:

[0018] Host A periodically monitors the health status of B and takes over the system when B fails.

[0019] Furthermore, in step 3, after host B broadcasts a system message to all computing nodes and device interfaces to determine that host B is the primary host and host A is the backup host, the following steps are also included:

[0020] Host B, as the master HOST, is responsible for completing system initialization, health management, and task scheduling.

[0021] Furthermore, in step 4, after the host HOST forms or updates the first system resource registration table, it also includes:

[0022] The primary HOST sends the current system resource registry to the backup HOST.

[0023] Further, in step 6, the application APP corresponding to the task command is loaded, specifically:

[0024] The main HOST stores the APP image in the non-volatile memory of the main HOST. The computing nodes and device interfaces locally cache the APPs loaded during the task cycle. When loading, they first query the task APP image in the local storage. If it does not hit, the image is read and loaded from the main HOST.

[0025] Further, step 7 specifically includes: when the system request for a certain APP increases, the main HOST dynamically allocates a new computing node to execute the same APP as the certain APP according to the resource status in the current resource registration table;

[0026] When the master HOST detects that the computing node is overloaded, it dynamically migrates part or all of the task to other nodes.

[0027] Furthermore, the computing node is overloaded, specifically, the computing resource usage rate exceeds 90%.

[0028] Furthermore, in step 4, when a computing node or a device interface fails or is removed, the following steps are also included:

[0029] The computing nodes and device interfaces periodically report resource utilization, bit error rate, BIT results, communication status, and device temperature to the main HOST; if the status is not reported for multiple consecutive cycles, the main HOST will initiate an inquiry message. If the computing nodes and device interfaces do not respond to the message, the main HOST determines that the resource is offline, updates the registry, and reallocates computing resources.

[0030] Beneficial effects:

[0031] (1) The signal processing computer architecture abstracts two computing resources, interface and processing, and adopts an open computing architecture with a small number of modules and good system scalability;

[0032] (2) Adopting an interconnection architecture that fully connects processing resources and front-end sensor devices to support the construction of virtualized sensor resource pools and processing resource pools;

[0033] (3) A heterogeneous processing array of multi-core CPU + multi-core DSP + large-scale FPGA is used to support high-performance parallel processing of massive signal data. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a principle block diagram of the integrated optoelectronic signal processing computing resource management platform of the present invention;

[0035] Figure 2 It is a principle block diagram of a signal processing interface module in a specific embodiment of the present invention;

[0036] Figure 3 It is a principle block diagram of a general signal processing module in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following is a detailed description with reference to the accompanying drawings and specific embodiments.

[0038] Figure 1 The figure is a principle block diagram of the present invention. In a specific embodiment of the present invention, the integrated optoelectronic signal processing computer system is composed of 2 signal processing interface modules and 3 general signal processing modules (the number of general signal processing modules can be cut / expanded). The signal processing interface module and the general signal processing module are connected through an internal interconnection bus, and an open computing architecture is adopted. The number of general signal processing modules can be cut and expanded. The front-end interconnection bus and the internal interconnection bus adopt a unified high-speed switching network to realize the fully connected mapping of processing resources and front-end devices, and the front-end sensor resource pool and processing resource pool can be constructed to provide customizable embedded computing services for integrated optoelectronic signal processing.

[0039] The signal processing interface module realizes the connection function of front-end interconnection and system interconnection, and provides certain signal processing capabilities. The general signal processing module realizes general signal processing and large-scale logical operation functions. The front-end interconnection bus is realized by the RapidIO high-speed bus, and optical signals are used to realize long-distance data interaction with the front-end equipment. The system interconnection bus is realized by special system buses such as FC and AFDX, and optical signals are used to realize cross-linking with other functional devices in the avionics system. The internal interconnection bus is realized by the RapidIO high-speed bus, and electrical or optical signals are used to realize interconnection communication.

[0040] The rate of RapidIO bus is configurable at 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps, 6.25Gbps, and 10.3125Gbps, and the SerDes interconnection line width (per channel) of RapidIO bus is configurable at 1x, 2x, and 4x. The internal interconnection bus interface between the signal processing interface module and the general signal processing module can be 1-way or 2-way, and the RapidIO interconnection between the internal processing nodes of the module (including multi-core DSP, multi-core CPU, and large-scale FPGA) can be 1-way or 2-way. When using optical signal interconnection, the photoelectric conversion circuit supports a communication rate of up to 10.3125Gbps.

[0041] The signal processing interface module is responsible for receiving, managing, and distributing sensor data transmitted by the front-end device and reporting the processing results. The general signal processing module is responsible for parallel processing of the digitized signals of the front-end device. At the same time, the signal processing interface module, as the control and management unit of the computer system, realizes the initial configuration, health management, and fault management functions of the system.

[0042] The front-end interconnection bus and the internal interconnection bus adopt a unified RapidIO switching network. Through the RapidIO switching devices on the signal processing interface module and the general signal processing module, a distributed RapidIO switching network is realized to achieve full interconnection of signal processing resources and full connection mapping of processing resources and front-end devices. The system interconnection bus is realized by the system interface bridge on the signal processing interface module. Each CPU host realizes an independent system bus interface. Multiple independent system bus interfaces provide redundant system interconnection communications.

[0043] like Figure 2 Shown is a principle block diagram of a signal processing interface module in a specific embodiment of the present invention.

[0044] The signal processing interface module outputs 4 1x 5Gbps RapidIO bus interfaces as front-end interconnection bus interfaces, 2 4.25Gbps FC as system interconnection bus interfaces, and 3 4x 5Gbps RapidIO buses as internal interconnection bus interfaces. RapidIO and FC high-speed buses are output in the form of optical signals through photoelectric conversion circuits. The 2 multi-core CPUs in the signal processing interface module use the HRDSP2040 processor of Huachuang Microelectronics, the 2 large-scale FPGAs use the JFM7K325T of Fudan Microelectronics, the RapidIO switching network is implemented by 1 NMS1800 of Tianjin Innovation Center, and the system bus interface bridge is implemented by Fudan Microelectronics' JFM7K325T.

[0045] HRDSP2040 accesses the switching chip through 2 channels of 4x 5Gbps RapidIO, and JFM7K325T accesses the switching chip through 1 channel of 4x5Gbps RapidIO. The switching chip outputs 3 channels of 4x 5Gbps and 4 channels of 1x 5Gpbs RapidIO. The two JFM7K325Ts are interconnected through 1 channel of 4x 10Gbps SerDes to achieve data communication of the custom expansion interface. The HRDSP2040 processor is equipped with 2 channels of 72-bit DDR3-1066 memory, 2 channels of 16-bit FLASH memory, and 1 channel of 8-bit NvRAM memory. JFM7K325T is equipped with 3 channels of 16-bit DDR3-1600 memory and implements customized algorithms dedicated to signal processing. The host interface of the system bus bridge JFM7K325T in the universal signal processing module is 1 4x 5Gbps PCIe, the system bus interface is 1 4.25Gbps FC, and each HRDSP2040 processor outputs 1 FC.

[0046] like Figure 3 Shown is a principle block diagram of a general signal processing module in a specific embodiment of the present invention.

[0047] The general signal processing module outputs two 4x 5Gbps RapidIO buses as internal interconnection bus interfaces. The RapidIO buses are output in the form of optical signals through photoelectric conversion circuits. The two multi-core DSPs in the signal processing interface module use the FT-M6678H processor from the National University of Defense Technology, the two large-scale FPGAs use the JFM7V690T from Fudan Microelectronics, and the RapidIO switching network is implemented using one NMS1800 from the Tianjin Innovation Center.

[0048] FT-M6678H accesses the switch chip through 2 channels of 4x 5Gbps RapidIO, JFM7V690T accesses the switch chip through 2 channels of 4x5Gbps RapidIO, and the switch chip outputs 2 channels of 4x 5Gbps RapidIO. The FT-M6678H processor is equipped with 1 channel of 72-bit DDR3-1600 memory, 1 channel of 16-bit FLASH memory, and 1 channel of 8-bit NvRAM memory. JFM7V690T is equipped with 3 channels of 16-bit DDR3-1600 memory and 3 channels of 36-bit QDRII+ memory, and implements customized algorithms dedicated to signal processing.

[0049] During the operation of the integrated optoelectronic signal processing computer system, the signal processing interface module serves as the control management unit of the computer system. Through the power grabbing or configuration blueprint, a certain signal processing interface module is determined as the system main HOST, and the other signal processing interface module is determined as the system backup HOST. The main HOST is responsible for the configuration management of the system, and the backup HOST monitors the status of the main HOST. When the main HOST fails, the backup HOST takes over the main HOST function. The two CPU processors on the signal processing interface module back up each other, one CPU realizes the main HOST function (called the main CPU), and the other monitors the heartbeat of the main CPU (called the backup CPU). When the main CPU fails, the backup CPU takes over the main HOST function.

[0050] The main HOST is responsible for the configuration management of the entire computer system, including: initial configuration, RapidIO network initialization (communication routing, link rate and line width, ID allocation, packet priority, etc.), front-end RapidIO device synchronization, CPU+DSP+FPGA heterogeneous parallel processing array task deployment, etc.; health management, RapidIO network traffic monitoring, communication status monitoring, system interface bridge communication status monitoring, processor and customized FPGA logic working status monitoring, etc. (including the computer's CPU usage, memory usage, various key types of power supplies, equipment temperature and other basic working conditions); fault management, fault task reconstruction, fault communication node recovery\isolation, fault site status recording, etc.

[0051] Based on the above-mentioned integrated optoelectronic signal processing computing resource management platform, integrated optoelectronic signal processing computing resource management is realized. The integrated optoelectronic signal processing computing resource management method includes:

[0052] Step 1: In the computing platform, two HSOT hosts (A and B) serve as redundant backups for each other. The priority assigned to host B by the hardware slot identification number is higher than that of host A. After the computing platform is started, host A starts RapidIO network enumeration and starts to establish a resource registry, identifies the resource type (computing resource or interface resource) through the capability register CAR of each port device, and locks the ID lock register CSR of the corresponding device, indicating that the resource has been acquired and locked.

[0053] Step 1 specifically includes: the enumeration process of the RapidIO network, using a maintenance package to perform system enumeration, the initial IDs of the computing nodes and device interfaces are all 0xFF, the initial ID of host B is 0x01, and the initial ID of host A is 0x00. The maintenance package in the RapidIO network uses "ID+hop count". In the present invention, in order to facilitate host A and host B to find each other as early as possible, a breadth-first search algorithm is used to perform system enumeration.

[0054] The resource registry is stored in the non-volatile memory of the HOST host, specifically an electronic disk or NorFLASH. During operation, the resource registry is read from the non-volatile memory and stored in the memory of the HOST host. When the resource registry is updated, it is written back to the non-volatile memory. Step 2: Host B starts to enumerate platform resources, finds another host (host A), stops enumeration and waits, and repeatedly tries to obtain the lock ID number. Host A finds another higher priority host (host B) in the platform and retreats (stops enumeration, and releases the locked resources according to A's local resource registry).

[0055] Step 2 specifically includes: after the computer is started, host B and host A first need to lock the ID lock register CSR of their own devices. When host B finds host A, the determination of the time period for stopping waiting and trying to obtain the locked ID number is related to the scale of the specific integrated optoelectronic signal processing computer platform (mainly depending on the complexity and node scale of the RapidIO network). Generally, in the specific implementation, a single HOST host will be used for system enumeration during the test phase. If the system enumeration time is T (for example, 400ms), the waiting time period of host B is determined to be ≤T / 2 (for example, 200ms). In addition, in order to prevent the ID number from being deadlocked during the network enumeration process, that is, after host A enumerates a certain computing node or device interface, host A fails, causing the ID number of the computing node or device interface to be deadlocked, and cannot be enumerated by host B, or even host B enters an infinite wait (which will cause the computing platform to fail to start). In the specific implementation, an ID number deadlock timeout release mechanism is set in each computing node or device interface, that is, after the computing node or device interface locks the ID number, if it does not receive a broadcast message from the HOST host within a certain period of time, the local ID number lock is automatically released, that is, the initial value of the ID lock register CSR is restored. Generally, the timeout period is set to twice the single HOST enumeration time (for example, 800ms).

[0056] Step 3: After Host B obtains the ID lock right, it continues to enumerate other devices on the platform. Host B completes the establishment of the resource registry of the computing platform, and reports a Ready message to the upper-level system through the system network interface, indicating that it can accept system tasks. At the same time, Host B broadcasts a system message to determine the identity of the main HOST. Host A is the backup HOST, periodically monitors the health status of B, and takes over the system when B fails. The main HOST is responsible for completing system initialization, health management, and task scheduling.

[0057] Step 3 specifically also includes: a resource registry, including resource type (computing node or device interface), quantity, logical location (location in the RapidIO network topology), capability (storage capacity, memory access bandwidth, interface bandwidth, computing power), operating status (usage rate of various resources), operating load (running APP type, quantity, coupling relationship) and health status (temperature, power consumption, bus communication status, BIT information, etc.).

[0058] After the computer starts, host B completes the establishment of the resource registry, which only establishes three items: type, quantity and logical location of the resource registry. Other specific contents need to be completed by host B after the computing nodes and device interfaces are initialized and report relevant information to host B.

[0059] Host A monitors the health status of host B by combining "extraction and push", that is, host B periodically (such as 500ms) reports the health status to host A, including (working temperature, BIT information, etc.), and host A reads the health status of host B once in several times of the cycle time (such as 10 times the cycle of 5s). If host B does not report for 10 consecutive cycles and host A cannot read the health status of host B, host B is judged to be faulty.

[0060] Step 4: After each sensor interface and computing resource (DSP, CPU, and FPGA) completes local initialization, the resource registry is updated at the main HOST to improve the resource registry, including resource type, computing power, communication capability, and operating load, to form a system resource registry. When a new device (interface or computing resource) is added to the system, the registry is updated; when a device fails or is removed, the registry is also updated. The main HOST periodically sends the registry to the backup HOST for backup.

[0061] Step 4 specifically includes: each device interface and computing resource completes local initialization, mainly refers to the completion of the local minimum operating system initialization (including storage, communication, functional logic and initial configuration of platform software). At the same time, after receiving the broadcast message from the main HOST, report its own capabilities (storage capacity, memory access bandwidth, interface bandwidth, computing power), operating status (usage rate of various resources), operating load (running APP type, quantity, coupling relationship) and health status (temperature, power consumption, bus communication status, BIT information, etc.) to the main HOST.

[0062] In the solution of the present invention, the computing platform adopts RapidIO network. When a new device is added, fails or removed, it is reported through a Port-write maintenance package. After the main HOST receives the reported Port-write maintenance package, it parses the source ID and fault information therein and updates the resource registration table.

[0063] Step 5: The main HOST forms a sensor interface resource pool and a computing resource pool based on the registry, and the system application task runs on the signal processing computing platform in a service manner. After the main HOST obtains the system task from the system interface, it queries the system resource registry, allocates the corresponding sensor interface and computing resources according to the current system operation load, and dynamically adjusts the routing of the RapidIO network to ensure that the sensor data can be correctly delivered to the allocated computing resources. After completing the resource allocation, the main HOST sends task commands to the sensor interface and computing resources.

[0064] Step 5 specifically also includes: the allocation algorithm of the device interface and the computing node can adopt a dynamic resource allocation algorithm, a time slice-based allocation algorithm, and a priority-based allocation algorithm. In this solution, a dynamic allocation algorithm similar to the "banker's algorithm" is adopted to avoid resource deadlock.

[0065] Dynamically adjust the routing of the RapidIO network. Specifically, in this solution, in order to avoid network jitter during the dynamic routing adjustment process, the RapidIO network is configured as fully interconnected during system initialization (i.e., any end node can pass data to other nodes on the computing platform through the ID number), and a layer of logical mapping table (i.e., the relationship between message publishing and subscription) is built on the basis of the RapidIO routing, and the logical mapping table is dynamically adjusted each time. Only when the device interface and the computing node are offline, the RapidIO routing table is updated, and the logical mapping table is updated at the same time.

[0066] Step 6: The task agent runs on both the computing resource node and the sensor interface. The agent is responsible for initializing local resources, registering with the main HOST after startup, parsing the main HOST's commands, and loading the corresponding application APP (the application APP image is stored in the non-volatile storage of the main HOST, and the APP loaded during the task cycle is cached locally. When loading, the task APP image is queried in the local storage. If it does not hit, the image is read from the main HOST).

[0067] The specific task commands of the host HOST include: APP attributes, APP image name, other related APPs, deployment resource type, deployment resource logical location, etc.

[0068] Step 7: The master HOST can flexibly allocate sensor resources and computing resources according to the system request. When the system request increases or the operating load increases, the master HOST dynamically starts a new computing node according to the resource status in the registry to perform the same type of tasks. When the master HOST detects that the operating load on the computing node is too heavy (the computing resource utilization rate exceeds 90%) or the node fails, it dynamically migrates the task (partial migration / full migration) to other nodes.

[0069] The above step 4 also includes: the agent program periodically reports the local resource utilization, bit error rate, BIT result, communication status, device temperature and other health conditions to the main HOST. If the status is not reported for multiple consecutive cycles, the main HOST will initiate an inquiry message. If the agent node does not respond to the message, the main HOST determines that the resource is offline, updates the registry, and reallocates computing resources.

Claims

1. A comprehensive optoelectronic signal processing computing resource management method, characterized in that: include: Step 1: After the computing platform is started, the two HSOT hosts A and B serve as each other's redundant backups. The priority assigned to host B through the hardware slot identification number is higher than that of host A. After the computing platform is started, hosts A and B simultaneously start RapidIO switching network enumeration and start to establish a resource registration table. The computing nodes and device interfaces connected to hosts A and B are identified through the capability register CAR of each port device, and the ID lock register CSR of the corresponding computing node and device interface is locked and identified. The ID lock register CSR of the corresponding computing node and device interface can only be identified by one host, and is counted as the first resource after identification; Step 2: When host B finds that a certain first resource has been locked and identified by host A, host B stops enumeration and waits, repeatedly obtaining the ID number of the first resource until host A releases the first resource; when host A finds that a certain first resource has been locked and identified by host B, host A retreats, and the retreat is to stop enumeration and release the locked resource according to the local resource registry; Step 3: Host B completes the establishment of the resource registry of the computing platform, and reports a Ready message to the upper-level system through the system network interface of Host B, indicating that it can accept system tasks; at the same time, Host B broadcasts a system message to all computing nodes and device interfaces as the first message, confirming the master host identity of Host B and Host A as the backup host; Step 4: After the computing platform is started, each computing node and device interface completes local initialization; after receiving the first message, each computing node and device interface reports its operating status to the HOST and enables the main HOST to update the resource registry of the main HOST to form a first system resource registry, wherein the operating status includes: computing power, storage capacity, communication capacity and operating load; When a new computing node or device interface is added to the system, the newly added computing node and device interface report their running status to the host and make the host update the first system resource registry to form a second system resource registry. When a computing node and a device interface fail or are removed, the switching network connecting the computing node and the device interface to the host A and the host B is offline interrupted, so that the master HOST updates the first system resource registry to form a third system resource registry; Step 5: The main HOST forms a device interface resource pool and a computing node resource pool based on the registry, and the system application task runs on the computing platform in a service manner: After the main HOST obtains the system task from the system network interface, it queries the system resource registry, allocates the corresponding device interface and computing node according to the current system operation load, and dynamically adjusts the routing table of the switching network. After completing the resource allocation, the main HOST sends a task command to the device interface and computing node; Step 6: The task agent program is run on both the computing node and the device interface. The agent program is responsible for initializing local resources, parsing the task command, and loading the APP corresponding to the task command; Step 7: The main HOST flexibly allocates device interfaces and computing nodes according to the request of the upper-level system to the APP.

2. The method according to claim 1, characterized in that In step 3, host B broadcasts a system message to all computing nodes and device interfaces to confirm that host B is the primary host and host A is the backup host. It also includes: Host A periodically monitors the health status of B and takes over the system when B fails.

3. The method according to claim 1, characterized in that In step 3, host B broadcasts a system message to all computing nodes and device interfaces to determine that host B is the primary host and host A is the backup host. The following steps are also included: Host B, as the master HOST, is responsible for completing system initialization, health management, and task scheduling.

4. The method according to claim 1, characterized in that: In step 4, after the host HOST forms or updates the first system resource registration table, it also includes: The primary HOST sends the current system resource registry to the backup HOST.

5. The method according to claim 1, characterized in that In step 6, the application APP corresponding to the task command is loaded, specifically: The main HOST stores the APP image in the non-volatile memory of the main HOST. The computing nodes and device interfaces locally cache the APPs loaded during the task cycle. When loading, they first query the task APP image in the local storage. If it does not hit, the image is read and loaded from the main HOST.

6. The method according to claim 1, characterized in that Step 7 specifically includes: when the system's request for a certain APP increases, the main HOST dynamically allocates a new computing node to execute the same APP as the certain APP according to the resource status in the current resource registration table; When the master HOST detects that the computing node is overloaded, it dynamically migrates part or all of the task to other nodes.

7. The method according to claim 6, characterized in that The computing node is overloaded, with computing resource usage exceeding 90%.

8. The method according to claim 1, characterized in that In step 4, when a computing node or device interface fails or is removed, the following steps are also included: The computing nodes and device interfaces periodically report resource utilization, bit error rate, BIT results, communication status, and device temperature to the main HOST; if the status is not reported for multiple consecutive cycles, the main HOST will initiate an inquiry message. If the computing nodes and device interfaces do not respond to the message, the main HOST determines that the resource is offline, updates the registry, and reallocates computing resources.

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