A method and device for controlling circuit voltage

Abstract

The present invention relates to a method and device for controlling circuit voltage, the method comprising: a main LDO receives a read / write operation instruction of a control port, generates a read / write voltage, records the read / write voltage as a first signal, and outputs the first signal to a sub-LDO; according to the module address configured by the top-level code stream, matches the module's own ID, generates a module selection signal, and selects a module according to the module selection signal; an LDO output voltage control signal selector selects the LDO output voltage control signal, and records the selected LDO output voltage control signal as a read / write enable signal; and the sub-LDO provides voltage to the circuit according to the first signal and the read / write enable signal. By the method for controlling circuit voltage provided by the present application, the power supply voltage of the memory in different working modes can be changed, so that the write operation is more reliable, while reducing power consumption, and changing the power supply voltage in different working modes can also increase the speed.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and more specifically, to a method and device for controlling circuit voltage. Background Art

[0002] FPGA memory is distributed throughout the entire FPGA chip and is the largest storage unit inside the chip. The data in it controls configurable logic resources such as wiring resources and lookup tables. The normal operation of the memory requires the normal supply of voltage to the memory.

[0003] In the prior art, one voltage is configured for all memories, and the modules in the memory are all at the same voltage. When one module can complete the required function, supplying power to all modules together obviously increases power consumption and causes waste. In addition, with a single memory supply voltage, the circuit cannot meet the characteristics of stably realizing functions and improving speed at the same time. Summary of the invention

[0004] In order to solve the above problems, the present application proposes a method and device for controlling circuit voltage.

[0005] In a first aspect, the present application provides a method for controlling a circuit voltage, the method comprising:

[0006] The main LDO receives a read / write operation instruction from the control port, records the read / write voltage generated by the operation instruction as a first signal, and outputs it to the sub-LDO;

[0007] According to the module address configured in the top-level code stream, the module ID is matched with the module itself, a module selection signal is generated, and a module is selected according to the module selection signal;

[0008] The LDO output voltage control signal selector selects the LDO output voltage control signal and records the selected LDO output voltage control signal as a read / write enable signal;

[0009] The sub-LDO provides a voltage to the circuit according to the first signal and the read / write enable signal.

[0010] Preferably, the LDO output voltage control signal selector selects the LDO output voltage control signal including:

[0011] The LDO output voltage control signal is determined according to the module selection signal.

[0012] Preferably, the method further comprises: a switching signal of an LDO is also present in the circuit;

[0013] The sub-LDO provides a voltage to the circuit according to the first signal and the read / write enable signal, comprising:

[0014] When the switch signal of the LDO is not 0, the sub-LDO provides a voltage to the circuit according to the first signal and the read / write enable signal.

[0015] Preferably, the voltage provided to the circuit module includes a write voltage or a read voltage.

[0016] Preferably, the write voltage is lower than the read voltage.

[0017] In a second aspect, the present application provides a device for controlling circuit voltage, comprising:

[0018] A first signal unit, configured to generate a read / write voltage according to a read / write operation instruction of a control port received by the main LDO, record it as a first signal, and output the first signal to the sub-LDO through the main LDO, record it as the first signal;

[0019] A selection unit, used for matching the module address configured in the top-level code stream with the module ID, generating a module selection signal, and selecting a module according to the module selection signal;

[0020] A second signal unit, used for selecting an LDO output voltage control signal according to the LDO output voltage control signal selector, and recording the selected LDO output voltage control signal as a read / write enable signal;

[0021] A power supply unit is used to enable the sub-LDO to provide voltage to the circuit according to the first signal and the read / write enable signal.

[0022] Preferably, the second signal unit is specifically used for:

[0023] The LDO output voltage control signal selector is determined according to the module selection signal, and the LDO output voltage control signal is selected according to the LDO output voltage control signal selector.

[0024] Preferably, the device further comprises: a judging unit, configured to judge an LDO switch signal existing in the circuit;

[0025] The power supply unit is specifically used for: when the judging unit judges that the LDO switch signal is not 0, the sub-LDO provides voltage to the circuit according to the first signal and the read / write enable signal.

[0026] Preferably, the voltage provided to the circuit module includes a write voltage or a read voltage.

[0027] Preferably, the write voltage is lower than the read voltage.

[0028] By using the method for controlling circuit voltage provided in the present application, the power supply voltage in the circuit can be changed in different working modes, making the write operation more reliable while reducing power consumption. Changing the power supply voltage in different working modes can also increase the speed.

[0029] Description of the attached drawings

[0030] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A schematic diagram of VC voltage distribution based on modules provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of VC voltage generation provided in an embodiment of the present application;

[0033] Figure 3 An internal logic diagram for generating a VC voltage provided in an embodiment of the present application;

[0034] Figure 4 A schematic diagram of a method for controlling a memory voltage provided in an embodiment of the present application:

[0035] Figure 5 This is a schematic diagram of the VC timing provided in the embodiment of the present application;

[0036] Figure 6 This is a schematic diagram of the delay time varying with the VC voltage provided in the embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] To facilitate the understanding of the embodiments of the present invention, the following will be further explained with reference to the accompanying drawings. The embodiments do not limit the embodiments of the present invention. The term "copy of a work", "copy" and "reproduction" used herein have the same meaning and refer to the reproduction of a work obtained by copying the work.

[0039] It should be noted that the method for controlling circuit voltage in the present application is specifically described by taking controlling the voltage of a memory as an example. It can be understood that the memory can also be equivalently replaced by circuit components in various other possible business scenarios.

[0040] Figure 1 Schematic diagram of VC voltage distribution based on modules provided in the embodiment of the present application. Figure 1 As shown, the main LDO receives a read operation instruction from the control port to generate a read voltage, or the main LDO receives a write operation instruction from the control port to generate a write voltage. The read operation instruction is recorded as main_ldo_ctrl_read, the write operation instruction is recorded as main_ldo_ctrl_write, the read voltage is recorded as n_read, and the write voltage is recorded as n_write. The read voltage n_read or the write voltage n_write is output to several modules. Each of the several modules determines whether the module is selected according to the module selection signal and the LDO switch signal, and the sub-LDO provides a VC voltage to the selected module. The module is recorded as block, the module selection signal is recorded as bk_sel, the LDO switch signal is recorded as cfgmem_ldo_pdb, and the sub-LDO is recorded as subldo.

[0041] Figure 2 Schematic diagram of VC voltage generation provided in the embodiment of the present application. Figure 2 As shown, the main LDO receives a read operation instruction from the control port to generate a read voltage, or the main LDO receives a write operation instruction from the control port to generate a write voltage. The module generates a VC voltage according to bk_sel, the LDO output voltage control signal, and the read voltage or the write voltage. The LDO output voltage control signal is recorded as cfgmem_ldo_sel.

[0042] Figure 3 This is a schematic diagram of the internal logic of the VC voltage generation provided in the embodiment of the present application. Figure 3 As shown, the read / write enable signal is determined according to bk_sel and cfgmem_ldo_sel, and the read / write enable signal is recorded as read_write_en. Then, the read voltage n_read or the write voltage n_write is determined according to the read / write enable signal read_write_en. Then, the VC voltage is determined according to the determined read voltage n_read or write voltage n_write and the LDO switch signal cfgmem_ldo_pdb.

[0043] Figure 4 This is a schematic diagram of a method for controlling a memory voltage provided in an embodiment of the present application. Figure 1 , Figure 2 and Figure 3 right Figure 4Further explanation is given. Figure 4 As shown, the method for controlling the memory voltage includes:

[0044] S201: The main LDO receives a read / write operation instruction from a control port, generates a read / write voltage, records the read / write voltage as a first signal, and outputs the first signal to the sub-LDO.

[0045] Specifically, please refer to Figure 2 When the first signal is a voltage generated by a read operation instruction, it is recorded as n_read; when the first signal is a voltage generated by a write operation instruction, it is recorded as n_write.

[0046] S202: Matching the module address configured in the top-level code stream with the module ID, generating a module selection signal, and selecting a module according to the module selection signal.

[0047] The VC voltage of the selected module can be read and written, and the VC voltage of the unselected module remains unchanged.

[0048] Specifically, the module address is recorded as bk_adr, and the module is recorded as block. For example, if there are 4 blocks, the IDs of the 4 blocks can be recorded as 00, 01, 10, and 11 respectively. The module selection signal can be obtained by comparing bk_adr with the block ID, and whether the memory module is turned on is determined according to the module selection signal.

[0049] S203: The LDO output voltage control signal selector selects the LDO output voltage control signal, and records the selected LDO output voltage control signal as a read / write enable signal.

[0050] In some possible embodiments, the LDO output voltage control signal selector selects the LDO output voltage control signal including: determining the LDO output voltage control signal according to the module selection signal.

[0051] For example, please refer to Figure 3 In this embodiment, the output voltage control signal selector is recorded as cfgmem_ldo_sel[1:0], and the read / write enable signal is recorded as read_write_en. When the module selection signal bk_sel is 1, cfgmem_ldo_sel[1] is selected; when the module selection signal bk_sel is 0, cfgmem_ldo_sel[0] is selected. The selected signal is marked as read_write_en.

[0052] The output voltage control signal selector cfgmem_ldo_sel[1:0] is 2 bits, and the specific value is configured by the top-level code stream.

[0053] For example, ldo_sel[1] is 1, ldo_sel[0] is 0, which is recorded as 10; ldo_sel[1] is 0, ldo_sel[0] is 1, which is recorded as 01.

[0054] S204: The sub-LDO provides a voltage to the memory according to the first signal and the read / write enable signal.

[0055] In some possible embodiments, the method for controlling the memory voltage also includes a switching signal of the LDO.

[0056] At this time, the sub-LDO provides a voltage to the memory according to the first signal and the read / write enable signal specifically including:

[0057] When the switch signal value of the LDO is not 0, the sub-LDO provides a voltage to the memory according to the first signal and the read / write enable signal.

[0058] In some possible embodiments, providing a voltage to the memory module includes a write voltage or a read voltage.

[0059] In a more specific example, the output voltage control signal selector cfgmem_ldo_sel[1:0] and the module selection signal bk_sel jointly select the VC value from the write voltage output by the main LDO or the read voltage output by the main LDO. For a specific truth table, please refer to Table 1. It can be understood that the truth table shown in Table 1 is one of the embodiments of the present application, and according to the design concept of the present application, it can also be applied to other truth tables.

[0060] Table 1

[0061] cfgmem_ldo_pdb cfgmem_ldo_sel[1:0] bk_sel VC 0 XX XX 0 1 00 0 / 1 VC_write 1 11 0 / 1 VC_read 1 X1 0 VC_read 1 X0 0 VC_write 1 1X 1 VC_read 1 0X 1 VC_write

[0062] X in the table refers to: The value of X is arbitrary.

[0063] As shown in Table 1, when the value of cfgmem_ldo_pdb is 0, because the priority of cfgmem_ldo_pdb is the highest, no matter how the subsequent cfgmem_ldo_sel[1:0] and bk_sel are set, the value of VC is 0. When the value of cfgmem_ldo_pdb is 1, VC has a value.

[0064] When the value of cfgmem_ldo_pdb is 1, the voltage starts to power up. If the value of cfgmem_ldo_sel[1:0] is 00, the read / write enable signal read_write_en is 0, and VC is VC_write, which is determined by the write operation instruction of the main LDO.

[0065] If the value of cfgmem_ldo_sel[1:0] is 11, the read / write enable signal read_write_en is 1, and VC is VC_read, which is determined by the read operation instruction of the main LDO.

[0066] If the value of bk_sel is 0, cfgmem_ldo_sel[0] is selected and the VC value is determined by cfgmem_ldo_sel[0].

[0067] If the value of bk_sel is 1, cfgmem_ldo_sel[1] is selected and the VC value is determined by cfgmem_ldo_sel[1].

[0068] In some possible embodiments, the write voltage is lower than the read voltage.

[0069] For example, the VC value during writing is 0.8V, and the VC value during reading is 1.3V. The VC value during writing is lower than the VC value during reading.

[0070] Figure 5 This is a schematic diagram of the VC timing provided in the embodiment of the present application. It can be understood that Figure 5 The timing diagram is one of the embodiments of the present application. According to the design concept of the present application, it can also be applied to other timing diagrams.

[0071] like Figure 5 As shown, the main LDO write control port is recorded as main_ldo_ctrl_write, the main LDO read control port is recorded as main_ldo_ctrl_read, the LDO output voltage control signal is recorded as cfgmem_ldo_sel, the module address is recorded as bk_adr, the memory initialization signal is recorded as inial_cmc, the LDO switch signal is recorded as cfgmem_ldo_pdb, and the module selection signal is recorded as bk_sel. The start stage is recorded as initial stage, the configuration stage is recorded as cfg stage, the user mode stage is recorded as user mode, and the module restart stage is recorded as block_re_initial.

[0072] The module address bk_adr is used to select the module and determine which module to configure the VC. The 1000 in the schematic diagram indicates that the highest bit of bk_adr is 1, which means that all modules are selected and the VC voltage of all module memories needs to be configured. The 0XXX in the schematic diagram indicates that the highest bit is 0, which means that only the selected module can be configured later.

[0073] The cfgmem_ldo_pdb signal controls the switch of the sub-LDO and starts to execute after reset and cfgmem_ldo_sel selection.

[0074] iniall_cmc clears the memory at the beginning and then sends a signal again at the next configuration restart.

[0075] It can be understood that VC starts to rise in the initialization phase and then enters the configuration phase. Both the initialization phase and the configuration phase are a memory writing process. The VC voltage at this time can be lower than that in the user mode, because the low VC voltage facilitates memory writing and saves power consumption. In the read phase, the VC voltage can be increased to make the memory easier to read, which can improve the accuracy of the read data and improve circuit performance. Figure 6 This is a schematic diagram of the delay time provided in the embodiment of the present application as a function of the VC voltage. The delay time decreases as the VC voltage increases. The higher the VC voltage, the lower the delay time. Please refer to Figure 6 When in user mode, the VC voltage can be increased to increase the circuit's operating speed. When restarting, the VC voltage will first drop to the minimum, and then increase the VC voltage according to the module selected by bk_adr.

[0076] By using the method for controlling the memory voltage provided in the present application, the power supply voltage of the memory in different working modes can be changed to make the write operation more reliable while reducing power consumption. Changing the power supply voltage in different working modes can also increase the speed.

[0077] Based on the method for controlling the memory voltage provided in the above embodiment, this embodiment further provides a device for controlling the memory voltage. The device for generating the property certificate of a copy of a work provided in this embodiment may include:

[0078] The first signal unit is used to record the read / write voltage generated according to the read / write operation instruction of the control port received by the main LDO as a first signal, and output the first signal to the sub-LDO through the main LDO.

[0079] The selection unit is used to match the module address configured in the top-level code stream with the module ID, generate a module selection signal, and select a module according to the module selection signal.

[0080] The second signal unit is used to select the LDO output voltage control signal according to the LDO output voltage control signal selector, and record the selected LDO output voltage control signal as the read / write enable signal.

[0081] In some possible embodiments, the second signal unit is specifically used for:

[0082] The LDO output voltage control signal selector is determined according to the module selection signal, and the LDO output voltage control signal is selected according to the LDO output voltage control signal selector.

[0083] A power supply unit is used to enable the sub-LDO to provide voltage to the memory module according to the first signal and the read / write enable signal.

[0084] In some possible embodiments, the device further includes:

[0085] The judging unit is used to judge the LDO switch signal existing in the circuit.

[0086] The power supply unit is specifically used for:

[0087] When the judging unit judges that the LDO switch signal is not 0, the sub-LDO provides a voltage to the memory module according to the first signal and the read / write enable signal.

[0088] In some possible embodiments, providing a voltage to the memory module includes a write voltage or a read voltage.

[0089] In some possible embodiments, the write voltage is lower than the read voltage.

[0090] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0091] The above specific implementation methods further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for controlling circuit voltage, characterized in that: The method comprises: The main LDO receives a read / write operation instruction from the control port, generates a read / write voltage, records the read / write voltage as a first signal, and outputs the first signal to the sub-LDO; According to the module address configured in the top-level code stream, the module ID is matched with the module itself, a module selection signal is generated, and a module is selected according to the module selection signal; The LDO output voltage control signal selector selects the LDO output voltage control signal, and records the selected LDO output voltage control signal as a read / write enable signal; wherein the LDO output voltage control signal selector selects the LDO output voltage control signal including: determining the LDO output voltage control signal selector according to the module selection signal, and selecting the LDO output voltage control signal according to the LDO output voltage control signal selector; The sub-LDO provides a voltage to the circuit according to the first signal and the read / write enable signal.

2. The method according to claim 1, characterized in that The method further comprises: There is also a switching signal of LDO in the circuit; The sub-LDO provides a voltage to the circuit according to the first signal and the read / write enable signal, comprising: When the switch signal of the LDO is not 0, the sub-LDO provides a voltage to the circuit according to the first signal and the read / write enable signal.

3. The method according to claim 1 or 2, characterized in that: The voltage provided to the circuit includes a write voltage or a read voltage.

4. The method according to claim 3, characterized in that The write voltage is lower than the read voltage.

5. A device for controlling circuit voltage, characterized in that: The device comprises: A first signal unit, configured to record a read / write voltage generated according to a read / write operation instruction of a control port received by the main LDO as a first signal, and output the first signal to the sub-LDO through the main LDO; A selection unit, used for matching the module address configured in the top-level code stream with the module ID, generating a module selection signal, and selecting a module according to the module selection signal; A second signal unit, configured to select an LDO output voltage control signal according to an LDO output voltage control signal selector, and record the selected LDO output voltage control signal as a read / write enable signal; wherein the second signal unit is specifically configured to: determine the LDO output voltage control signal selector according to the module selection signal, and select the LDO output voltage control signal according to the LDO output voltage control signal selector; A power supply unit is used to enable the sub-LDO to provide voltage to the circuit according to the first signal and the read / write enable signal.

6. The device according to claim 5, characterized in that The device also includes: A judging unit, used for judging an LDO switch signal existing in the circuit; The power supply unit is specifically used for: When the determination unit determines that the LDO switch signal is not 0, the sub-LDO provides a voltage to the circuit according to the first signal and the read / write enable signal.

7. The device according to claim 5 or 6, characterized in that The voltage provided to the circuit includes a write voltage or a read voltage.

8. The device according to claim 7, characterized in that The write voltage is lower than the read voltage.

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