A method for preparing NOR flash memory

Abstract

The present invention provides a method for preparing a NOR flash memory, comprising: providing a substrate having a gate stack formed thereon; forming a stacked layer on the substrate, the stacked layer covering the substrate and outer walls of the gate stack, the stacked layer comprising an oxide layer, a silicon nitride layer, and a first porous carbon layer sequentially stacked on the substrate; etching the stacked layer to form a first opening exposing the substrate, the first opening being located between adjacent gate stacks; performing a first ion implantation process on the substrate below the first opening to form a first drain region; removing the first porous carbon layer through a thermal oxidation process; and forming a self-aligned metal silicide layer on the first drain region. The substrate and the oxide layer do not react during the thermal oxidation process, thereby avoiding lateral etching of the substrate and the oxide layer during the removal of the first porous carbon layer, thereby ensuring the accuracy of the self-aligned process window and reducing leakage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for preparing a NOR flash memory. Background Art

[0002] Advances in semiconductor technology have led to the development of flash memory, a storage device with relatively fast access speeds. Flash memory can store, read, and erase information repeatedly, and the stored information persists even after a power outage. Therefore, it has become a widely used non-volatile memory in personal computers and electronic devices. NOR (NOR) flash memory can be read and programmed using random access, and due to its non-volatility, durability, and fast access times, it is widely used in mobile devices.

[0003] For NOR flash memory, as the critical dimensions continue to shrink, the aspect ratio of the storage area becomes larger and larger, and the difficulty of making the contact holes in the storage area is also increasing. In the existing technology, the accuracy of the self-aligned process window when forming metal silicide is difficult to guarantee, which will cause leakage and affect the performance and reliability of NOR flash memory. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for preparing a NOR flash memory, improve the accuracy of the self-aligned process window of the self-aligned metal silicide layer, and reduce the leakage phenomenon.

[0005] In order to achieve the above object, the present invention provides a method for preparing a NOR flash memory, comprising:

[0006] providing a substrate, on which a gate stack is formed;

[0007] forming a stacked layer on the substrate, the stacked layer covering the substrate and an outer wall of the gate stack, the stacked layer comprising an oxide layer, a silicon nitride layer, and a first porous carbon layer sequentially stacked on the substrate;

[0008] Etching the stacked layer to form a first opening exposing the substrate, wherein the first opening is located between adjacent gate stacks;

[0009] performing a first ion implantation process on the substrate below the first opening to form a first drain region;

[0010] removing the first porous carbon layer by a thermal oxidation process;

[0011] A self-aligned metal silicide layer is formed on the first drain region.

[0012] Optionally, the temperature of the thermal oxidation process is 500 degrees Celsius to 800 degrees Celsius.

[0013] Optionally, the substrate has a peripheral logic area and a storage area, and the gate stack is located on the storage area.

[0014] Optionally, when forming the gate stack, a logic gate is simultaneously formed on the peripheral logic region.

[0015] Optionally, the gate stack and the logic gate are connected via a word line.

[0016] Optionally, when the stacked layer is formed on the gate stack, the stacked layer is also formed on the logic gate simultaneously, and the stacked layer also covers the substrate of the peripheral logic region and the logic gate.

[0017] Optionally, after forming the first drain region and before removing the first porous carbon layer, the method further includes:

[0018] forming a second porous carbon layer on the substrate, wherein the second porous carbon layer covers the first porous carbon layer and the first drain region;

[0019] Etching away a portion of the second porous carbon layer and the stacked layer on both sides of the logic gate to form a second opening exposing the substrate;

[0020] A second ion implantation process is performed on the substrate below the second opening to form a second drain region.

[0021] Optionally, after forming the second drain region, the first porous carbon layer and the second porous carbon layer are simultaneously removed by the thermal oxidation process.

[0022] Optionally, after removing the second porous carbon layer, the self-aligned metal silicide layer is simultaneously formed on the first drain region and the second drain region.

[0023] Optionally, after forming the self-aligned metal silicide layer, the method further includes: forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the self-aligned silicide layer, the silicon nitride layer, the gate stack and the logic gate.

[0024] The present invention provides a method for preparing a NOR flash memory, comprising: providing a substrate having a gate stack formed thereon; forming a stacked layer on the substrate, the stacked layer covering the substrate and outer walls of the gate stack, the stacked layer comprising an oxide layer, a silicon nitride layer, and a first porous carbon layer sequentially stacked on the substrate; etching the stacked layer to form a first opening exposing the substrate, the first opening being located between adjacent gate stacks; performing a first ion implantation process on the substrate below the first opening to form a first drain region; removing the first porous carbon layer through a thermal oxidation process; and forming a self-aligned metal silicide layer on the first drain region. The substrate and the oxide layer do not react during the thermal oxidation process, thereby avoiding lateral etching of the substrate and the oxide layer during the removal of the first porous carbon layer. This ensures the accuracy of the self-aligned process window when forming the self-aligned metal silicide, reduces leakage, and improves the reliability of the NOR flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flowchart of a method for preparing a NOR flash memory provided by an embodiment of the present invention;

[0026] Figures 2 to 12 A schematic structural diagram corresponding to the corresponding steps of the method for preparing a NOR flash memory provided by an embodiment of the present invention;

[0027] Figure 13 is a scanning electron microscope morphology image of the oxide layer when side etching occurs;

[0028] The accompanying drawings are as follows:

[0029] 100 - substrate; 101 - tunneling oxide material layer; 103 - floating gate polysilicon layer; 105 - gate dielectric material layer; 107 - control gate polysilicon layer; 102 - tunneling oxide layer; 104 - floating gate layer; 106 - gate dielectric layer; 108 - control gate layer; 109 - logic gate; 111 - gate stack; 110 - oxide layer; 112 - silicon nitride layer; 114 - first porous carbon layer; 115 - first opening; 116 - first drain region; 118 - second porous carbon layer; 119 - second opening; 120 - second drain region; 122 - self-aligned metal silicide layer;

[0030] A-storage area; B-peripheral logic area. DETAILED DESCRIPTION

[0031] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0032] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms, when used in this manner, are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the steps presented herein are not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0033] Figure 1 The flowchart of the method for preparing the NOR flash memory provided in this embodiment is as follows: Figure 1 As shown, the method for preparing the semiconductor structure includes:

[0034] Step S1: providing a substrate, on which a gate stack is formed;

[0035] Step S2: forming a stacked layer on the substrate, the stacked layer covering the substrate and an outer wall of the gate stack, the stacked layer comprising an oxide layer, a silicon nitride layer, and a first porous carbon layer stacked sequentially on the substrate;

[0036] Step S3: etching the stacked layer to form a first opening exposing the substrate, wherein the first opening is located between adjacent gate stacks;

[0037] Step S4: performing a first ion implantation process on the substrate below the first opening to form a first drain region;

[0038] Step S5: removing the first porous carbon layer by a thermal oxidation process;

[0039] Step S6: forming a self-aligned metal silicide layer on the first drain region.

[0040] Figures 2 to 12 The structural diagram corresponding to the corresponding steps of the preparation method of the NOR flash memory provided in this embodiment is shown below in conjunction with the attached Figures 2 to 12 The method for preparing the NOR flash memory provided in this embodiment is described in more detail, wherein a preferred embodiment of the present invention is illustrated.

[0041] like Figure 2 and Figure 3As shown, a substrate 100 is provided, the substrate 100 having a memory area A and a peripheral logic area B. A tunneling oxide material layer 101, a floating gate polysilicon layer 103, and a gate dielectric material layer 105 are sequentially formed on the substrate 100. Photoresist is spin-coated on the surface of the gate dielectric material layer 105 and patterned. The gate dielectric material layer 105 and the floating gate polysilicon layer 103 on the peripheral logic area B are etched away using the patterned photoresist as a mask. Portions of the gate dielectric material layer 105 and the floating gate polysilicon layer 103 on the memory area A are also removed. The remaining gate dielectric material layer 105 and the floating gate polysilicon layer 103 form a gate dielectric layer 106 and a floating gate layer 104, respectively.

[0042] like Figure 4 As shown, a control gate polysilicon layer 107 is formed on the substrate 100 , and the control gate polysilicon layer 107 conformally covers the substrate 100 , the gate dielectric layer 106 and the tunneling oxide material layer 101 .

[0043] like Figure 5 As shown, photoresist is spin-coated on the surface of the control gate polysilicon layer 107 and patterned, and the patterned photoresist layer is used as a mask to etch away the control gate polysilicon layer 107 and the tunneling oxide material layer 101 outside the floating gate layer 104 on the storage area A to form a tunneling oxide layer 102 and a control gate layer 108. The control gate layer 108, the gate dielectric layer 106, the floating gate layer 104 and the tunneling oxide layer 102 constitute a gate stack 111, and the gate stack 111 is located on the storage area A.

[0044] When etching to form the gate stack 111, part of the control gate polysilicon layer 107 and the tunneling oxide material layer 101 on the peripheral logic area B are also synchronously etched away. The remaining control gate polysilicon layer 107 and the tunneling oxide material layer 101 constitute a logic gate 109 corresponding to the gate stack 111. The gate stack 111 and the logic gate 109 are connected by a word line.

[0045] The gate dielectric layer 106 is a dielectric material such as oxide or nitride. In this embodiment, the gate dielectric layer 106 is an ONO structure, that is, a stack of oxide-nitride-oxide is used, so that the gate dielectric layer 106 has good dielectric properties and a suitable thickness.

[0046] like Figure 6 As shown, a stacked layer is formed on the substrate 100, and the stacked layer covers the substrate 100, the gate stack 111 and the outer wall of the logic gate 109. The stacked layer includes an oxide layer 110, a silicon nitride layer 112 and a first porous carbon layer 114 stacked in sequence on the substrate 100.

[0047] like Figure 7 As shown, photoresist is spin-coated on the first porous carbon layer 114 and patterned, and the stacked layer is etched using the patterned photoresist layer as a mask to remove the top surface of the gate stack 111 and part of the stacked layer between adjacent gate stacks 111, and form a first opening 115 between adjacent gate stacks 111 to expose the substrate 100.

[0048] like Figure 8 As shown, a first ion implantation process is performed on the substrate 100 below the first opening 115 to form a first drain region 116 in the substrate 100 .

[0049] like Figure 9 and Figure 10 As shown, a second porous carbon layer 118 is formed on the substrate 100, covering the first drain region 116, the top surface of the gate stack 111, and the stacked layer. The second porous carbon layer 118 and the stacked layer are removed from the top surface of the logic gate 109 by etching, and the second porous carbon layer 118 and the stacked layer are removed from the peripheral logic region B. A second opening 119 is formed on both sides of the logic gate 109, exposing the substrate 100. A second ion implantation process is then performed on the substrate 100 below the second opening 119, forming a second drain region 120 within the substrate 100.

[0050] like Figure 11 As shown, the first porous carbon layer 114 and the second porous carbon layer 118 are removed by a thermal oxidation process, and the temperature of the thermal oxidation process is 500 degrees Celsius to 800 degrees Celsius.

[0051] like Figure 12 As shown, a metal layer is formed on the substrate 100, covering the gate stack 111, the first drain region 116, the logic gate 109, the second drain region 120, and the silicon nitride layer 112. An annealing process is performed on the substrate 100 to allow the metal layer to react with the silicide in the first drain region 116 and the second drain region 120, thereby forming a self-aligned metal silicide layer 122 on the first drain region 116 and the second drain region 120 for subsequently leading out the first drain region 116 and the second drain region 120. Finally, the remaining metal layer is removed by wet etching.

[0052] The material of the metal layer may be titanium, cobalt, nickel or other metals.

[0053] An interlayer dielectric layer (not shown) is formed on the substrate 100 , and the interlayer dielectric layer covers the salicide layer 122 , the silicon nitride layer 112 , the gate stack 111 , and the logic gate 109 .

[0054] If the first porous carbon layer and the second porous carbon layer are removed by wet etching, the wet etching solution accumulates in the first opening, causing the oxide layer and the substrate to be lateral-etched. Figure 13 This is the scanning electron microscope morphology when the oxide layer is lateral etched, as shown in Figure 13 As shown, when the self-aligned metal silicide layer is formed on the first drain region and the second drain region, a cavity (the circled part in the figure) is formed between the self-aligned metal silicide and the oxide, and the accuracy of the self-aligned process window of the self-aligned metal silicide layer is difficult to ensure, which is prone to leakage and affects the performance of the semiconductor device.

[0055] In this embodiment, when the first porous carbon layer and the second porous carbon layer are removed by the thermal oxidation process, the substrate and the oxide layer do not react in the thermal oxidation process, thereby avoiding lateral etching of the oxide layer and the substrate by wet etching, fundamentally avoiding the formation of a cavity under the silicon nitride between the gate stacks, thereby ensuring the accuracy of the self-aligned metal silicide layer self-aligned process window and reducing leakage.

[0056] In summary, the present invention provides a method for preparing a NOR flash memory, comprising: providing a substrate 100, on which a gate stack 111 is formed; forming a stacking layer on the substrate 100, wherein the stacking layer covers the substrate 100 and the outer wall of the gate stack 111, and the stacking layer comprises an oxide layer 110, a silicon nitride layer 112 and a first porous carbon layer 114 stacked in sequence on the substrate 100; etching the stacking layer to form a first opening 115 exposing the substrate 100, wherein the first opening 115 is located between adjacent gate stacks 111; performing a first ion implantation process on the substrate 100 below the first opening 115 to form a first drain region 116; removing the first porous carbon layer 114 through a thermal oxidation process; and forming a self-aligned metal silicide layer 122 on the first drain region 116. The substrate 100 and the oxide layer 110 do not react during the thermal oxidation process, thereby avoiding lateral etching of the substrate 100 and the oxide layer 110 during the removal of the first porous carbon layer 114, thereby ensuring the accuracy of the self-aligned process window when forming the self-aligned metal silicide 122, reducing leakage, and improving the reliability of the NOR flash memory device.

[0057] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A method for preparing a NOR flash memory, characterized in that: include: Providing a substrate, on which a gate stack and a logic gate are formed; forming a stacked layer on the substrate, the stacked layer covering the substrate, an outer wall of the gate stack, and an outer wall of the logic gate, the stacked layer comprising an oxide layer, a silicon nitride layer, and a first porous carbon layer sequentially stacked on the substrate; Etching the stacked layer to form a first opening exposing the substrate, wherein the first opening is located between adjacent gate stacks; performing a first ion implantation process on the substrate below the first opening to form a first drain region; forming a second porous carbon layer on the substrate, wherein the second porous carbon layer covers the first porous carbon layer and the first drain region; Etching away a portion of the second porous carbon layer and the stacked layer on both sides of the logic gate to form a second opening exposing the substrate; performing a second ion implantation process on the substrate below the second opening to form a second drain region; removing the first porous carbon layer and the second porous carbon layer by a thermal oxidation process at a temperature of 500 degrees Celsius to 800 degrees Celsius; A self-aligned metal silicide layer is formed on the first drain region and the second drain region.

2. The method for preparing a NOR flash memory according to claim 1, wherein: The substrate is provided with a peripheral logic area and a storage area, and the gate stack is located on the storage area.

3. The method for preparing a NOR flash memory according to claim 2, wherein: The gate stack and the logic gate are connected via a word line.

4. The method for preparing a NOR flash memory according to claim 1, wherein: After forming the self-aligned metal silicide layer, the method further includes: forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the self-aligned metal silicide layer, the silicon nitride layer, the gate stack and the logic gate.

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