Display substrate, manufacturing method thereof, and display device

Abstract

The present application discloses a display substrate, a manufacturing method thereof, and a display device, belonging to the field of display technology. The display substrate includes a base substrate, display wiring, a shielding structure, and a touch wiring. The base substrate includes a display area and a peripheral area that at least partially surrounds the display area. The display wiring is located in the peripheral area and at least partially surrounds the display area. The shielding structure is located on the side of the display wiring away from the base substrate. The touch wiring is located on the side of the shielding structure away from the base substrate. The orthographic projections of the display wiring, the shielding structure, and the touch wiring on the base substrate at least partially overlap. The present application can shield the mutual interference between the display signal in the display wiring and the touch signal in the touch wiring.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Flexible Multi-Layer On Cell (FMLOC) technology refers to the process of fabricating a touch-sensitive structure on the packaging structure of a display substrate. The touch-sensitive structure typically includes touch electrodes and touch traces, with the touch traces used to provide touch signals to the touch electrodes. Because display substrates typically include integrated gate on array (GOA) circuits, display signals transmitted in display traces, such as the input and output traces of the GOA circuits, can easily interfere with touch signals transmitted in the touch traces, affecting the touch and display performance of the display substrate. Therefore, shielding the display and touch signals from interfering with each other is an urgent problem that needs to be solved. Summary of the Invention

[0003] The present application provides a display substrate and a manufacturing method thereof, as well as a display device, which can shield the mutual interference between the display signal transmitted in the display wiring and the touch signal transmitted in the touch wiring. The technical solution is as follows:

[0004] In a first aspect, a display substrate is provided, comprising:

[0005] a base substrate, comprising a display area and a peripheral area at least partially surrounding the display area;

[0006] a display trace located in the peripheral area and at least partially surrounding the display area;

[0007] a shielding structure, located on a side of the display trace away from the base substrate, wherein an orthographic projection of the shielding structure on the base substrate is located in the peripheral area;

[0008] a touch line located on a side of the shielding structure away from the base substrate, wherein an orthographic projection of the touch line on the base substrate is located in the peripheral area and at least partially surrounds the display area;

[0009] The orthographic projections of the display wiring, the shielding structure and the touch wiring on the base substrate at least partially overlap.

[0010] Optionally, the display area includes a first boundary, the peripheral area includes a first peripheral area extending along the first boundary, and the orthographic projection of the shielding structure on the base substrate is located in the first peripheral area.

[0011] Optionally, the shielding structure includes a first shielding portion and a second shielding portion, the first shielding portion and the second shielding portion are symmetrical about a first cross-section of the display substrate, and the first cross-section is perpendicular to the first boundary.

[0012] Optionally, an intersection line between the first cross section and the substrate bisects the first boundary.

[0013] Optionally, the display area further includes a second boundary and a third boundary, the second boundary and the third boundary respectively intersect with the first boundary, the orthographic projection of the first shielding portion on the base substrate is close to the intersection position of the first boundary and the second boundary, and the orthographic projection of the second shielding portion on the base substrate is close to the intersection position of the first boundary and the third boundary.

[0014] Optionally, the distance between the first shielding portion and the second shielding portion ranges from 50 mm to 60 mm.

[0015] Optionally, the display substrate further includes: a negative power line, located on a side of the display line away from the base substrate, the positive projection of the negative power line on the base substrate being located in the peripheral area and at least partially surrounding the display area; the shielding structure is located on a side of the negative power line away from the base substrate, the shielding structure is electrically connected to the negative power line, and the positive projection of the shielding structure on the base substrate at least partially overlaps with the positive projection of the negative power line on the base substrate.

[0016] Optionally, the width of the overlapping area between the shielding structure and the negative power line is in the range of 50 microns to 60 microns, and the overlapping area between the shielding structure and the negative power line is the overlapping area of ​​the orthographic projection of the shielding structure on the substrate and the orthographic projection of the negative power line on the substrate.

[0017] Optionally, the display substrate further includes: a cathode located on a side of the shielding structure away from the base substrate, the cathode being electrically connected to the negative power line, and the touch line located on a side of the cathode away from the base substrate; the orthographic projection of the shielding structure on the base substrate at least partially overlaps with the orthographic projection of the cathode on the base substrate.

[0018] Optionally, the width of the overlapping area between the shielding structure and the cathode is in the range of 20 microns to 25 microns, and the overlapping area between the shielding structure and the cathode is the overlapping area between the orthographic projection of the shielding structure on the base substrate and the orthographic projection of the cathode on the base substrate.

[0019] Optionally, the display substrate further includes: a positive power line, located on the side of the display line away from the base substrate, the orthographic projection of the positive power line on the base substrate being located in the peripheral area and at least partially surrounding the display area; the orthographic projection of the shielding structure on the base substrate at least partially overlaps with the orthographic projection of the positive power line on the base substrate.

[0020] Optionally, the width of the overlapping area between the shielding structure and the positive power line is in the range of 4 microns to 6 microns, and the overlapping area between the shielding structure and the positive power line is the overlapping area of ​​the orthographic projection of the shielding structure on the substrate and the orthographic projection of the positive power line on the substrate.

[0021] Optionally, the negative power line includes a first routing segment and a second routing segment, the first routing segment is electrically connected to the second routing segment, and the shielding structure is electrically connected to the second routing segment; the positive power line and the first routing segment are located on the same layer, and the second routing segment is located on the side of the first routing segment away from the substrate.

[0022] Optionally, the display substrate further includes: a blocking wall, the orthographic projection of the blocking wall on the base substrate being located in the peripheral area and surrounding the display area, the orthographic projection of the shielding structure on the base substrate being located between the display area and the orthographic projection of the blocking wall on the base substrate; the distance between the orthographic projection of the shielding structure on the base substrate and the orthographic projection of the blocking wall on the base substrate is in the range of 12 microns to 16 microns.

[0023] Optionally, the display substrate further includes: a negative power line and a positive power line;

[0024] The orthographic projection of the shielding structure on the base substrate is located in a first peripheral region, the orthographic projection of the negative power line on the base substrate is at least partially located in the first peripheral region, and the orthographic projection of the positive power line on the base substrate is at least partially located in the first peripheral region;

[0025] The width of the orthographic projection of the shielding structure on the substrate is in the range of 105 microns to 115 microns, the width of the orthographic projection of the negative power line in the first peripheral area is in the range of 145 microns to 155 microns, and the width of the orthographic projection of the positive power line in the first peripheral area is in the range of 95 microns to 105 microns.

[0026] In a second aspect, a method for manufacturing a display substrate is provided, the method comprising:

[0027] providing a base substrate, the base substrate comprising a display area and a peripheral area at least partially surrounding the display area;

[0028] A display trace, a shielding structure, and a touch trace are sequentially formed on the base substrate. The display trace is located in the peripheral area and at least partially surrounds the display area. The orthographic projection of the shielding structure on the base substrate is located in the peripheral area. The orthographic projection of the touch trace on the base substrate is located in the peripheral area and at least partially surrounds the display area. The orthographic projections of the display trace, the shielding structure, and the touch trace on the base substrate at least partially overlap.

[0029] Optionally, the method further includes: forming a negative power line on a side of the display line away from the substrate substrate, the positive projection of the negative power line on the substrate substrate being located in the peripheral area and at least partially surrounding the display area, the shielding structure being located on a side of the negative power line away from the substrate substrate, the shielding structure being electrically connected to the negative power line, and the positive projection of the shielding structure on the substrate substrate at least partially overlapping with the positive projection of the negative power line on the substrate substrate.

[0030] Optionally, the method further includes: forming a cathode on a side of the shielding structure away from the substrate, the cathode being electrically connected to the negative power line, the touch line being located on a side of the cathode away from the substrate, and the orthographic projection of the shielding structure on the substrate at least partially overlapping with the orthographic projection of the cathode on the substrate.

[0031] Optionally, the method further includes: forming a positive power line on a side of the display trace away from the substrate, the positive power line's orthographic projection on the substrate being located in the peripheral area and at least partially surrounding the display area, and the shielding structure's orthographic projection on the substrate at least partially overlaps with the positive power line's orthographic projection on the substrate.

[0032] In a third aspect, a display device is provided, comprising: the display substrate according to the first aspect or any optional implementation of the first aspect.

[0033] The beneficial effects of the technical solution provided by this application are:

[0034] The display substrate, manufacturing method thereof, and display device provided by the present application include a shielding structure, display wiring, and touch wiring in the display substrate. The shielding structure is located on the side of the display wiring away from the base substrate, and the touch wiring is located on the side of the shielding structure away from the base substrate (that is, the shielding structure is located between the display wiring and the touch wiring). Moreover, the orthographic projections of the display wiring, shielding structure, and touch wiring on the base substrate at least partially overlap. Therefore, the shielding structure can shield the display signal transmitted in the display wiring from mutual interference with the touch signal transmitted in the touch wiring, thereby preventing the display signal from affecting the touch effect, and also preventing the touch signal from affecting the display effect, thereby ensuring the display and touch effects of the display substrate.

[0035] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1 is a front view of a display substrate provided in an embodiment of the present application;

[0038] Figure 2 yes Figure 1 A cross-sectional view of the AA portion of the display substrate shown;

[0039] Figure 3 yes Figure 1 A cross-sectional view of the BB portion of the display substrate shown;

[0040] Figure 4 is a flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application;

[0041] Figure 5 is a flow chart of another method for manufacturing a display substrate provided in an embodiment of the present application;

[0042] Figure 6 This is a schematic diagram of a display trace formed on a substrate provided by an embodiment of the present application;

[0043] Figure 7 This is a schematic diagram of an embodiment of the present application, in which a negative power line and a positive power line are formed on a side of the display wiring away from the substrate;

[0044] Figure 8This is a schematic diagram of an embodiment of the present application, in which a shielding structure is formed on a side of a negative power line and a positive power line away from a substrate;

[0045] Figure 9 This is a schematic diagram of an embodiment of the present application after a cathode is formed on a side of a shielding structure away from a substrate.

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of this application more clear, this application will be further described in detail below with reference to the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0048] With the development of display technology, display devices have begun to develop in the direction of narrow bezels and full screens, and FMLOC technology has come into being. FMLOC technology is a technology that makes a touch structure on the packaging structure of a display substrate to integrate the touch function in the display substrate. Among them, the touch structure may include touch electrodes and touch traces, and the touch traces are used to provide touch signals to the touch electrodes. The touch traces are also called FMLOC signal lines, and the touch signals are also called FMLOC signals. The display substrate usually also includes a GOA circuit. The display signals transmitted in the display traces such as the input traces of the GOA circuit and the output traces of the GOA circuit are easily interfered with the touch signals transmitted in the touch traces, affecting the display effect and touch effect of the display substrate. Therefore, how to shield the mutual interference between the display signal and the touch signal is an urgent problem to be solved.

[0049] Embodiments of the present application provide a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a shielding structure, display wiring, and touch wiring. The shielding structure is located between the display wiring and the touch wiring, and the orthographic projections of the display wiring, shielding structure, and touch wiring on the base substrate at least partially overlap. Therefore, the shielding structure can shield the display signal transmitted in the display wiring from interfering with the touch signal transmitted in the touch wiring, thereby preventing the display signal from affecting the touch effect, and vice versa, thereby ensuring the display and touch effects of the display substrate.

[0050] The technical solutions of the embodiments of the present application are described below with reference to the accompanying drawings.

[0051] Figure 1is a front view of a display substrate provided in an embodiment of the present application, Figure 2 yes Figure 1 The cross-sectional view of the AA portion of the display substrate is shown. Figure 1 and Figure 2 The display substrate includes a base substrate 01, a display trace 02 located on the base substrate 01, a shielding structure 03 located on the side of the display trace 02 away from the base substrate 01, and a touch trace 04 located on the side of the shielding structure 03 away from the base substrate 01. The base substrate 01 includes a display area 011 and a peripheral area 012 that at least partially surrounds the display area 011. The display trace 02 is located in the peripheral area 012 and at least partially surrounds the display area 011. The orthographic projection of the shielding structure 03 on the base substrate 01 is located in the peripheral area 012. The orthographic projection of the touch trace 04 on the base substrate 01 is located in the peripheral area 012 and at least partially surrounds the display area 011. The orthographic projections of the display trace 02, the shielding structure 03, and the touch trace 04 on the base substrate 01 at least partially overlap.

[0052] Since the shielding structure 03 is located on the side of the display trace 02 away from the base substrate 01, and the touch trace 04 is located on the side of the shielding structure 03 away from the base substrate 01, the shielding structure 03 is located between the display trace 02 and the touch trace 04. The shielding structure 03 can block the display signal transmitted in the display trace 02 and the touch signal transmitted in the touch trace 04, thereby shielding the display signal transmitted in the display trace 02 from interfering with the touch signal transmitted in the touch trace 04, and shielding the touch signal transmitted in the touch trace 04 from interfering with the display signal transmitted in the display trace 02.

[0053] To sum up, the display substrate provided in the embodiment of the present application includes a shielding structure, display wiring and touch wiring. The shielding structure is located between the display wiring and the touch wiring, and the orthographic projections of the display wiring, the shielding structure and the touch wiring on the base substrate at least partially overlap. Therefore, the shielding structure can shield the mutual interference between the display signal transmitted in the display wiring and the touch signal transmitted in the touch wiring, thereby preventing the display signal transmitted in the display wiring from affecting the touch effect of the display substrate, and preventing the touch signal transmitted in the touch wiring from affecting the display effect of the display substrate.

[0054] Optional, such as Figure 1As shown, display area 011 is a rectangular area, including a first boundary 0111, a second boundary 0112, a third boundary 0113, and a fourth boundary 0114. First boundary 0111 is opposite to fourth boundary 0114. Second boundary 0112 is opposite to third boundary 0113. First boundary 0111 intersects with second boundary 0112 and third boundary 0113, respectively, and fourth boundary 0114 intersects with second boundary 0112 and third boundary 0113, respectively (i.e., first boundary 0111, second boundary 0112, fourth boundary 0114, and third boundary 0113 are sequentially connected). Peripheral area 012 extends along the four boundaries of display area 011. For example, peripheral area 012 includes a first peripheral area 0121 extending along first boundary 0111, a second peripheral area 0122 extending along second boundary 0112, a third peripheral area 0123 extending along third boundary 0113, and a fourth peripheral area 0124 extending along fourth boundary 0114. Optionally, peripheral area 012 is shaped as a closed ring surrounding display area 011. Figure 1 The shapes of the display area 011 and the peripheral area 012 shown in the figure are merely exemplary. The shape of the display area 011 may also be circular, elliptical, pentagonal, hexagonal, etc. Correspondingly, the shape of the peripheral area 012 may be a circular ring, an elliptical ring, a pentagonal ring, a hexagonal ring, etc. surrounding the display area 011. Alternatively, the shape of the peripheral area 012 may be a non-enclosed ring that at least partially surrounds the display area 011. The shapes of the display area 011 and the peripheral area 012 are not limited in this embodiment of the application.

[0055] Optional, such as Figure 1 As shown, display trace 02 surrounds the second boundary 0112, third boundary 0113, and fourth boundary 0114 of display area 011, and also surrounds a portion of the first boundary 0111 of display area 011. The orthographic projection of touch trace 04 on base substrate 01 surrounds the second boundary 0112, third boundary 0113, and fourth boundary 0114 of display area 011, and also surrounds a portion of the first boundary 0111 of display area 011. The orthographic projection of shielding structure 03 on base substrate 01 is located in first peripheral region 0121 and extends along first boundary 0111 of display area 011. In embodiments of the present application, a display substrate may have a binding side, which refers to the side of the display substrate used for binding to a circuit board. First peripheral region 0121 is located on the binding side of the display substrate and may correspond to the bottom bezel of a display device based on the display substrate. First peripheral region 0121 may be referred to as the bottom bezel region of the display substrate.

[0056] Optional, such as Figure 1As shown, shielding structure 03 includes a first shielding portion 031 and a second shielding portion 032. The first shielding portion 031 and the second shielding portion 032 may be symmetrical about a first cross-section x of the display substrate. For example, the orthographic projection of the first shielding portion 031 onto the base substrate 01 has the same shape as the orthographic projection of the second shielding portion 032 onto the base substrate 01, and the orthographic projection of the first shielding portion 031 onto the base substrate 01 has the same area as the orthographic projection of the second shielding portion 032 onto the base substrate 01. In other words, the orthographic projections of the first shielding portion 031 onto the base substrate 01 are congruent with the orthographic projections of the second shielding portion 032 onto the base substrate 01. The first cross-section x is perpendicular to the first boundary 0111 of the display area 011, and the intersection of the first cross-section x and the base substrate 01 bisects the first boundary 0111. In other words, the intersection of the first cross-section x and the base substrate 01 perpendicularly bisects the first boundary 0111.

[0057] Optional, such as Figure 1 As shown, the orthographic projection of the first shielding portion 031 on the base substrate 01 is close to the intersection of the first boundary 0111 and the second boundary 0112. The orthographic projection of the second shielding portion 032 on the base substrate 01 is close to the intersection of the first boundary 0111 and the third boundary 0113. The distance between the first shielding portion 031 and the second shielding portion 032 can range from 50 mm to 60 mm. For example Figure 1 As shown, the distance between the first shielding portion 031 and the second shielding portion 032 is k, that is, the value range of k can be 50 mm to 60 mm. For example, k is 54 mm, 55 mm, 56 mm, etc. In the embodiment of the present application, the first shielding portion 031 has a boundary close to the second shielding portion 032 (for example, referred to as the first shielding boundary), and the second shielding portion 032 has a boundary close to the first shielding portion 031 (for example, referred to as the second shielding boundary). The distance k between the first shielding portion 031 and the second shielding portion 032 refers to the distance between the first shielding boundary and the second shielding boundary. In other words, there is a gap between the first shielding portion 031 and the second shielding portion 032, and the distance between the first shielding portion 031 and the second shielding portion 032 refers to the width of the gap.

[0058] Optional, such as Figure 1 and Figure 2As shown, the display substrate also includes a negative power line 05. The negative power line 05 is located on the side of the display trace 02 away from the substrate substrate 01. The positive projection of the negative power line 05 on the substrate substrate 01 is located in the peripheral area 012 and at least partially surrounds the display area 011. For example, the positive projection of the negative power line 05 on the substrate substrate 01 extends around the first boundary 0111, the second boundary 0112, the third boundary 0113 and the fourth boundary 0114 of the display area 011. The shielding structure 03 can be located on the side of the negative power line 05 away from the substrate substrate 01, and the shielding structure 03 is electrically connected to the negative power line 05. The positive projection of the connection position of the shielding structure 03 and the negative power line 05 on the substrate substrate 01 can be located in the first peripheral area 0121. For example, as Figure 2 As shown, negative power line 05 includes a first routing segment 051 and a second routing segment 052. Second routing segment 052 is located on the side of first routing segment 051 away from substrate 01. First routing segment 051 is electrically connected to second routing segment 052, and shielding structure 03 is electrically connected to second routing segment 052, thereby electrically connecting shielding structure 03 to negative power line 05. Shielding structure 03 can be located on the side of second routing segment 052 away from substrate 01, and a portion of shielding structure 03 can overlap the side of second routing segment 052 away from substrate 01, thereby electrically connecting shielding structure 03 to second routing segment 052. Both first routing segment 051 and second routing segment 052 can surround display area 011. An insulating layer can be provided between first routing segment 051 and second routing segment 052. Second routing segment 052 can be electrically connected to first routing segment 051 via a via extending through the insulating layer. For example, a passivation (PVX) layer 08 is provided between the first routing segment 051 and the second routing segment 052 , and the second routing segment 052 is electrically connected to the first routing segment 051 through a via penetrating the PVX layer 08 .

[0059] In the embodiment of the present application, shielding structure 03 is electrically connected to negative power line 05, and the negative power signal in negative power line 05 can be transmitted to shielding structure 03. Under the action of the negative power signal, shielding structure 03 can isolate the display signal transmitted in display trace 02 from the touch signal transmitted in touch trace 04, thereby shielding the display signal transmitted in display trace 02 from interfering with the touch signal transmitted in touch trace 04, and shielding the touch signal transmitted in touch trace 04 from interfering with the display signal transmitted in display trace 02. For example, the electromagnetic waves generated by the negative power signal transmitted in shielding structure 03 can interfere with the propagation of the electromagnetic waves generated by the display signal, causing the electromagnetic waves generated by the display signal to be attenuated and unable to propagate to touch trace 04, thereby preventing the display signal transmitted in display trace 02 from interfering with the touch signal transmitted in touch trace 04. Similarly, the electromagnetic waves generated by the negative power signal transmitted in shielding structure 03 can interfere with the propagation of the electromagnetic waves generated by the touch signal, attenuating the electromagnetic waves generated by the touch signal and preventing them from propagating to display trace 02. This prevents the display signal transmitted in touch trace 04 from interfering with the touch signal transmitted in display trace 02. In other words, the negative power signal can block the display signal transmitted in display trace 02 from the touch signal transmitted in touch trace 04. Furthermore, because the negative power signal is a DC constant voltage signal, while the display signal transmitted in display trace 02 and the touch signal transmitted in touch trace 04 are both AC signals, the DC constant voltage signal has a constant magnitude and is not affected by the AC signal. Therefore, the negative power signal in negative power line 05 is not interfered with by the display signal transmitted in display trace 02 or the touch signal transmitted in touch trace 04.

[0060] In the embodiment of the present application, the orthographic projection of the shielding structure 03 on the substrate substrate 01 at least partially overlaps with the orthographic projection of the negative power line 05 on the substrate substrate 01. As mentioned above, the orthographic projection of the shielding structure 03 on the substrate substrate 01 is located in the first peripheral area 0111. Therefore, the orthographic projection of the shielding structure 03 on the substrate substrate 01 at least partially overlaps with the orthographic projection of the negative power line 05 in the first peripheral area 0111. Optionally, the overlapping area of ​​the orthographic projection of the shielding structure 03 on the substrate substrate 01 and the orthographic projection of the negative power line 05 on the substrate substrate 01 is referred to as the overlapping area of ​​the shielding structure 03 and the negative power line 05. Figure 1As shown, the width of the overlapping area between the shielding structure 03 and the negative power line 05 is c, and c can range from 50 microns to 60 microns. For example, c is 54 microns, 55 microns, 56 microns, etc. Among them, the width c of the overlapping area between the shielding structure 03 and the negative power line 05 is the size of the overlapping area in the direction perpendicular to the first boundary 0111. In the embodiment of the present application, the width of the overlapping area between the shielding structure 03 and the negative power line 05 is controlled within 50 microns to 60 microns. On the one hand, it can reduce the thickness of the peripheral area of ​​the display substrate, facilitating the thinning of the display substrate. On the other hand, it can make the width of the overlapping area between the shielding structure 03 and the negative power line 05 smaller, facilitating the reduction of the width of the lower frame area of ​​the display substrate, and achieving a narrow frame of the display substrate.

[0061] Optionally, the display substrate provided in the embodiment of the present application may be an organic light-emitting diode (OLED) display substrate or a quantum dot light-emitting diode (QLED) display substrate. Figure 1 and Figure 2 As shown, the display substrate further includes a cathode 06. The cathode 06 is located on the side of the shielding structure 03 away from the base substrate 01. The cathode 06 is electrically connected to the negative power line 05. The touch trace 04 can be located on the side of the cathode 06 away from the base substrate 01. The cathode 06 can be a whole-layer structure or a patterned structure. The embodiment of the present application takes the cathode 06 as a whole-layer structure as an example. There can be one or more connection positions between the cathode 06 and the negative power line 05. The orthographic projection of the connection position between the cathode 06 and the negative power line 05 on the base substrate 01 can be located in the second peripheral area 0122 and / or the third peripheral area 0123. For example, there is an insulating layer between the cathode 06 and the negative power line 05, and the insulating layer has a plurality of connection holes. The orthographic projections of the plurality of connection holes on the base substrate 01 are located in the second peripheral area 0122 and the third peripheral area 0123. The cathode 06 is electrically connected to the negative power line 05 through the plurality of connection holes.

[0062] In the embodiment of the present application, the orthographic projection of the shielding structure 03 on the base substrate 01 at least partially overlaps with the orthographic projection of the cathode 06 on the base substrate 01. As previously mentioned, the orthographic projection of the shielding structure 03 on the base substrate 01 is located in the first peripheral area 0111. Therefore, the orthographic projection of the shielding structure 03 on the base substrate 01 at least partially overlaps with the orthographic projection of the cathode 06 in the first peripheral area 0111. Optionally, the overlapping area of ​​the orthographic projection of the shielding structure 03 on the base substrate 01 and the orthographic projection of the cathode 06 on the base substrate 01 is referred to as the overlapping area of ​​the shielding structure 03 and the cathode 06. Figure 1As shown, the width of the overlapping area between the shielding structure 03 and the cathode 06 is b, and b can range from 20 microns to 25 microns. For example, b is 22 microns, 23 microns, 24 microns, etc. Among them, the width b of the overlapping area between the shielding structure 03 and the cathode 06 is the size of the overlapping area in the direction perpendicular to the first boundary 0111. In the embodiment of the present application, the width of the overlapping area between the shielding structure 03 and the cathode 06 is controlled within 20 microns to 25 microns. On the one hand, it can reduce the thickness of the peripheral area of ​​the display substrate, facilitating the thinning of the display substrate. On the other hand, it can make the width of the overlapping area between the shielding structure 03 and the negative power line 05 smaller, facilitating the reduction of the width of the lower frame area of ​​the display substrate, and realizing a narrow frame of the display substrate.

[0063] In the embodiment of the present application, cathode 06 is electrically connected to negative power line 05, so the negative power signal in negative power line 05 can be transmitted to cathode 06. Since the negative power signal is a DC constant voltage signal, the display signal transmitted in display trace 02 and the touch signal transmitted in touch trace 04 are both AC signals. The DC constant voltage signal has a constant magnitude and is not affected by the AC signal. Therefore, the negative power signal transmitted in cathode 06 is not interfered with by the display signal transmitted in display trace 02 or the touch signal transmitted in touch trace 04.

[0064] As can be seen from the above description, in a direction perpendicular to the surface of the display substrate, the negative power line 05 and the cathode 06 are both located between the display trace 02 and the touch trace 04, and the negative power signal in the negative power line 05 and the negative power signal in the cathode 06 are not interfered with by the display signal in the display trace 02 and the touch signal in the touch trace 04. Therefore, by designing the structure and position of the negative power line 05 and the structure and position of the cathode 06, the orthographic projection of the negative power line 05 and / or the cathode 06 on the base substrate 01 can be made to at least partially overlap with the orthographic projection of the display trace 02 and the orthographic projection of the touch trace 04 on the base substrate 01. In this way, the negative power line 05 and / or the cathode 06 can also serve as a shielding structure to shield the display signal in the display trace 02 and the touch signal in the touch trace 04 from interfering with each other. For example, the orthographic projections of the negative power line 05, the display line 02, and the touch line 04 on the base substrate 01 at least partially overlap, and the orthographic projections of the cathode 06, the display line 02, and the touch line 04 on the base substrate 01 at least partially overlap. Figure 1As shown, the orthographic projections of the negative power line 05, the display trace 02 and the touch trace 04 in the second peripheral area 0112 partially overlap, and the orthographic projections of the cathode 06, the display trace 02 and the touch trace 04 in the second peripheral area 0112 partially overlap; the orthographic projections of the negative power line 05, the display trace 02 and the touch trace 04 in the third peripheral area 0113 partially overlap, and the orthographic projections of the cathode 06, the display trace 02 and the touch trace 04 in the third peripheral area 0113 partially overlap; the orthographic projections of the negative power line 05, the display trace 02 and the touch trace 04 in the fourth peripheral area 0114 partially overlap, and the orthographic projections of the cathode 06, the display trace 02 and the touch trace 04 in the fourth peripheral area 0114 partially overlap. In the second peripheral area 0112, the third peripheral area 0113, and the fourth peripheral area 0114, the negative power line 05 and the cathode 06 can shield the display signal in the display trace 02 from the touch signal in the touch trace 04 from interfering with each other. In this embodiment of the present application, the negative power line 05 can both transmit the negative power signal and shield against signal interference, thus achieving multiplexing of the negative power line 05. Similarly, the cathode 06 can both transmit the negative power signal and shield against signal interference, thus achieving multiplexing of the cathode 06.

[0065] Optional, such as Figure 1 and Figure 2 As shown, the display substrate further includes a positive power line 07. Positive power line 07 is located on the side of display trace 02 away from base substrate 01. The orthographic projection of positive power line 07 on base substrate 01 is located in peripheral region 012 and at least partially surrounds display region 011. For example, positive power line 07 and first trace segment 051 of negative power line 05 are located on the same layer, and the orthographic projection of positive power line 07 on base substrate 01 is located in first peripheral region 0121. The display substrate includes subpixels located in display region 011, and positive power line 07 can be electrically connected to the subpixels to apply positive power signals to the subpixels.

[0066] In the embodiment of the present application, the orthographic projection of the shielding structure 03 on the substrate substrate 01 and the orthographic projection of the positive power line 07 on the substrate substrate 01 at least partially overlap. As mentioned above, the orthographic projection of the shielding structure 03 on the substrate substrate 01 is located in the first peripheral area 0111. Therefore, the orthographic projection of the shielding structure 03 on the substrate substrate 01 and the orthographic projection of the positive power line 07 in the first peripheral area 0111 at least partially overlap. Optionally, the orthographic projection of the shielding structure 03 on the substrate substrate 01 and the orthographic projection of the positive power line 07 on the substrate substrate 01 are referred to as the overlapping area of ​​the shielding structure 03 and the positive power line 07. Figure 1As shown, the width of the overlapping area between the shielding structure 03 and the positive power line 07 is a, and a can range from 4 microns to 6 microns. For example, a is 4.5 microns, 5 microns, 5.5 microns, etc. Among them, the width a of the overlapping area between the shielding structure 03 and the positive power line 07 is the size of the overlapping area in the direction perpendicular to the first boundary 0111. In the embodiment of the present application, the width of the overlapping area between the shielding structure 03 and the positive power line 07 is controlled within 4 microns to 6 microns. On the one hand, the thickness of the display substrate can be reduced, which facilitates the realization of a lightweight and thin display substrate. On the other hand, the width of the overlapping area between the shielding structure 03 and the positive power line 07 can be made smaller, which facilitates reducing the width of the lower frame area of ​​the display substrate and realizing a narrow frame of the display substrate.

[0067] In the embodiment of the present application, the orthographic projection of shielding structure 03 on substrate 01 is located in first peripheral region 0121. The width d of the orthographic projection of shielding structure 03 on substrate 01 can range from 105 microns to 115 microns, for example, d is 108 microns, 110 microns, 112 microns, etc. The orthographic projection of negative power line 05 on substrate 01 is at least partially located in first peripheral region 0121. The width of the orthographic projection of negative power line 05 in first peripheral region 0121 can range from 145 microns to 155 microns, for example, 148 microns, 150 microns, 152 microns, etc. The orthographic projection of positive power line 07 on substrate 01 is at least partially located in first peripheral region 0121. The width of the orthographic projection of positive power line 07 in first peripheral region 0121 can range from 95 microns to 105 microns, for example, 98 microns, 100 microns, 102 microns, etc. The width of the orthographic projection of the shielding structure 03 on the base substrate 01 is the dimension of the orthographic projection in a direction perpendicular to the first boundary 0111. The width of the orthographic projection of the negative power line 05 in the first peripheral region 0121 is the dimension of the orthographic projection in a direction perpendicular to the first boundary 0111. The width of the orthographic projection of the positive power line 07 in the first peripheral region 0121 is the dimension of the orthographic projection in a direction perpendicular to the first boundary 0111. In this embodiment of the present application, the width of the orthographic projection of the shielding structure 03 on the base substrate 01 is controlled within a range of 105 to 115 microns, the width of the orthographic projection of the negative power line 05 in the first peripheral region 0121 is controlled within a range of 145 to 155 microns, and the width of the orthographic projection of the positive power line 07 in the first peripheral region 0121 is controlled within a range of 95 to 105 microns. This facilitates reducing the width of the lower border region of the display substrate and achieving a narrow border for the display substrate. In addition, by setting the width of the positive projection part of the positive power line 07 in the first peripheral area 0121 to be greater than 95 microns, the impedance of the positive power line 07 can be reduced, the loss of the positive power signal transmitted by the positive power line 07 can be reduced, and the ability of the positive power line 07 to transmit the positive power signal is improved, which helps to ensure the uniformity of the brightness of the picture displayed by the display substrate.

[0068] Optionally, the display substrate provided in the embodiments of the present application further includes a barrier wall. The orthographic projection of the barrier wall on the base substrate 01 can be located in the peripheral region 012 and surround the display region 011. The orthographic projection of the shielding structure 03 on the base substrate 01 can be located between the display region 011 and the orthographic projection of the barrier wall on the base substrate 01. The barrier wall is used to block external water and oxygen from entering the display substrate, preventing the light-emitting units in the sub-pixels within the display substrate from reacting with the water and oxygen and corroding.

[0069] In an embodiment of the present application, the distance between the orthographic projection of the shielding structure 03 on the substrate substrate 01 and the orthographic projection of the blocking wall on the substrate substrate 01 may be in the range of 12 microns to 16 microns. For example, the distance between the orthographic projection of the shielding structure 03 on the substrate substrate 01 and the orthographic projection of the blocking wall on the substrate substrate 01 is 13 microns, 14 microns or 15 microns. Optionally, the display substrate includes a plurality of blocking walls, and the plurality of blocking walls may be distributed around the display area 011 in a direction away from the display area 011. In this case, the orthographic projection of the shielding structure 03 on the substrate substrate 01 may be located between the display area 011 and the orthographic projection of the blocking wall closest to the display area 011 on the substrate substrate 01, and the distance between the orthographic projection of the shielding structure 03 on the substrate substrate 01 and the orthographic projection of the blocking wall closest to the display area 011 on the substrate substrate 01 is in the range of 12 microns to 16 microns. For example, as Figure 2 As shown, the display substrate includes a first barrier wall 091 and a second barrier wall 092. The first barrier wall 091 and the second barrier wall 092 are arranged around the display area 011, away from the display area 011. The orthographic projection of the second barrier wall 092 on the base substrate 01 is located between the orthographic projection of the first barrier wall 091 on the base substrate 01 and the edge of the display substrate. In other words, the first barrier wall 091 is the barrier wall closest to the display area 011. The orthographic projection of the shielding structure 03 on the base substrate 01 is located between the display area 011 and the orthographic projection of the first barrier wall 091 on the base substrate 01. The distance between the orthographic projection of the shielding structure 03 on the base substrate 01 and the orthographic projection of the first barrier wall 091 on the base substrate 01 ranges from 12 microns to 16 microns. In the embodiment of the present application, the distance between the orthographic projection of the shielding structure 03 on the base substrate 01 and the orthographic projection of the blocking wall on the base substrate 01 is controlled within 12 microns to 16 microns, which can facilitate reducing the width of the lower frame area of ​​the display substrate and realize a narrow frame of the display substrate.

[0070] Figure 3 yes Figure 1 The cross-sectional view of the BB portion of the display substrate is shown as Figure 3As shown, the display substrate also includes a plurality of sub-pixels 10 for implementing the display function of the display substrate. The sub-pixels 10 may include a switching unit 101 and a light-emitting unit 102. The switching unit 101 is used to control the light-emitting unit 102 to emit light. The switching unit 101 may include a gate 1011, an active layer 1012, a source 1013, and a drain 1014. The light-emitting unit 102 may include an anode 1021, a light-emitting layer 1022, and a cathode 06 stacked in sequence. The drain 1014 of the switching unit 101 is electrically connected to the anode 1021 of the light-emitting unit 102, and the source 1013 of the switching unit 101 may be electrically connected to the positive power line 07. The first routing segment 051 of the negative power line 05, the positive power line 07, the source 1013, and the drain 1014 may be located on the same layer. In an embodiment of the present application, the display trace 02 refers to a trace that provides a display signal to the sub-pixel 10. The display trace 02 may include a signal line directly connected to the sub-pixel 10, or may include a signal line indirectly connected to the sub-pixel 10. For example, the display substrate includes a GOA circuit, and the display trace 02 may include an input trace of the GOA circuit, an output trace of the GOA circuit, and the like. Among them, the input trace of the GOA circuit and the output trace of the GOA circuit may be located on the same layer as the gate 1011. The input trace of the GOA circuit may be used for the GOA circuit to receive a timing control signal, and the output trace of the GOA circuit may be used for the GOA circuit to provide a gate drive signal to the switching unit 101. Both the timing control signal and the gate drive signal may be the display signal described in the embodiment of the present application. The embodiment of the present application takes the display trace 02 as an input trace of the GOA circuit or an output trace of the GOA circuit as an example, combined with Figure 2 and Figure 3 The display wiring 02 is located on the same layer as the gate 1011. The display wiring 02 may also include other wirings for providing display signals to the sub-pixels 10, which is not limited in this embodiment of the present application.

[0071] In an optional embodiment, as Figure 2 and Figure 3As shown, the display substrate provided in the embodiment of the present application further includes a first planarization (PLN) layer 11, and the first PLN layer 11 is located on the side of the second routing segment 052 away from the base substrate 01. Typically, the PLN layer will extend to the edge of the base substrate and be flush with the side of the base substrate, but this can easily lead to a larger thickness in the peripheral area of ​​the display substrate. In the embodiment of the present application, when manufacturing the first PLN layer 11, the first PLN layer 11 can be patterned to remove the portion of the first PLN layer 11 located in the peripheral area 012. For example, at least a portion of the first PLN layer 11 located in the first peripheral area 0121 is removed to expose the second routing segment 052 of the negative power line 05. This can, on the one hand, reduce the thickness of the peripheral area of ​​the display substrate, and on the other hand, allow at least a portion of the shielding structure 03 to be directly superimposed on the side of the second routing segment 052 away from the base substrate 01, thereby achieving electrical connection between the shielding structure 03 and the second routing segment 052. For example Figure 2 As shown, the orthographic projection of the edge of the first PLN layer 11 on the substrate 01 is located inside the substrate 01, the orthographic projection of the first PLN layer 11 on the substrate 10 and the orthographic projection of the second routing segment 052 on the substrate 10 do not at least partially overlap, and a partial area of ​​the shielding structure 03 is superimposed on the side of the second routing segment 052 away from the substrate 01.

[0072] In an optional embodiment, as Figure 2 and Figure 3 As shown, the display substrate also includes a gate insulator (GI) layer 12, an interlayer dielectric (ILD) layer 13, a second PLN layer 14, a pixel definition layer (PDL) 15, and a cathode protection layer (CPL) 16. The GI layer 12 is located between the gate 1011 and the active layer 1012. The ILD layer 13 can be located between the active layer 1012 and the source and drain layer (referring to the layer where the source 1013 and the drain 1014 are located). The second PLN layer 14 is located on the side of the ILD layer 13 away from the base substrate 01. The shielding structure 03 is located between the first PLN layer 11 and the second PLN layer 14. The second PLN layer 14 can not only play a planarizing role, but also protect the shielding structure 03 and insulate it from other conductive structures. The PDL 15 is located on a side of the second PLN layer 14 away from the base substrate 01 . The PDL 15 may include a pixel opening, and the light emitting unit 102 may be located in the pixel opening. The CPL 16 is located on a side of the cathode 06 away from the base substrate 01 to protect the cathode 06 .

[0073] In an optional embodiment, as Figure 3 As shown, the display substrate further includes touch electrodes 17, which are electrically connected to touch traces 04. Touch traces 04 are used to provide touch signals to touch electrodes 17, enabling touch electrodes 17 to implement touch functions. Touch electrodes 17 and touch traces 04 can be located on the same layer or on different layers. For example, when a touch object (e.g., a finger) touches the display substrate, the touch signal applied to touch electrodes 17 changes. The touch position can be determined based on the change in the touch signal, thereby implementing the touch function of the display substrate.

[0074] Optional, such as Figure 2 and Figure 3 As shown, the display substrate further includes an encapsulation structure 18. The encapsulation structure 18 is located on the side of the CPL 16 away from the base substrate 01, and the touch trace 04 is located on the side of the encapsulation structure 18 away from the base substrate 01. The encapsulation structure 18 is used to encapsulate the light-emitting unit 102 in the display area 011 to prevent external water and oxygen from entering the interior of the display substrate and corroding the light-emitting unit 102. The encapsulation structure 18 can be a thin film encapsulation structure, which includes alternating inorganic layers and organic layers. For example Figure 2 and Figure 3 As shown, the encapsulation structure 18 includes a first inorganic layer 181, an organic layer 182, and a second inorganic layer 183 stacked sequentially in a direction away from the base substrate 01. The first inorganic layer 181 covers the surface of the CPL 16 away from the base substrate 01. The organic layer 182 is located on the surface of the first inorganic layer 181 away from the base substrate 01. The orthographic projection of the organic layer 182 on the base substrate 01 is located within the orthographic projection of the first inorganic layer 181 on the base substrate 01. The second inorganic layer 183 covers the organic layer 182 and the portion of the first inorganic layer 181 not covered by the organic layer 182.

[0075] In the embodiment of the present application, the height of the second barrier wall 092 can be greater than the height of the first barrier wall 091 to ensure the water and oxygen barrier effect of the first barrier wall 091 and the second barrier wall 092. For example, the first barrier wall 091 and the second barrier wall 092 are both located on the side of the second trace segment 052 away from the base substrate 01, and both the first barrier wall 091 and the second barrier wall 092 have a multi-layer structure. For example, the first barrier wall 091 is composed of a first barrier sublayer, a second barrier sublayer, and a third barrier sublayer stacked in a direction away from the base substrate 01, and the second barrier wall 092 is composed of a fourth barrier sublayer, a fifth barrier sublayer, a sixth barrier sublayer, and a seventh barrier sublayer stacked in a direction away from the base substrate 01. The first and fourth blocking sublayers may be located on the same layer as the PDL 15 , the second and sixth blocking sublayers may be located on the same layer as the first inorganic layer 181 , and the third and seventh blocking sublayers may be located on the same layer as the second inorganic layer 183 .

[0076] Figures 1 to 3 The structure of the display substrate is shown only as an example. Figures 1 to 3 In addition to the structure shown, the display substrate may also include other structures. For example, the display substrate may further include a polyimide (PI) layer located between the base substrate 01 and the display trace 02, and a buffer layer located between the PI layer and the display trace 02. This embodiment of the application does not limit the structure of the display substrate.

[0077] To sum up, the display substrate provided in the embodiment of the present application includes a shielding structure, display wiring and touch wiring. The shielding structure is located between the display wiring and the touch wiring, and the orthographic projections of the display wiring, the shielding structure and the touch wiring on the base substrate at least partially overlap. Therefore, the shielding structure can shield the mutual interference between the display signal transmitted in the display wiring and the touch signal transmitted in the touch wiring, thereby preventing the display signal transmitted in the display wiring from affecting the touch effect of the display substrate, and preventing the touch signal transmitted in the touch wiring from affecting the display effect of the display substrate.

[0078] The above is an introduction to the display substrate embodiments of the present application. The following describes a method for manufacturing the display substrate. The manufacturing method and manufacturing principle of the display substrate can be found in the descriptions of the embodiments below.

[0079] Please refer to Figure 4 , which shows a flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application. The method for manufacturing a display substrate can be used to manufacture the above-mentioned display substrate. The method comprises the following steps:

[0080] In S401 , a base substrate is provided, wherein the base substrate includes a display area and a peripheral area at least partially surrounding the display area.

[0081] In S402, a display trace, a shielding structure, and a touch trace are sequentially formed on the base substrate, wherein the display trace is located in the peripheral area and at least partially surrounds the display area, the orthographic projection of the shielding structure on the base substrate is located in the peripheral area, the orthographic projection of the touch trace on the base substrate is located in the peripheral area and at least partially surrounds the display area, and the orthographic projections of the display trace, the shielding structure, and the touch trace on the base substrate at least partially overlap.

[0082] In summary, the display substrate manufacturing method provided by the present application includes a shielding structure, display wiring, and touch wiring. The shielding structure is located between the display wiring and the touch wiring, and the orthographic projections of the display wiring, shielding structure, and touch wiring on the base substrate at least partially overlap. Therefore, the shielding structure can shield the display signal transmitted in the display wiring from interfering with the touch signal transmitted in the touch wiring, thereby preventing the display signal transmitted in the display wiring from affecting the touch effect of the display substrate, and also preventing the touch signal transmitted in the touch wiring from affecting the display effect of the display substrate.

[0083] Please refer to Figure 5 , which shows a flow chart of another method for manufacturing a display substrate provided by an embodiment of the present application. The method for manufacturing a display substrate can be used to manufacture the above-mentioned display substrate. Figure 5 As shown, the method includes the following steps S501 to S506. Figure 5 In the illustrated embodiment, only the relevant drawings of a portion of the peripheral area (eg, the first peripheral area) are shown for the sake of simplicity.

[0084] In S501 , a base substrate is provided, wherein the base substrate includes a display area and a peripheral area at least partially surrounding the display area.

[0085] The substrate may be a rigid substrate made of a material having a certain degree of rigidity, such as glass, quartz, or transparent resin, for example, an epoxy resin substrate. Alternatively, the substrate may be a flexible substrate made of a flexible material such as polyimide (PI).

[0086] like Figure 1As shown, base substrate 01 includes a display area 011 and a peripheral area 012 surrounding display area 011. Display area 011 includes a first boundary 0111, a second boundary 0112, a third boundary 0113, and a fourth boundary 0114. Peripheral area 012 includes a first peripheral area 0121 extending along first boundary 0111, a second peripheral area 0122 extending along second boundary 0112, a third peripheral area 0123 extending along third boundary 0113, and a fourth peripheral area 0124 extending along fourth boundary 0114.

[0087] In S502 , a display trace is formed on the base substrate, where the display trace is located in the peripheral area and at least partially surrounds the display area.

[0088] Figure 6 FIG2 is a schematic diagram of an embodiment of the present application showing a display trace 02 formed on a base substrate 01. The display trace 02 may be located in a peripheral region 012 of the base substrate 01 and at least partially surround a display area 011. For example, the display trace 02 surrounds a second boundary 0112, a third boundary 0113, and a fourth boundary 0114 of the display area 011, and also surrounds a portion of a first boundary 0111 of the display area 011.

[0089] The display traces 02 may be made of metal. For example, a metal layer is formed on the base substrate 01 and the metal layer is processed through a single patterning process to obtain the display traces 02 .

[0090] In the embodiment of the present application, the gate 1011 in the switch unit 101 and the display trace 02 can be located in the same layer. While the display trace 02 is formed in the peripheral area 012, the gate 1011 can also be formed in the display area 011. The embodiment of the present application does not limit this.

[0091] In S503, a negative power line and a positive power line are formed on a side of the display line away from the base substrate, the positive power line's positive projection on the base substrate is located in the peripheral area and at least partially surrounds the display area, and the positive power line's positive projection on the base substrate is located in the peripheral area and at least partially surrounds the display area.

[0092] Figure 7This is a schematic diagram provided by an embodiment of the present application after a negative power line 05 and a positive power line 07 are formed on the side of the display wiring 02 away from the base substrate 01. The positive projection of the negative power line 05 on the base substrate 01 is located in the peripheral area 012 and at least partially surrounds the display area 011. The positive projection of the positive power line 07 on the base substrate 01 is located in the peripheral area 012 and at least partially surrounds the display area 011. For example, the positive projection of the negative power line 05 on the base substrate 01 extends around the first boundary 0111, the second boundary 0112, the third boundary 0113 and the fourth boundary 0114 of the display area 011. The positive projection of the positive power line 07 on the base substrate 01 is located in the first peripheral area 0121. As shown in FIG. Figure 7 As shown, negative power line 05 includes a first routing segment 051 and a second routing segment 052. Second routing segment 052 is located on the side of first routing segment 051 away from substrate 01. A PVX layer 08 is located between first and second routing segments 051 and 052. Second routing segment 052 is electrically connected to first routing segment 051 through vias in PVX layer 08. Positive power line 07 is located on the same layer as first routing segment 051.

[0093] The negative power line 05 and the positive power line 07 can both be made of metal. For example, forming the negative power line 05 and the positive power line 07 on the side of the display trace 02 away from the base substrate 01 includes sequentially forming a first metal layer, a PVX layer 08, and a second metal layer on the side of the display trace 02 away from the base substrate 01. The first metal layer includes a first trace segment 051 and the positive power line 07. The second metal layer includes a second trace segment 052. The PVX layer 08 has a via, through which the second trace segment 052 is electrically connected to the first trace segment 051. The first trace segment 051 and the second trace segment 052 constitute the negative power line 05.

[0094] In the embodiment of the present application, the source 1013 and drain 1014 in the switch unit 101 can be located in the same layer as the first routing segment 051. While the first routing segment 051 and the positive power line 07 are formed in the peripheral region 012, the source 1013 and drain 1014 can also be formed in the display region 011. For example, the first metal layer also includes the source 1013 and drain 1014. Furthermore, the sub-pixel 10 can further include a connecting electrode for connecting the switch unit 101 and the light-emitting unit 102. The connecting electrode and the second routing segment 052 can be located in the same layer. While the second routing segment 052 is formed in the peripheral region 012, the connecting electrode can also be formed in the display region 011. For example, the second metal layer also includes the connecting electrode.

[0095] Combine Figure 2 、 Figure 3 and Figure 7As shown, the display substrate further includes a GI layer 12, an active layer 1012, and an ILD layer 13, which are sequentially located between the layer where the display trace 02 is located and the layer where the first trace segment 051 is located, along a direction away from the base substrate 10. Before executing S503, the GI layer 12, the active layer 1012, and the ILD layer 13 can be sequentially formed on the side of the display trace 02 away from the base substrate 01. Subsequently, a negative power line 05 and a positive power line 07 are formed on the side of the ILD layer 13 away from the base substrate 01, although this is not limited in this embodiment of the present application.

[0096] In S504 , a shielding structure is formed on a side of the negative power line and the positive power line away from the base substrate. The orthographic projection of the shielding structure on the base substrate is located in the peripheral area. The shielding structure is electrically connected to the negative power line.

[0097] Figure 8 This is a schematic diagram of an embodiment of the present application, wherein a shielding structure 03 is formed on the side of the negative power line 05 and the positive power line 07 away from the base substrate 01. The orthographic projection of the shielding structure 03 on the base substrate 10 is located within the peripheral area 012. For example, the orthographic projection of the shielding structure 03 on the base substrate 10 is located within the first peripheral area 0121. In this embodiment of the present application, the shielding structure 03 includes a first shielding portion 031 and a second shielding portion 032. The orthographic projection of the first shielding portion 031 on the base substrate 01 is located near the intersection of the first boundary 0111 and the second boundary 0112. The orthographic projection of the second shielding portion 032 on the base substrate 01 is located near the intersection of the first boundary 0111 and the third boundary 0113. Both the first shielding portion 031 and the second shielding portion 032 are electrically connected to the negative power line 05. For example, the first shielding portion 031 and the second shielding portion 032 are respectively superimposed on the side of the second trace segment 051 of the negative power line 05 away from the base substrate 01.

[0098] The material of the shielding structure 03 is a metal material or a metal oxide material, for example, the material of the shielding structure 03 is indium tin oxide (ITO). For example, an ITO material layer is formed on the side of the negative power line 05 and the positive power line 07 away from the base substrate 01 (for example, on the side of the second metal layer away from the base substrate 10). The ITO layer is processed through a single patterning process to obtain a first shielding portion 031 and a second shielding portion 032. The first shielding portion 031 and the second shielding portion 032 are respectively superimposed on the side of the second trace segment 051 away from the base substrate 01. The first shielding portion 031 and the second shielding portion 032 constitute the shielding structure 03.

[0099] Combine Figure 2 、 Figure 3 and Figure 8As shown, the display substrate further includes a first PLN layer 11 located between the second metal layer and the shielding structure 03. Before executing S504, the first PLN layer 11 can be formed on the side of the second metal layer away from the base substrate 01. Then, the shielding structure 03 is formed on the side of the first PLN layer 11 away from the base substrate 01, which is not limited in this embodiment of the present application.

[0100] In S505 , a cathode is formed on a side of the shielding structure away from the base substrate. The cathode is electrically connected to a negative power line. The orthographic projection of the shielding structure on the base substrate at least partially overlaps with the orthographic projection of the cathode on the base substrate.

[0101] Figure 9 This is a schematic diagram of an embodiment of the present application, wherein a cathode 06 is formed on a side of a shielding structure 03 away from a base substrate 01. Cathode 06 is electrically connected to a negative power line 05. The orthographic projection of the connection between cathode 06 and negative power line 05 on base substrate 01 can be located in second peripheral region 0122 and / or third peripheral region 0123. The orthographic projection of shielding structure 03 on base substrate 01 at least partially overlaps with the orthographic projection of cathode 06 on base substrate 01. For example, the orthographic projection of shielding structure 03 on base substrate 01 at least partially overlaps with the orthographic projection of cathode 06 on first peripheral region 0111.

[0102] The cathode 06 may be made of a transparent conductive material, such as ITO. For example, an ITO layer is formed on the side of the shielding structure 03 away from the base substrate 01 , and the cathode 06 is obtained by processing the ITO layer through a single patterning process.

[0103] Combine Figure 2 、 Figure 3 and Figure 9 As shown, the display substrate further includes a second PLN layer 14, an anode 1021, a PDL 15, and a light-emitting layer 1022 located between the layer where the shielding structure 03 is located and the cathode 06. Before executing S505, the second PLN layer 14, the anode 1021, the PDL 15, and the light-emitting layer 1022 can be formed in sequence on the side of the shielding structure 03 away from the base substrate 01. Then, the cathode 06 is formed on the side of the light-emitting layer 1022 away from the base substrate 01, although this embodiment of the present application is not limited thereto.

[0104] In S506, a touch trace is formed on a side of the cathode away from the base substrate, wherein the orthographic projection of the touch trace on the base substrate is located in the peripheral area and at least partially surrounds the display area. The orthographic projections of the display trace, the shielding structure, and the touch trace on the base substrate at least partially overlap.

[0105] The schematic diagram after the touch trace 04 is formed on the side of the cathode 06 away from the substrate 01 can be referred to Figure 2 The orthographic projection of the touch trace 04 on the base substrate 01 is located in the peripheral area 012 and at least partially surrounds the display area 011. The orthographic projections of the display trace 02, the shielding structure 03, and the touch trace 04 on the base substrate 01 at least partially overlap. For example, the orthographic projection of the touch trace 04 on the base substrate 01 surrounds the second boundary 0112, the third boundary 0113, and the fourth boundary 0114 of the display area 011, and also surrounds a portion of the first boundary 0111 of the display area 011. The orthographic projections of the display trace 02, the shielding structure 03, and the touch trace 04 on the first peripheral area 0111 of the base substrate 01 partially overlap.

[0106] The material of the touch trace 04 can be a transparent conductive material, for example, ITO. For example, an ITO material layer is formed on the side of the cathode 06 away from the base substrate 01, and the touch trace 04 is obtained by processing the ITO material layer through a single patterning process.

[0107] In the embodiment of the present application, the touch electrodes 17 and the touch traces 04 in the display substrate can be located in the same layer. While the touch traces 04 are formed in the peripheral area 012 , the touch electrodes 17 can also be formed in the display area 011 . This embodiment of the present application does not limit this.

[0108] like Figure 2 and Figure 3 As shown, the display substrate further includes a CPL 16 and an encapsulation structure 18, which are sequentially located between the cathode 06 and the layer where the touch trace 04 is located, in a direction away from the base substrate 10. Before executing S506, the CPL 16 and the encapsulation structure 18 can be sequentially formed on the side of the cathode 06 away from the base substrate 01. Then, the touch trace 04 is formed on the side of the encapsulation structure 18 away from the base substrate 01.

[0109] In the embodiment of the present application, during the manufacturing process of the display substrate, a barrier wall may be formed. The orthographic projection of the barrier wall on the base substrate 01 is located in the peripheral region 012 of the base substrate 01 and surrounds the display region 011. For example, during the manufacturing process of the display substrate, a first barrier wall 091 and a second barrier wall 092 are formed. The orthographic projection of the second barrier wall 092 on the base substrate 01 is located between the orthographic projection of the first barrier wall 091 on the base substrate 01 and the edge of the display substrate. The first barrier wall 091 is composed of a first barrier sublayer, a second barrier sublayer, and a third barrier sublayer, stacked along a distance from the base substrate 01. The second barrier wall 092 is composed of a fourth barrier sublayer, a fifth barrier sublayer, a sixth barrier sublayer, and a seventh barrier sublayer, stacked along a distance from the base substrate 01. The first and fourth barrier sublayers may be located on the same layer as the PDL 15. The second barrier sublayer and the sixth barrier sublayer can be located on the same layer as the first inorganic layer 181 of the encapsulation structure 18, and the third barrier sublayer and the seventh barrier sublayer can be located on the same layer as the second inorganic layer 183 of the encapsulation structure 18, which is not limited in this embodiment of the present application.

[0110] In summary, the display substrate manufacturing method provided by the present application includes a shielding structure, display wiring, and touch wiring. The shielding structure is located between the display wiring and the touch wiring, and the orthographic projections of the display wiring, shielding structure, and touch wiring on the base substrate at least partially overlap. Therefore, the shielding structure can shield the display signal transmitted in the display wiring from interfering with the touch signal transmitted in the touch wiring, thereby preventing the display signal transmitted in the display wiring from affecting the touch effect of the display substrate, and also preventing the touch signal transmitted in the touch wiring from affecting the display effect of the display substrate.

[0111] In the embodiment of the present application, the process for forming the material layer may be deposition, magnetron sputtering, thermal evaporation, or other processes, such as plasma-enhanced chemical vapor deposition (PECVD). For example, in step S502, a metal material layer may be formed on the substrate 01 by deposition, magnetron sputtering, thermal evaporation, or other processes. In addition, the one-time patterning process involved in the embodiment of the present application includes photoresist coating, exposure, development, etching and photoresist stripping. The material layer (e.g., metal material layer) is processed by the one-time patterning process, including: coating a layer of photoresist on the material layer (e.g., metal material layer) to form a photoresist layer, exposing the photoresist layer using a mask so that the photoresist layer forms a completely exposed area and a non-exposed area, then using a development process to completely remove the photoresist in the completely exposed area and retain all the photoresist in the non-exposed area, etching the area corresponding to the completely exposed area on the material layer (e.g., metal material layer) using an etching process, and finally stripping the photoresist in the non-exposed area to obtain the corresponding structure (e.g., display trace 02). Here, the photoresist is a positive photoresist as an example for explanation. When the photoresist is a negative photoresist, the process of the one-time patterning process can refer to the description in this paragraph, and the embodiment of the present application will not be repeated here.

[0112] The order of steps in the method for manufacturing a display substrate provided in the embodiment of the present application can be appropriately adjusted, and the steps can be increased or decreased accordingly according to the circumstances. Any technician familiar with this technical field can easily think of a method of change within the technical scope disclosed in this application, and the method should be covered within the scope of protection of this application, so it will not be repeated here.

[0113] An embodiment of the present application also provides a display device, which includes the display substrate provided by the above embodiment. The display device can be any product or component with a display function, such as a smart phone, tablet computer, smart bracelet, smart watch, laptop computer, digital photo frame or navigator.

[0114] In this application, the terms "first," "second," "third," "fourth," etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" refers to one or more, and "plurality" refers to two or more. Unless otherwise expressly defined, the same applies to the term "at least one." The term "electrically connected" means that the connection can transfer charge, but does not necessarily require charge transfer. For example, the electrical connection between A and B means that A and B are connected and charge can be transferred between A and B, but does not necessarily require charge transfer between A and B.

[0115] It should be noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or intervening layers may exist. Furthermore, it will be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or one or more intervening layers or elements may exist.

[0116] The above is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display substrate, characterized in that: The display substrate has a binding side, where the binding side is a side where the display substrate is bound to the circuit board. The display substrate includes: A base substrate, comprising a display area and a peripheral area at least partially surrounding the display area, wherein the display area comprises a first boundary, and the peripheral area comprises a first peripheral area extending along the first boundary; a display trace located in the peripheral area and at least partially surrounding the display area; a shielding structure located on a side of the display trace away from the base substrate, the orthographic projection of the shielding structure on the base substrate located in the first peripheral region and extending along the first boundary, the first peripheral region being located on the binding side of the display substrate; the shielding structure comprising a first shielding portion and a second shielding portion, a gap being defined between the first shielding portion and the second shielding portion, the first shielding portion and the second shielding portion being symmetrical about a first cross-section of the display substrate, the first cross-section being perpendicular to the first boundary, and an intersection line of the first cross-section and the base substrate bisecting the first boundary; a touch line located on a side of the shielding structure away from the base substrate, wherein an orthographic projection of the touch line on the base substrate is located in the peripheral area and at least partially surrounds the display area; The orthographic projections of the display wiring, the shielding structure and the touch wiring on the base substrate at least partially overlap.

2. The display substrate according to claim 1, wherein: The display area also includes a second boundary and a third boundary, the second boundary and the third boundary respectively intersect with the first boundary, the orthographic projection of the first shielding portion on the base substrate is close to the intersection of the first boundary and the second boundary, and the orthographic projection of the second shielding portion on the base substrate is close to the intersection of the first boundary and the third boundary.

3. The display substrate according to claim 1, wherein The distance between the first shielding portion and the second shielding portion ranges from 50 mm to 60 mm.

4. The display substrate according to any one of claims 1 to 3, wherein: The display substrate further includes: a negative power line, located on a side of the display line away from the base substrate, wherein an orthographic projection of the negative power line on the base substrate is located in the peripheral area and at least partially surrounds the display area; The shielding structure is located on a side of the negative power line away from the base substrate, the shielding structure is electrically connected to the negative power line, and the orthographic projection of the shielding structure on the base substrate at least partially overlaps with the orthographic projection of the negative power line on the base substrate.

5. The display substrate according to claim 4, wherein: The width of the overlapping area between the shielding structure and the negative power line is in the range of 50 microns to 60 microns, and the overlapping area between the shielding structure and the negative power line is the overlapping area of ​​the orthographic projection of the shielding structure on the base substrate and the orthographic projection of the negative power line on the base substrate.

6. The display substrate according to claim 4, wherein: The display substrate further includes: a cathode located on a side of the shielding structure away from the substrate, the cathode being electrically connected to the negative power line, and the touch control trace being located on a side of the cathode away from the substrate; An orthographic projection of the shielding structure on the base substrate at least partially overlaps with an orthographic projection of the cathode on the base substrate.

7. The display substrate according to claim 6, wherein: The width of the overlapping area between the shielding structure and the cathode is in the range of 20 microns to 25 microns. The overlapping area between the shielding structure and the cathode is the overlapping area between the orthographic projection of the shielding structure on the substrate and the orthographic projection of the cathode on the substrate.

8. The display substrate according to claim 4, wherein: The display substrate further includes: a positive power line, located on a side of the display line away from the base substrate, wherein an orthographic projection of the positive power line on the base substrate is located in the peripheral area and at least partially surrounds the display area; An orthographic projection of the shielding structure on the base substrate at least partially overlaps with an orthographic projection of the positive power line on the base substrate.

9. The display substrate according to claim 8, wherein: The width of the overlapping area between the shielding structure and the positive power line is in the range of 4 microns to 6 microns, and the overlapping area between the shielding structure and the positive power line is the overlapping area between the orthographic projection of the shielding structure on the substrate and the orthographic projection of the positive power line on the substrate.

10. The display substrate according to claim 8 or 9, characterized in that: The negative power line includes a first routing segment and a second routing segment, the first routing segment is electrically connected to the second routing segment, and the shielding structure is electrically connected to the second routing segment; The positive power line and the first routing segment are located on the same layer, and the second routing segment is located on a side of the first routing segment away from the substrate.

11. The display substrate according to any one of claims 1 to 3, and 5 to 9, characterized in that: The display substrate further includes: a blocking wall, wherein an orthographic projection of the blocking wall on the base substrate is located in the peripheral area and surrounds the display area, and an orthographic projection of the shielding structure on the base substrate is located between the display area and the orthographic projection of the blocking wall on the base substrate; The distance between the orthographic projection of the shielding structure on the base substrate and the orthographic projection of the blocking wall on the base substrate is in a range of 12 micrometers to 16 micrometers.

12. The display substrate according to any one of claims 1 to 3, and 5 to 9, characterized in that: The display substrate further includes: a negative power line and a positive power line; The orthographic projection of the shielding structure on the base substrate is located in a first peripheral region, the orthographic projection of the negative power line on the base substrate is at least partially located in the first peripheral region, and the orthographic projection of the positive power line on the base substrate is at least partially located in the first peripheral region; The width of the orthographic projection of the shielding structure on the substrate is in the range of 105 microns to 115 microns, the width of the orthographic projection of the negative power line in the first peripheral area is in the range of 145 microns to 155 microns, and the width of the orthographic projection of the positive power line in the first peripheral area is in the range of 95 microns to 105 microns.

13. A method for manufacturing a display substrate, characterized in that: The display substrate has a binding side, where the binding side is a side where the display substrate is bound to the circuit board. The method includes: Providing a base substrate, the base substrate comprising a display area and a peripheral area at least partially surrounding the display area, the display area comprising a first boundary, and the peripheral area comprising a first peripheral area extending along the first boundary; A display trace, a shielding structure, and a touch trace are sequentially formed on the base substrate. The display trace is located in the peripheral region and at least partially surrounds the display region. The orthographic projection of the shielding structure on the base substrate is located in the first peripheral region and extends along the first boundary. The first peripheral region is located on the binding side of the display substrate. The shielding structure includes a first shielding portion and a second shielding portion. A gap is defined between the first shielding portion and the second shielding portion. The first shielding portion and the second shielding portion are symmetrical about a first cross-section of the display substrate. The first cross-section is perpendicular to the first boundary, and an intersection line of the first cross-section and the base substrate bisects the first boundary. The orthographic projection of the touch trace on the base substrate is located in the peripheral region and at least partially surrounds the display region. The orthographic projections of the display trace, the shielding structure, and the touch trace on the base substrate at least partially overlap.

14. The method according to claim 13, characterized in that The method further comprises: A negative power line is formed on a side of the display line away from the substrate, the positive projection of the negative power line on the substrate is located in the peripheral area and at least partially surrounds the display area, the shielding structure is located on a side of the negative power line away from the substrate, the shielding structure is electrically connected to the negative power line, and the positive projection of the shielding structure on the substrate at least partially overlaps with the positive projection of the negative power line on the substrate.

15. The method according to claim 14, characterized in that The method further comprises: A cathode is formed on a side of the shielding structure away from the base substrate, the cathode is electrically connected to the negative power line, the touch line is located on a side of the cathode away from the base substrate, and the orthographic projection of the shielding structure on the base substrate at least partially overlaps with the orthographic projection of the cathode on the base substrate.

16. The method according to any one of claims 13 to 15, characterized in that The method further comprises: A positive power line is formed on a side of the display line away from the base substrate, the orthographic projection of the positive power line on the base substrate is located in the peripheral area and at least partially surrounds the display area, and the orthographic projection of the shielding structure on the base substrate at least partially overlaps with the orthographic projection of the positive power line on the base substrate.

17. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 12.

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