Display substrate, preparation method thereof and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device. The display substrate includes a substrate and a plurality of sub-pixels on the substrate. The sub-pixel includes a first electrode, an organic light-emitting layer, and a second electrode arranged in sequence. The first electrode includes at least one conductive layer. A partition is arranged between the first electrodes of adjacent sub-pixels. The partition includes at least one partition opening. The organic light-emitting layer includes a plurality of light-emitting layers of different colors arranged in a stack and a charge generation layer arranged between the light-emitting layers of different colors. The partition opening includes a first surface and a second surface arranged opposite to each other and a third side surface arranged between the first surface and the second surface. The third side surface includes at least one side recess structure. In a direction perpendicular to the display substrate, a height difference between the partition and the first electrode is less than or equal to the thickness of any one of the conductive layers. The display effect is improved.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate, a method for preparing the substrate, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are a type of display technology that has emerged in recent years, with silicon-based OLEDs being one example. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve lightweight design. Silicon-based OLEDs are fabricated using mature complementary metal-oxide-semiconductor (CMOS) integrated circuit technology, offering advantages such as small size, high resolution (Pixels Per Inch, PPI), and high refresh rate. They are widely used in near-eye displays for virtual reality (VR) and augmented reality (AR). Summary of the Invention

[0003] This disclosure provides a display substrate and its preparation method, as well as a display device, which can improve the display effect.

[0004] This disclosure provides a display substrate, which includes a substrate and a plurality of sub-pixels located on the substrate. Each sub-pixel includes a first electrode, an organic light-emitting layer and a second electrode disposed sequentially. The first electrode includes at least one conductive layer. A partition is disposed between the first electrodes of adjacent sub-pixels. The partition includes at least one partition opening. The organic light-emitting layer includes a plurality of light-emitting layers of different colors stacked together and a charge-generating layer disposed between the plurality of light-emitting layers of different colors.

[0005] The partition opening includes a first surface near the substrate, a second surface away from the substrate, and a third side surface disposed between the first and second surfaces. The third side surface includes at least one recessed structure. In a direction perpendicular to the display substrate, the height difference between the surface of the partition away from the substrate and the surface of the first electrode away from the substrate is less than or equal to the thickness of any conductive layer.

[0006] In an exemplary embodiment, in a direction perpendicular to the display substrate, the distance between the surface of the charge generating layer away from the substrate and the surface of the first electrode away from the substrate is less than or equal to the height of the side recess structure.

[0007] In an exemplary embodiment, in a direction perpendicular to the display substrate, the surface of the partition portion away from the substrate is flush with the surface of the first electrode away from the substrate.

[0008] In an exemplary embodiment, the display substrate further includes a first insulating layer located on the side of the first electrode near the substrate; the partition portion further includes an etching barrier layer disposed between the partition opening and the first insulating layer, and the orthographic projection of the etching barrier layer on the substrate covers the orthographic projection of the partition opening on the substrate.

[0009] In an exemplary embodiment, the second electrode includes at least one second electrode slope, the orthographic projection of the second electrode slope on the substrate overlaps with the orthographic projection of the side concave structure on the substrate, and the distance from the upper edge of the first electrode near the partition opening side to any point on the second electrode slope is equal to or approximately equal to the height difference between the first electrode and the second electrode.

[0010] In an exemplary embodiment, the display substrate further includes a pixel definition layer, the partition portion and the partition opening are formed by the pixel definition layer, and the orthographic projection of the pixel definition layer on the substrate does not overlap with the orthographic projection of the first electrode on the substrate.

[0011] In an exemplary embodiment, the pixel definition layer includes a first pixel definition layer and a second pixel definition layer stacked sequentially from bottom to top, wherein:

[0012] The first pixel definition layer includes a first sub-isolation opening, and the second pixel definition layer includes a second sub-isolation opening. The first sub-isolation opening and the second sub-isolation opening are interconnected, and the orthographic projection of the first sub-isolation opening on the substrate is greater than the orthographic projection of the second sub-isolation opening on the substrate. The first sub-isolation opening and the second sub-isolation opening form a first side-concave structure.

[0013] In an exemplary embodiment, along a direction parallel to the display substrate, the distance between the edge of the first sub-partition opening and the edge of the second sub-partition opening is between 0.1 and 1.5 times the width of the first sub-partition opening.

[0014] In an exemplary embodiment, the pixel definition layer further includes a third pixel definition layer and a fourth pixel definition layer stacked on the second pixel definition layer, wherein:

[0015] The third pixel definition layer includes a third sub-isolation port, and the fourth pixel definition layer includes a fourth sub-isolation port. The first sub-isolation port, the second sub-isolation port, the third sub-isolation port, and the fourth sub-isolation port are interconnected. The orthographic projection of the third sub-isolation port on the substrate is greater than the orthographic projection of the fourth sub-isolation port on the substrate. The third sub-isolation port and the fourth sub-isolation port form a second concave structure.

[0016] In an exemplary embodiment, the area where the edge of the first electrode near the partition opening connects with the side of the first pixel definition layer is greater than the area where the edge of the first electrode near the partition opening connects with the side of the other pixel definition layer.

[0017] In an exemplary embodiment, along a direction perpendicular to the display substrate, the thickness of the first pixel definition layer is greater than the thickness of the second pixel definition layer, and the thickness of the third pixel definition layer is greater than the thickness of the fourth pixel definition layer.

[0018] In an exemplary embodiment, the partition portion includes a first flat portion, a second flat portion, and a partition electrode located between the first flat portion and the second flat portion, wherein the partition opening is formed by the partition electrode.

[0019] In an exemplary embodiment, in a direction parallel to the display substrate, the width of the first flat portion is equal to or approximately equal to the width of the second flat portion, and the width of the blocking electrode is between 1 and 2 times the width of the first flat portion.

[0020] This disclosure also provides a display device, including: a display substrate as described above.

[0021] This disclosure also provides a method for fabricating a display substrate, the display substrate comprising a plurality of sub-pixels, the fabrication method comprising:

[0022] A first electrode is formed on a substrate. The first electrode includes at least one conductive layer. A partition portion is provided between the first electrodes of adjacent sub-pixels. The partition portion includes at least one partition opening. The partition opening includes a first surface near the substrate, a second surface away from the substrate, and a third side surface disposed between the first surface and the second surface. The third side surface includes at least one side recess structure. In a direction perpendicular to the display substrate, the height difference between the surface of the partition portion away from the substrate and the surface of the first electrode away from the substrate is less than or equal to the thickness of any conductive layer.

[0023] An organic light-emitting layer is formed on the first electrode. The organic light-emitting layer includes a plurality of light-emitting layers of different colors stacked together and a charge-generating layer side recess disposed between the plurality of light-emitting layers of different colors.

[0024] A second electrode is formed on the organic light-emitting layer.

[0025] The display substrate, its fabrication method, and display device of this disclosure effectively isolate the charge generation layers between adjacent sub-pixels by providing a partition portion between the first electrodes of adjacent sub-pixels. This partition portion includes at least one partition opening, and at least one side recess structure is provided on the side of the partition opening. The charge generation layer is discontinuous at the location of the side recess structure. The height difference between the partition portion and the first electrode is less than or equal to the thickness of any conductive layer in the first electrode. This avoids crosstalk between adjacent sub-pixels. Since the pixel definition layer exposes the first electrode, the pixel aperture ratio is increased, preventing the second electrode morphology above the edge of the first electrode from puncturing. Furthermore, the fabrication process of this disclosure is highly compatible with existing fabrication processes, is simple to implement, easy to execute, has high production efficiency, low production cost, and high yield.

[0026] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0028] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure;

[0029] Figure 2 This is a schematic diagram of the pixel arrangement structure of a display panel provided in an embodiment of the present disclosure;

[0030] Figure 3 This is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0031] Figure 4 This is a schematic diagram of another display substrate provided in an embodiment of the present disclosure;

[0032] Figure 5 for Figure 3 The diagram shows the structure of the display substrate after the first insulating layer has been formed.

[0033] Figure 6 forFigure 3 The diagram shows the structure of the display substrate after the first electrode has been formed.

[0034] Figures 7a to 7b for Figure 3 The diagram shown illustrates the process of forming a pixel definition layer on a display substrate.

[0035] Figure 7c for Figure 7b Enlarged structural diagram of region A in the middle;

[0036] Figure 7d This is a schematic diagram of another pixel definition layer structure provided in an embodiment of the present disclosure;

[0037] Figure 7e This is a schematic diagram of another pixel definition layer structure provided in an embodiment of the present disclosure;

[0038] Figure 8 and Figure 9 These are schematic diagrams of the structures of two organic light-emitting layers provided in embodiments of this disclosure;

[0039] Figure 10 for Figure 4 The diagram shows the structure of the display substrate after the first electrode and the isolation electrode have been formed.

[0040] Figure 11 for Figure 4 The diagram shows the structure of the display substrate after the first and second planar portions are formed.

[0041] Figure 12a for Figure 4 The diagram shows the structure of the display substrate after the isolation electrodes have been etched.

[0042] Figure 12b for Figure 12a A magnified structural diagram of region B in the middle. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0044] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0045] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0046] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0047] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0048] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0049] In this specification, to distinguish the two terminals of a transistor other than the control terminal, one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0050] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0051] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0052] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0053] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0054] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0055] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0056] Figure 1 This is a schematic diagram of the structure of a silicon-based OLED display device. Figure 1 As shown, a silicon-based OLED display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, and may provide clock signals, scan start signals, etc., of specifications suitable for the scan signal driver to the scan signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver may use a clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a sub-pixel row basis, where n can be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, a scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. A sub-pixel array can include multiple sub-pixels PXij. Each sub-pixel PXij can be connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. A sub-pixel PXij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and connected to the j-th data signal line.

[0057] Figure 2 This is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device. Figure 2As shown, the display area may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuit in each sub-pixel is connected to a scan signal line and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The display light-emitting device in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0058] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel emitting red (R) light, the second sub-pixel P2 can be a blue sub-pixel emitting blue (B) light, and the third sub-pixel P3 can be a green sub-pixel emitting green (G) light. In an exemplary embodiment, the shape of the sub-pixels can be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons, and other polygons, and they can be arranged in horizontal parallel, vertical parallel, X-shaped, cross-shaped, triangular, square, diamond-shaped, or delta-shaped arrangements, etc., without limitation herein.

[0059] In an exemplary embodiment, a pixel unit may include four sub-pixels, which is not limited herein.

[0060] Currently, Micro-OLED display panels mainly use a tandem structure to improve brightness. However, due to the close proximity of pixels, this structure is prone to color mixing issues.

[0061] This disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels located on the substrate; each sub-pixel includes a first electrode, an organic light-emitting layer and a second electrode disposed sequentially, the first electrode including at least one conductive layer, a partition portion being disposed between the first electrodes of adjacent sub-pixels, the partition portion including at least one partition opening, the organic light-emitting layer including a plurality of light-emitting layers of different colors stacked together and a charge-generating layer disposed between the plurality of light-emitting layers of different colors; the partition opening includes a first surface near the substrate, a second surface away from the substrate, and a third side surface disposed between the first surface and the second surface, the third side surface including at least one side recess structure; in a direction perpendicular to the display substrate, the height difference between the surface of the partition portion away from the substrate and the surface of the first electrode away from the substrate (i.e., the height difference between the partition portion and the first electrode) is less than or equal to the thickness of the first electrode.

[0062] In this embodiment, the charge generation layer is discontinuous at the location of the side recess structure in a direction parallel to the display substrate.

[0063] The display substrate of this disclosure provides a partition between the first electrodes of adjacent sub-pixels. The partition includes at least one partition opening, and at least one side recess structure is provided on the side of the partition opening. The charge generation layer is discontinuous at the position of the side recess structure. The height difference between the partition and the first electrode is less than or equal to the thickness of any conductive layer in the first electrode. This effectively isolates the charge generation layer between adjacent sub-pixels, avoids crosstalk between adjacent sub-pixels, and reduces the second electrode puncture problem at the light emission edge of the organic light-emitting layer.

[0064] like Figure 3 or Figure 4 and combined Figure 7c or Figure 12b As shown, the display substrate includes: a substrate 10 and a plurality of sub-pixels located on the substrate 10; each sub-pixel includes a first electrode 40, an organic light-emitting layer 60 and a second electrode 70 arranged sequentially, and a partition is provided between the first electrodes of adjacent sub-pixels. The partition includes at least one partition opening K2. The organic light-emitting layer 60 includes a plurality of light-emitting layers EML of different colors stacked together and a charge-generating layer CGL disposed between the plurality of light-emitting layers EML of different colors; the partition opening K2 includes a first surface K2a on the side close to the substrate 10, a second surface K2b on the side away from the substrate 10 and a third side surface K2c disposed between the first surface K2a and the second surface K2b. The third side surface K2c includes at least one side recess structure. In the direction parallel to the display substrate, the charge-generating layer CGL is discontinuous at the position of the side recess structure.

[0065] The first electrode 40 includes at least one conductive layer (for example, the first electrode 40 may include four conductive layers, such as a first titanium layer, an aluminum layer, a second titanium layer and a transparent metal oxide film layer arranged sequentially from bottom to top; or, the first electrode 40 may include three conductive layers, such as a first transparent metal oxide film layer, a silver layer and a second transparent metal oxide film layer arranged sequentially from bottom to top). In the direction perpendicular to the display substrate, the height difference between the surface of the partition portion away from the substrate 10 and the surface of the first electrode 40 away from the substrate 10 is less than or equal to the thickness of any conductive layer.

[0066] In an exemplary embodiment, the height difference between the surface of the partition portion away from the substrate 10 and the surface of the first electrode 40 away from the substrate 10 can be 0 ± 100 nm.

[0067] In an exemplary embodiment, in a direction perpendicular to the display substrate, the surface of the partition portion away from the substrate 10 is flush with the surface of the first electrode 40 away from the substrate 10.

[0068] It should be noted that the “equal height” described in this disclosure not only includes the case where the height of the partition is equal to the height of the first electrode 40, but also the case where the two are approximately equal, that is, a certain error range is allowed between the two. For example, the error range can be between 0 and 50 nm.

[0069] In an exemplary implementation, such as Figure 3 or Figure 4 As shown, in the direction perpendicular to the display substrate, the distance h2 between the surface of the charge generation layer CGL away from the substrate 10 and the surface of the first electrode 40 away from the substrate 10 is less than or equal to the height h1 of the side recess structure.

[0070] In an exemplary implementation, such as Figure 3 As shown, the partition portion and the partition opening K2 are formed by a pixel definition layer, and the orthographic projection of the pixel definition layer on the substrate 10 does not overlap with the orthographic projection of the first electrode 40 on the substrate 10.

[0071] In an exemplary implementation, such as Figure 3 As shown, the pixel definition layer includes a first pixel definition layer 501 and a second pixel definition layer 502 stacked sequentially from bottom to top, wherein:

[0072] The first pixel definition layer 501 includes a first sub-isolation opening K21, and the second pixel definition layer 502 includes a second sub-isolation opening K22. The first sub-isolation opening K21 and the second sub-isolation opening K22 are connected, and the orthographic projection of the first sub-isolation opening K21 on the substrate 10 is greater than the orthographic projection of the second sub-isolation opening K22 on the substrate 10. The first sub-isolation opening K21 and the second sub-isolation opening K22 form a first side-concave structure.

[0073] In an exemplary implementation, such as Figure 3 As shown, the pixel definition layer also includes a third pixel definition layer 503 disposed above the second pixel definition layer 502 and a fourth pixel definition layer 504 disposed above the third pixel definition layer 503, wherein:

[0074] The third pixel definition layer 503 includes a third sub-partition opening K23, and the fourth pixel definition layer 504 includes a fourth sub-partition opening K24. The third sub-partition opening K23 and the fourth sub-partition opening K24 are connected, and the orthogonal projection of the third sub-partition opening K23 on the substrate 10 is greater than the orthogonal projection of the fourth sub-partition opening K24 on the substrate 10. The third sub-partition opening K23 and the fourth sub-partition opening K24 form a second side-concave structure.

[0075] To form a concave structure, this can be achieved by adjusting the etching rate between pixel definition layers. For example, materials with different etching rates are used to construct the first pixel definition layer, the second pixel definition layer, the third pixel definition layer, and the fourth pixel definition layer, respectively. Specifically, the etching rate of the first pixel definition layer is greater than that of the second pixel definition layer, and the etching rate of the third pixel definition layer is greater than that of the fourth pixel definition layer.

[0076] In an exemplary embodiment, the material of the first pixel definition layer 501 is the same as the material of the third pixel definition layer 503, and the material of the second pixel definition layer 502 is the same as the material of the fourth pixel definition layer 504.

[0077] In an exemplary embodiment, the material of the first pixel definition layer 501 may be silicon nitride (SiNx), and the material of the second pixel definition layer 502 may be silicon oxide (SiOx); or, the material of the first pixel definition layer 501 may be silicon nitride (SiNx), and the material of the second pixel definition layer 502 may be aluminum oxide (Al2O3).

[0078] In an exemplary embodiment, the thickness of the second pixel definition layer is between 200 angstroms and 600 angstroms along a direction perpendicular to the display substrate, and the thickness of the fourth pixel definition layer is between 200 angstroms and 600 angstroms.

[0079] In an exemplary embodiment, along a direction parallel to the display substrate, the distance between the edge of the first sub-partition opening and the edge of the second sub-partition opening is between 0.1 and 1.5 times the width of the first sub-partition opening; the distance between the edge of the third sub-partition opening and the edge of the fourth sub-partition opening is between 0.1 and 1.5 times the width of the first sub-partition opening.

[0080] In an exemplary implementation, such as Figure 3 or Figure 4 As shown, the second electrode 70 includes at least one slope 701. The orthographic projection of the slope 701 onto the substrate 10 overlaps with the orthographic projection of the side-concave structure onto the substrate 10. The distance from the upper edge of the first electrode 40 near the partition opening K2 to any point on the slope 701 of the second electrode (e.g., ...) Figure 3 or Figure 4 R2 or R3 in the figure is equal to or approximately equal to the height difference R1 between the first electrode 40 and the second electrode 70. In this embodiment, "approximately equal to" means that, when there is a process error, the distance from the edge of the first electrode 40 near the partition opening K2 to any point on the slope surface 701 of the second electrode (e.g., ...) is equal to or approximately equal to the height difference R1 between the first electrode 40 and the second electrode 70. Figure 3 The difference between R2 or R3 and the height difference R1 between the first electrode 40 and the second electrode 70 is between 0 μm and 0.1 μm. In this embodiment, since the distance between the second electrode and the first electrode is equal or approximately equal at the edge of the first electrode 40 near the partition opening K2, the electric field between the second electrode and the first electrode will also be equal or approximately equal, thereby reducing leakage current and improving the performance of the display substrate.

[0081] In an exemplary embodiment, the height difference R1 between the first electrode 40 and the second electrode 70 can be between 3000 angstroms and 10000 angstroms. It should be noted that the height difference R1 between the first electrode 40 and the second electrode 70 may vary depending on the different display substrate structures.

[0082] In an exemplary implementation, such as Figure 3 As shown, a pixel definition layer is provided between adjacent first electrodes.

[0083] In an exemplary implementation, such as Figure 3 As shown, in the direction perpendicular to the display substrate, the surface of the pixel definition layer away from the substrate 10 is flush with the surface of the first electrode 40 away from the substrate 10.

[0084] In an exemplary implementation, such as Figure 4 As shown, the partition includes a first flat portion 41a, a second flat portion 41b, and a partition electrode 40b located between the first flat portion 41a and the second flat portion 41b. The partition opening K2 is formed by the partition electrode 40b.

[0085] This embodiment, by setting a first flat portion 41a, a second flat portion 41b, and a partition electrode 40b located between the first flat portion 41a and the second flat portion 41b, can control the distance between the second electrode puncture and the first electrode, thereby effectively solving the problem of uneven brightness around the organic light-emitting layer caused by the second electrode puncture.

[0086] In an exemplary implementation, such as Figure 11 As shown, in the direction parallel to the display substrate, the width w1 of the first flat portion 41a and the width w3 of the second flat portion 41b are equal or approximately equal (i.e., a certain error range is allowed between them; exemplarily, this error range can be between 0 and 100 nm), and the width w2 of the blocking electrode 40b is between 1 and 2 times the width w1 of the first flat portion 41a. For example, the width w1 of the first flat portion 41a can be greater than or equal to 0.2 μm. The width w3 of the second flat portion 41b can be greater than or equal to 0.2 μm. The width w2 of the blocking electrode 40b can be greater than or equal to 0.2 μm.

[0087] In an exemplary implementation, such as Figure 4 As shown, in the direction perpendicular to the display substrate, the height h31 of the first flat portion 41a and the height h32 of the second flat portion 41b are equal to the height h4 of the first electrode 40 (that is, the surface of the first flat portion 41a away from the substrate 10, the surface of the second flat portion 41b away from the substrate 10, and the surface of the first electrode 40 away from the substrate 10 are at the same height).

[0088] In an exemplary implementation, such as Figure 12a and Figure 12b As shown, the isolation electrode includes a first isolation electrode 401b, a second isolation electrode 402b, a third isolation electrode 403b, and a fourth isolation electrode 404b arranged sequentially from bottom to top. The second isolation electrode 402b includes a first sub-isolation opening K21, and the third isolation electrode 403b and the fourth isolation electrode 404b include a second sub-isolation opening K22. The first sub-isolation opening K21 and the second sub-isolation opening K22 are connected to form an isolation opening K2, and the orthogonal projection of the first sub-isolation opening K21 on the substrate 10 is greater than the orthogonal projection of the second sub-isolation opening K22 on the substrate 10. The first sub-isolation opening K21 and the second sub-isolation opening K22 form a side-concave structure.

[0089] In an exemplary embodiment, the first isolation electrode 401b is made of titanium, the second isolation electrode 402b is made of aluminum, the third isolation electrode 403b is made of titanium, and the fourth isolation electrode 404b is made of metal oxide.

[0090] In some other exemplary embodiments, the isolation electrode 40b includes a first isolation electrode, a second isolation electrode, and a third isolation electrode arranged sequentially from bottom to top. The second isolation electrode includes a first sub-isolation opening K21, and the third isolation electrode includes a second sub-isolation opening K22. The first sub-isolation opening K21 and the second sub-isolation opening K22 are connected, and the orthographic projection of the first sub-isolation opening K21 on the substrate 10 is greater than the orthographic projection of the second sub-isolation opening K22 on the substrate 10. The first sub-isolation opening K21 and the second sub-isolation opening K22 form a side-concave structure.

[0091] In an exemplary embodiment, the first isolation electrode is made of metal oxide, the second isolation electrode is made of silver, and the third isolation electrode is made of metal oxide.

[0092] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display device. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0093] In an exemplary embodiment, Figure 3 The fabrication process of the display substrate shown may include the following steps:

[0094] (11) Forming a substrate 10, for example, the substrate 10 may be a silicon-based substrate. The process for forming the substrate 10 may employ a mature IC (Integrated Circuit) wafer fabrication process, which will not be elaborated here.

[0095] (12) Forming a driving circuit layer 20. The driving circuit layer 20 can be fabricated on the substrate 10 using silicon semiconductor technology (e.g., complementary metal oxide semiconductor (CMOS) technology). The driving circuit layer 20 can include multiple circuit units, and each circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected to the scan signal line and the data signal line, respectively. The pixel driving circuit can include multiple transistors and storage capacitors. The transistors can include a control electrode, a first electrode, and a second electrode. The control electrode, the first electrode, and the second electrode can be connected to the corresponding connection electrode through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (such as traces) through the connection electrodes.

[0096] (13) Forming a first insulating layer 30. In an exemplary embodiment, forming a pattern of the first insulating layer 30 includes: depositing a first insulating film on a substrate on which the aforementioned pattern is formed, and patterning the first insulating film using a patterning process to form a pattern of the first insulating layer 30 covering the driving circuit layer 20, such as... Figure 5 As shown.

[0097] (14) Forming a first electrode layer 40. In an exemplary embodiment, forming the pattern of the first electrode layer 40 includes: depositing a first electrode material thin film on a substrate on which the aforementioned pattern is formed, and patterning the first electrode material thin film using a patterning process to form a first electrode layer 40 pattern disposed on the first insulating layer 30, such as... Figure 6 As shown.

[0098] In some exemplary embodiments, the first electrode layer may include a plurality of spaced-apart sub-first electrode blocks.

[0099] In some exemplary embodiments, the material of the first electrode block may be a metal or a metal oxide.

[0100] In some exemplary embodiments, the sub-first electrode block can be a stacked structure.

[0101] In some exemplary implementations, such as Figure 6 As shown, the first electrode block may include a metal film layer and a transparent metal oxide film layer 404 located above the metal film layer. The metal film layer may include a first titanium layer 401, an aluminum layer 402 and a second titanium layer 403 sequentially stacked on the first insulating layer 30; the transparent metal oxide film layer 404 may be indium tin oxide (ITO) or indium zinc oxide (IZO).

[0102] In some other exemplary embodiments, the sub-first electrode block may include two transparent metal oxide film layers and a metal film layer (not shown in the figure) located between the two transparent metal oxide film layers. The material of the transparent metal oxide film layer may be indium tin oxide (ITO) or indium zinc oxide (IZO), and the material of the metal film layer may be metallic silver.

[0103] (15) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern includes the following steps:

[0104] A multilayer film is formed between sub-first electrode blocks of adjacent sub-pixels. The multilayer film includes at least a first pixel definition film 501 and a second pixel definition film 502 located on top of the first pixel definition film 501. In an exemplary embodiment, the multilayer film may include a first pixel definition film 501, a second pixel definition film 502, a third pixel definition film 503, and a fourth pixel definition film 504 stacked sequentially from bottom to top, such as... Figure 7a As shown. In this embodiment of the present disclosure, the two adjacent pixel definition films need to be made of materials with a large difference in etching rate ratio. For example, along the direction away from the substrate, the (2n-1)th pixel definition film can be a silicon nitride (SiNx) film, and the (2n)th pixel definition film can be a silicon oxide (SiOx) film (the etching rate of the SiNx film is greater than that of the SiOx film); or, the (2n-1)th pixel definition film can be a silicon nitride (SiNx) film, and the (2n)th pixel definition film can be an aluminum oxide (Al2O3) film (the etching rate of the SiNx film is greater than that of the Al2O3 film), where n is a natural number greater than or equal to 1. In some other exemplary embodiments, the two adjacent pixel definition films can also be made of other materials with a large difference in etching rate ratio, and this disclosure does not limit this. In some other exemplary embodiments, the multilayer film can also include any number of layers, such as two, five, six, etc., and this disclosure does not limit this.

[0105] Etching is performed on multiple pixel definition films, forming a sub-isolation opening in each pixel definition film. Multiple sub-isolation openings form a total isolation opening K2. During etching, the etching rate of the (2n-1)th pixel definition film is greater than that of the (2n)th pixel definition film along the direction away from the substrate. Therefore, the sub-isolation opening of the (2n-1)th pixel definition film is larger than that of the (2n)th pixel definition film. Figure 7b and Figure 7cAs shown. For example, the first pixel definition film 501 forms a first sub-partition opening K21, the second pixel definition film 502 forms a second sub-partition opening K22, the third pixel definition film 503 forms a third sub-partition opening K23, and the fourth pixel definition film 504 forms a fourth sub-partition opening K24. The first sub-partition opening K21 is larger than the second sub-partition opening K22, and the third sub-partition opening K23 is larger than the fourth sub-partition opening K24, so that every two stacked pixel definition layers form a side-concave structure.

[0106] Optionally, dry etching can be used to etch the multilayer pixel definition layer film. Since the etching rate of the (2n-1)th pixel definition layer film is much faster than that of the (2n)th pixel definition layer film, under the same etching conditions, the opening of the (2n-1)th pixel definition layer film is larger than that of the (2n)th pixel definition layer film. Here, dry etching includes, but is not limited to, sputtering and ion beam milling, plasma etching, high-pressure plasma etching, high-density plasma etching, and reactive ion etching.

[0107] Alternatively, wet etching can be used to etch the multilayer pixel definition layer film, and an etching solution with a higher etching rate for the (2n-1)th pixel definition layer film than for the (2n)th pixel definition layer film can be selected.

[0108] For example, the thickness of the first pixel defining film 501 is greater than the thickness of the second pixel defining film 502, and the thickness of the third pixel defining film 503 is greater than the thickness of the fourth pixel defining film 504, so as to increase the height of the side concave structure and enable the partition portion to better play the role of preventing crosstalk. However, this disclosure does not limit it.

[0109] For example, such as Figure 7c As shown, the thickness h6 of the second pixel defining film 502 is between 200 angstroms and 600 angstroms, and the thickness h8 of the fourth pixel defining film 504 is between 200 angstroms and 600 angstroms.

[0110] For example, such as Figure 7cAs shown, the thickness h5 of the first pixel defining film 501 can be greater than the thickness h7 of the third pixel defining film 503, and the thickness h5 of the first pixel defining film 501 can also be less than the thickness h7 of the third pixel defining film 503; this disclosure does not limit this. In this embodiment, the thickness h5 of the first pixel defining film 501 and the thickness h7 of the third pixel defining film 503 are set according to the thickness h6 of the second pixel defining film 502 and the thickness h8 of the fourth pixel defining film 504. Since the height of the concave structure is greater than or equal to the height difference between the charge generation layer and the first electrode, the sum of the thickness h5 of the first pixel defining film 501 and the thickness h7 of the third pixel defining film 503 is greater than or equal to the difference between the height difference between the charge generation layer and the first electrode and the thickness h6 of the second pixel defining film 502 and the thickness h8 of the fourth pixel defining film 504, so that the partition portion can partition the CGL layer (when the CGL layer contains multiple layers, the partition portion of this application can also partition all CGL layers), thereby preventing crosstalk between adjacent sub-pixels.

[0111] In an exemplary implementation, such as Figure 7c As shown, along the direction parallel to the display substrate, the distance d1 between the edge of the first sub-partition opening K21 and the edge of the second sub-partition opening K22 is between 0.1 and 1.5 times the width w of the first sub-partition opening K21.

[0112] In an exemplary implementation, such as Figure 7c As shown, along a direction parallel to the display substrate, the distance d1 between the edge of the first sub-partition opening K21 and the edge of the second sub-partition opening K22 is between 0.1 micrometers and 0.6 micrometers.

[0113] In an exemplary implementation, such as Figure 7c As shown, along the direction parallel to the display substrate, the distance d2 between the edge of the third sub-partition K23 and the edge of the fourth sub-partition K24 is between 0.1 and 1.5 times the width w of the first sub-partition K21.

[0114] In an exemplary implementation, such as Figure 7c As shown, along a direction parallel to the display substrate, the distance d2 between the edge of the third sub-partition K23 and the edge of the fourth sub-partition K24 is between 0.1 micrometers and 0.6 micrometers.

[0115] In an exemplary implementation, such as Figure 7b As shown, the orthographic projections of pixel definition layers 501 to 504 on the substrate 10 do not overlap with the orthographic projections of the first electrode 40 on the substrate 10, thereby improving the aperture ratio.

[0116] In an exemplary implementation, such as Figure 7cAs shown, while achieving the separation, the width of the first sub-separation opening K21 is minimized to improve the resolution and aperture ratio of the display panel. For example, the width w of the first sub-separation opening K21 along the direction parallel to the display substrate is between 0.4 micrometers and 1 micrometer.

[0117] In other exemplary embodiments, when the pixel definition layer includes only a first pixel definition layer and a second pixel definition layer, the thickness h6 of the second pixel definition film 502 can be between 0.4 and 3 times the thickness h5 of the first pixel definition film 501 along the direction perpendicular to the display substrate. For example, the thickness h6 of the second pixel definition film 502 is between 400 angstroms and 1500 angstroms, and the thickness h5 of the first pixel definition film 501 is between 300 angstroms and 1000 angstroms.

[0118] In an exemplary embodiment, when the pixel definition layer includes only the first pixel definition layer and the second pixel definition layer, the sum of the thickness h5 of the first pixel definition film 501 and the thickness h7 of the second pixel definition film 502 is greater than or equal to the height difference between the charge generation layer and the first electrode, thereby enabling the partition portion to partition the CGL layer (when the CGL layer contains multiple layers, the partition portion of this application can also partition all CGL layers), thereby preventing crosstalk between adjacent sub-pixels.

[0119] It should be noted that, considering actual manufacturing processes, each layer in the pixel definition layer of the display substrate of this application will partially overlap with the first electrode during fabrication. To achieve flush alignment and prevent puncture by the second electrode, a polishing process is used to smooth the overlapping portion of the pixel definition layer with the first electrode, ultimately achieving flush alignment between the pixel definition layer and the first electrode. For example, the actual fabricated pixel definition layer structure is as follows: Figure 7d As shown.

[0120] In an exemplary implementation, such as Figure 7d As shown, the area where the edge of the first electrode near the partition opening connects with the side of the first pixel definition layer is greater than the area where the edge of the first electrode near the partition opening connects with the side of the other pixel definition layer.

[0121] In an exemplary implementation, such as Figure 7e As shown, the partition also includes an etching barrier layer 80 disposed on the first insulating layer 30. The etching barrier layer 80 is located between the partition opening K2 and the first insulating layer 30. The etching barrier layer 80 can be used to prevent over-etching of the first insulating layer 30 when etching the multilayer pixel definition film. For example, the etching barrier layer 80 can be a metal or an indium tin oxide (ITO) material.

[0122] In an exemplary embodiment, the etch barrier layer 80 may be prepared co-layered with any sublayer in the first electrode layer, or prepared after the formation of the first electrode layer and before the formation of the pixel definition layer.

[0123] (16) Form the pattern of the organic light-emitting layer 60 and the second electrode 70.

[0124] Figure 8 This is a schematic diagram of one structure of the organic light-emitting layer 60 disclosed herein. Figure 8 As shown, the structure of the organic light-emitting layer disclosed herein includes a first light-emitting sublayer 601, a first charge-generating layer 602, a second light-emitting sublayer 603, a second charge-generating layer 604, and a third light-emitting sublayer 605 sequentially stacked between the first electrode 40 and the second electrode 70. The first light-emitting sublayer 601 emits first color light and includes a first hole transport layer (HTL) 6011, a first light-emitting material layer (EML) 6012, and a first electron transport layer (ETL) 6013 sequentially stacked. The second light-emitting sublayer 603 emits second color light and includes a second hole transport layer 6031, a second light-emitting material layer 6032, and a second electron transport layer 6033 sequentially stacked. The third light-emitting sublayer 605 emits third color light and includes a third hole transport layer 6051, a third light-emitting material layer 6052, and a third electron transport layer 6053 sequentially stacked. A first charge-generating layer 602 is disposed between a first light-emitting sublayer 601 and a second light-emitting sublayer 603, for connecting the two light-emitting sublayers in series to achieve carrier transfer. A second charge-generating layer 604 is disposed between a second light-emitting sublayer 603 and a third light-emitting sublayer 605, for connecting the two light-emitting sublayers in series to achieve carrier transfer. Since the organic light-emitting layer of this disclosure includes a first light-emitting material layer emitting a first color light, a second light-emitting material layer emitting a second color light, and a third light-emitting material layer emitting a third color light, the light ultimately emitted by the organic light-emitting layer is mixed light. For example, the first light-emitting material layer can be configured to be a red light-emitting material layer emitting red light, the second light-emitting material layer to be a green light-emitting material layer emitting green light, and the third light-emitting material layer to be a red light-emitting material layer emitting blue light, thus the organic light-emitting layer ultimately emits white light.

[0125] In an exemplary embodiment, Figure 8 The organic light-emitting layer shown is merely an example structure, and this disclosure does not limit it. In actual implementation, the structure of the organic light-emitting layer can be designed according to actual needs. For example, in each light-emitting sublayer, in order to improve the efficiency of electron and hole injection into the light-emitting material layer, a hole injection layer (HIL) and an electron injection layer (EIL) can also be provided. Furthermore, to simplify the structure of the organic light-emitting layer, the first electron transport layer 6013, the first charge generation layer 602, and the second hole transport layer 6031 can be omitted; that is, the second light-emitting material layer 6032 can be directly disposed on the first light-emitting material layer 6012, such as...Figure 9 As shown.

[0126] In some possible implementations, the organic light-emitting layer may be an organic light-emitting layer that emits a first color light and an organic light-emitting layer that emits a complementary light of the first color light. The two organic light-emitting layers are stacked in sequence relative to the substrate, thereby emitting white light as a whole. This disclosure does not limit this, as long as white light emission can be achieved.

[0127] To more clearly see whether the charge generation layer (CGL) has experienced film fracture, such as Figure 3 As shown, we simply divide the organic light-emitting layer into 5 layers: the first hole transport layer (HTL1), the red-green light-emitting material layer (RG-EML), the charge generation layer (CGL), the second hole transport layer (HTL2), and the blue light-emitting material layer (B-EML). From Figure 3 The deposition results of these five layers on the substrate forming the aforementioned pattern show that the charge generation layer (CGL) undergoes film fracture at the side recess structure of the pixel definition layer, thereby preventing crosstalk between adjacent sub-pixels. Simultaneously, it reduces the morphological puncture of the second electrode above the edge of the first electrode, improving the display effect. Furthermore, the fabrication process disclosed herein is highly compatible with existing fabrication processes, is simple to implement, easy to execute, has high production efficiency, low production cost, and high yield.

[0128] In some exemplary embodiments, subsequent fabrication processes may include processes such as forming a first encapsulation layer, a color filter structure layer, a second encapsulation layer, and a cover plate layer.

[0129] In an exemplary embodiment, the first encapsulation layer and the second encapsulation layer can be thin film encapsulation (TFE) to ensure that external moisture cannot enter the light-emitting structure layer. The cover layer can be made of glass or colorless polyimide, etc.

[0130] In an exemplary embodiment, the color filter structure layer may include a black matrix (BM) and a color filter (CF). The position of the color filter may correspond to the position of the light-emitting device. The black matrix may be located between adjacent color filters. The color filters are configured to filter the white light emitted by the light-emitting device into red (R) light, green (G) light, and blue (B) light, forming red sub-pixels, green sub-pixels, and blue sub-pixels.

[0131] In an exemplary embodiment, Figure 4 The fabrication process of the display substrate shown may include the following steps:

[0132] (21) Forming a substrate 10.

[0133] (22) Form the driving circuit layer 20.

[0134] (23) Form the first insulating layer 30. The preparation process of steps (21) to (23) can be referred to the aforementioned steps (11) to (13), and will not be repeated here.

[0135] (24) Forming the first electrode 40 and the blocking electrode 40b. In an exemplary embodiment, forming the pattern of the first electrode layer 40 includes: depositing a first electrode material thin film on a substrate on which the aforementioned pattern is formed, and patterning the first electrode material thin film by a patterning process to form the pattern of the first electrode layer 40 disposed on the first insulating layer 30, such as... Figure 10 As shown.

[0136] In some exemplary embodiments, the materials of the first electrode 40 and the blocking electrode 40b may be metal or metal oxide.

[0137] In some exemplary embodiments, the first electrode 40 and the blocking electrode 40b may be a stacked structure.

[0138] Optional, such as Figure 10 As shown, the first electrode 40 may include a metal film layer and a transparent metal oxide film layer 404 located above the metal film layer. The metal film layer may include a first titanium layer 401, an aluminum layer 402, and a second titanium layer 403 sequentially stacked on the first insulating layer 30; the transparent metal oxide film layer 404 may be indium tin oxide (ITO) or indium zinc oxide (IZO). The blocking electrode 40b includes a first blocking electrode 401b, a second blocking electrode 402b, a third blocking electrode 403b, and a fourth blocking electrode 404b sequentially arranged from bottom to top. The first blocking electrode 401b is formed in the same layer as the first titanium layer 401, the second blocking electrode 402b is formed in the same layer as the aluminum layer 402, the third blocking electrode 403b is formed in the same layer as the third titanium layer 403, and the fourth blocking electrode 404b is formed in the same layer as the transparent metal oxide film layer 404.

[0139] Optionally, the first electrode 40 and the blocking electrode 40b may include two transparent metal oxide film layers and a metal film layer located between the two transparent metal oxide film layers (not shown in the figure). The material of the transparent metal oxide film layer may be indium tin oxide (ITO) or indium zinc oxide (IZO), and the material of the metal film layer may be metallic silver.

[0140] In some exemplary embodiments, the first electrode 40 and the blocking electrode 40b are spaced apart. The first electrode 40 is connected to the subsequently formed organic light-emitting layer 60, and the blocking electrode 40b forms a blocking portion with the subsequently formed first flat portion 41a and second flat portion 41b.

[0141] (25) Forming the first flat portion and the second flat portion. In an exemplary embodiment, forming the first flat portion and the second flat portion pattern includes: depositing a first flat film on a substrate on which the aforementioned pattern is formed, and patterning the first flat film using a patterning process to form the first flat portion 41a and the second flat portion 41b pattern disposed on the first insulating layer 30, such as... Figure 11 As shown.

[0142] In some exemplary embodiments, the first flat portion 41a and the second flat portion 41b are disposed in the gap region between the first electrode 40 and the blocking electrode 40b, and the first flat portion 41a and the second flat portion 41b fill the gap region between the electrode 40 and the blocking electrode 40b. Along a direction perpendicular to the display substrate, the height difference between the first flat portion 41a and the second flat portion 41b and the height of the first electrode layer 40 is less than or equal to the thickness of any conductive layer in the first electrode 40. Exemplarily, the height of the first flat portion 41a and the second flat portion 41b can be the same as the height of the first electrode layer 40.

[0143] (26) Etching the isolation electrode 40b. In an exemplary embodiment, since the etching rate of the third isolation electrode 403b is close to the etching rate of the fourth isolation electrode 404b, the third isolation electrode 403b and the fourth isolation electrode 404b form a second sub-isolation opening K22. The etching rate of the second isolation electrode 402b is greater than the etching rate of the third isolation electrode 403b (or the etching rate of the fourth isolation electrode 404b), and the second isolation electrode 402b forms a first sub-isolation opening K21. The first sub-isolation opening K21 and the second sub-isolation opening K22 form a total isolation opening K2, such as... Figure 12a and Figure 12b As shown. The orthographic projection of the first sub-partition opening K21 on the substrate 10 includes the orthographic projection of the second sub-partition opening K22 on the substrate 10. That is, the orthographic projection of the second sub-partition opening K22 on the substrate 10 falls within the range of the orthographic projection of the first sub-partition opening K21 on the substrate 10. The first sub-partition opening K21 and the second sub-partition opening K22 form a concave structure.

[0144] In an exemplary implementation, such as Figure 12b As shown, along the direction perpendicular to the display substrate, the height h8 of the second sub-partition opening K22 is between 0.4 and 3 times the height h7 of the first sub-partition opening K21.

[0145] For example, such as Figure 12b As shown, the height h8 of the second sub-partition opening K22 is between 400 angstroms and 1500 angstroms, and the height h7 of the first sub-partition opening K21 is between 300 angstroms and 1000 angstroms.

[0146] In an exemplary implementation, such as Figure 12b As shown, along the direction parallel to the display substrate, the distance d1 between the edge of the first sub-partition opening K21 and the edge of the second sub-partition opening K22 is between 0.1 and 1.5 times the width w of the first sub-partition opening K21.

[0147] In an exemplary implementation, such as Figure 12b As shown, along a direction parallel to the display substrate, the distance d1 between the edge of the first sub-partition opening K21 and the edge of the second sub-partition opening K22 is between 0.1 micrometers and 0.6 micrometers.

[0148] In an exemplary implementation, such as Figure 12b As shown, along the direction parallel to the display substrate, the width w of the first sub-partition opening K21 is between 0.4 micrometers and 1 micrometer.

[0149] (27) Form the pattern of the organic light-emitting layer 60 and the second electrode 70.

[0150] To more clearly see whether the charge generation layer (CGL) has experienced film fracture, such as Figure 4 As shown, we simply divide the organic light-emitting layer into 5 layers: the first hole transport layer (HTL1), the red-green light-emitting material layer (RG-EML), the charge generation layer (CGL), the second hole transport layer (HTL2), and the blue light-emitting material layer (B-EML). From Figure 4 The deposition results of these five layers on the substrate forming the aforementioned pattern show that the charge generation layer (CGL) undergoes film fracture at the concave structure of the blocking electrode 40b, thereby preventing crosstalk between adjacent sub-pixels. Simultaneously, the display substrate of this embodiment also reduces the morphological puncture problem of the second electrode above the edge of the first display electrode, improving the display effect. Furthermore, the fabrication process disclosed herein is highly compatible with existing fabrication processes, is simple to implement, easy to execute, has high production efficiency, low production cost, and high yield.

[0151] The structure of the display substrate and its fabrication process shown in this disclosure are merely illustrative examples. In some exemplary embodiments, the corresponding structure and the patterning process may be changed or reduced as needed, and this disclosure does not limit them.

[0152] As can be seen from the structure and fabrication process of the display substrate in this embodiment, by setting an isolation opening on the pixel definition layer and a side-recessed structure within the isolation opening, and the height of the side-recessed structure being greater than or equal to the height difference between the charge generation layer and the first electrode, the charge generation layers between adjacent sub-pixels are effectively isolated, avoiding crosstalk between adjacent sub-pixels and reducing the second electrode puncture problem at the light-emitting edge of the organic light-emitting layer. The fabrication process disclosed herein can be realized using mature fabrication equipment, requires minimal process modification, has high compatibility, a simple process flow, is easy to periodically maintain equipment, has high production efficiency, low production cost, high yield, and is suitable for large-scale mass production. The fabricated display substrate can be used in virtual reality devices or augmented reality devices, or in other types of display devices, and has good application prospects.

[0153] This disclosure also provides a method for fabricating a display substrate to prepare the display substrate provided in the above embodiments. In some exemplary embodiments, the method for fabricating the display substrate may include the following steps:

[0154] A first electrode is formed on a substrate. The first electrode includes at least one conductive layer. A partition portion is provided between the first electrodes of adjacent sub-pixels. The partition portion includes at least one partition opening. The partition opening includes a first surface near the substrate, a second surface away from the substrate, and a third side surface disposed between the first surface and the second surface. The third side surface includes at least one side recess structure. In a direction perpendicular to the display substrate, the height difference between the surface of the partition portion away from the substrate and the surface of the first electrode away from the substrate is less than or equal to the thickness of any conductive layer.

[0155] An organic light-emitting layer is formed on the first electrode. The organic light-emitting layer includes a plurality of light-emitting layers of different colors stacked together and a charge-generating layer disposed between the plurality of light-emitting layers of different colors. In a direction parallel to the display substrate, the charge-generating layer is discontinuous at the position of the side recess structure.

[0156] A second electrode is formed on the organic light-emitting layer.

[0157] The display substrate prepared by the method of preparing the display substrate disclosed herein has a similar implementation principle and effect to the aforementioned display substrate, and will not be described again here.

[0158] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. As a silicon-based OLED microdisplay, the display device can be applied to helmet displays, stereoscopic displays, and eye-mounted displays, etc.

[0159] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, include: A substrate and a plurality of sub-pixels located on the substrate; The sub-pixel includes a first electrode, an organic light-emitting layer, and a second electrode arranged sequentially. The first electrode includes at least one conductive layer. A partition is provided between the first electrodes of adjacent sub-pixels. The partition includes at least one partition opening. The organic light-emitting layer includes multiple light-emitting layers of different colors stacked together and a charge-generating layer disposed between the multiple light-emitting layers of different colors. The partition opening includes a first surface near the substrate, a second surface away from the substrate, and a third side surface disposed between the first and second surfaces. The third side surface includes at least one recessed structure. In a direction perpendicular to the display substrate, the height difference between the surface of the partition away from the substrate and the surface of the first electrode away from the substrate is less than or equal to the thickness of any conductive layer. The display substrate includes multiple pixel definition layers stacked together, the multiple pixel definition layers forming at least one side-concave structure, the multiple pixel definition layers and the first electrode being located away from the surface of the substrate, and each of the multiple pixel definition layers being flush with the same height at the junction of the pixel definition layer and the first electrode.

2. The display substrate according to claim 1, characterized in that, In a direction perpendicular to the display substrate, the distance between the surface of the charge generating layer away from the substrate and the surface of the first electrode away from the substrate is less than or equal to the height of the side recess structure.

3. The display substrate according to claim 1, characterized in that, In a direction perpendicular to the display substrate, the surface of the partition portion away from the substrate is flush with the surface of the first electrode away from the substrate.

4. The display substrate according to claim 1, characterized in that, It also includes a first insulating layer located on the side of the first electrode near the substrate; the partition portion further includes an etching barrier layer disposed between the partition opening and the first insulating layer, and the orthographic projection of the etching barrier layer on the substrate covers the orthographic projection of the partition opening on the substrate.

5. The display substrate according to claim 1, characterized in that, The second electrode includes at least one second electrode slope, the orthographic projection of the second electrode slope on the substrate overlaps with the orthographic projection of the side concave structure on the substrate, and the distance from the upper edge of the first electrode near the partition opening to any point on the second electrode slope is equal to or approximately equal to the height difference between the first electrode and the second electrode.

6. The display substrate according to claim 1, characterized in that, The orthographic projection of the pixel definition layer on the substrate does not overlap with the orthographic projection of the first electrode on the substrate.

7. The display substrate according to claim 6, characterized in that, The pixel definition layer includes a first pixel definition layer and a second pixel definition layer stacked sequentially from bottom to top, wherein: The first pixel definition layer includes a first sub-isolation port, and the second pixel definition layer includes a second sub-isolation port. The first sub-isolation port and the second sub-isolation port are interconnected, and the orthographic projection of the first sub-isolation port on the substrate is greater than the orthographic projection of the second sub-isolation port on the substrate. The first sub-isolation port and the second sub-isolation port form a first side-concave structure.

8. The display substrate according to claim 7, characterized in that, Along a direction parallel to the display substrate, the distance between the edge of the first sub-partition opening and the edge of the second sub-partition opening is between 0.1 and 1.5 times the width of the first sub-partition opening.

9. The display substrate according to claim 7, characterized in that, The pixel definition layer further includes a third pixel definition layer and a fourth pixel definition layer stacked on top of the second pixel definition layer, wherein: The third pixel definition layer includes a third sub-isolation port, and the fourth pixel definition layer includes a fourth sub-isolation port. The first sub-isolation port, the second sub-isolation port, the third sub-isolation port, and the fourth sub-isolation port are interconnected. The orthographic projection of the third sub-isolation port on the substrate is greater than the orthographic projection of the fourth sub-isolation port on the substrate. The third sub-isolation port and the fourth sub-isolation port form a second concave structure.

10. The display substrate according to claim 9, characterized in that, The area where the edge of the first electrode near the partition opening connects to the side of the first pixel definition layer is greater than the area where the edge of the first electrode near the partition opening connects to the side of other pixel definition layers.

11. The display substrate according to claim 9, characterized in that, Along a direction perpendicular to the display substrate, the thickness of the first pixel definition layer is greater than the thickness of the second pixel definition layer, and the thickness of the third pixel definition layer is greater than the thickness of the fourth pixel definition layer.

12. A display device, characterized in that, include: The display substrate as described in any one of claims 1 to 11.

13. A method for preparing a display substrate, characterized in that, The display substrate includes multiple sub-pixels, and the fabrication method includes: A first electrode and a multilayer pixel definition layer are sequentially formed on a substrate. The first electrode includes at least one conductive layer. A partition portion is provided on the pixel definition layer between the first electrodes of adjacent sub-pixels. The partition portion includes at least one partition opening. The partition opening includes a first surface near the substrate, a second surface away from the substrate, and a third side surface disposed between the first surface and the second surface. The third side surface includes at least one side recess structure. In a direction perpendicular to the display substrate, the height difference between the surface of the partition portion away from the substrate and the surface of the first electrode away from the substrate is less than or equal to the thickness of any conductive layer. A polishing process is used to make the multilayer pixel definition layers flush with the surface of the first electrode away from the substrate. Each of the multilayer pixel definition layers is flush with the first electrode at the junction of the pixel definition layer and the first electrode. An organic light-emitting layer is formed on the first electrode. The organic light-emitting layer includes a plurality of light-emitting layers of different colors stacked together and a charge-generating layer side recess disposed between the plurality of light-emitting layers of different colors. A second electrode is formed on the organic light-emitting layer.

Images