Electroluminescent display panel and display device

Abstract

The present disclosure discloses an electroluminescent display panel and a display device, wherein the electroluminescent display panel comprises: a plurality of repeating units, each repeating unit comprises a plurality of sub-pixels, each sub-pixel comprises: a first conductive layer, located above a substrate; a first insulating layer, located above the first conductive layer and comprising a first via hole, the first via hole exposing a portion of the first conductive layer; an anode, located on the first insulating layer and comprising a main part and an auxiliary part, which are electrically connected to each other; the auxiliary part is electrically connected to the first conductive layer through the first via hole; in at least one sub-pixel, an orthographic projection of the main part on the substrate does not overlap with an orthographic projection of the first via hole on the substrate.

Description

[0001] This patent application document is a divisional application of the invention patent application document with application date of July 31, 2019, application number 201980001210.3, and invention name “Electroluminescent Display Panel and Display Device”. Technical Field

[0002] The embodiments of the present disclosure relate to the field of display technology, and in particular to an electroluminescent display panel and a display device. Background Art

[0003] With the continuous development of display technology, organic light emitting diode (OLED) display panels have been increasingly used in various electronic devices due to their advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, and high response speed. With the increasing requirements for OLED display panels, in order to achieve high-resolution design in display panels, OLED display panels usually adopt SPR pixel arrangement, that is, pixel borrowing method. Summary of the invention

[0004] The embodiment of the present disclosure provides a display substrate, including a base substrate, a plurality of sub-pixels; the plurality of sub-pixels include a planar layer, an anode layer, and a plurality of pixel driving circuits; the plurality of pixel driving circuits include a first conductive layer; the first conductive layer, the planar layer, and the anode layer are sequentially arranged in a direction away from the base substrate;

[0005] The first conductive layer includes a plurality of power lines extending along the second direction and arranged at intervals, a plurality of data lines extending along the second direction and arranged at intervals, and a plurality of anode transfer blocks; wherein the plurality of power lines extending along the second direction include adjacent first power lines and second power lines, and the plurality of data lines extending along the second direction include adjacent first data lines and second data lines;

[0006] The anode layer includes a plurality of anodes, and the plurality of pixel driving circuits drive corresponding anodes respectively; the first anode of the first sub-pixel overlaps with the orthographic projections of the first power line, the second power line, the first data line, and the second data line on the substrate;

[0007] The anode is directly connected to the anode adapter block; the first anode has a bisector in the first direction, the first power line and the first data line are located on one side of the bisector, and the second power line and the second data line are located on the other side of the bisector; wherein the first direction intersects with the second direction.

[0008] In some examples, the multiple sub-pixels include a reference conductive layer and a second interlayer insulating layer arranged in a direction away from the base substrate, the first power line is electrically connected to the first capacitor upper plate of the reference conductive layer through a first via hole penetrating the second interlayer insulating layer, the second power line is electrically connected to the second capacitor upper plate of the reference conductive layer through a second via hole penetrating the second interlayer insulating layer, the orthographic projection of the first anode on the base substrate overlaps with the orthographic projection of the first via hole on the base substrate and the orthographic projection of the second via hole on the base substrate, and the overlapping areas are approximately equal.

[0009] In some examples, the multiple sub-pixels also include an active semiconductor layer and a first interlayer insulating layer arranged in sequence in a direction away from the base substrate, the first interlayer insulating layer includes a third via and a fourth via, the source level of the fifth transistor of the first sub-pixel is electrically connected to the first power line through the third via, and the source level of the fifth transistor of the second sub-pixel is electrically connected to the second power line through the fourth via; the orthographic projection of the first anode on the base substrate overlaps with the orthographic projection of the third via on the base substrate and the orthographic projection of the fourth via on the base substrate, respectively.

[0010] In some examples, the orthographic projection of the anode of the second sub-pixel on the substrate does not overlap with the orthographic projection of the lower plate of the capacitor of the corresponding pixel driving circuit on the substrate, the orthographic projection of the power line of the second sub-pixel on the substrate overlaps with the orthographic projection of the lower plate of the capacitor corresponding to the second sub-pixel on the substrate, and the lower plate of the capacitor also serves as the gate of the driving transistor; the lower plate of the capacitor is located on the side of the upper plate of the capacitor close to the substrate.

[0011] In some examples, the orthographic projection of the first anode on the substrate overlaps with the orthographic projection of a light emitting control signal line on the substrate, the light emitting control signal line is used to control the opening of a light emitting control transistor, and the drain of the light emitting control transistor is connected to the anode.

[0012] In some examples, the orthographic projection of the third anode of the third subpixel on the substrate overlaps with the orthographic projection of the third power line on the substrate, the orthographic projection of the fourth power line on the substrate, the orthographic projection of the third data line on the substrate, and the orthographic projection of the fourth data line on the substrate, and the third anode overlaps with the reset power signal line of the third subpixel, and the reset power signal line is used to provide a reset voltage to the third anode.

[0013] In some examples, the reset power signal line is connected to the source of the reset transistor via a first connection portion extending along the second direction, and an orthographic projection of the third anode on the base substrate overlaps an orthographic projection of the first connection portion on the base substrate.

[0014] In some examples, the orthographic projection of the first anode on the substrate overlaps with the orthographic projection of the lower plate of the capacitor of the first sub-pixel on the substrate and the orthographic projection of the lower plate of the capacitor of the second sub-pixel on the substrate, and the first sub-pixel is adjacent to the second sub-pixel.

[0015] In some examples, the upper plate of the capacitor of the first sub-pixel has a fifth via, the upper plate of the capacitor of the second sub-pixel has a sixth via, the drain of the compensation transistor of the first sub-pixel is connected to the lower plate of the capacitor through the fifth via, and the drain of the compensation transistor of the second sub-pixel is connected to the lower plate of the capacitor through the sixth via; the fifth via is closer to the bisector of the first anode in the first direction than the sixth via.

[0016] In some examples, the orthographic projection of the fourth anode on the substrate overlaps with the orthographic projection of the second connection portion of a pixel driving circuit on the substrate, and the orthographic projection of the second anode on the substrate overlaps with the orthographic projection of the second connection portion of another pixel driving circuit on the substrate, and the second connection portion is used to connect the drain of the compensation transistor and the gate of the driving transistor.

[0017] In some examples, the first anode is connected to the first anode adapter block through the first anode hole, the second anode is connected to the second anode adapter block through the second anode hole, the third anode is connected to the third anode adapter block through the third anode hole, and the fourth anode is connected to the fourth anode adapter block through the fourth anode hole, and the fourth anode hole and the second anode hole do not overlap with the third effective light-emitting area and the fourth effective light-emitting area in the second direction; the light-emitting color of the fourth sub-pixel and the second sub-pixel is different from the light-emitting color of the first sub-pixel.

[0018] In some examples, the orthographic projection of the third anode on the substrate has a first overlapping portion with the orthographic projection of the third power line on the substrate, and the orthographic projection of the third anode on the substrate has a second overlapping portion with the orthographic projection of the fourth data line on the substrate, and the first overlapping portion and the second overlapping portion are respectively located on both sides of a bisector of the third anode in the first direction.

[0019] In some examples, the sizes of the first anode and the third anode in the first direction are both larger than their sizes in the second direction; the orthographic projection of the second anode on the substrate overlaps with the orthographic projection of a power line on the substrate, and the orthographic projection of the fourth anode on the substrate overlaps with the orthographic projection of another power line on the substrate.

[0020] In some examples, in the first direction, a maximum span between the second anode and the fourth anode is greater than a maximum span of the first anode.

[0021] In some examples, an axis of symmetry is defined between adjacent second anodes and fourth anodes, and adjacent second anodes and fourth anodes are symmetrically disposed about the axis of symmetry.

[0022] In some examples, the light emitting color of the first sub-pixel is different from the light emitting color of the second sub-pixel.

[0023] In some examples, the second subpixel includes the second anode, and the fourth subpixel includes the fourth anode;

[0024] The second sub-pixel and the fourth sub-pixel emit the same light color.

[0025] The embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a is a schematic diagram of a top view structure of a display panel in the related art;

[0027] Figure 1b for Figure 1a A schematic cross-sectional structure diagram of the display panel along the AA' direction is shown;

[0028] Figure 2a is a schematic diagram of the structure of some pixel driving circuits in the present disclosure;

[0029] Figure 2b Schematic diagram of the top view structure of some active semiconductor layers in the present disclosure;

[0030] Figure 2c Schematic diagram of top view structure of some gate conductive layers in the present disclosure;

[0031] Figure 2d Schematic diagrams of top views of some reference conductive layers in the present disclosure;

[0032] Figure 2e Schematic diagram of the top view structure of some source and drain metal layers in the present disclosure;

[0033] Figure 2f Schematic diagram of the top view structure of some auxiliary metal layers in the present disclosure;

[0034] Figure 2g A schematic diagram of the stacking position relationship of the active semiconductor layer, the gate conductive layer, the reference conductive layer, the source and drain metal layer, and the auxiliary metal layer in the present disclosure;

[0035] Figure 3a Schematic diagram of a top view of some display panels in the present disclosure;

[0036] Figure 3b Schematic diagrams of top views of some other display panels in the present disclosure;

[0037] Figure 3c Schematic diagrams of top views of some other display panels in the present disclosure;

[0038] Figure 4 It is a schematic structural diagram of an anode, a first via hole, and a second via hole of some display panels in the present disclosure;

[0039] Figure 5a It is a schematic structural diagram of a first conductive layer, a second via hole, and a third via hole in some display panels of the present disclosure;

[0040] Figure 5b Schematic diagram of the structure of the first conductive layer, the second via hole and the third via hole in some other display panels in the present disclosure;

[0041] Figure 6a for Figure 3a A schematic cross-sectional structure diagram of the display panel along the AA' direction is shown;

[0042] Figure 6b for Figure 3a A schematic diagram of a cross-sectional structure of a display panel along the BB' direction is shown;

[0043] Figure 6c for Figure 3b A schematic cross-sectional structure diagram of the display panel along the AA' direction is shown;

[0044] Figure 7a for Figure 3a A schematic cross-sectional structure diagram of a display panel along the CC' direction is shown;

[0045] Figure 7b for Figure 3a A schematic cross-sectional structure diagram of a display panel along the DD' direction shown;

[0046] Figure 8a for Figure 3a A schematic cross-sectional structure diagram of a display panel along the EE' direction is shown;

[0047] Figure 8b for Figure 3a A schematic cross-sectional structure diagram of the display panel along the FF' direction shown;

[0048] Figure 8c for Figure 3b A schematic diagram of a cross-sectional structure of a display panel along the BB' direction is shown;

[0049] Figure 9a Schematic diagrams of top views of some other display panels in the present disclosure;

[0050] Figure 9b Schematic diagrams of top views of some other display panels in the present disclosure;

[0051] Fig.10 for Figure 9a A schematic structural diagram of an anode and a first via hole of a display panel shown;

[0052] Fig.11 for Figure 9a A schematic structural diagram of a first conductive layer and a first via hole in the display panel shown;

[0053] Fig.12 for Figure 9a A schematic cross-sectional structure diagram of the display panel along the AA' direction is shown;

[0054] Fig.13 for Figure 9a A schematic diagram of a cross-sectional structure of a display panel along the BB' direction is shown;

[0055] Fig.14 for Figure 9a A schematic cross-sectional structure diagram of a display panel along the CC' direction is shown;

[0056] Fig.15 for Figure 9a A schematic cross-sectional structure diagram of a display panel along the DD' direction shown;

[0057] Fig.16 for Figure 9b A schematic cross-sectional structure diagram of the display panel along the AA' direction is shown;

[0058] Fig.17 for Figure 9b The cross-sectional structure diagram of the display panel along the BB' direction is shown. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0060] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "electrically connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0061] A typical OLED display panel includes a base substrate, a pixel driving circuit arranged on the base substrate, a planar layer arranged on a side of the pixel driving circuit away from the base substrate, an anode arranged on a side of the planar layer away from the base substrate, a light-emitting layer arranged on a side of the anode away from the base substrate, and a cathode arranged on a side of the light-emitting layer away from the base substrate.

[0062] Figure 1a Schematic diagram of the top view structure of some display panels. Figure 1b for Figure 1a The cross-sectional structure diagram of the display panel along the AA' direction is shown in FIG. Figure 1a and Figure 1b As shown, the display panel may include: a substrate 10, a pixel driving circuit 20, a flat layer 30, an anode 40, a light-emitting layer 50, a cathode 60 and a pixel defining layer 80; the pixel defining layer 80 has an opening to define an effective light-emitting area through the opening. Among them, the pixel driving circuit 20 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, and the generated electrical signal is input to the anode 40 through the connecting line 21. And the cathode 60 is loaded with a corresponding voltage, which can drive the light-emitting layer 50 to emit light. The flat layer 30 has a via 31, and the anode 40 is electrically connected to the connecting line 21 through the via 31. However, since the via 31 has a certain depth, the anode 40 and the light-emitting layer 50 on the anode 40 are recessed in the area where the via 31 exists, resulting in an uneven anode 40, which in turn causes the display panel to produce a color shift phenomenon.

[0063] Combination Figure 2a As shown, the pixel driving circuit 0121 may include: a pixel driving circuit 0122, a first light emitting control circuit 0123, a second light emitting control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128 and a reset circuit 0129. The pixel driving circuit 0122 includes a control terminal, a first terminal and a second terminal, and is configured to provide a driving current for driving the light emitting element 0120 to emit light to the light emitting element 0120. For example, the first light emitting control circuit 0123 is connected to the first terminal of the pixel driving circuit 0122 and the first voltage terminal VDD, and is configured to realize the connection between the pixel driving circuit 0122 and the first voltage terminal VDD is turned on or off, and the second light emitting control circuit 0124 is electrically connected to the second terminal of the pixel driving circuit 0122 and the first light emitting voltage applying electrode of the light emitting element 0120, and is configured to realize the connection between the pixel driving circuit 0122 and the light emitting element 0120 is turned on or off. The data writing circuit 0126 is electrically connected to the first terminal of the pixel driving circuit 0122, and is configured to write the data signal into the storage circuit 0127 under the control of the scanning signal; the storage circuit 0127 is electrically connected to the control terminal and the first voltage terminal VDD of the pixel driving circuit 0122, and is configured to store the data signal; the threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the pixel driving circuit 0122, and is configured to perform threshold compensation on the pixel driving circuit 0122; the reset circuit 0129 is electrically connected to the control terminal of the pixel driving circuit 0122 and the first light emitting voltage applying electrode of the light emitting element 0120, and is configured to reset the control terminal of the pixel driving circuit 0122 and the first light emitting voltage applying electrode of the light emitting element 0120 under the control of the reset control signal. Among them, the light emitting device 0120 includes an anode 40, a light emitting layer 50, and a cathode 60 arranged in a stacked manner.

[0064] For example, in combination Figure 2a As shown, the pixel driving circuit 0122 includes: a driving transistor T1, the control end of the pixel driving circuit 0122 includes the gate of the driving transistor T1, the first end of the pixel driving circuit 0122 includes the first electrode of the driving transistor T1, and the second end of the pixel driving circuit 0122 includes the second electrode of the driving transistor T1.

[0065] For example, in combination Figure 2aAs shown, the data write circuit 0126 includes a data write transistor T2, the storage circuit 0127 includes a third capacitor C2, the threshold compensation circuit 0128 includes a threshold compensation transistor T3, the first light-emitting control circuit 0123 includes a first light-emitting control transistor T4, the second light-emitting control circuit 0124 includes a second light-emitting control transistor T5, the reset circuit 0129 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.

[0066] Specifically, the first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1, the second electrode of the data writing transistor T2 is configured to be electrically connected to the data line Vd to receive the data signal, and the gate of the data writing transistor T2 is configured to be electrically connected to the first scanning signal line Ga1 to receive the scanning signal; the first electrode of the third capacitor C2 is electrically connected to the first power supply terminal VDD, and the second electrode of the third capacitor C2 is electrically connected to the gate of the driving transistor T1; the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the gate of the threshold compensation transistor T3 is configured to be electrically connected to the second scanning signal line Ga2 to receive the compensation control signal; the first electrode of the first reset transistor T6 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal, the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1, and the gate of the first reset transistor T6 is configured to be electrically connected to the first reset control signal line Rst1 to receive the first sub-reset control signal; the second reset The first electrode of the transistor T7 is configured to be electrically connected to the second reset power supply terminal Vinit2 to receive the second reset signal, the second electrode of the second reset transistor T7 is electrically connected to the first light-emitting voltage applying electrode of the light-emitting element 120, and the gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2 to receive the second sub-reset control signal; the first electrode of the first light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD, the second electrode of the first light-emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate of the first light-emitting control transistor T4 is configured to be electrically connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal; the first electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the second light-emitting control transistor T5 is electrically connected to the first light-emitting voltage applying electrode of the light-emitting element 120, and the gate of the second light-emitting control transistor T5 is configured to be electrically connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal; the second light-emitting voltage applying electrode of the light-emitting element 120 is electrically connected to the second power supply terminal VSS. The first electrode and the second electrode can be determined as a source electrode or a drain electrode according to actual application, and are not limited here.

[0067] Exemplarily, one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal. Figure 2a In the illustrated embodiment, the first power supply terminal VDD is a voltage source to output a constant first voltage, the first voltage being a positive voltage, and the second power supply terminal VSS is a voltage source to output a constant second voltage, the second voltage being a negative voltage, etc. For example, in some examples, the second power supply terminal VSS may be grounded.

[0068] It should be noted that, in the embodiment of the present disclosure, the pixel driving circuit of the sub-pixel can be Figure 2a In addition to the structure shown, the structure may also include other numbers of transistors, which is not limited in the embodiments of the present disclosure.

[0069] Figure 2b to Figure 2g Schematic diagram of each layer of the pixel driving circuit provided in some embodiments of the present disclosure. Figure 2b~2g Describe the positional relationship of each circuit in the pixel driving circuit on the substrate, Figure 2b~2g The example shown takes a pixel driving circuit of a sub-pixel as an example. Figure 2b~2g Also shown are the first scanning signal line Ga1a, the second scanning signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first reset power signal line Init1a of the first reset power terminal Vinit1a, the second reset power signal line Init2a of the second reset power terminal Vinit2a, the first light emitting control signal line EM1a, the second light emitting control signal line EM2a, the data line Vd, the first power signal line VDD1 of the first power terminal VDD, and the second power signal line VDD2. The first power signal line VDD1 and the second power signal line VDD2 are electrically connected to each other. It should be noted that in Figure 2b~2g In the example shown, the first scanning signal line Ga1a and the second scanning signal line Ga2a are the same signal line, the first reset power signal line Init1a and the second reset power signal line Init2a are the same signal line, the first reset control signal line Rst1a and the second reset control signal line Rst2a are the same signal line, and the first light-emitting control signal line EM1a and the second light-emitting control signal line EM2a are the same signal line.

[0070] For example, Figure 2bThe active semiconductor layer 0310 of the pixel driving circuit 0121 is shown. The active semiconductor layer 0310 can be formed by patterning a semiconductor material. The active semiconductor layer 0310 can be used to make the active layers of the above-mentioned driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7, and each active layer may include a source region, a drain region and a channel region between the source region and the drain region. For example, the active layers of each transistor are arranged in one piece.

[0071] For example, the active semiconductor layer 0310 may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and the drain region may be regions doped with n-type impurities or p-type impurities.

[0072] For example, the gate metal layer of the pixel driving circuit 0121 may include a gate conductive layer 0320. A gate insulating layer (not shown) is formed on the active semiconductor layer 0310 to protect the active semiconductor layer 0310. Figure 2c The gate conductive layer 0320 of the pixel driving circuit 0121 is shown, and the gate conductive layer 0320 is disposed on the gate insulating layer, thereby being insulated from the active semiconductor layer 0310. The gate conductive layer 0320 may include a second electrode CC2a of the third capacitor C2, a first scanning signal line Ga1a, a second scanning signal line Ga2a, a first reset control signal line Rst1a, a second reset control signal line Rst2a, a first light emission control signal line EM1a, a second light emission control signal line EM2a, and gates of a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7.

[0073] For example, Figure 2cAs shown, the gate of the data writing transistor T2 may be the portion where the first scanning signal line Ga1a overlaps with the active semiconductor layer 0310, the gate of the first light emission control transistor T4 may be the first portion where the first light emission control signal line EM1a / the second light emission control signal line EM2a overlaps with the active semiconductor layer 0310, the gate of the second light emission control transistor T5 may be the second portion where the first light emission control signal line EM1a / the second light emission control signal line EM2a overlaps with the active semiconductor layer 0310, the gate of the first reset transistor T6 may be the first reset control signal line Rst1a / the second reset control signal line Rst2a. The signal line Rst2a overlaps the first part of the active semiconductor layer 0310, the gate of the second reset transistor T7 is the second part of the first reset control signal line Rst1a / the second reset control signal line Rst2a overlaps the active semiconductor layer 0310, the threshold compensation transistor T3 may be a thin film transistor with a dual-gate structure, the first gate of the threshold compensation transistor T3 may be the part of the second scanning signal line Ga2a overlapping the active semiconductor layer 0310, and the second gate of the threshold compensation transistor T3 may be the part of the protrusion protruding from the second scanning signal line Ga2a overlapping the active semiconductor layer 0310. Figure 2a and 2c As shown, the gate of the driving transistor T1 may be the second electrode CC2a of the third capacitor C2.

[0074] It should be noted that Figure 2b The dashed rectangular boxes in 030 show the portions where the gate conductive layer 0320 overlaps with the active semiconductor layer 0310 .

[0075] For example, Figure 2c As shown, the first scanning signal line Ga1a / the second scanning signal line Ga2a, the first reset control signal line Rst1a / the second reset control signal line Rst2a and the first light emission control signal line EM1a / the second light emission control signal line EM2a are arranged along the second direction F2. The first scanning signal line Ga1a / the second scanning signal line Ga2a is located between the first reset control signal line Rst1a / the second reset control signal line Rst2a and the first light emission control signal line EM1a / the second light emission control signal line EM2a.

[0076] For example, in the second direction F2, the second electrode CC2a of the third capacitor C2 is located between the first scanning signal line Ga1a / the second scanning signal line Ga2a and the first light emission control signal line EM1 / a and the second light emission control signal line EM2a. The protrusion protruding from the second scanning signal line Ga2a is located on the side of the second scanning signal line Ga2a away from the first light emission control signal line EM1a / the second light emission control signal line EM2a.

[0077] For example, combined with Figure 2bAs shown, in the second direction F2, the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 are all located on the first side of the gate of the driving transistor T1, and the gate of the first light emitting control transistor T4 and the gate of the second light emitting control transistor T5 are all located on the second side of the gate of the driving transistor T1.

[0078] For example, in some embodiments, Figure 2b to Figure 2g As shown, in the first direction F1, the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located on the third side of the gate of the driving transistor T1, and the first gate of the threshold compensation transistor T3, the gate of the second light emission control transistor T5 and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1. The third side and the fourth side of the gate of the driving transistor T1 are two sides of the gate of the driving transistor T1 that are opposite to each other in the first direction F1.

[0079] For example, a first interlayer insulating layer (not shown) is formed on the gate conductive layer 0320 to protect the gate conductive layer 0320 . Figure 2d The reference conductive layer 0330 of the pixel driving circuit 120a is shown, and the reference conductive layer 0330 includes a first electrode CC1a of the third capacitor C2, a first reset power signal line Init1a, and a second reset power signal line Init2a. The first electrode CC1a of the third capacitor C2 at least partially overlaps with the second electrode CC2a of the third capacitor C2 to form the third capacitor C2.

[0080] For example, a second interlayer insulating layer (not shown) is formed on the reference conductive layer 0330 to protect the reference conductive layer 0330 . Figure 2e The source-drain metal layer 0340 of the pixel driving circuit 0121 is shown. The source-drain metal layer 0340 includes a data line Vd and a first power signal line VDD1.

[0081] For example, a third interlayer insulating layer (not shown) is formed on the source-drain metal layer 0340 to protect the source-drain metal layer 0340 . Figure 2f The auxiliary metal layer 0350 of the pixel driving circuit 0121 is shown, and the auxiliary metal layer 0350 includes a second power signal line VDD2.

[0082] Figure 2g Schematic diagram of the stacking position relationship of the active semiconductor layer 0310, the gate conductive layer 0320, the reference conductive layer 0330, the source and drain metal layer 0340, and the auxiliary metal layer 0350. Figure 2e to Figure 2gAs shown, the data line Vd is electrically connected to the source region of the data writing transistor T2 in the active semiconductor layer 0310 through at least one via hole (e.g., via hole 381a) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The first power signal line VDD1 is electrically connected to the source region of the corresponding first light emission control transistor T4 in the active semiconductor layer 0310 through at least one via hole (e.g., via hole 382a) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The first power signal line VDD1 is electrically connected to the first electrode CC1a of the third capacitor C2 in the reference conductive layer 0330 through at least one via hole (e.g., via hole 3832a) in the second insulating layer. The first power signal line VDD1 is also electrically connected to the second power signal line VDD2 in the auxiliary metal layer 0350 through at least one via hole (e.g., via hole 3831a) in the second insulating layer.

[0083] For example, Figure 2e and 2g As shown, the source-drain metal layer 0340 further includes a connection portion 341a, a connection portion 342a, and a connection portion 343a. One end of the connection portion 341a is electrically connected to the drain region of the corresponding threshold compensation transistor T3 in the active semiconductor layer 0310 through at least one via hole (e.g., via hole 384a) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The other end of the connection portion 341a is electrically connected to the gate of the driving transistor T1 in the gate conductive layer 0320 (i.e., the second electrode CC2a of the third capacitor C2) through at least one via hole (e.g., via hole 385a) in the first interlayer insulating layer and the second interlayer insulating layer. One end of the connection portion 342a is electrically connected to the first reset power signal line Init1a / the second reset power signal line Init2a through a via hole (e.g., via hole 386a) in the second insulating layer, and the other end of the connection portion 342a is electrically connected to the drain region of the second reset transistor T7 in the active semiconductor layer 0310 through at least one via hole (e.g., via hole 387a) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The connection portion 343a is electrically connected to the drain region of the second light emission control transistor T5 in the active semiconductor layer 0310 through at least one via hole (e.g., via hole 388a) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer.

[0084] For example, Figure 2f and 2g As shown, the auxiliary metal layer 0350 further includes a connection portion 351a. The connection portion 351a is electrically connected to the connection portion 343a through a via hole (eg, via hole 385b) penetrating the third interlayer insulating layer.

[0085] For example, Figure 2b to Figure 2gAs shown, in the second direction F2, the first scanning signal line Ga1a, the second scanning signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first reset power signal line Init1a and the second reset power signal line Init2a are all located on the first side of the gate of the driving transistor T1, and the first light-emitting control signal line EM1a and the second light-emitting control signal line EM2a are both located on the second side of the driving transistor T1.

[0086] For example, the first scanning signal line Ga1a, the second scanning signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first light-emitting control signal line EM1a, the second light-emitting control signal line EM2a, the first reset power signal line Init1a and the second reset power signal line Init2a all extend along the first direction F1, and the data line Vd extends along the second direction F2.

[0087] For example, the first power signal line VDD1 extends along the second direction F2, and the second power signal line VDD2 extends along the second direction F2. That is, on the entire display substrate, the first power signal line VDD1 and the second power signal line VDD2 are electrically connected, so that the signal line of the first power terminal VDD has a smaller resistance and a lower voltage drop, thereby improving the stability of the power voltage provided by the first power terminal VDD.

[0088] For example, the first scanning signal line Ga1a, the second scanning signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first light emission control signal line EM1a, the second light emission control signal line EM2a are located on the same layer, the first reset power signal line Init1a, the second reset power signal line Init2a, and the second power signal line VDD2a are located on the same layer. The first power signal line VDD1 and the data line Vd are located on the same layer.

[0089] It should be noted that the positional arrangement relationship of the pixel driving circuit, the first light emitting control circuit, the second light emitting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit and the reset circuit in each pixel driving circuit is not limited to Figure 2b to Figure 2g In the example shown, the positions of the pixel driving circuit, the first light emitting control circuit, the second light emitting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit and the reset circuit can be specifically set according to actual application requirements.

[0090] Combination Figures 3a to 8cAs shown, the electroluminescent display panel provided by the embodiment of the present disclosure may include a plurality of repeating units 001, each repeating unit 001 includes a plurality of sub-pixels, and each sub-pixel may include: a first conductive layer 200 located above a substrate 100, a first insulating layer 300 located above the first conductive layer 200, and an anode 400 located on the first insulating layer 300. The first insulating layer 300 includes a first via hole 310, and the first via hole 310 exposes a portion of the first conductive layer 200. The anode 400 includes a main portion 410 and an auxiliary portion 420 electrically connected to each other, and the auxiliary portion 420 is electrically connected to the first conductive layer 200 through the first via hole 310. In at least one sub-pixel, the orthographic projection of the main portion 410 on the substrate 100 does not overlap with the orthographic projection of the first via hole 310 on the substrate 100. Furthermore, in at least one sub-pixel, the size of the main body 410 in the first direction F1 is larger than the size in the second direction F2, and in at least one sub-pixel, the first via 310 and the main body 410 are arranged in the second direction F2; wherein the first direction F1 is different from the second direction F2.

[0091] The electroluminescent display panel provided by the embodiment of the present disclosure is configured such that the anode includes a main body part and an auxiliary part which are electrically connected to each other, and the auxiliary part is electrically connected to the first conductive layer through a first via hole, so that the anode is electrically connected to the pixel driving circuit through the first conductive layer. In addition, in at least one sub-pixel, the size of the main body part in the first direction is larger than the size in the second direction, and in at least one sub-pixel, the first via hole and the main body part are arranged in the second direction; wherein the first direction is different from the second direction. Since in at least one sub-pixel, the orthographic projection of the main body part on the substrate does not overlap with the orthographic projection of the first via hole on the substrate, the first via hole in the sub-pixel can be avoided so that the main body part of the anode in the sub-pixel is not affected by the depth of the first via hole, thereby avoiding the main body part of the anode from being concave, and avoiding the unevenness of the anode caused by the first via hole, thereby improving the color deviation of the display panel.

[0092] In a specific implementation, the first via hole and the main body are arranged in the second direction, for example, the first via hole and the main body are projected on a straight line parallel to the second direction, and the projection of the first via hole and the projection of the main body do not completely overlap, for example, the projection of the first via hole and the projection of the main body do not overlap, or only overlap partially; the first via hole and the main body are projected on a straight line parallel to the first direction, and the projection of the first via hole completely falls within the projection of the main body. In a specific implementation, the first via hole and the main body are arranged in the second direction, for example, the main body has a first side substantially parallel to the first direction, and the first via hole is located on a side of the first side of the main body away from the main body. In a specific implementation, the first via hole and the main body are arranged in the second direction, for example, the angle between a virtual line connecting the center of the first via hole and any point of the main body and the second direction is less than 90°, further, it can be less than 60°, and further, it can be less than 45°.

[0093] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 8c As shown, the main part and the auxiliary part in the same sub-pixel are an integrated structure. For example, the main part and the auxiliary part in the same sub-pixel are formed by a single patterning process.

[0094] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 8c As shown, the first conductive layer 200 may include: a first power line 210 and a first connection line 220 arranged at intervals from each other; wherein, in each sub-pixel, the auxiliary part 420 is electrically connected to the first connection line 220 through the first via hole 310. Exemplarily, the first conductive layer 200 is, for example, the auxiliary metal layer 0350 mentioned above. wherein, the first power line 210 is, for example, the second power signal line VDD2 mentioned above, and the first connection line 220 is, for example, the connection part 351a mentioned above. and the corresponding relationship of the via holes is not repeated here.

[0095] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 8cAs shown, the electroluminescent display panel may further include: a second conductive layer 600 located between the first conductive layer 200 and the substrate 100, and a second insulating layer 500 located between the second conductive layer 600 and the first conductive layer 200. The second conductive layer 600 has a second power line 610 and a second connecting line 620 arranged at intervals. The second insulating layer 500 has a second via hole 520 exposing the second connecting line 620 and a third via hole 630 exposing a portion of the second power line 610. In addition, the first power line 210 is electrically connected to the second power line 610 through the third via hole 530 to achieve the effect of reducing resistance. The first connecting line 220 is electrically connected to the second connecting line 620 through the second via hole 520, and the second connecting line 620 is electrically connected to the drain of the transistor in the pixel driving circuit to achieve signal transmission. Exemplarily, the second conductive layer 600 is, for example, the above-mentioned source-drain metal layer 0340. The second power line 610 is, for example, the first power signal line VDD1, and the second connection line 620 is, for example, the connection portion 343a. The corresponding relationship between the via hole and the insulating layer and the remaining film layers can refer to the implementation of the active semiconductor layer 0310, the gate conductive layer 0320, and the reference conductive layer 0330, which will not be described in detail.

[0096] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 8c As shown, for the first connection line 220 and the second connection line 620 that are electrically connected to each other, the orthographic projection of the first connection line 220 on the substrate 100 overlaps with the orthographic projection of the second connection line 620 on the substrate 100 at least partially. Optionally, the orthographic projection of the first connection line 220 on the substrate 100 overlaps with the orthographic projection of the second connection line 620 on the substrate 100. Optionally, the orthographic projection of the first connection line 220 on the substrate 100 partially overlaps with the orthographic projection of the second connection line 620 on the substrate 100. This can improve the effect of mutual electrical connection.

[0097] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 8c As shown, the orthographic projection of the first power line 210 on the substrate 100 at least partially overlaps with the orthographic projection of the second power line 610 on the substrate 100. Optionally, the orthographic projection of the first power line 210 on the substrate 100 overlaps with the orthographic projection of the second power line 610 on the substrate 100. Optionally, the orthographic projection of the first power line 210 on the substrate 100 partially overlaps with the orthographic projection of the second power line 610 on the substrate 100. This can improve the effect of mutual electrical connection.

[0098] In the specific implementation, in the embodiment of the present disclosure, if Figure 3aAs shown, the third vias 530 are distributed in an array on the substrate 100. Exemplarily, a plurality of third vias 530 are evenly arranged along the first direction F1 and the second direction F2. Exemplarily, the first power line 210 can be configured as a power line for transmitting a driving voltage. In this way, the second power line 610 can also be configured as a power line for transmitting a driving voltage. Thereby, the adverse effect of the load on the transmitted driving voltage can be reduced. Further, in a specific implementation, the second conductive layer 600 also has a data line and a bridge line respectively arranged with the second power line 610 and the second connection line 620. The bridge line is configured to electrically connect two of the gates, sources and drains of some transistors in the pixel driving circuit. The data line is configured to transmit a data signal, and the setting method of the data line and the bridge line can be substantially the same as the setting method in the related art, which will not be repeated here.

[0099] In the specific implementation, in the embodiment of the present disclosure, if Figure 6a As shown, each sub-pixel may further include a pixel defining layer 80 located on the side of the anode 400 facing away from the substrate 100, a light emitting layer 50 located on the side of the anode 400 facing away from the substrate 100, and a cathode 60 located on the side of the anode facing away from the light emitting layer 50. The pixel defining layer 80 has an opening, and the opening exposes at least a portion of the main portion 410 of the anode 400, and the light emitting layer 50 is located in the opening and in contact with the area of ​​the main portion 410 exposed by the opening. Then, the area where the light emitting layer 50 in the opening is located is used for emitting light, so that the effective light emitting area 90 can be defined by the opening. That is, the partial area where the opening of the pixel defining layer 80 overlaps with the main portion 410 of the anode 400 is the effective light emitting area 90 of each sub-pixel. Exemplarily, the partial area where the opening of the pixel defining layer 80 in the third color sub-pixel 030 overlaps with the main portion 413 of the anode 400 is the effective light emitting area 90-030 of the third color sub-pixel 030. The partial area where the opening of the pixel defining layer 80 in the first color sub-pixel 010 overlaps with the main portion 411 of the anode 400 is the effective light-emitting area 90-010 of the first color sub-pixel 010. The partial area where the opening of the pixel defining layer 80 in the second color sub-pixel 021 overlaps with the main portion 4121 of the anode 400 is the effective light-emitting area 90-021 of the second color sub-pixel 021. The partial area where the opening of the pixel defining layer 80 in the second color sub-pixel 022 overlaps with the main portion 4122 of the anode 400 is the effective light-emitting area 90-022 of the second color sub-pixel 022.

[0100] It should be noted that in the embodiments of the present disclosure, each light-emitting layer may include the electroluminescent layer itself and other common layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer, etc., but in the drawings of the present disclosure, only the electroluminescent layer in the light-emitting layer is shown, and other common layers are not shown. Exemplarily, the material of the electroluminescent layer may include: organic electroluminescent material, so that the electroluminescent display panel can be an OLED display panel. Alternatively, the material of the electroluminescent layer may also include: quantum dot electroluminescent material, so that the electroluminescent display panel can be a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display panel.

[0101] In the specific implementation, in the embodiment of the present disclosure, combined with Figure 3a and Figure 4 As shown, in the same sub-pixel, the orthographic projection of the first via hole 310 on the substrate 100 does not overlap with the orthographic projection of the second via hole 520 on the substrate 100. This can avoid the problem that the anode cannot be electrically connected to the second connection line due to the via hole being too deep.

[0102] For example, in a specific implementation, in the embodiments of the present disclosure, if Figure 3a , Figure 3b and Figure 5a As shown, the first power line 210 may include: a plurality of sub-power lines 211 arranged along a first direction F1 and extending along a second direction F2. The first direction F1 is different from the second direction F2. Exemplarily, the first direction F1 is perpendicular to the second direction F2. Exemplarily, the first direction F1 may be a row direction of the display panel, i.e., a direction in which the gate lines extend, and the second direction F2 may be a column direction of the display panel, i.e., a direction in which the data lines extend. Of course, the embodiments of the present disclosure include but are not limited to this.

[0103] In the specific implementation, in the embodiment of the present disclosure, if Figure 3c and Figure 5b As shown, the first power line 210 may include: a plurality of sub-power lines 211 arranged along the first direction F1 and extending along the second direction F2, and a conductive line 212 electrically connecting each sub-power line 211. This can further reduce the resistance of the first power line 210. Exemplarily, the first direction F1 is perpendicular to the second direction F2. Of course, the embodiments of the present disclosure include but are not limited to this.

[0104] In the specific implementation, in the embodiment of the present disclosure, if Figure 3c and Figure 5bAs shown, the sub-power lines 211 and the conducting lines 212 roughly form a grid structure, a first connecting line 220 is disposed inside each grid, and there are intervals between the first connecting line 220 and the sub-power lines 211 and the conducting lines 212 .

[0105] Generally, in the display field, a pixel usually includes multiple sub-pixels that can display a single color (such as red, green or blue). By controlling the ratio of sub-pixels of different colors, different colors can be displayed. Therefore, the above sub-pixels can be single-color sub-pixels. Figures 3a to 4 As shown, each of the multiple repeating units 001 may include: a first color sub-pixel 010, a second color sub-pixel pair 020, and a third color sub-pixel 030 arranged along the second direction F2. Among them, the second color sub-pixel pair 020 may include two second color sub-pixels 021 and 022 arranged along the first direction F1. Among them, the first color sub-pixel 010 is configured to emit light of the first color, the second color sub-pixels 021 and 022 are configured to emit light of the second color, and the third color sub-pixel is configured to emit light of the third color. In some examples, the first color, the second color, and the third color can be selected from red, green, and blue. For example, the first color is red, the second color is green, and the third color is blue. Thus, the repeating unit 001 is an arrangement structure of red, green, and blue sub-pixels. Of course, the embodiments of the present disclosure include but are not limited to this. The above-mentioned first color, second color, and third color may also be other colors.

[0106] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, a plurality of repeating units 001 are arranged along the second direction F2 to form a repeating unit group, the repeating unit group is arranged along the first direction F1, and the repeating units 001 in two adjacent repeating unit groups are arranged in a staggered manner. Exemplarily, the repeating units 001 in two adjacent repeating unit groups differ by 1 / 2 of the size of the repeating unit 001. It should be noted that the size of the above-mentioned one repeating unit 001 can be: the distance between the centers of the same color sub-pixels in two adjacent repeating units 001 in the second direction F2. For example, the size of the above-mentioned one repeating unit 001 can be: the distance between the centers of the first color sub-pixels 010 in two adjacent repeating units 001 in the second direction F2.

[0107] Or, for example, the repeating units in adjacent repeating unit groups are staggered from each other along the second direction, that is, adjacent repeating units in adjacent repeating unit groups have a certain offset along the second direction. Therefore, sub-pixels of the same color in adjacent repeating unit groups are not aligned in the second direction. In some examples, the offset of sub-pixels of the same color in adjacent repeating unit groups in the second direction can be half of the size of the repeating unit in the second direction. For example, the size of the repeating unit in the second direction can be the pitch of the repeating unit in the second direction.

[0108] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, since the second color sub-pixel pair 020 may include two second color sub-pixels 021 and 022 arranged along the first direction F1, when the light-emitting layer is prepared by the FMM evaporation process, the light-emitting layers of the two second color sub-pixels 021 and 022 in each second color sub-pixel pair 020 may be connected, and the light-emitting layers of the two second color sub-pixels 021 and 022 in each second color sub-pixel pair 020 may be formed through one evaporation hole of the FMM. When the second color is green, the process difficulty of preparing the light-emitting layer of the green sub-pixel may be reduced to a certain extent.

[0109] In addition, although the shape of the main part of each sub-pixel in the drawings includes a strict angle formed by two line segments, in some embodiments, the shape of the effective light-emitting area of ​​each sub-pixel can be a rounded shape. That is, on the basis of the above-mentioned various graphic shapes, the corners of the effective light-emitting area of ​​each sub-pixel are rounded. For example, in the case where the light-emitting layer is evaporated through a mask, the part of the light-emitting layer located at the corner may naturally form a rounded shape.

[0110] In some examples, such as Figures 3a to 4 As shown, the main parts of the first color sub-pixel 010 and the third color sub-pixel 030 may be in the shape of a hexagon, and the three groups of opposite sides of the hexagon are parallel. The main part of each second color sub-pixel 021, 022 may be in the shape of a pentagon, and the pentagon includes two sides that do not cross at right angles, a group of parallel opposite sides, and a vertical side, the vertical side is perpendicular to the group of parallel opposite sides, and the two sides that do not cross at right angles are connected between the group of parallel opposite sides; wherein the vertical sides of the second color sub-pixels 021, 022 in each second color sub-pixel pair 020 are arranged adjacent to each other.

[0111] In some examples, such as Figures 3a to 4As shown, a set of longer parallel opposite sides in the main part of the first color sub-pixel 010 and a set of longer parallel opposite sides in the main part of the third color sub-pixel 030 are respectively parallel to a set of parallel opposite sides in the main part of the second color sub-pixels 021 and 022. Further, illustratively, a set of longer parallel opposite sides in the effective light-emitting area 90-010 of the first color sub-pixel 010 and a set of longer parallel opposite sides in the effective light-emitting area 90-030 of the third color sub-pixel 030 are respectively parallel to a set of parallel opposite sides in the effective light-emitting areas 90-021 and 90-022 of the second color sub-pixels 021 and 022.

[0112] In some examples, such as Figures 3a to 4 As shown, the area of ​​the first color sub-pixel 010 is larger than the area of ​​one second color sub-pixel 020, and the area of ​​the third color sub-pixel 030 is larger than the area of ​​one second color sub-pixel 020. For example, the area of ​​the effective light-emitting area 90-010 of the first color sub-pixel 010 is larger than the area of ​​the effective light-emitting areas 90-021 and 90-022 of one second color sub-pixel 020, and the area of ​​the effective light-emitting area 90-030 of the third color sub-pixel 030 is larger than the area of ​​the effective light-emitting areas 90-021 and 90-022 of one second color sub-pixel 020.

[0113] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the interleaving distance of two adjacent repeating units in the first direction F1 in the second direction F2 is greater than one or a combination of the maximum span of the first color sub-pixel 010, the maximum span of the second color sub-pixel 021, the maximum span of the second color sub-pixel 022, and the maximum span of the third color sub-pixel 030. For example, the interleaving distance of two adjacent repeating units in the first direction F1 in the second direction F2 is greater than one or a combination of the maximum span d010 of the effective light-emitting area 90-010 of the first color sub-pixel 010, the maximum span d020 of the effective light-emitting area 90-021 of the second color sub-pixel 021, the maximum span d020 of the effective light-emitting area 90-022 of the second color sub-pixel 022, and the maximum span d030 of the effective light-emitting area 90-030 of the third color sub-pixel 030.

[0114] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4As shown, in a repeating unit 001, the farthest distance between the second color sub-pixel 021 and the second color sub-pixel 022 in the second color sub-pixel pair 020 in the first direction F1 is greater than the farthest distance between any two points of the first color sub-pixel 010 in the first direction F1. For example, in a repeating unit 001, the farthest distance between the effective light-emitting area 90-021 of the second color sub-pixel 021 and the effective light-emitting area 90-022 of the second color sub-pixel 022 in the first direction F1 is greater than the farthest distance between any two points of the effective light-emitting area 90-010 of the first color sub-pixel 010 in the first direction F1.

[0115] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in a repeating unit 001, the farthest distance between the second color sub-pixel 021 and the second color sub-pixel 022 in the second color sub-pixel pair 020 in the first direction F1 is greater than the farthest distance between any two points of the third color sub-pixel 030 in the first direction F1. For example, in a repeating unit 001, the farthest distance between the effective light-emitting area 90-021 of the second color sub-pixel 021 and the effective light-emitting area 90-022 of the second color sub-pixel 022 in the first direction F1 is greater than the farthest distance between any two points of the effective light-emitting area 90-030 of the third color sub-pixel 030 in the first direction F1.

[0116] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the adjacent sub-pixels of the first color sub-pixel do not include the first color sub-pixel, the adjacent sub-pixels of the second color sub-pixel do not include the second color sub-pixel, and the adjacent sub-pixels of the third color sub-pixel do not include the third color sub-pixel.

[0117] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the first direction F1 and the second direction F2, the two first color sub-pixels 010 are divided by other sub-pixels except the first color sub-pixels, the two third color sub-pixels 030 are divided by other sub-pixels except the third color sub-pixels, and the two second color sub-pixel pairs are divided by other sub-pixels except the second color sub-pixels.

[0118] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4As shown, two adjacent repeating units in the first direction F1 are arranged as a repeating group. Exemplarily, in the same repeating group, the second color sub-pixel pair in one repeating unit is between the maximum span of a first color sub-pixel and a third color sub-pixel in another repeating unit in the second direction F2. For example, in the same repeating group, the effective light-emitting area of ​​the second color sub-pixel pair in one repeating unit is between the maximum span of an effective light-emitting area of ​​a first color sub-pixel and an effective light-emitting area of ​​a third color sub-pixel in another repeating unit in the second direction F2.

[0119] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, two adjacent repeating units in the first direction F1 are arranged as a repeating group. Exemplarily, in the same repeating group, the first color sub-pixel in one repeating unit is between the maximum span of a second color sub-pixel pair and a third color sub-pixel in another repeating unit in the second direction F2. For example, in the same repeating group, the effective light-emitting area of ​​the first color sub-pixel in one repeating unit is between the maximum span of an effective light-emitting area of ​​a second color sub-pixel pair and an effective light-emitting area of ​​a third color sub-pixel in another repeating unit in the second direction F2.

[0120] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, two adjacent repeating units in the first direction F1 are arranged as a repeating group. Exemplarily, in the same repeating group, the third color sub-pixel in one repeating unit is between the maximum span of a second color sub-pixel pair and a first color sub-pixel in another repeating unit in the second direction F2. For example, in the same repeating group, the effective light-emitting area of ​​the third color sub-pixel in one repeating unit is between the maximum span of an effective light-emitting area of ​​a second color sub-pixel pair and an effective light-emitting area of ​​a first color sub-pixel in another repeating unit in the second direction F2.

[0121] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the same repeating unit 001, the minimum distance between the two second color sub-pixels 021 and 022 in the same second color sub-pixel pair 020 in the first direction F1 is smaller than the maximum span of one first color sub-pixel 010 in the first direction F1. For example, in the same repeating unit 001, the minimum distance between the effective light-emitting area 90-021 of the second color sub-pixel 021 and the effective light-emitting area 90-022 of the second color sub-pixel 022 in the first direction F1 is smaller than the maximum span d010 of the effective light-emitting area 90-010 of one first color sub-pixel 010 in the first direction F1.

[0122] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the same repeating unit 001, the minimum distance between the two second color sub-pixels 021 and 022 in the same second color sub-pixel pair 020 in the first direction F1 is smaller than the maximum span of a third color sub-pixel 030 in the first direction F1. For example, in the same repeating unit 001, the minimum distance between the effective light-emitting area 90-021 of the second color sub-pixel 021 and the effective light-emitting area 90-022 of the second color sub-pixel 022 in the first direction F1 is smaller than the maximum span d030 of the effective light-emitting area 90-030 of the third color sub-pixel 030 in the first direction F1.

[0123] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the sub-pixels in the repeating units in the odd-numbered columns of the repeating unit group are arranged in the same manner, and the sub-pixels in the repeating units in the even-numbered columns of the repeating unit group are arranged in the same manner. For example, except for the edge portion of the display area of ​​the substrate, the center line of the two green sub-pixels in each repeating unit is located between the centers of the two adjacent red and blue sub-pixels in the adjacent repeating unit group. In addition, the edges of the above two green sub-pixels are on the inner side of the outer edges of the above two adjacent red and blue sub-pixels, where the outer edges refer to the edges of the two sub-pixels that are opposite to each other along the first direction F1. That is to say, in the first direction F1, the extension range of a green sub-pixel pair in the first direction F1 is not greater than the extension range of the above two adjacent red and blue sub-pixels in the first direction F1. In addition, in the embodiments of the present disclosure, if not otherwise specified, the "center" of a sub-pixel refers to the geometric center of the shape of the sub-pixel (e.g., the first color sub-pixel, the second color sub-pixel, or the third color sub-pixel).

[0124] It should be noted that when designing the sub-pixel arrangement structure, the sub-pixel is generally designed to be a regular shape, such as a hexagon, a pentagon, a trapezoid or other shapes. When designing, the center of the sub-pixel can be the geometric center of the above-mentioned regular shape. However, in the actual manufacturing process, the shape of the sub-pixel formed generally has a certain deviation from the regular shape of the above-mentioned design. For example, each corner of the above-mentioned regular shape may become a rounded corner, so the shape of the sub-pixel can be a rounded corner figure. In addition, the shape of the sub-pixel actually manufactured may also have other changes from the designed shape. For example, the shape of the sub-pixel designed as a hexagon may become an approximate ellipse in actual manufacturing. Therefore, the center of the sub-pixel may not be the strict geometric center of the irregular shape of the sub-pixel formed by the manufacturing. In the embodiment of the present disclosure, the center of the sub-pixel may have a certain offset from the geometric center of the shape of the sub-pixel. The center of the sub-pixel refers to any point in the area surrounded by a specific point on the radial line segment starting from the geometric center of the sub-pixel to each point on the edge of the sub-pixel, and the specific point on the radial line segment is at a distance from the geometric center 1 / 3 of the length of the radial line segment. The definition of the sub-pixel center is applicable to the center of a sub-pixel with a regular shape, and is also applicable to the center of a sub-pixel with an irregular shape.

[0125] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in each adjacent group of three repeating units, the three adjacent columns include the first column, the second column and the third column in sequence along the row direction (i.e., the first direction F1), and the shortest distance in the row direction between the centers of the two second color sub-pixels 021 and 022 in the pair of second color sub-pixels 020 in the second column is smaller than the shortest distance in the row direction between the centers of the first color sub-pixel 010 in the first column and the centers of the first color sub-pixel 010 in the third column.

[0126] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the side of the first color sub-pixel 010 in the second direction F2 is arranged in parallel with the side of the third color sub-pixel 030 in the second direction F2.

[0127] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in each repeating unit 001 , the arrangement order of the first color sub-pixel 010 , the second color sub-pixel pair 020 , and the third color sub-pixel 030 is the same.

[0128] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4As shown, the size of the main part 411 of the first color sub-pixel 010 in the second direction F2 is smaller than the size of the main part 413 of the third color sub-pixel 030 in the second direction F2. Moreover, the size of the main part 411 of the first color sub-pixel 010 in the first direction F1 is larger than the size of the main part 413 of the third color sub-pixel 030 in the first direction F1. Exemplarily, the size of the main part 413 of the third color sub-pixel 030 in the second direction F2 is smaller than the size of the main part 413 of the third color sub-pixel 030 in the first direction F1, and the size of the main part 411 of the first color sub-pixel 010 in the second direction F2 is smaller than the size of the main part 411 of the first color sub-pixel 010 in the first direction F1. Of course, the embodiments of the present disclosure include but are not limited to this, and the relationship between the above-mentioned sizes can also be in other forms.

[0129] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 8c As shown, each sub-pixel further includes: a pixel driving circuit located on the side of the first conductive layer 200 facing the substrate 100; wherein the pixel driving circuits in each sub-pixel are distributed in an array. It should be noted that the structure of each layer of the pixel driving circuit can be referred to Figure 2a to Figure 2g The structure shown will not be described in detail here.

[0130] In the specific implementation, in the embodiment of the present disclosure, if Figure 2g and Figure 3b As shown, the pixel driving circuit in the third color sub-pixel 030, the pixel driving circuit in the first second color sub-pixel 021, the pixel driving circuit in the first color sub-pixel 010, and the pixel driving circuit in the second second color sub-pixel 022 are sequentially arranged along the first direction F1. Of course, the present disclosure includes but is not limited to this.

[0131] In the specific implementation, in the embodiment of the present disclosure, if Figure 2g and Figure 3b As shown, the size of the area where each layer pattern in each pixel driving circuit is located in the second direction F2 is greater than the size in the first direction F1. Of course, the present disclosure includes but is not limited to this.

[0132] In the specific implementation, in the embodiment of the present disclosure, if Figure 2g and Figure 3bAs shown, there is a first angle θ1 between the extension direction S1 of the main part 411 of the first color sub-pixel 010 and the length direction S2 of the area where the pixel driving circuit of the first color sub-pixel 010 is located; wherein the first angle θ1 is between 45 degrees and 165 degrees. Exemplarily, θ1 can be approximately 90 degrees, that is, the extension direction S1 of the main part 411 of the first color sub-pixel 010 (for example, the extension direction of the main part 411 of the first color sub-pixel 010 can be the first direction F1) and the length direction of the area where the pixel driving circuit of the first color sub-pixel 010 is located (for example, the length direction of the area where the pixel driving circuit of the first color sub-pixel 010 is located can be the second direction F2) are approximately perpendicular. Of course, θ1 can also be approximately between 45 degrees and 135 degrees, between 75 degrees and 115 degrees, or 50 degrees, 80 degrees, 100 degrees, 120 degrees, 140 degrees. The present disclosure is included but not limited to this.

[0133] In the specific implementation, in the embodiment of the present disclosure, if Figure 2g and Figure 3b As shown, there is a second angle θ2 between the extension direction S3 of the main part 413 of the third color sub-pixel 030 and the length direction S2 of the area where the pixel driving circuit of the third color sub-pixel 010 is located; wherein the second angle θ2 is between 45 degrees and 165 degrees. Exemplarily, θ2 can be approximately 90 degrees, that is, the extension direction S1 of the main part 413 of the third color sub-pixel 030 (for example, the extension direction of the main part 411 of the third color sub-pixel 030 is the first direction F1) and the length direction S2 of the area where the pixel driving circuit of the third color sub-pixel 010 is located (for example, the length direction of the area where the pixel driving circuit of the third color sub-pixel 010 is located is the second direction F2) are approximately perpendicular. Of course, θ2 can also be approximately 45 degrees, 75 degrees, 115 degrees, or 135 degrees. The present disclosure is not limited to this.

[0134] In the specific implementation, in the embodiment of the present disclosure, if Figure 2g and Figure 3bAs shown, there is a third angle θ3 between the extension direction S4 of the second color sub-pixel pair 020 and the length direction S2 of the region where the pixel driving circuit of the second color sub-pixel pair 020 is located; wherein the third angle θ3 is between 45 degrees and 165 degrees. Exemplarily, θ3 can be approximately 90 degrees, that is, the extension direction S4 of the second color sub-pixel pair 020 (for example, the extension direction of the second color sub-pixel pair 020 is the first direction F1) and the length direction S2 of the region where the pixel driving circuit of the second color sub-pixel pair 020 is located (for example, the length direction of the region where the pixel driving circuit of the second color sub-pixel pair 020 is located is the second direction F2) are approximately perpendicular. Of course, θ3 can also be approximately between 45 degrees and 135 degrees, between 75 degrees and 115 degrees, or 50 degrees, 80 degrees, 100 degrees, 120 degrees, 140 degrees. The present disclosure is included but not limited to this.

[0135] In a specific implementation, for example, a rectangular area is defined to include the patterns of each film layer of a pixel driving circuit of a sub-pixel, for example Figure 2g As shown in the dotted box, the rectangular areas defining the pixel driving circuits of each sub-pixel are arranged in a matrix on the substrate, and the long side direction of the rectangular area is substantially perpendicular to the extension direction of the main body of the first color sub-pixel.

[0136] In a specific implementation, for example, a rectangular area is defined to include the patterns of each film layer of a pixel driving circuit of a sub-pixel, for example Figure 2g As shown in the dotted box, the rectangular areas defining the pixel driving circuits of each sub-pixel are arranged in a matrix on the substrate, and the long side direction of the rectangular area is substantially perpendicular to the extension direction of the main body of the third color sub-pixel.

[0137] In the specific implementation, in the embodiment of the present disclosure, if Figures 2a to 6c As shown, in the third color sub-pixel 030, the orthographic projection of the main body part 413 on the substrate 100 does not overlap with the driving transistor in the pixel driving circuit, the orthographic projection of the main body part 413 on the substrate 100 overlaps with the orthographic projection of the reset control signal line (i.e., the first reset control signal line Rst1a or the second reset control signal line Rst2a of the next row) and the reset power signal line (i.e., the first reset power signal line Init1a or the second reset power signal line Init2a of the next row) electrically connected to the pixel driving circuit adjacent to the pixel driving circuit on the substrate 100, the orthographic projection of the main body part 413 on the substrate 100 overlaps with the orthographic projection of the two data lines Vd on the substrate 100, and the orthographic projection of the main body part 413 on the substrate 100 overlaps with the orthographic projection of the two second power lines 610 on the substrate 100. Exemplarily, the data lines Vd and the power lines 610 whose orthographic projections overlap with the main body part 413 are arranged alternately. Of course, the present disclosure includes but is not limited to this.

[0138] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 5b As shown, in the third color sub-pixel 030, the orthographic projection of the main body portion 413 on the substrate 100 covers the orthographic projection of the two sub-power lines 211 on the substrate 100. And the two sub-power lines 211 overlapping with the orthographic projection of the main body portion 413 on the substrate 100 are arranged in parallel on both sides of the center of the main body portion 413. Exemplarily, the orthographic projections of the two sub-power lines 211 overlapping with the orthographic projection of the main body portion 413 on the substrate 100 pass through the orthographic projection of the main body portion 413.

[0139] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 5b As shown, in the first color sub-pixel 010, the orthographic projection of the main body portion 411 on the substrate 100 covers the orthographic projection of the two sub-power lines 211 on the substrate 100. And the two sub-power lines 211 overlapping with the orthographic projection of the main body portion 411 on the substrate 100 are arranged in parallel on both sides of the center of the main body portion 411. Exemplarily, the orthographic projections of the two sub-power lines 211 overlapping with the orthographic projection of the main body portion 411 on the substrate 100 pass through the orthographic projection of the main body portion 411.

[0140] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 6c As shown, in the first color sub-pixel 010, the orthogonal projection of the main body 411 on the substrate 100 overlaps with the driving transistor in the pixel driving circuit, the orthogonal projection of the main body 411 on the substrate 100 overlaps with the orthogonal projection of the light emitting control signal line (the first light emitting control signal line EM1a or the second light emitting control signal line EM2a) electrically connected to the pixel driving circuit on the substrate 100, the orthogonal projection of the main body 411 on the substrate 100 overlaps with the orthogonal projections of the two data lines Vd on the substrate 100, and the orthogonal projection of the main body 411 on the substrate 100 overlaps with the orthogonal projections of the two second power lines 610 on the substrate 100. Of course, the present disclosure includes but is not limited to this.

[0141] In the specific implementation, in the embodiment of the present disclosure, if Figure 3c and Figure 5b As shown, in the second color sub-pixel, the orthographic projection of the main body on the substrate at least partially overlaps with the orthographic projection of a sub-power line and a conductive line electrically connected to the sub-power line on the substrate. Figure 3c and Figure 5bAs shown, the second color sub-pixel pair 020 may include a first second color sub-pixel 021 and a second second color sub-pixel 022. Among them, in the first second color sub-pixel 021, the orthographic projection of the main body part 4121 on the substrate 100 overlaps with a sub-power line 211 and a conductive line 212 electrically connected to the sub-power line 211 on the orthographic projection portion of the substrate 100. Exemplarily, the sub-power line 211 and the conductive line 212 overlapping with the orthographic projection of the main body part 4121 on the substrate 100 can be arranged in a cross shape. Of course, the embodiments of the present disclosure include but are not limited to this. The above-mentioned sub-power line 211 and the conductive line 212 overlapping with the orthographic projection of the main body part 4121 on the substrate 100 can also be arranged in other forms.

[0142] In the specific implementation, in the embodiment of the present disclosure, if Figure 3b , Figure 5b as well as Figure 6c As shown, in the first second color sub-pixel 021, the orthographic projection of the main body 4121 on the substrate 100 does not overlap with the driving transistor in the pixel driving circuit, and the orthographic projection of the main body 4121 on the substrate 100 overlaps with the orthographic projection of the reset control signal line (i.e., the first reset control signal line Rst1a or the second reset control signal line Rst2a of the next row) and the scanning signal line (i.e., the first scanning signal line Ga1a or the second scanning signal line Ga2a of the next row) electrically connected to the pixel driving circuit adjacent to the pixel driving circuit on the substrate. Of course, the present disclosure includes but is not limited to this.

[0143] In the specific implementation, in the embodiment of the present disclosure, if Figure 3b , Figure 5b as well as Figure 6c As shown, in the second second color sub-pixel 022, the orthographic projection of the main body 4122 on the substrate 100 does not overlap with the driving transistor in the pixel driving circuit, and the orthographic projection of the main body 4122 on the substrate 100 overlaps with the orthographic projection of the reset control signal line (i.e., the first reset control signal line Rst1a or the second reset control signal line Rst2a of the next row) and the scanning signal line (i.e., the first scanning signal line Ga1a or the second scanning signal line Ga2a of the next row) electrically connected to the pixel driving circuit adjacent to the pixel driving circuit on the substrate 100. Of course, the present disclosure includes but is not limited to this.

[0144] For example, Figure 3c and Figure 5bAs shown, in the second second color sub-pixel 022, the orthographic projection of the main body part 4122 on the substrate 100 overlaps with a sub-power line 211 and a conductive line 212 electrically connected to the sub-power line 211 on the orthographic projection of the substrate 100. Exemplarily, the sub-power line 211 and the conductive line 212 overlapping with the orthographic projection of the main body part 4122 on the substrate 100 can be arranged in a cross shape. Of course, the embodiments of the present disclosure include but are not limited to this. The above-mentioned sub-power line 211 and the conductive line 212 overlapping with the orthographic projection of the main body part 4122 on the substrate 100 can also be arranged in other forms.

[0145] In the specific implementation, in the embodiment of the present disclosure, if Figure 3c and Figure 5b As shown, the sub-power lines 211 and the conductive lines 212 are electrically connected to each other, so that the first power lines 210 form a grid structure. Exemplarily, the conductive lines 212 are arranged in an array on the substrate 100. For example, Figure 3c and Figure 5b As shown, for the adjacent third color sub-pixel 030 and first color sub-pixel 010 in the same repeating unit group, a conductive line 212 is arranged between the main body 413 in the third color sub-pixel 030 and the main body 411 in the first color sub-pixel 010. The conductive line 212 covered by the main body 4121 and the main body 4122 in the second color sub-pixel pair 020 extends on the same straight line along the first direction F1.

[0146] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 6c As shown, in each third color sub-pixel 030, the main part 413 and the auxiliary part 423 are electrically connected to each other, the auxiliary part 423 is electrically connected to the first connection line 223 through the first via hole 310, the first connection line 223 is electrically connected to the second connection line 623 through the second via hole 520, and the second connection line 623 is electrically connected to the drain of the transistor in the pixel driving circuit to input the electrical signal generated by the pixel driving circuit into the anode 400, and also to drive the light-emitting layer 50 to emit light by loading a corresponding voltage on the cathode 60.

[0147] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 as well as Figure 6a and Figure 6c As shown, in each third color sub-pixel 030, the orthographic projection of the main portion 413 on the substrate 100 does not overlap with the orthographic projection of the first via hole 310 on the substrate 100. In this way, the main portion 413 in each third color sub-pixel 030 is not affected by the first via hole 310, so as to avoid the main portion 413 being uneven due to the first via hole 310, thereby improving the color shift phenomenon of the display panel.

[0148] Generally, the distance between the first via hole 310 and the second via hole 520 should not be too far or too close. In specific implementation, in the disclosed embodiment, in each third color sub-pixel 030, along the second direction F2, the minimum value of the distance W between the first via hole 310 and the second via hole 520 can satisfy the range of 1 micron to 2 microns. Among them, the minimum value of the distance W between the first via hole 310 and the second via hole 520 can be made to be. The minimum value of the distance W between the first via hole 310 and the second via hole 520 can also be made to be, or the minimum value of the distance W between the first via hole 310 and the second via hole 520 can also be made to be. Of course, in actual applications, the distance W between the first via hole 310 and the second via hole 520 can be designed and determined according to the actual application environment, and is not limited here.

[0149] Optionally, the first insulating layer may be configured as a flat layer, so that the body portion located on the first insulating layer may have a higher flatness.

[0150] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 as well as Figure 6a and Figure 6c As shown, in the third color sub-pixel 030, the orthographic projection of the main body portion 413 on the substrate 100 at least partially overlaps with the orthographic projection of the second via hole 520 on the substrate 100. For example, the orthographic projection of the main body portion 413 on the substrate 100 covers the orthographic projection of the second via hole 520 on the substrate 100. Since the second via hole 520 is located in the second insulating layer 500, and there are the first insulating layer 300 and the first conductive layer 200 between the second insulating layer 500 and the main body portion 413, the second via hole 520 has little effect on the main body portion 413, and can even be ignored.

[0151] In the specific implementation, in the embodiment of the present disclosure, if Figure 3b and Figure 6c As shown, in the third color sub-pixel 030, the first via hole 310 is arranged close to the driving transistor in the pixel driving circuit relative to the second via hole 520. Of course, the present disclosure includes but is not limited to this.

[0152] In the specific implementation, in the embodiment of the present disclosure, if Figure 3b As shown, each sub-pixel further includes: a fourth via hole 710. Optionally, the fourth via holes 710 are arranged in a straight line along the first direction F1, and the spacing between two adjacent fourth via holes 710 on the same straight line is substantially the same. The fourth via hole 710 may be the via hole 388a.

[0153] In the specific implementation, in the embodiment of the present disclosure, if Figure 3b and Figure 6cAs shown, in the third color sub-pixel 030, the orthographic projection of the fourth via hole 710 on the substrate 100 overlaps with the orthographic projection of the second via hole 520 on the substrate 100. Of course, the present disclosure includes but is not limited to this.

[0154] In the specific implementation, in the embodiment of the present disclosure, combined with Figures 3b to 8c As shown, in the third color sub-pixel 030, the orthographic projection of the first via 310 on the substrate 100 overlaps with the orthographic projection of the light-emitting control signal line electrically connected to the drive circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100, and the orthographic projection of the second via 520 on the substrate 100 does not overlap with the orthographic projection of the light-emitting control signal line electrically connected to the drive circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100, and the orthographic projection of the fourth via 710 on the substrate 100 does not overlap with the orthographic projection of the light-emitting control signal line electrically connected to the drive circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100.

[0155] In the specific implementation, in the embodiment of the present disclosure, if Figure 3a and Figure 6b As shown, in the third color sub-pixel 030, the orthographic projection of the main body portion 413 on the substrate 100 at least partially overlaps with the orthographic projections of the two third via holes 530 on the substrate 100. For example, in the third color sub-pixel 030, the orthographic projection of the main body portion 413 on the substrate 100 partially overlaps with the orthographic projections of the two third via holes 530 on the substrate 100.

[0156] In the specific implementation, in the embodiment of the present disclosure, if Figure 3a , Figure 3c and Figure 6b As shown, in the third color sub-pixel 030, the first via hole 310 is arranged close to one side of the center line LZ1 of the two third via holes 530 overlapping with the orthographic projection of the main part 413 on the substrate 100, and the second via hole 520 is arranged close to the other side of the center line LZ1 of the two third via holes 530 overlapping with the orthographic projection of the main part 413 on the substrate 100. In this way, the first via hole 310 and the second via hole 520 in the third color sub-pixel 030 can be arranged at a relatively close distance. It should be noted that the center line LZ1 is parallel to the first direction F1. In addition, the center line LZ1 is a line passing through the centers of the two third via holes 530, which is virtual and not a real line.

[0157] It should be noted that in the disclosed embodiments, in a plane parallel to the plane where the substrate is located, the cross-section of the via hole can be a regular shape, such as a rectangle, a regular polygon (square, regular pentagon, regular hexagon, etc.), a circle, an ellipse, etc., and the center of the via hole can refer to the geometric center of the regular shape. Of course, in a plane parallel to the plane where the substrate is located, the cross-section of the via hole can also be an irregular shape, and the center of the via hole can refer to the equivalent geometric center of the irregular shape.

[0158] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the third color sub-pixel 030, the main body 413 may be an axisymmetric figure, and the first via hole 310 may be located on the symmetry axis of the main body 413 along the second direction F2. Exemplarily, the main body 413 in the third color sub-pixel 030 may have a first symmetry axis along the second direction F2, and the first via hole 310 in the third color sub-pixel 030 is substantially axisymmetric about the first symmetry axis. Exemplarily, the main body 413 in the third color sub-pixel 030 is substantially hexagonal or elliptical in shape, and the long symmetry axis of the hexagon or the long axis of the ellipse is substantially parallel to the first direction F1, and the short symmetry axis of the hexagon or the short axis of the ellipse is substantially parallel to the second direction F2, and the short symmetry axis of the hexagon or the short axis of the ellipse may be used as the first symmetry axis. For example, the first via hole 310 in the third color sub-pixel 030 may be arranged substantially axially symmetrically with respect to the first symmetry axis, or the first via hole 310 in the third color sub-pixel 030 may only intersect with the first symmetry axis, but not be arranged substantially axially symmetrically with respect to the first symmetry axis. Of course, in actual applications, the implementation of the first via hole 310 in the third color sub-pixel 030 may be designed and determined according to the actual application environment, and is not limited here.

[0159] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the third color sub-pixel 030, the second via hole 520 can be located on the symmetry axis of the main part 413 along the second direction F2. Exemplarily, the second via hole 520 in the third color sub-pixel 030 is arranged approximately axisymmetrically with respect to the first symmetry axis. Exemplarily, the second via hole 520 in the third color sub-pixel 030 can be arranged approximately axisymmetrically with respect to the first symmetry axis, or the second via hole 520 in the third color sub-pixel 030 can only intersect with the first symmetry axis, and is not arranged approximately axisymmetrically with respect to the first symmetry axis. Of course, in actual applications, the implementation method of the second via hole 520 in the third color sub-pixel 030 can be designed and determined according to the actual application environment, and is not limited here.

[0160] In the specific implementation, in the embodiment of the present disclosure, if Figure 3a to Figure 3c as well as Figure 6c and Figure 7a As shown, in each first color sub-pixel 010, the main part 411 and the auxiliary part 421 are electrically connected to each other, the auxiliary part 421 is electrically connected to the first connection line 221 through the first via hole 310, the first connection line 221 is electrically connected to the second connection line 621 through the second via hole 520, and the second connection line 621 is electrically connected to the drain of the transistor in the pixel driving circuit to input the electrical signal generated by the pixel driving circuit into the anode 400, and also to drive the light-emitting layer 50 to emit light by loading a corresponding voltage on the cathode 60.

[0161] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 as well as Figure 6c and Figure 7a As shown, in each first color sub-pixel 010, the orthographic projection of the main part 411 on the substrate 100 does not overlap with the orthographic projection of the first via hole 310 on the substrate 100. In this way, the main part 411 in each first color sub-pixel 010 is not affected by the first via hole 310, so as to avoid the main part 411 being uneven due to the first via hole, thereby improving the color shift phenomenon of the display panel.

[0162] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 as well as Figures 6c to 7a As shown, in the first color sub-pixel 010, the orthographic projection of the main body portion 411 on the substrate 100 at least partially overlaps with the orthographic projection of the second via hole 520 on the substrate 100. Exemplarily, the orthographic projection of the main body portion 411 on the substrate 100 covers the orthographic projection of the second via hole 520 on the substrate 100. Since the second via hole 520 is located in the second insulating layer 500, and there are the first insulating layer 300 and the first conductive layer 200 between the second insulating layer 500 and the main body portion 411, the second via hole 520 has little effect on the main body portion 411, and can even be ignored.

[0163] In the specific implementation, in the embodiment of the present disclosure, if Figure 3b As shown, in the first color sub-pixel 010, the first via hole 310 is arranged away from the driving transistor in the pixel driving circuit relative to the second via hole 520. Of course, the present disclosure includes but is not limited to this.

[0164] In the specific implementation, in the embodiment of the present disclosure, if Figure 3b and Figure 6c As shown, in the first color sub-pixel 010, the orthographic projection of the fourth via hole 710 on the substrate 100 overlaps with the orthographic projection of the first via hole 310 on the substrate 100. Of course, the present disclosure includes but is not limited to this.

[0165] In the specific implementation, in the embodiment of the present disclosure, if Figure 3b and Figure 6cAs shown, in the first color sub-pixel 010, the orthographic projection of the first via hole 310 on the substrate 100 does not overlap with the orthographic projection of the light-emitting control signal line electrically connected to the driving circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100, and the orthographic projection of the second via hole on the substrate overlaps with the orthographic projection of the light-emitting control signal line electrically connected to the driving circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100, and the orthographic projection of the fourth via hole 710 on the substrate 100 does not overlap with the orthographic projection of the light-emitting control signal line electrically connected to the driving circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100. Of course, the present disclosure includes but is not limited to this.

[0166] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 as well as Figure 6c and Figure 7b As shown, in the first color sub-pixel 010, the orthographic projection of the main body portion 411 on the substrate 100 at least partially overlaps with the orthographic projections of the two third via holes 530 on the substrate 100. Exemplarily, in the first color sub-pixel 010, the orthographic projection of the main body portion 411 on the substrate 100 partially overlaps with the orthographic projections of the two third via holes 530 on the substrate 100.

[0167] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the first color sub-pixel 010, the first via hole 310 is arranged close to one side of the center line LZ2 of the two third via holes 530 overlapped by the orthographic projection, and the second via hole 520 is arranged close to the other side of the center line LZ2 of the two third via holes 530 overlapped by the orthographic projection. In this way, the first via hole 310 and the second via hole 520 in the first color sub-pixel 010 can be arranged at a relatively close distance. It should be noted that the center line LZ2 is parallel to the first direction F1. And the center line LZ2 is a line passing through the centers of the two third via holes 530, which is virtual and not a real line.

[0168] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4As shown, in the first color sub-pixel 010, the main body 411 may be an axisymmetric figure, and the first via 310 is located on the symmetry axis of the main body 411 along the second direction F2. Exemplarily, the main body 411 in the first color sub-pixel 010 may have a second symmetry axis along the second direction F2. Exemplarily, the shape of the main body 411 in the first color sub-pixel 010 is roughly hexagonal or elliptical, the long symmetry axis of the hexagon or the long axis of the ellipse is roughly parallel to the first direction F1, and the short symmetry axis of the hexagon or the short axis of the ellipse is roughly parallel to the second direction F2, then the short symmetry axis of the hexagon or the short axis of the ellipse can be used as the second symmetry axis. Exemplarily, the first via 310 in the first color sub-pixel 010 can be arranged roughly axisymmetrically with respect to the second symmetry axis, or the first via 310 in the first color sub-pixel 010 can only intersect with the second symmetry axis, and is not arranged roughly axisymmetrically with respect to the second symmetry axis. Of course, in actual applications, the implementation of the first via hole 310 in the first color sub-pixel 010 may be designed and determined according to the actual application environment, and is not limited here.

[0169] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the first color sub-pixel 010, the second via hole 520 is located on the symmetry axis of the main body 411 along the second direction F2. For example, the second via hole 520 in the first color sub-pixel 010 can be arranged approximately axisymmetrically with respect to the second symmetry axis, or the second via hole 520 in the first color sub-pixel 010 can only intersect with the second symmetry axis, and is not arranged approximately axisymmetrically with respect to the second symmetry axis. Of course, in actual applications, the implementation of the second via hole 520 in the first color sub-pixel 010 can be designed and determined according to the actual application environment, and is not limited here.

[0170] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 as well as Figure 8a and Figure 8c As shown, in each first second color sub-pixel 021, the main part 4121 and the auxiliary part 4221 are electrically connected to each other, the auxiliary part 4221 is electrically connected to the first connection line 2221 through the first via hole 310, the first connection line 2221 is electrically connected to the second connection line 6221 through the second via hole 520, and the second connection line 6221 is electrically connected to the drain of the transistor in the pixel driving circuit to input the electrical signal generated by the pixel driving circuit into the anode 400, and also to drive the light-emitting layer 50 to emit light by loading a corresponding voltage on the cathode 60.

[0171] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 as well as Figure 8b and Figure 8cAs shown, in each second second color sub-pixel 022, the main part 4122 and the auxiliary part 4222 are electrically connected to each other, the auxiliary part 4222 is electrically connected to the first connection line 2222 through the first via hole 310, the first connection line 2222 is electrically connected to the second connection line 6222 through the second via hole 520, and the second connection line 6222 is electrically connected to the drain of the transistor in the pixel driving circuit to input the electrical signal generated by the pixel driving circuit into the anode 400, and also to drive the light-emitting layer 50 to emit light by loading a corresponding voltage on the cathode 60.

[0172] Alternatively, if Figures 3a to 4 as well as Figures 8a to 8c As shown, in each second color sub-pixel, the orthographic projection of the main body portion on the substrate does not overlap with the orthographic projection of the first via hole on the substrate. Figures 3a to 4 as well as Figure 8a and Figure 8c As shown, in the first second color sub-pixel 021, the orthographic projection of the main part 4121 on the substrate 100 does not overlap with the orthographic projection of the first via hole 310 on the substrate 100. In this way, the main part 4121 in each first second color sub-pixel 021 is not affected by the first via hole 310, so as to avoid the main part 4121 being uneven due to the first via hole 310, thereby improving the color shift phenomenon of the display panel.

[0173] For example, Figures 3a to 4 as well as Figure 8a and Figure 8c As shown, in the second second color sub-pixel 021, the orthographic projection of the main part 4122 on the substrate 100 does not overlap with the orthographic projection of the first via hole 310 on the substrate 100. In this way, the main part 4122 in each second second color sub-pixel 022 is not affected by the first via hole 310, so as to avoid the main part 4122 being uneven due to the first via hole 310, thereby improving the color shift phenomenon of the display panel.

[0174] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the second color sub-pixel pair 020 includes a first second color sub-pixel 021 and a second second color sub-pixel 022; wherein, in the same repeating unit 001, the first via hole 310 of the first second color sub-pixel 021 is located on the side of the first second color sub-pixel 021 away from the third color sub-pixel 030. Moreover, in the same repeating unit 001, the first via hole 310 of the second second color sub-pixel 022 is located on the side of the second second color sub-pixel 022 away from the third color sub-pixel 030.

[0175] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4As shown, for the first color sub-pixel 010 and the first second color sub-pixel 021 in the same repeating unit 001, and for the third color sub-pixel 030 that is the closest neighbor to both the first color sub-pixel 010 and the first second color sub-pixel 021 in the same repeating unit 001, the first via hole 310 of the first second color sub-pixel 021 is located in the gap between the first color sub-pixel 010 and the third color sub-pixel 030. Moreover, for the first color sub-pixel 010 and the second second color sub-pixel 022 in the same repeating unit 001, and for the third color sub-pixel 030 that is the closest neighbor to both the first color sub-pixel 010 and the second second color sub-pixel 022 in the same repeating unit 001, the first via hole 310 of the second second color sub-pixel 022 is located in the gap between the first color sub-pixel 010 and the third color sub-pixel 030.

[0176] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, for the first color sub-pixel 010 and the first second color sub-pixel 021 in the same repeating unit 001, and for the third color sub-pixel 030 that is the closest neighbor to both the first color sub-pixel 010 and the first second color sub-pixel 021 in the same repeating unit 001, the second via hole 520 of the first second color sub-pixel 021 is located in the gap between the first color sub-pixel 010 and the third color sub-pixel 030. Moreover, for the first color sub-pixel 010 and the second second color sub-pixel 022 in the same repeating unit 001, and for the third color sub-pixel 030 that is the closest neighbor to both the first color sub-pixel 010 and the second second color sub-pixel 022 in the same repeating unit 001, the second via hole 520 of the second second color sub-pixel 022 is located in the gap between the first color sub-pixel 010 and the third color sub-pixel 030.

[0177] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the first via holes 310 in the same color sub-pixels are located on the same side of the color sub-pixels. Exemplarily, the first via holes 310 of the first color sub-pixel 010 are located on the same side of the first color sub-pixel 010. The first via holes 310 of the second color sub-pixels 021 and 022 are located on the same side of the second color sub-pixels 021 and 022. The first via holes 310 of the third color sub-pixel 030 are located on the same side of the third color sub-pixel 030.

[0178] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4As shown, in the same repeating unit 001, the first via hole 310 and the second via hole 520 of the first second color sub-pixel 021 are arranged close to one side of the first color sub-pixel 010, and the first via hole 310 and the second via hole 520 of the second second color sub-pixel 022 are arranged close to the other side of the first color sub-pixel 010. That is, the first via hole 310 of the first second color sub-pixel 021 and the first via hole 310 of the second second color sub-pixel 022 are respectively located on both sides of the first color sub-pixel 010. The second via hole 520 of the first second color sub-pixel 021 and the second via hole 520 of the second second color sub-pixel 022 are respectively located on both sides of the first color sub-pixel 010. Exemplarily, in the same repeating unit 001, the first via hole 310 and the second via hole 520 of the first second color sub-pixel 021 can be arranged between the main body 411 in the first color sub-pixel 010 in the repeating unit 001 and the main body 413 in the third color sub-pixel 030 adjacent to the left side of the main body 411. Furthermore, in the same repeating unit 001, the first via hole 310 and the second via hole 520 of the second second color sub-pixel 022 can be arranged between the main part 411 in the first color sub-pixel 010 in the repeating unit 001 and the main part 413 in the third color sub-pixel 030 adjacent to the right side of the main part 411.

[0179] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the first second color sub-pixel 021, the second via hole 520 can be located at the side of the first via hole 310 away from the main body portion 4121. Of course, the embodiments of the present disclosure include but are not limited to this.

[0180] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the first second color sub-pixel 021, the first via hole 310 and the second via hole 520 can be arranged on the same straight line along the second direction F2. Of course, the embodiments of the present disclosure include but are not limited to this.

[0181] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figure 3b As shown, in the first second color sub-pixel 021, the first via hole 310 is arranged away from the driving transistor in the pixel driving circuit relative to the second via hole 520. Of course, the embodiments of the present disclosure include but are not limited to this.

[0182] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figure 3b and Figure 8c As shown, in the first second color sub-pixel 021, the orthographic projection of the fourth via hole 710 on the substrate 100 overlaps with the orthographic projection of the first via hole 310 on the substrate 100. Of course, the embodiments of the present disclosure include but are not limited to this.

[0183] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figure 3b and Figure 8c As shown, in the first second color sub-pixel 021, the orthographic projection of the first via hole 310 on the substrate 100 does not overlap with the orthographic projection of the light-emitting control signal line electrically connected to the driving circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100, and the orthographic projection of the second via hole 520 on the substrate 100 overlaps with the orthographic projection of the light-emitting control signal line electrically connected to the driving circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100, and the orthographic projection of the fourth via hole 710 on the substrate 100 does not overlap with the orthographic projection of the light-emitting control signal line electrically connected to the driving circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100. Of course, the embodiments of the present disclosure include but are not limited to this.

[0184] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 as well as Figure 8b and Figure 8c As shown, in the second second color sub-pixel 022, the second via hole 520 can be located at the side of the first via hole 310 away from the main body portion 4122. Of course, the embodiments of the present disclosure include but are not limited to this.

[0185] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 as well as Figure 8b and Figure 8c As shown, in the second second color sub-pixel 022, the first via hole 310 and the second via hole 520 can be arranged on the same straight line along the second direction F2. Of course, the embodiments of the present disclosure include but are not limited to this.

[0186] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figure 3b As shown, in the second second color sub-pixel 022, the first via hole 310 is arranged away from the driving transistor in the pixel driving circuit relative to the second via hole 520. Of course, the embodiments of the present disclosure include but are not limited to this.

[0187] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figure 3b and Figure 8c As shown, in the second second color sub-pixel 022, the orthographic projection of the fourth via hole 710 on the substrate 100 overlaps with the orthographic projection of the first via hole 310 on the substrate 100. Of course, the embodiments of the present disclosure include but are not limited to this.

[0188] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figure 3b and Figure 8c As shown, in the second second color sub-pixel 022, the orthographic projection of the first via hole 310 on the substrate 100 does not overlap with the orthographic projection of the light-emitting control signal line electrically connected to the driving circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100, and the orthographic projection of the second via hole 520 on the substrate 100 overlaps with the orthographic projection of the light-emitting control signal line electrically connected to the driving circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100, and the orthographic projection of the fourth via hole 710 on the substrate 100 does not overlap with the orthographic projection of the light-emitting control signal line electrically connected to the driving circuit (i.e., the first light-emitting control signal line EM1a or the second light-emitting control signal line EM2a of this row) on the substrate 100. Of course, the embodiments of the present disclosure include but are not limited to this.

[0189] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the same repeating unit 001, the first via hole 310 of the first second color sub-pixel 021 in the second color sub-pixel pair 020, the first via hole 310 of the first color sub-pixel 010, and the first via hole 310 of the second second color sub-pixel 022 are sequentially arranged on the same first sub-folding line Z1 along the first direction F1. Exemplarily, in a repeating unit 001 of the second column repeating unit group, the first via hole 310 of the first second color sub-pixel 021 in the second color sub-pixel pair 020, the first via hole 310 of the first color sub-pixel 010, and the first via hole 310 of the second second color sub-pixel 022 can make these three first via holes 310 sequentially arranged on the first sub-folding line Z1 along the direction indicated by the arrow of the first direction F1, thereby reducing the difficulty of designing the mask used when preparing these three first via holes 310.

[0190] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, for a first color sub-pixel 010 in a repeating unit group and a third color sub-pixel 030 in an adjacent repeating unit group and closest to the first color sub-pixel 010, the first via hole 310 of the first color sub-pixel 010 and the first via hole 310 of the third color sub-pixel 030 are arranged on the same second sub-fold line Z2 along a third direction; wherein the third direction intersects with the first direction and is not perpendicular to it.

[0191] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4As shown, the fold line may include: a first sub-fold line Z1 and a second sub-fold line Z2; in two adjacent repeating units 001 in different columns, the first via hole 310 of the third color sub-pixel 030 in the first repeating unit and the first via hole 310 of the first second color sub-pixel 021, the first via hole 310 of the first color sub-pixel 010 and the first via hole 310 of the second second color sub-pixel 022 in the second repeating unit are sequentially arranged on the fold line. In other words, in two adjacent repeating units 001 in different columns, the first via hole 310 of the third color sub-pixel 030 in the first repeating unit and the first via hole 310 of the first second color sub-pixel 021, the first via hole 310 of the first color sub-pixel 010 and the first via hole 310 of the second second color sub-pixel 022 in the second repeating unit are repeatedly arranged. This can also reduce the difficulty of designing the mask used when preparing these first via holes 310.

[0192] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the first via holes 310 of the third color sub-pixel 030 and the first via holes 310 of the first color sub-pixel 010 in the same repeating unit 001 are arranged on the same straight line along the second direction F2. This can also reduce the difficulty of designing the mask used in preparing the three first via holes 310.

[0193] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in two adjacent repeating units 001 in different columns, the first via hole 310 of the first second color sub-pixel 021 in one repeating unit 001 and the first via hole 310 of the second second color sub-pixel 022 in another repeating unit 001 are arranged on the same straight line along the second direction F2. This can also reduce the difficulty of designing the mask used when preparing these first via holes 310.

[0194] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the second via hole 520 of the third color sub-pixel 030 in the odd-numbered column repeating unit group is arranged on the same straight line along the first direction F1 with the first via hole 310 of the first color sub-pixel 010, the first via hole 310 of the first second color sub-pixel 021, and the first via hole 310 of the second second color sub-pixel 022 in the even-numbered column repeating unit group. Exemplarily, the second via hole 520 of the third color sub-pixel 030 in the first and third column repeating unit groups is arranged on the same straight line along the first direction F1 with the first via hole 310 of the first color sub-pixel 010, the first via hole 310 of the first second color sub-pixel 021, and the first via hole 310 of the second second color sub-pixel 022 in the second column repeating unit group.

[0195] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the odd-numbered repeating unit group, the first via hole 310 of the first color sub-pixel 010 in the same row of repeating unit 001, the first via hole 310 of the first second color sub-pixel 021 in the second color sub-pixel pair 020, and the first via hole 310 of the second second color sub-pixel 022 are arranged on the same straight line along the first direction F1. This can also reduce the difficulty of designing the mask used when preparing the three first via holes 310 in the display panel.

[0196] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the odd-numbered repeating unit group, the first via holes 310 of the third color sub-pixels 030 in the same row of repeating units 001 are arranged on the same straight line along the first direction F1. This can also reduce the difficulty of designing the mask used when preparing the three first via holes 310 in the display panel.

[0197] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the even-numbered repeating unit group, the first via hole 310 of the first color sub-pixel 010 in the same row of repeating unit 001, the first via hole 310 of the first second color sub-pixel 021 in the second color sub-pixel pair 020, and the first via hole 310 of the second second color sub-pixel 022 are arranged on the same straight line along the first direction F1. This can also reduce the difficulty of designing the mask used when preparing the three first via holes 310 in the display panel.

[0198] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, in the even-numbered repeating unit group, the first via holes 310 of the third color sub-pixels 030 in the same row of repeating units 001 are arranged on the same straight line along the first direction F1. This can also reduce the difficulty of designing the mask used when preparing the three first via holes 310 in the display panel.

[0199] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the intervals between two adjacent first via holes 310 along the first direction F1 may be substantially the same. Of course, the embodiments of the present disclosure include but are not limited to this.

[0200] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the intervals between two adjacent first via holes 310 along the second direction F2 may be substantially the same. Of course, the embodiments of the present disclosure include but are not limited to this.

[0201] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the intervals between two adjacent second via holes 520 along the first direction F1 may be substantially the same. Of course, the embodiments of the present disclosure include but are not limited to this.

[0202] In the specific implementation, in the embodiment of the present disclosure, if Figures 3a to 4 As shown, the intervals between two adjacent second via holes 520 along the second direction F2 may be substantially the same. Of course, the embodiments of the present disclosure include but are not limited to this.

[0203] Based on the same inventive concept, the embodiments of the present disclosure also provide other electroluminescent display panels, such as Figures 9a to 15 As shown, some implementation methods in the above embodiment are modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0204] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 15 As shown, a plurality of repeating units 001 may be included, each repeating unit 001 includes a plurality of sub-pixels, and each sub-pixel may include: a first conductive layer 200 located above the substrate 100, a first insulating layer 300 (i.e., a flat layer) located above the first conductive layer 200, and an anode 400 located on the first insulating layer 300. The first insulating layer 300 includes a first via hole 310, and the first via hole 310 exposes a portion of the first conductive layer 200. The anode 400 includes a main portion 410 and an auxiliary portion 420 electrically connected to each other, and the auxiliary portion 420 is electrically connected to the first conductive layer 200 through the first via hole 310. In at least one sub-pixel, the orthographic projection of the main portion 410 on the substrate 100 does not overlap with the orthographic projection of the first via hole 310 on the substrate 100. Furthermore, in at least one sub-pixel, the size of the main body portion 410 in the first direction F1 is greater than the size in the second direction F2, and in at least one sub-pixel, the first via hole 310 and the main body portion 410 are arranged in the second direction F2; wherein the first direction F1 is different from the second direction F2. Exemplarily, the plurality of pixel driving circuits include a first conductive layer 200.

[0205] The electroluminescent display panel provided by the embodiment of the present disclosure makes the anode include a main part and an auxiliary part electrically connected to each other, and adopts the auxiliary part to be electrically connected to the first conductive layer through a first via hole, so that the anode is electrically connected to the pixel driving circuit through the first conductive layer. In addition, since the orthographic projection of the main part on the substrate and the orthographic projection of the first via hole on the substrate do not overlap in at least one sub-pixel, the first via hole in the sub-pixel can be avoided, so that the main part of the anode in the sub-pixel is not affected by the depth of the first via hole, thereby avoiding the main part of the anode from being concave, avoiding the unevenness of the anode caused by the first via hole, and thus improving the color deviation phenomenon of the display panel.

[0206] In the specific implementation, in the embodiment of the present disclosure, if Figure 9a , Figure 9b , Fig.11 , Fig.12 As shown, the first conductive layer 200 may include: a power line, an anode adapter block and a data line 230 that are spaced apart from each other. That is to say, the first power line 210 can be used as a power line, and the first connecting line 220 can be used as an anode adapter block. Among them, in each sub-pixel, the auxiliary part 420 is electrically connected to the first connecting line 220 through the first via 310. The first connecting line 220 is electrically connected to the drain of the transistor in the pixel driving circuit to realize signal transmission. It should be noted that the above is only explained by taking the third color sub-pixel 030 as an example, and the settings in the remaining sub-pixels are similar, which will not be repeated here.

[0207] like Figure 9a , Figure 9b , Fig.11 , Fig.12 As shown, the power lines in the first conductive layer 200 may include adjacent first power lines and second power lines, and the data lines in the first conductive layer 200 may include adjacent first data lines and second data lines. The first anode (such as 411) of the first sub-pixel (such as 010) overlaps with the orthographic projections of the first power line, the second power line, the first data line and the second data line on the base substrate 100. In addition, the first anode (such as 411) has a bisector in the first direction F1, the first power line and the first data line are located on one side of the bisector, and the second power line and the second data line are located on the other side of the bisector. In this way, the structures of the first conductive layer located on both sides of the bisector corresponding to the first anode can be symmetrically arranged, thereby improving the flatness of the first anode.

[0208] Furthermore, in the specific implementation, in the embodiments of the present disclosure, if Figure 9a and Figure 9b , Fig.11 , Fig.12As shown, the first conductive layer 200 may further include: a bridge line 240 spaced apart from the first power line 210, the first connection line 220 and the data line 230. The bridge line is configured to electrically connect two of the gate, source and drain of some transistors in the pixel driving circuit. The setting method of the bridge line may be substantially the same as that in the related art, and will not be described in detail here.

[0209] Exemplarily, the first conductive layer 200 may be, for example, the source-drain metal layer 0340. The first power line 210 may be, for example, the first power signal line VDD1, the data line 230 may be, for example, the data line Vd, the first connection line 220 may be, for example, the connection portion 343a, and the bridge line 240 may be, for example, at least one of the connection portions 341a and 342a. That is, compared with the above-mentioned embodiment, the auxiliary metal layer 0350 is not provided in this embodiment, and the corresponding relationship between the vias and the insulating layer and the remaining film layers can refer to the implementation of the above-mentioned active semiconductor layer 0310, the gate conductive layer 0320, and the reference conductive layer 0330, which will not be described in detail here.

[0210] In the specific implementation, in the embodiment of the present disclosure, if Fig.12 As shown, each sub-pixel may further include a pixel defining layer 80 located on the side of the anode 400 facing away from the substrate 100, a light emitting layer 50 located on the side of the anode 400 facing away from the substrate 100, and a cathode 60 located on the side of the anode facing away from the light emitting layer 50. The pixel defining layer 80 has an opening, and the opening exposes at least a portion of the main body 410 of the anode 400, and the light emitting layer 50 is located in the opening and in contact with the area of ​​the main body 410 exposed by the opening. The area where the light emitting layer 50 is located in the opening is used for emitting light, so that an effective light emitting area 90 can be defined by the opening. It should be noted that the implementation of the effective light emitting area 90 of each sub-pixel mentioned above can refer to the above embodiment, and will not be repeated here.

[0211] In a specific implementation, the first power line can be configured as a power line for transmitting a driving voltage. The data line can be configured as a signal line for transmitting a data voltage. Figure 9a , Figure 9b and Fig.11 As shown, the first power line 210 and the data line 230 are arranged along the first direction F1 and extend along the second direction F2; and the first direction F1 is different from the second direction F2. Exemplarily, the first direction F1 is perpendicular to the second direction F2. Exemplarily, the first direction F1 can be the row direction of the display panel, that is, the direction in which the gate lines extend, and the second direction F2 can be the column direction of the display panel, that is, the direction in which the data lines extend. Of course, the embodiments of the present disclosure include but are not limited to this.

[0212] Generally, in the display field, a pixel usually includes multiple sub-pixels that can display a single color (such as red, green or blue). By controlling the ratio of sub-pixels of different colors, different colors can be displayed. Therefore, the above sub-pixels can be single-color sub-pixels. Figures 9a to 10 As shown, each of the multiple repeating units 001 may include: a first color sub-pixel 010, a second color sub-pixel pair 020, and a third color sub-pixel 030 arranged along the second direction F2. Among them, the second color sub-pixel pair 020 may include two second color sub-pixels 021 and 022 arranged along the first direction F1. Among them, the first color sub-pixel 010 is configured to emit light of the first color, the second color sub-pixels 021 and 022 are configured to emit light of the second color, and the third color sub-pixel is configured to emit light of the third color. In some examples, the first color, the second color, and the third color can be selected from red, green, and blue. For example, the first color is red, the second color is green, and the third color is blue. Thus, the repeating unit 001 is an arrangement structure of red, green, and blue sub-pixels. Of course, the embodiments of the present disclosure include but are not limited to this. The above-mentioned first color, second color, and third color may also be other colors. It should be noted that the arrangement of the above-mentioned sub-pixels can refer to the above-mentioned embodiment, which will not be repeated here.

[0213] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10 As shown, a plurality of repeating units 001 are arranged along the second direction F2 to form a repeating unit group, the repeating unit group is arranged along the first direction F1, and the repeating units 001 in two adjacent repeating unit groups are arranged in a staggered manner. Exemplarily, the repeating units 001 in two adjacent repeating unit groups differ by 1 / 2 of the size of the repeating unit 001. It should be noted that the size of the above-mentioned one repeating unit 001 can be: the distance between the centers of the same color sub-pixels in two adjacent repeating units 001 in the second direction F2. For example, the size of the above-mentioned one repeating unit 001 can be: the distance between the centers of the first color sub-pixels 010 in two adjacent repeating units 001 in the second direction F2.

[0214] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10As shown, the size of the main part 411 of the first color sub-pixel 010 in the second direction F2 is smaller than the size of the main part 413 of the third color sub-pixel 030 in the second direction F2. Moreover, the size of the main part 411 of the first color sub-pixel 010 in the first direction F1 is larger than the size of the main part 413 of the third color sub-pixel 030 in the first direction F1. Exemplarily, the size of the main part 413 of the third color sub-pixel 030 in the second direction F2 is smaller than the size of the main part 413 of the third color sub-pixel 030 in the first direction F1, and the size of the main part 411 of the first color sub-pixel 010 in the second direction F2 is smaller than the size of the main part 411 of the first color sub-pixel 010 in the first direction F1. Of course, the embodiments of the present disclosure include but are not limited to this, and the relationship between the above-mentioned sizes can also be in other forms.

[0215] In specific implementation, Figures 9a to 11 As shown, with one adjacent first power line 210 and one data line 230 as a signal line group, in the embodiment of the present disclosure, in the third color sub-pixel 030, the orthographic projection of the main body part 413 on the substrate 100 covers the orthographic projections of the two signal line groups on the substrate 100. In addition, the two signal line groups overlapping with the orthographic projection of the main body part 413 on the substrate 100 are arranged in parallel on both sides of the center of the main body part 413. Exemplarily, in the third color sub-pixel 030, the orthographic projection of the main body part 413 on the substrate 100 covers the orthographic projections of the two first power lines 210 and the two data lines 230 on the substrate 100. In addition, one first power line 210 and one data line 230 are arranged in parallel on one side of the main body part 413, and another first power line 210 and another data line 230 are arranged in parallel on the other side of the main body part 413.

[0216] Furthermore, in the specific implementation, in the embodiments of the present disclosure, if Figures 9a to 11 As shown, in the third color sub-pixel 030, the orthographic projection of the main body portion 413 on the substrate 100 at least partially overlaps with the orthographic projections of the two bridge lines 240 on the substrate 100. Exemplarily, the orthographic projection of the main body portion 413 on the substrate 100 covers and overlaps with the orthographic projection of one bridge line 240 on the substrate 100, and the orthographic projection of the main body portion 413 on the substrate 100 overlaps with the edge of the orthographic projection of another bridge line 240 on the substrate 100.

[0217] In specific implementation, Figures 9a to 11As shown, in the first color sub-pixel 010, the orthographic projection of the main body part 411 on the substrate 100 covers the orthographic projection of the two signal line groups on the substrate 100. In addition, the two signal line groups overlapping with the orthographic projection of the main body part 411 on the substrate 100 are arranged in parallel on both sides of the main body part 411. Exemplarily, in the first color sub-pixel 010, the orthographic projection of the main body part 411 on the substrate 100 covers the orthographic projection of the two first power lines 210 and the two data lines 230 on the substrate 100. In addition, one first power line 210 and one data line 230 are arranged in parallel on one side of the main body part 411, and another first power line 210 and another data line 230 are arranged in parallel on the other side of the main body part 411. The anode in the first color sub-pixel 010 can be a first electrode, so that the structure of the first conductive layer on both sides of the first anode can be symmetrical, thereby improving the flatness of the first anode.

[0218] In specific implementation, Figures 9a to 11 As shown, the plurality of sub-pixels include a reference conductive layer and a second interlayer insulating layer arranged in a direction away from the substrate, the first power line (such as the power line 210 located on the left side of the bisector corresponding to the anode 411) is electrically connected to the first capacitor upper plate of the reference conductive layer (such as the first electrode CC1a of the third capacitor C2 in the pixel driving circuit located on the left side of the bisector corresponding to the anode 411) through a first via hole (such as the via hole 3832a corresponding to the pixel driving circuit located on the left side of the bisector corresponding to the anode 411) penetrating the second interlayer insulating layer, and the second power line (such as the via hole 3832a corresponding to the pixel driving circuit located on the left side of the bisector corresponding to the anode 411) is electrically connected to the first capacitor upper plate of the reference conductive layer (such as the first electrode CC1a of the third capacitor C2 in the pixel driving circuit located on the left side of the bisector corresponding to the anode 411). The power line 210 on the right side of the bisector corresponding to the anode 411) is electrically connected to the second capacitor upper plate of the reference conductive layer (such as the first electrode CC1a of the third capacitor C2 in the pixel driving circuit on the right side of the bisector corresponding to the anode 411) through the second via hole (such as the via hole 3832a corresponding to the pixel driving circuit on the right side of the bisector corresponding to the anode 411) penetrating the second interlayer insulating layer, and the orthographic projection of the first anode (such as 411) on the base substrate 100 overlaps with the orthographic projection of the first via hole on the base substrate and the orthographic projection of the second via hole on the base substrate. This can make the anode flatter.

[0219] In specific implementation, Figures 9a to 11As shown, the plurality of sub-pixels further include an active semiconductor layer and a first interlayer insulating layer sequentially arranged in a direction away from the base substrate, the first interlayer insulating layer includes a third via hole and a fourth via hole, the source of the fifth transistor (such as T4) of the first sub-pixel (such as 010) is electrically connected to the first power line (such as the power line 210 located on the left side of the bisector corresponding to the anode 411) through the third via hole (such as the via hole 3832a in the first sub-pixel), and the source of the fifth transistor (such as T4) of the second sub-pixel (such as 022) is electrically connected to the second power line (such as the power line 210 located on the right side of the bisector corresponding to the anode 411) through the fourth via hole (such as the via hole 3832a in the second sub-pixel); the orthographic projection of the first anode (such as 411) on the base substrate overlaps with the orthographic projection of the third via hole on the base substrate and the orthographic projection of the fourth via hole on the base substrate respectively. The two sides of the anode can be symmetrically kept flat.

[0220] In specific implementation, Figures 9a to 11 As shown, the positive projection of the anode (such as 4122) of the second sub-pixel (such as 022) on the substrate 100 does not overlap with the positive projection of the capacitor lower plate of the corresponding pixel driving circuit (such as the second pole CC2a of the third capacitor C2 in the pixel driving circuit electrically connected to the anode 4122) on the substrate 100, the positive projection of the power line corresponding to the second sub-pixel (such as 022) on the substrate 100 overlaps with the positive projection of the capacitor lower plate (such as the second pole CC2a of the third capacitor C2 in the pixel driving circuit electrically connected to the anode 4122) on the substrate 100, and the capacitor lower plate (the second pole CC2a of the third capacitor C2 in the pixel driving circuit) simultaneously serves as the gate of the driving transistor; the capacitor lower plate (the second pole CC2a of the third capacitor C2 in the pixel driving circuit) is located on the side of the capacitor upper plate (the first pole CC1a of the third capacitor C2 in the pixel driving circuit) close to the substrate. Since the anode cannot evenly cover each N1 node (such as Figure 2a The connection point between the gate of the driving transistor and the capacitor C2 shown in the figure can be covered with a power line to ensure the uniformity of the N1 node of each display driving circuit.

[0221] In specific implementation, Figures 9a to 11 As shown, the orthographic projection of the first anode (such as 411) on the base substrate 100 overlaps with the orthographic projection of the light emitting control signal line (such as EM1a / EM2a) on the base substrate 100, and the light emitting control signal line is used to control the opening of the light emitting control transistor, and the drain of the light emitting control transistor is connected to the anode. In this way, it is convenient for the first anode to be connected to the drain of the light emitting control transistor.

[0222] In specific implementation, Figures 9a to 11 As shown, the second anode (such as 413) of the third sub-pixel (such as 030) overlaps with the orthographic projection of the third power line (such as the power line 210 on the left side of the anode 413) on the substrate substrate, the orthographic projection of the fourth power line (such as the power line 210 on the right side of the anode 413) on the substrate substrate, the orthographic projection of the third data line (such as the data line 230 on the left side of the anode 413) on the substrate substrate, and the orthographic projection of the fourth data line (such as the data line 230 on the right side of the anode 413) on the substrate substrate, and the third anode (such as 413) overlaps with the reset power signal line (such as Init1a / Init2a) of the third sub-pixel (such as 030), and the reset power signal line (such as Init1a / Init2a) is used to provide a reset voltage to the third anode. In this way, the transmittance can be increased, and the anode is reset by the reset voltage.

[0223] In specific implementation, Figures 9a to 11 As shown, the reset power signal line (such as Init1a / Init2a) is connected to the source of the reset transistor through the first connection portion (such as 342a) extending along the second direction F2, and the orthographic projection of the third anode (such as 413) on the base substrate 100 overlaps with the orthographic projection of the first connection portion (such as 342a) on the base substrate 100. In this way, the transmittance can be increased, and the anode can be reset by the reset voltage.

[0224] In specific implementation, Figures 9a to 11 As shown, the positive projection of the first anode (such as 411) on the substrate 100 overlaps with the positive projection of the capacitor lower plate of the first sub-pixel (such as 010) (such as the second electrode CC2a of the third capacitor C2 in the pixel driving circuit) on the substrate 100 and the positive projection of the capacitor lower plate of the second sub-pixel (such as 022) (such as the second electrode CC2a of the third capacitor C2 in the pixel driving circuit) on the substrate 100, and the first sub-pixel (such as 010) is adjacent to the second sub-pixel (such as 022). In this way, the parasitic capacitance environment of the N1 node can be kept the same, ensuring uniform light emission.

[0225] In specific implementation, Figures 9a to 11As shown, the upper plate of the capacitor of the first sub-pixel (such as 010) (such as the first electrode CC1a of the third capacitor C2 in the pixel driving circuit) has a fifth via hole (such as the hollow area in the first electrode CC1a of the third capacitor C2 in the pixel driving circuit of the first sub-pixel), the upper plate of the capacitor of the second sub-pixel (such as 022) (such as the first electrode CC1a of the third capacitor C2 in the pixel driving circuit) has a sixth via hole (such as the hollow area in the first electrode CC1a of the third capacitor C2 in the pixel driving circuit of the second sub-pixel), and the drain of the compensation transistor of the first sub-pixel (such as 010) is connected to the lower plate of the capacitor through the fifth via hole. (such as the first electrode CC1a of the third capacitor C2 in the pixel driving circuit of the first sub-pixel), the drain of the compensation transistor of the second sub-pixel (such as 022) is connected to the lower plate of the capacitor (such as the first electrode CC1a of the third capacitor C2 in the pixel driving circuit of the second sub-pixel) through the sixth via hole; the fifth via hole (such as the hollowed-out area in the first electrode CC1a of the third capacitor C2 in the pixel driving circuit of the first sub-pixel) is closer to the bisector of the first anode (such as 411) in the first direction relative to the sixth via hole (such as the hollowed-out area in the first electrode CC1a of the third capacitor C2 in the pixel driving circuit of the second sub-pixel). In this way, the fifth via hole can be closer to the center to make the overlapping area larger, thereby having less impact on flatness.

[0226] In specific implementation, Figures 9a to 11 As shown, the orthographic projection of the fourth anode (such as 4121) on the substrate 100 overlaps with the orthographic projection of a pixel driving circuit (such as a pixel driving circuit located in the same column as the pixel driving circuit electrically connected to the anode 4121 and adjacent to the next row) on the substrate 100, and the orthographic projection of the second anode (such as 4122) on the substrate 100 overlaps with the orthographic projection of the second connecting portion (such as 341a) of another pixel driving circuit on the substrate 100, and the second connecting portion (such as 341a) is used to connect the drain of the compensation transistor and the gate of the driving transistor. In this way, the uniformity of the coverage of the N1 node by different sub-pixels can be maintained.

[0227] In specific implementation, Figures 9a to 11As shown, the first anode (such as 411) is connected to the first anode adapter block (such as the first connection line 220 in the first subpixel) through the first anode hole (such as the first via hole 310 in the first subpixel), the second anode (such as 4122) is connected to the second anode adapter block (such as the first connection line 220 in the second subpixel) through the second anode hole (such as the first via hole 310 in the second subpixel), and the third anode (such as 413) is connected to the third anode adapter block (such as the first connection line 220 in the third subpixel) through the third anode hole (such as the first via hole 310 in the third subpixel). The fourth anode (such as 4121) is connected to the fourth anode adapter block (such as the first connecting line 220 in the fourth sub-pixel) through the fourth anode hole (such as the first via hole 310 in the fourth sub-pixel), and the fourth anode hole and the second anode hole do not overlap with the third effective light-emitting area (such as the effective light-emitting area in the third sub-pixel) and the fourth effective light-emitting area (such as the effective light-emitting area in the fourth sub-pixel) in the second direction F2; the light-emitting colors of the fourth sub-pixel (such as 021) and the second sub-pixel (such as 022) are different from the light-emitting color of the first sub-pixel (such as 010).

[0228] In specific implementation, Figures 9a to 11 As shown, the orthographic projection of the third anode (such as 413) on the base substrate 100 has a first overlapping portion with the orthographic projection of the third power line on the base substrate 100, and the orthographic projection of the third anode (such as 413) on the base substrate 100 has a second overlapping portion with the orthographic projection of the fourth data line on the base substrate 100, and the first overlapping portion and the second overlapping portion are respectively located on both sides of the bisector of the third anode (such as 413) in the first direction. In this way, the third power line and the fourth data line whose orthographic projection overlaps with the second anode can be arranged as symmetrically as possible.

[0229] In specific implementation, Figures 9a to 11 As shown, the sizes of the first anode (such as 411) and the third anode (such as 413) in the first direction F1 are both larger than their sizes in the second direction F2; the orthographic projection of the second anode (such as 4122) on the base substrate 100 overlaps with the orthographic projection of a power line on the base substrate 100, and the orthographic projection of the fourth anode (such as 4121) on the base substrate 100 overlaps with the orthographic projection of another power line on the base substrate 100. Since the first anode or the second anode is larger in size, it needs to overlap more with the power line or the data line.

[0230] In specific implementation, Figures 9a to 11 As shown, in the first direction F1, the maximum span between the second anode (eg, 4122) and the fourth anode (eg, 4121) is greater than the maximum span of the first anode (eg, 411).

[0231] In specific implementation, Figures 9a to 11 As shown, there is a symmetry axis between the adjacent second anodes (such as 4122) and the fourth anodes (such as 4121), and the adjacent second anodes (such as 4122) and the fourth anodes (such as 4121) are symmetrically arranged around the symmetry axis.

[0232] In specific implementation, Figures 9a to 11 As shown, the luminous color of the first sub-pixel (such as 010) is different from the luminous color of the second sub-pixel (such as 022). For example, the luminous color of the first sub-pixel may be red, and the luminous color of the second sub-pixel may be green.

[0233] In specific implementation, Figures 9a to 11 As shown, the second sub-pixel (such as 022) includes the second anode (such as 4122), and the fourth sub-pixel (such as 021) includes the fourth anode (such as 4121); the second sub-pixel (such as 022) and the fourth sub-pixel (021) have the same luminous color. For example, the luminous colors of the second sub-pixel and the fourth sub-pixel can both be green.

[0234] Furthermore, in the specific implementation, in the embodiments of the present disclosure, if Figures 9a to 11 As shown, in the first color sub-pixel 010, the orthographic projection of the main part 411 on the substrate 100 overlaps with the orthographic projection of a bridge line 240 on the substrate 100. Exemplarily, the orthographic projection of the main part 411 on the substrate 100 overlaps with the edge of the orthographic projection of a bridge line 240 on the substrate 100.

[0235] In specific implementation, Figures 9a to 11 As shown, in the second color sub-pixel, the orthographic projection of the main part on the substrate 100 overlaps with the orthographic projection of a signal line group on the substrate 100. Moreover, in the same second color sub-pixel pair 020, the signal line group overlapping with the orthographic projection of the main parts of the two second color sub-pixels on the substrate 100 is arranged adjacent to each other. Exemplarily, the second color sub-pixel pair 020 may include a first second color sub-pixel 021 and a second second color sub-pixel 022. Among them, in the first second color sub-pixel 021, the orthographic projection of the main part 4121 on the substrate 100 overlaps with the orthographic projection of a first power line 210 and a data line 220 on the substrate 100. In the second second color sub-pixel 022, the orthographic projection of the main part 4122 on the substrate 100 overlaps with the orthographic projection of another first power line 210 and another data line 220 on the substrate 100. Since the sizes of the first anode and the second anode are large, they need to overlap with more power lines and data lines.

[0236] Furthermore, in the specific implementation, if Figures 9a to 11As shown, the orthographic projection of the main portion 4121 in the first second-color sub-pixel 021 on the substrate 100 may also overlap with the edge of the orthographic projection of a bridge line 240 on the substrate 100 .

[0237] Furthermore, in the specific implementation, if Figures 9a to 11 As shown, the orthographic projection of the main portion 4122 in the second second-color sub-pixel 022 on the substrate 100 may also overlap with the edges of the orthographic projections of the two bridge lines 240 on the substrate 100 .

[0238] In the specific implementation, in the embodiment of the present disclosure, if Figure 9a , Figure 9b , Fig.12 as well as Fig.16 As shown, in each third color sub-pixel 030, the main part 413 and the auxiliary part 423 are electrically connected to each other, the auxiliary part 423 is electrically connected to the first connecting line 223 through the first via 310, and the first connecting line 223 is electrically connected to the drain of the transistor in the pixel driving circuit 20 to input the electrical signal generated by the pixel driving circuit 20 to the anode 400, and also to drive the light-emitting layer 50 to emit light by loading a corresponding voltage on the cathode 60.

[0239] In the specific implementation, in the embodiment of the present disclosure, if Figure 9a , Figure 9b , Fig.12 as well as Fig.16 As shown, in each third color sub-pixel 030, the orthographic projection of the main portion 413 on the substrate 100 does not overlap with the orthographic projection of the first via hole 310 on the substrate 100. In this way, the main portion 413 in each third color sub-pixel 030 is not affected by the first via hole 310, so as to avoid the main portion 413 being uneven due to the first via hole 310, thereby improving the color shift phenomenon of the display panel.

[0240] Optionally, the first insulating layer may be configured as a flat layer, so that the body portion located on the first insulating layer may have a higher flatness.

[0241] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10 , Fig.12 as well as Fig.16As shown, in the third color sub-pixel 030, the main body 413 may be an axisymmetric figure, and the first via 310 may be located on the symmetry axis of the main body 413 along the second direction F2. Exemplarily, the main body 413 in the third color sub-pixel 030 may have a first symmetry axis along the second direction F2. Exemplarily, the shape of the main body 413 in the third color sub-pixel 030 is roughly hexagonal or elliptical, the long symmetry axis of the hexagon or the long axis of the ellipse is roughly parallel to the first direction F1, and the short symmetry axis of the hexagon or the short axis of the ellipse is roughly parallel to the second direction F2, then the short symmetry axis of the hexagon or the short axis of the ellipse can be used as the first symmetry axis. Exemplarily, the first via 310 in the third color sub-pixel 030 can be arranged roughly axisymmetrically with respect to the first symmetry axis. It is also possible that the first via 310 in the third color sub-pixel 030 only intersects with the first symmetry axis, and is not arranged roughly axisymmetrically with respect to the first symmetry axis. Of course, in actual applications, the implementation of the first via hole 310 in the third color sub-pixel 030 may be designed and determined according to the actual application environment, and is not limited here.

[0242] In the specific implementation, in the embodiment of the present disclosure, if Figure 9a , Figure 9b , Fig.13 as well as Fig.16 As shown, in each first color sub-pixel 010, the main part 411 and the auxiliary part 421 are electrically connected to each other, the auxiliary part 421 is electrically connected to the first connection line 221 through the first via hole 310, and the first connection line 221 is electrically connected to the drain of the transistor in the pixel driving circuit 20, so as to facilitate the anode connection to the drain of the light-emitting control transistor to input the electrical signal generated by the pixel driving circuit 20 to the anode 400, and also to drive the light-emitting layer 50 to emit light by loading a corresponding voltage on the cathode 60.

[0243] In the specific implementation, in the embodiment of the present disclosure, if Figure 9a , Figure 9b , Fig.13 as well as Fig.16 As shown, in each first color sub-pixel 010, the orthographic projection of the main part 411 on the substrate 100 does not overlap with the orthographic projection of the first via hole 310 on the substrate 100. In this way, the main part 411 in each first color sub-pixel 010 is not affected by the first via hole 310, so as to avoid the main part 411 being uneven due to the first via hole, thereby improving the color shift phenomenon of the display panel.

[0244] In the specific implementation, in the embodiment of the present disclosure, if Figure 9a , Figure 9b , Fig.10As shown, in the first color sub-pixel 010, the main body 411 may be an axisymmetric figure, and the first via 310 may be located on the symmetry axis of the main body 411 along the second direction F2. Exemplarily, the main body 411 in the first color sub-pixel 010 may have a second symmetry axis along the second direction F2. Exemplarily, the shape of the main body 411 in the first color sub-pixel 010 is roughly hexagonal or elliptical, the long symmetry axis of the hexagon or the long axis of the ellipse is roughly parallel to the first direction F1, and the short symmetry axis of the hexagon or the short axis of the ellipse is roughly parallel to the second direction F2, then the short symmetry axis of the hexagon or the short axis of the ellipse can be used as the second symmetry axis. Exemplarily, the first via 310 in the first color sub-pixel 010 can be arranged roughly axisymmetrically about the second symmetry axis. It is also possible that the first via 310 in the first color sub-pixel 010 only intersects with the second symmetry axis, and is not arranged roughly axisymmetrically about the second symmetry axis. Of course, in actual applications, the implementation of the first via hole 310 in the first color sub-pixel 010 may be designed and determined according to the actual application environment, and is not limited here.

[0245] In the specific implementation, in the embodiment of the present disclosure, if Figure 9a , Figure 9b , Fig.10 , Fig.14 and Fig.17 As shown, in each first second color sub-pixel 021, the main part 4121 and the auxiliary part 4221 are electrically connected to each other, the auxiliary part 4221 is electrically connected to the first connecting line 2221 through the first via hole 310, and the first connecting line 2221 is electrically connected to the drain of the transistor in the pixel driving circuit 20 to input the electrical signal generated by the pixel driving circuit 20 to the anode 400, and also to drive the light-emitting layer 50 to emit light by loading a corresponding voltage on the cathode 60.

[0246] In the specific implementation, in the embodiment of the present disclosure, if Figure 9a , Figure 9b , Fig.10 , Fig.15 and Fig.17 As shown, in each second second color sub-pixel 022, the main part 4122 and the auxiliary part 4222 are electrically connected to each other, the auxiliary part 4222 is electrically connected to the first connecting line 2222 through the first via 310, and the first connecting line 2222 is electrically connected to the drain of the transistor in the pixel driving circuit 20 to input the electrical signal generated by the pixel driving circuit 20 to the anode 400, and also to drive the light-emitting layer 50 to emit light by loading a corresponding voltage on the cathode 60.

[0247] Alternatively, if Figure 9a , Figure 9b , Fig.10 , Figures 14 to 17 As shown, in each second color sub-pixel, the orthographic projection of the main body portion on the substrate does not overlap with the orthographic projection of the first via hole on the substrate. Figure 9a , Figure 9b , Fig.10 , Fig.14 and Fig.17 As shown, in the first second color sub-pixel 021, the orthographic projection of the main part 4121 on the substrate 100 does not overlap with the orthographic projection of the first via hole 310 on the substrate 100. In this way, the main part 4121 in each first second color sub-pixel 021 is not affected by the first via hole 310, so as to avoid the main part 4121 being uneven due to the first via hole 310, thereby improving the color shift phenomenon of the display panel.

[0248] For example, Figure 9a , Figure 9b , Fig.10 , Fig.15 and Fig.17 As shown, in the second second color sub-pixel 021, the orthographic projection of the main part 4122 on the substrate 100 does not overlap with the orthographic projection of the first via hole 310 on the substrate 100. In this way, the main part 4122 in each second second color sub-pixel 022 is not affected by the first via hole 310, so as to avoid the main part 4122 being uneven due to the first via hole 310, thereby improving the color shift phenomenon of the display panel.

[0249] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10 As shown, in the same repeating unit 001, the first via hole 310 of the first second color sub-pixel 021 is arranged close to one side of the first color sub-pixel 010, and the first via hole 310 of the second second color sub-pixel 022 is arranged close to the other side of the first color sub-pixel 010. That is, the first via hole 310 of the first second color sub-pixel 021 and the first via hole 310 of the second second color sub-pixel 022 are respectively located on both sides of the first color sub-pixel 010. Exemplarily, in the same repeating unit 001, the first via hole 310 of the first second color sub-pixel 021 can be arranged between the main body 411 in the first color sub-pixel 010 in the repeating unit 001 and the main body 413 in the third color sub-pixel 030 adjacent to the left side of the main body 411. Furthermore, in the same repeating unit 001 , the first via hole 310 of the second second color sub-pixel 022 may be disposed between the main portion 411 of the first color sub-pixel 010 in the repeating unit 001 and the main portion 413 of the third color sub-pixel 030 adjacent to the right side of the main portion 411 .

[0250] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10 As shown, in the same repeating unit 001, the first via hole 310 of the first color sub-pixel 010, the first via hole 310 of the first second color sub-pixel 021 in the second color sub-pixel pair 020, and the first via hole 310 of the second second color sub-pixel 022 are arranged on the same straight line along the first direction F1. Exemplarily, in a repeating unit 001 of the second column repeating unit group, the first via hole 310 of the first color sub-pixel 010, the first via hole 310 of the first second color sub-pixel 021 in the second color sub-pixel pair 020, and the first via hole 310 of the second second color sub-pixel 022 can make the three first via holes 310 arranged on the same straight line along the first direction F1, thereby reducing the difficulty of designing the mask used when preparing the three first via holes 310.

[0251] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10 As shown, the first via holes 310 of the third color sub-pixel 030 and the first via holes 310 of the first color sub-pixel 010 in the same repeating unit 001 are arranged on the same straight line along the second direction F2. This can also reduce the difficulty of designing the mask used in preparing the three first via holes 310.

[0252] Optionally, in a specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10 As shown, in the same repeating unit group, the first via hole 310 of the third color sub-pixel 030 and the first via hole 310 of the first color sub-pixel 010 are arranged on the same straight line along the second direction F2. Also, in the same repeating unit group, the first via hole 310 of the first second color sub-pixel 021 in each second color sub-pixel pair 020 is arranged on the same straight line along the second direction F2. And in the same repeating unit group, the first via hole 310 of the second second color sub-pixel 022 in each second color sub-pixel pair 020 is arranged on the same straight line along the second direction F2. This can also reduce the difficulty of designing the mask used when preparing these first via holes 310.

[0253] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10 As shown, in the odd-numbered repeating unit group, the first via hole 310 of the first color sub-pixel 010 in the same row of repeating unit 001, the first via hole 310 of the first second color sub-pixel 021 in the second color sub-pixel pair 020, and the first via hole 310 of the second second color sub-pixel 022 are arranged on the same straight line along the first direction F1. This can also reduce the difficulty of designing the mask used when preparing the three first via holes 310 in the display panel.

[0254] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10 As shown, in the odd-numbered repeating unit group, the first via holes 310 of the third color sub-pixels 030 in the same row of repeating units 001 are arranged on the same straight line along the first direction F1. This can also reduce the difficulty of designing the mask used when preparing the three first via holes 310 in the display panel.

[0255] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10 As shown, in the even-numbered repeating unit group, the first via hole 310 of the first color sub-pixel 010 in the same row of repeating unit 001, the first via hole 310 of the first second color sub-pixel 021 in the second color sub-pixel pair 020, and the first via hole 310 of the second second color sub-pixel 022 are arranged on the same straight line along the first direction F1. This can also reduce the difficulty of designing the mask used when preparing the three first via holes 310 in the display panel.

[0256] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 10 As shown, in the even-numbered repeating unit group, the first via holes 310 of the third color sub-pixels 030 in the same row of repeating units 001 are arranged on the same straight line along the first direction F1. This can also reduce the difficulty of designing the mask used when preparing the three first via holes 310 in the display panel.

[0257] Furthermore, it should be noted that the implementation of the first via hole in this embodiment can also refer to the implementation of the first via hole in the above embodiment, which will not be described in detail here.

[0258] It should be noted that due to the limitation of process conditions or other factors, the similarities among the above-mentioned features may not be completely the same and may have some deviations. Therefore, as long as the similarities among the above-mentioned features roughly meet the above-mentioned conditions, they all belong to the protection scope of the present invention. For example, the above-mentioned similarities may be the same as allowed within the tolerance range.

[0259] Furthermore, due to limitations of process conditions or other factors, the different vias cannot be arranged completely in a straight line along the first direction or the second direction, and there may be some deviations. Therefore, as long as the relationship of the above-mentioned arrangement in a straight line roughly meets the above-mentioned conditions, it belongs to the protection scope of the present invention.

[0260] The electroluminescent display panel provided by the embodiment of the present disclosure is as follows: Figure 9a , Figure 9b , Fig.11 , Fig.12As shown, it includes: a base substrate 100; a plurality of sub-pixels, each of which includes a pixel driving circuit; the pixel driving circuit includes a semiconductor layer (such as 0310); the pixel driving circuit includes a first conductive layer (such as 200), which is located above the base substrate 100; the first conductive layer 200 includes an anode connecting portion (such as 220), a data line (such as 230), and a power line (such as 210) which are arranged at intervals from each other; wherein the size of the data line in the second direction F2 is greater than its size in the first direction F1, the size of the power line in the second direction F2 is greater than its size in the first direction F1, and the first direction F1 is different from the second direction F2. An anode 400 is located on the side of the first conductive layer 200 away from the base substrate 100; there is at least one film layer between the layer where the anode 400 is located and the first conductive layer 200, and the anode 400 is directly connected to the anode connecting portion (such as 220) through a first via 310 that penetrates the at least one film layer. The sub-pixel includes a first sub-pixel (such as 010) and a second sub-pixel (such as 022), the first sub-pixel (such as 010) includes a first pixel driving circuit, and the second sub-pixel (such as 022) includes a second pixel driving circuit; the first pixel driving circuit includes a first semiconductor pattern located in the semiconductor layer, and the second pixel driving circuit includes a second semiconductor pattern located in the semiconductor layer; the first pixel driving circuit and the second pixel driving circuit are arranged along a first direction F1. The anode includes a first anode; the first anode (such as anode 400 of the first color sub-pixel 010) is electrically connected to the first pixel driving circuit. The data line includes a first data line and a second data line; the first data line is electrically connected to the first pixel driving circuit, and the second data line is electrically connected to the second pixel driving circuit. The power line includes a first power line and a second power line; the orthographic projection of the first power line on the substrate 100 overlaps with the orthographic projection of the first semiconductor pattern on the substrate 100, and the orthographic projection of the second power line on the substrate 100 overlaps with the orthographic projection of the second semiconductor pattern on the substrate 100. Furthermore, the orthographic projection of the first anode (such as the anode 400 of the first color sub-pixel 010) electrically connected to the first pixel driving circuit overlaps with the orthographic projection of the first data line, the orthographic projection of the second data line, the orthographic projection of the first power line and the orthographic projection of the second power line on the substrate 100. By setting it in this way, the positional relationship between the anode and the metal film layer closest to it can be made as follows: the anode overlaps with the two data lines and the two power lines connected to the pixel driving circuits in the two adjacent sub-pixels, respectively, which can improve the flatness of the anode and avoid color deviation.

[0261] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the size of the first anode (such as the anode 400 of the first color sub-pixel 010) in the first direction F1 is greater than the size of the first anode (such as the anode 400 of the first color sub-pixel 010) in the second direction F2; the pixel driving circuit includes a capacitor (such as a third capacitor C2), and the capacitor (such as the third capacitor C2) includes a capacitor lower plate (such as the second pole CC2a of the third capacitor C2) close to the substrate 100 and a capacitor upper plate (such as the first pole CC1a of the third capacitor C2) away from the substrate 100; wherein, the first pixel driving circuit includes a first capacitor lower plate (such as the second pole CC2a of the third capacitor C2 in the first sub-pixel (such as 010)), and the second pixel driving circuit includes a second capacitor lower plate (such as the second pole CC2a of the third capacitor C2 in the second sub-pixel); wherein, the first capacitor lower plate (such as the second pole CC2a of the third capacitor C2 in the first sub-pixel (such as 010)) and the second capacitor lower plate (such as the second pole CC2a of the third capacitor C2 in the second sub-pixel) are arranged on the same layer. Furthermore, the orthographic projection of the first anode electrically connected to the first pixel driving circuit (such as the anode 400 of the first color sub-pixel 010) on the substrate substrate 100 overlaps with the orthographic projection of the first capacitor lower plate (such as the second electrode CC2a of the third capacitor C2 in the first sub-pixel (such as 010)) on the substrate substrate 100 and the orthographic projection of the second capacitor lower plate (such as the second electrode CC2a of the third capacitor C2 in the second sub-pixel) on the substrate substrate 100, respectively, and the overlapping area between the first anode (such as the anode 400 of the first color sub-pixel 010) and the first capacitor lower plate (such as the second electrode CC2a of the third capacitor C2 in the first sub-pixel (such as 010)) is greater than the overlapping area between the first anode (such as the anode 400 of the first color sub-pixel 010) and the second capacitor lower plate (such as the second electrode CC2a of the third capacitor C2 in the second sub-pixel). By such a configuration, the coverage area of ​​the first anode (such as the anode 400 of the first color sub-pixel 010) on the lower plate of the first capacitor (such as the second electrode CC2a of the third capacitor C2 in the first sub-pixel (such as 010)) can be made larger than the overlapping area on the lower plate of the second capacitor (such as the second electrode CC2a of the third capacitor C2 in the second sub-pixel), which can avoid anode offset, reduce the area of ​​the anode, and improve the transmittance, which is beneficial to under-screen fingerprint recognition.

[0262] In some embodiments of the present disclosure, Figures 9a to 15As shown, each pixel driving circuit includes a driving transistor T1; the driving transistor T1 includes a gate; the lower plate of the first capacitor (such as the second electrode CC2a of the third capacitor C2 in the first sub-pixel (such as 010)) serves as the gate of the driving transistor T1 in the first pixel driving circuit; the lower plate of the second capacitor (such as the second electrode CC2a of the third capacitor C2 in the second sub-pixel) serves as the gate of the driving transistor T1 in the second pixel driving circuit.

[0263] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the orthographic projection of the power line (such as 210) on the base substrate 100 overlaps with the orthographic projection of the gate of the driving transistor T1 on the base substrate 100. This can stabilize the power line voltage and shield the external jump voltage from affecting the gate of the driving transistor T1.

[0264] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the overlapping area of ​​the orthogonal projection of the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate 100 and the orthogonal projection of the first data line (i.e., the data line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the substrate 100 is substantially equal to the overlapping area of ​​the orthogonal projection of the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate 100 and the orthogonal projection of the second data line (i.e., the data line connected to the second pixel driving circuit of the second sub-pixel) on the substrate 100. In this way, the flatness of the anode can be further improved.

[0265] In some embodiments of the present disclosure, Figures 9a to 15As shown, the anode 400 includes a main part 410 and an auxiliary part 420 that are electrically connected to each other; the orthographic projection of the effective light-emitting area 90 of the anode on the base substrate 100 is located inside the orthographic projection of the main part 410 on the base substrate 100, and the main part 410 and the anode 400 have at least partially the same boundary; the orthographic projection of the first via 310 on the base substrate 100 is located inside the orthographic projection of the auxiliary part 420 on the base substrate 100, and the auxiliary part 420 and the anode have at least partially the same boundary; the first anode The overlapping area of ​​the orthographic projection of the main part 410 in the anode 400 of the first color sub-pixel 010 on the substrate 100 and the orthographic projection of the first data line (i.e., the data line connected to the first pixel driving circuit of the first sub-pixel (e.g., 010)) on the substrate 100 and the overlapping area of ​​the orthographic projection of the main part 410 in the first anode (e.g., the anode 400 of the first color sub-pixel 010) on the substrate 100 and the orthographic projection of the second data line (i.e., the data line connected to the second pixel driving circuit of the second sub-pixel) on the substrate 100 are substantially equal. In this way, by setting the main part to include the effective light-emitting area, the flatness of the anode is further improved.

[0266] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the distance between the first data line (i.e., the data line connected to the first pixel driving circuit of the first sub-pixel (e.g., 010)) and the first power line (i.e., the power line connected to the first pixel driving circuit of the first sub-pixel (e.g., 010)) is smaller than the distance between the first power line (i.e., the power line connected to the first pixel driving circuit of the first sub-pixel (e.g., 010)) and the second power line (i.e., the power line connected to the second pixel driving circuit of the second sub-pixel).

[0267] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the overlapping area of ​​the orthographic projection of the effective light-emitting area (such as 90-010) corresponding to the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate 100 and the orthographic projection of the first data line (i.e., the data line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the substrate 100 is substantially equal to the overlapping area of ​​the orthographic projection of the effective light-emitting area (such as 90-010) corresponding to the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate 100 and the orthographic projection of the second data line (i.e., the data line connected to the second pixel driving circuit of the second sub-pixel) on the substrate 100. In this way, the flatness of the effective light-emitting area can be further improved.

[0268] In some embodiments of the present disclosure, Figures 9a to 15As shown, each pixel driving circuit includes a storage capacitor; the storage capacitor includes an upper plate of the capacitor (such as the first electrode CC1a of the third capacitor C2); the upper plate of the capacitor (such as the first electrode CC1a of the third capacitor C2) is located between the lower plate of the capacitor (such as the second electrode CC2a of the third capacitor C2) and the first conductive layer 200; the upper plate of the capacitor (such as the first electrode CC1a of the third capacitor C2) has a plate hole; the orthographic projection of the first anode (such as the anode 400 of the first color sub-pixel 010) on the base substrate 100 overlaps with the orthographic projection of the plate hole of the upper plate of the capacitor (such as the first electrode CC1a of the third capacitor C2) in the first sub-pixel (such as 010) on the base substrate 100.

[0269] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the edge portion of the first anode (such as the anode 400 of the first color sub-pixel 010) in the first direction F1 has a first anode size in the second direction F2; the middle portion of the first anode (such as the anode 400 of the first color sub-pixel 010) in the first direction F1 has a second anode (such as 4122) size in the second direction F2; the first anode size is smaller than the second anode (such as 4122) size.

[0270] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the edge portion of the anode in the second sub-pixel in the second direction F2 has a third anode size in the first direction F1; the middle portion of the anode in the second sub-pixel in the second direction F2 has a fourth anode (such as 4121) size in the first direction F1; the third anode size is smaller than the fourth anode (such as 4121) size.

[0271] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the minimum distance between the centers of effective light-emitting areas of two sub-pixels having a first light-emitting color is smaller than the minimum distance between the centers of effective light-emitting areas of other sub-pixels of the same light-emitting color, which is different from the first light-emitting color.

[0272] In some embodiments of the present disclosure, Figures 9a to 15As shown, the sub-pixel includes a third sub-pixel (such as 030); the direction in which the auxiliary part 420 in the first sub-pixel (such as 010) protrudes the main part 410 in the first color sub-pixel 010 is a first protruding direction; the direction in which the auxiliary part 420 in the second color sub-pixel protrudes the main part 410 in the second color sub-pixel is a second protruding direction; the direction in which the auxiliary part 420 in the third color sub-pixel protrudes the main part 410 in the third color sub-pixel is a third protruding direction; the angle between the first protruding direction and the third protruding direction is smaller than the angle between the first protruding direction and the second protruding direction.

[0273] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the minimum distance between the anode 400 in the first color sub-pixel 010 and the anode in the second color sub-pixel (such as 021, 022) is less than the length of the auxiliary part 420 in the second color sub-pixel (such as 021, 022).

[0274] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the distance between the first via hole 310 in the second color sub-pixel (such as 021, 022) and the first via hole 310 in the third color sub-pixel 030 is smaller than the length of the anode in the third color sub-pixel 030 in the first direction F1.

[0275] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the ratio between the orthographic projection of the main part 410 in the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate 100 and the orthographic projection of the first power line (i.e., the power line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the substrate 100 and the orthographic projection of the second power line (i.e., the power line connected to the second pixel driving circuit of the second sub-pixel) on the substrate 100 is substantially the same. In this way, the flatness of the anode can be further improved.

[0276] In some embodiments of the present disclosure, Figures 9a to 15As shown, the sum of the overlapping areas of the main part 410 in the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate substrate 100, the first power line (i.e., the power line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the substrate substrate 100, and the first data line (i.e., the data line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the substrate substrate 100 is the first area sum; the sum of the overlapping areas of the main part 410 in the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate substrate 100, the second power line (i.e., the power line connected to the second pixel driving circuit of the second sub-pixel) on the substrate substrate 100, and the second data line (i.e., the data line connected to the second pixel driving circuit of the second sub-pixel) on the substrate substrate 100 is the second area sum; the first area sum is substantially equal to the second area sum. In this way, the flatness of the anode can be further improved.

[0277] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the sum of the overlapping areas of the orthographic projection of the effective luminous area (such as 90-010) corresponding to the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate substrate 100, the orthographic projection of the first power line (i.e., the power line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the substrate substrate 100, and the orthographic projection of the first data line (i.e., the data line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the substrate substrate 100 is the third area sum; the sum of the overlapping areas of the orthographic projection of the effective luminous area (such as 90-010) corresponding to the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate substrate 100, the orthographic projection of the second power line (i.e., the power line connected to the second pixel driving circuit of the second sub-pixel) on the substrate substrate 100, and the orthographic projection of the second data line (i.e., the data line connected to the second pixel driving circuit of the second sub-pixel) on the substrate substrate 100 is the fourth area sum; the third area sum is substantially equal to the fourth area sum. In this way, the flatness of the anode can be further improved.

[0278] In some embodiments of the present disclosure, Figures 9a to 15As shown, the positive projection of one of the anodes 400 on the base substrate 100 overlaps with the positive projections of the scanning signal line (such as the second scanning signal line Ga2a), the reset control signal line (such as the first reset control signal line Rst1a / the second reset control signal line Rst2a) and the reset power signal line (such as the first reset power signal line Init1a / the second reset power signal line Init2a) on the base substrate 100; the scanning signal line (such as the second scanning signal line Ga2a) is used to control the threshold compensation transistor T3 in the pixel driving circuit; the reset control signal line (such as the first reset control signal line Rst1a / the second reset control signal line Rst2a) is used to control the first reset transistor T6 in the pixel driving circuit;

[0279] The reset power signal line (such as the first reset power signal line Init1a / the second reset power signal line Init2a) is used to provide an initialization voltage.

[0280] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1, and the reset power signal line (such as the first reset power signal line Init1a / the second reset power signal line Init2a) is electrically connected to the gate of the driving transistor T1 through the first reset transistor T6.

[0281] In some embodiments of the present disclosure, Figures 9a to 15 As shown, a first connection block (such as 341a) disposed in a conductive layer electrically connects the gate of the driving transistor T1 and the source or drain region of the threshold compensation transistor T3 in the semiconductor layer;

[0282] The first conductive layer 200 is disposed between the anode 400 and the semiconductor layer (eg, 0310).

[0283] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the orthographic projection of the scan signal line on the base substrate 100 overlaps with the orthographic projection of the first connection block on the base substrate 100 .

[0284] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the second connection block disposed in the one conductive layer electrically connects the reset power signal line and the source region of the first reset transistor T6 in the semiconductor layer.

[0285] In some embodiments of the present disclosure, Figures 9a to 15As shown, the reset control signal line (such as the first reset control signal line Rst1a / the second reset control signal line Rst2a) has an orthographic projection on the substrate 100 between the orthographic projection of the scan signal line (such as the second scan signal line Ga2a) on the substrate 100 and the orthographic projection of the reset power signal line (such as the first reset power signal line Init1a / the second reset power signal line Init2a) on the substrate 100.

[0286] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the power line is electrically connected to the upper plate of the capacitor (such as the first electrode CC1a of the third capacitor C2) disposed on the reference conductive layer 0330.

[0287] In some embodiments of the present disclosure, Figures 9a to 15 As shown, at least one film layer is provided on a side of the first conductive layer 200 away from the layer where the anode 400 is located; the power line (such as 210) is electrically connected to the corresponding pixel driving circuit through a connecting through hole (such as 3832a) penetrating the at least one film layer, and the first anode (such as the anode 400 of the first color sub-pixel 010) is electrically connected to the connecting through hole (such as 3832a) corresponding to the first power line (i.e., the power line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the orthographic projection of the substrate 100 and the connecting through hole (such as 3832a) corresponding to the second power line (i.e., the power line connected to the second pixel driving circuit of the second sub-pixel) on the orthographic projection of the substrate 100. a) The orthographic projections of the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate 100 overlap, and the overlapping area of ​​the orthographic projection of the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate 100 and the orthographic projection of the connecting through hole (such as 3832a) corresponding to the first power line (i.e., the power line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the substrate 100 and the orthographic projection of the connecting through hole (such as 3832a) corresponding to the second power line (i.e., the power line connected to the second pixel driving circuit of the second sub-pixel) on the substrate 100 are substantially equal. In this way, the connecting through hole can have a recess, so that the environment on both sides of the anode is as similar as possible, and the flatness is improved.

[0288] In some embodiments of the present disclosure, Figures 9a to 15As shown, the main part 410 of the first anode (such as the anode 400 of the first color sub-pixel 010) in the orthographic projection on the substrate 100 and the corresponding effective light-emitting area (90-010) in the orthographic projection on the substrate 100 overlap with the orthographic projection of the light-emitting control signal line (such as EM1a / EM2a) in the substrate 100; the light-emitting control signal line (such as EM1a / EM2a) is used to control the light-emitting control transistors in the first pixel driving circuit and the second pixel driving circuit.

[0289] In some embodiments of the present disclosure, Figures 9a to 15 As shown, there is an orthographic projection of the upper plate of the capacitor (such as the first electrode CC1a of the third capacitor C2) on the substrate 100 between the orthographic projection of the light-emitting control signal line (such as EM1a / EM2a) on the substrate 100 and the orthographic projection of the scanning signal line (such as the second scanning signal line Ga2a) on the substrate 100.

[0290] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the anode 400 includes a main part 410 and an auxiliary part 420 electrically connected to each other; the main part 4 of the anode in at least two color sub-pixels does not overlap with the corresponding capacitor lower plate (such as the second electrode CC2a of the third capacitor C2) on the substrate 100. In this way, the anode signal can change more greatly, and the non-overlapping can reduce the signal interference to the gate of the driving tube.

[0291] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the at least two colors are different from the luminous colors of the sub-pixel where the first pixel driving circuit is located.

[0292] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the anode 400 includes a main portion 410 and an auxiliary portion 420 which are electrically connected to each other; the auxiliary portions 420 of at least two anodes extend in different directions.

[0293] In some embodiments of the present disclosure, Figures 9a to 15As shown, the anode also includes a fourth anode (such as 4121); the size of the fourth anode (such as 4121) in the first direction F1 is larger than its size in the second direction F2; the orthographic projection of the fourth anode (such as 4121) on the base substrate 100 is respectively connected to the orthographic projection of the first data line (that is, the data line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the base substrate 100, the orthographic projection of the second data line (that is, the data line connected to the second pixel driving circuit of the second sub-pixel) on the base substrate 100, and the first power line ( That is, the orthographic projection of the power line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the substrate substrate 100 and the orthographic projection of the second power line (that is, the power line connected to the second pixel driving circuit of the second sub-pixel) on the substrate substrate 100 overlap; the orthographic projection of the effective light-emitting area (such as 90-010) corresponding to the first anode (such as the anode 400 of the first color sub-pixel 010) on the substrate substrate 100 and the orthographic projection of the effective light-emitting area corresponding to the fourth anode (such as 4121) on the substrate substrate 100 cannot overlap after translation.

[0294] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the overlapping area of ​​the orthographic projection of the fourth anode (such as 4121) on the base substrate 100 and the orthographic projection of the first power line (i.e., the power line connected to the first pixel driving circuit of the first sub-pixel (such as 010)) on the base substrate 100 is greater than the overlapping area of ​​the orthographic projection of the second anode (such as 4122) on the base substrate 100 and the orthographic projection of the second power line (i.e., the power line connected to the second pixel driving circuit of the second sub-pixel) on the base substrate 100.

[0295] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the orthographic projection of the main portion 410 of the anode in the plurality of sub-pixels on the base substrate 100 does not overlap with the orthographic projection of the corresponding anode connecting portion (such as 220 ) on the base substrate 100 .

[0296] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the multiple sub-pixels include green sub-pixels (such as 021 and 022); the orthographic projection of the anode connection portion (such as 220) in the green sub-pixels (such as 021 and 022) on the base substrate 100 does not overlap with the orthographic projection of the main portion (such as 4121 in 021 and 4122 in 022) of the corresponding anode (such as the anode in 021 and the anode in 022) on the base substrate 100.

[0297] In some embodiments of the present disclosure, Figures 9a to 15As shown, in the green sub-pixel (such as 021 and 022), the orthographic projection of the first via hole 310 on the base substrate 100 does not overlap with the orthographic projection of the corresponding main part of the anode (such as 4121 in 021 and 4122 in 022) on the base substrate 100 in the first direction F1, and the orthographic projection of the first via hole 310 on the base substrate 100 does not overlap with the orthographic projection of the corresponding effective light-emitting area (such as 90-021 in 021 and 90-022 in 022) on the base substrate 100 in the first direction F1.

[0298] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the first via holes 310 in the plurality of sub-pixels are located on the same straight line extending along the first direction F1; wherein the orthographic projections of the effective light-emitting areas corresponding to at least two of the first via holes 310 on the base substrate 100 cannot overlap after translation.

[0299] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the first via holes 310 in the plurality of sub-pixels are located on the same straight line extending along the first direction F1; wherein, the orthographic projections of at least two of the first via holes 310 on the base substrate 100 do not overlap with the orthographic projections of the corresponding main parts 410 of the anode on the base substrate 100 in the second direction F2, and the orthographic projections of at least two of the first via holes 310 on the base substrate 100 do not overlap with the orthographic projections of the corresponding effective light-emitting areas on the base substrate 100 in the second direction F2.

[0300] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the auxiliary part (such as 4221 in 021 and 4222 in 022) in the green sub-pixel (such as 021 and 022) includes an anode hole setting part and an anode hole connecting part; the anode hole setting part and the anode hole connecting part are both in the shape of long strips; the anode hole connecting part is used to electrically connect the main part 410 and the anode hole setting part; in the green sub-pixel (such as 021 and 022), the orthographic projection of the first via 310 on the base substrate 100 is located inside the orthographic projection of the anode hole setting part on the base substrate 100, and the maximum width of the anode hole setting part is greater than the maximum width of the anode hole connecting part.

[0301] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the overlapping areas between at least two anodes and the corresponding lower plates of the capacitors (such as the second electrode CC2a of the third capacitor C2) are approximately equal; the effective light-emitting areas corresponding to the at least two anodes cannot overlap after the orthographic projection of the base substrate 100 is translated.

[0302] In some embodiments of the present disclosure, Figures 9a to 15 As shown, the two anodes both correspond to green sub-pixels (eg, 021 and 022).

[0303] Based on the same inventive concept, the embodiment of the present disclosure also provides a display device, including the electroluminescent display panel provided by the embodiment of the present disclosure. The principle of solving the problem by the display device is similar to that of the electroluminescent display panel, so the implementation of the display device can refer to the implementation of the electroluminescent display panel, and the repeated parts will not be repeated here.

[0304] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0305] The electroluminescent display panel and display device provided by the embodiments of the present disclosure make the anode include a main part and an auxiliary part electrically connected to each other, and the auxiliary part is electrically connected to the first conductive layer through a first via hole, so that the anode is electrically connected to the pixel driving circuit through the first conductive layer. In addition, since the orthographic projection of the main part on the substrate and the orthographic projection of the first via hole on the substrate do not overlap in at least one sub-pixel, the first via hole in the sub-pixel can be avoided, so that the main part of the anode in the sub-pixel is not affected by the depth of the first via hole, thereby avoiding the main part of the anode from being concave, avoiding the unevenness of the anode caused by the first via hole, and thus improving the color deviation phenomenon of the display panel.

[0306] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display substrate, comprising a base substrate, a plurality of sub-pixels; the plurality of sub-pixels comprising a planar layer, an anode layer, and a plurality of pixel driving circuits; the plurality of pixel driving circuits comprising a first conductive layer; the first conductive layer, the planar layer, and the anode layer are sequentially arranged in a direction away from the base substrate; The first conductive layer includes a plurality of power lines extending along the second direction and arranged at intervals, a plurality of data lines extending along the second direction and arranged at intervals, and a plurality of anode transfer blocks; wherein, The plurality of power lines extending along the second direction include adjacent first power lines and second power lines, and the plurality of data lines extending along the second direction include adjacent first data lines and second data lines; The anode layer includes a plurality of anodes, and the plurality of pixel driving circuits drive corresponding anodes respectively; the first anode of the first sub-pixel overlaps with the orthographic projections of the first power line, the second power line, the first data line, and the second data line on the substrate; The anode is directly connected to the anode adapter block; the first anode has a bisector in the first direction, the first power line and the first data line are located on one side of the bisector, and the second power line and the second data line are located on the other side of the bisector; wherein the first direction intersects with the second direction.

2. The display substrate according to claim 1, wherein: The multiple sub-pixels include a reference conductive layer and a second interlayer insulating layer arranged in a direction away from the base substrate, the first power line is electrically connected to the first capacitor upper plate of the reference conductive layer through a first via hole penetrating the second interlayer insulating layer, the second power line is electrically connected to the second capacitor upper plate of the reference conductive layer through a second via hole penetrating the second interlayer insulating layer, and the orthographic projection of the first anode on the base substrate overlaps with the orthographic projection of the first via hole on the base substrate and the orthographic projection of the second via hole on the base substrate.

3. The display substrate according to claim 2, wherein: The plurality of sub-pixels further include an active semiconductor layer and a first interlayer insulating layer sequentially arranged in a direction away from the base substrate, the first interlayer insulating layer includes a third via hole and a fourth via hole, the source of the fifth transistor of the first sub-pixel is electrically connected to the first power line through the third via hole, and the source of the fifth transistor of the second sub-pixel is electrically connected to the second power line through the fourth via hole; The orthographic projection of the first anode on the base substrate overlaps with the orthographic projection of the third via hole on the base substrate and the orthographic projection of the fourth via hole on the base substrate respectively.

4. The display substrate according to claim 3, wherein: The orthographic projection of the anode of the second sub-pixel on the substrate does not overlap with the orthographic projection of the lower plate of the capacitor of the corresponding pixel driving circuit on the substrate, the orthographic projection of the power line of the second sub-pixel on the substrate overlaps with the orthographic projection of the lower plate of the capacitor corresponding to the second sub-pixel on the substrate, and the lower plate of the capacitor also serves as the gate of the driving transistor; the lower plate of the capacitor is located on the side of the upper plate of the capacitor close to the substrate.

5. The display substrate according to claim 4, wherein: The orthographic projection of the first anode on the base substrate overlaps with the orthographic projection of the light emitting control signal line on the base substrate. The light emitting control signal line is used to control the opening of the light emitting control transistor. The drain of the light emitting control transistor is connected to the anode.

6. The display substrate according to claim 5, wherein: The orthographic projection of the third anode of the third sub-pixel on the substrate overlaps with the orthographic projection of the third power line on the substrate, the orthographic projection of the fourth power line on the substrate, the orthographic projection of the third data line on the substrate, and the orthographic projection of the fourth data line on the substrate, and the third anode overlaps with the reset power signal line of the third sub-pixel, and the reset power signal line is used to provide a reset voltage to the third anode.

7. The display substrate according to claim 6, wherein: The reset power signal line is connected to the source of the reset transistor via a first connection portion extending along the second direction, and an orthographic projection of the third anode on the base substrate overlaps with an orthographic projection of the first connection portion on the base substrate.

8. The display substrate according to claim 7, wherein: The orthographic projection of the first anode on the substrate overlaps with the orthographic projection of the capacitor lower plate of the first sub-pixel on the substrate and the orthographic projection of the capacitor lower plate of the second sub-pixel on the substrate, and the first sub-pixel is adjacent to the second sub-pixel.

9. The display substrate according to claim 8, wherein: The upper plate of the capacitor of the first sub-pixel has a fifth via hole, the upper plate of the capacitor of the second sub-pixel has a sixth via hole, the drain of the compensation transistor of the first sub-pixel is connected to the lower plate of the capacitor through the fifth via hole, and the drain of the compensation transistor of the second sub-pixel is connected to the lower plate of the capacitor through the sixth via hole; The fifth via hole is closer to a bisector of the first anode in the first direction than the sixth via hole.

10. The display substrate according to claim 9, wherein: The orthographic projection of the fourth anode on the substrate overlaps with the orthographic projection of the second connection part of a pixel driving circuit on the substrate, and the orthographic projection of the second anode on the substrate overlaps with the orthographic projection of the second connection part of another pixel driving circuit on the substrate, and the second connection part is used to connect the drain of the compensation transistor and the gate of the driving transistor.

11. The display substrate according to claim 10, wherein: The first anode is connected to the first anode adapter block through the first anode hole, the second anode is connected to the second anode adapter block through the second anode hole, the third anode is connected to the third anode adapter block through the third anode hole, and the fourth anode is connected to the fourth anode adapter block through the fourth anode hole, and the fourth anode hole and the second anode hole do not overlap with the third effective light-emitting area and the fourth effective light-emitting area in the second direction; the light-emitting color of the fourth sub-pixel and the second sub-pixel is different from the light-emitting color of the first sub-pixel.

12. The display substrate according to claim 11, wherein: The orthographic projection of the third anode on the substrate has a first overlapping portion with the orthographic projection of the third power line on the substrate, and the orthographic projection of the third anode on the substrate has a second overlapping portion with the orthographic projection of the fourth data line on the substrate, and the first overlapping portion and the second overlapping portion are respectively located on both sides of the bisector of the third anode in the first direction.

13. The display substrate according to claim 12, wherein: The sizes of the first anode and the third anode in the first direction are both larger than their sizes in the second direction; the orthographic projection of the second anode on the substrate overlaps with the orthographic projection of a power line on the substrate, and the orthographic projection of the fourth anode on the substrate overlaps with the orthographic projection of another power line on the substrate.

14. The display substrate according to claim 13, wherein: In the first direction, a maximum span between the second anode and the fourth anode is greater than a maximum span of the first anode.

15. The display substrate according to claim 14, wherein: An axis of symmetry is defined between the adjacent second anodes and the adjacent fourth anodes, and the adjacent second anodes and the adjacent fourth anodes are symmetrically arranged via the axis of symmetry.

16. The display substrate according to claim 15, wherein: The light-emitting color of the first sub-pixel is different from the light-emitting color of the second sub-pixel.

17. The display substrate according to claim 16, wherein: The second sub-pixel includes the second anode, and the fourth sub-pixel includes the fourth anode; The second sub-pixel and the fourth sub-pixel emit the same light color.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

Images