Thin-film transistors, methods for manufacturing thin-film transistors, and display devices including thin-film transistors.

Abstract

A thin-film transistor (TFT) and its manufacturing method are disclosed. The TFT includes: an active layer; a gate electrode spaced apart from and partially overlapping the active layer; and a gate insulating film between the active layer and the gate electrode. The active layer includes: a channel portion overlapping the gate electrode; a conductive portion not overlapping the gate electrode; and a gradient portion between the channel portion and the conductive portion, not overlapping the gate electrode. The conductive portion and the gradient portion of the active layer are doped with dopants. The gate insulating film covers the upper surface of the active layer facing the gate electrode during the doping of the active layer. In the gradient portion, the concentration of the dopant increases along the direction from the channel portion toward the conductive portion. A display device including a TFT is also disclosed.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0131180, filed on October 12, 2020, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to a thin-film transistor, a method of manufacturing a thin-film transistor, and a display device including a thin-film transistor. More particularly, it relates to a thin-film transistor that can be driven even by a short channel due to the gradient portion of the active layer, a method of manufacturing a thin-film transistor, and a display device including a thin-film transistor. Background Technology

[0004] Thin-film transistors (TFTs) have been widely used as switching or driving elements in display devices such as liquid crystal displays (LCDs) or organic light-emitting diodes (OLEDs) because they can be fabricated on glass or plastic substrates.

[0005] Based on the material constituting the active layer, thin-film transistors can be classified into: amorphous silicon thin-film transistors using amorphous silicon as the active layer, polycrystalline silicon thin-film transistors using polycrystalline silicon as the active layer, and oxide semiconductor thin-film transistors using oxide semiconductors as the active layer.

[0006] Because amorphous silicon can be deposited to form the active layer in a short time, amorphous silicon thin-film transistors (a-Si TFTs) have the advantages of short manufacturing time and low production cost. On the other hand, the disadvantages of amorphous silicon thin-film transistors are that their use in active-matrix organic light-emitting diodes (AMOLEDs) is limited due to poor current driving capability caused by low mobility and threshold voltage variation.

[0007] Polycrystalline silicon thin-film transistors (poly-Si TFTs) can be fabricated by depositing amorphous silicon and then crystallizing the deposited amorphous silicon. The advantages of polycrystalline silicon TFTs include high electron mobility, excellent stability, thin profiles, high resolution, and high power efficiency. Examples of polycrystalline silicon TFTs include low-temperature polycrystalline silicon (LTPS) TFTs and polycrystalline silicon TFTs. However, the fabrication process for polycrystalline silicon TFTs requires a crystallization step of the amorphous silicon, which increases the manufacturing cost due to the increased number of process steps and the need for high-temperature crystallization. Therefore, it is difficult to apply polycrystalline silicon TFTs to large-size display devices. Due to the polycrystalline nature, it is also difficult to ensure the uniformity of polycrystalline silicon TFTs.

[0008] Oxide-semiconductor thin-film transistors (TFTs), with their high mobility and large resistance variation depending on oxygen content, offer advantages in terms of easily achieving desired characteristics. Furthermore, the manufacturing cost of TFTs is reduced because the oxide constituting the active layer is grown at relatively low temperatures during the fabrication process. Additionally, due to the properties of oxides, which are transparent, transparent displays can be advantageously realized. However, compared to polycrystalline silicon TFTs, TFTs suffer from stability and mobility degradation issues.

[0009] Oxide-semiconductor thin-film transistors (OSTs) can be fabricated as bottom-gate back-channel etch (BCE) structures or etch-stop layer (ES) structures, or as top-gate coplanar structures. In the case of coplanar OSTs, it is important to control the conductive region to ensure the channel length, and the process conditions for forming the conductive region need to be managed. Summary of the Invention

[0010] In view of the above problems, this disclosure was made. One object of this disclosure is to provide a thin-film transistor in which the active layer has a gradient portion between the channel portion and the conductive portion, and the gradient portion has a first region and a second region. As a result, the thin-film transistor has excellent electrical stability and can even be driven by a short channel.

[0011] Another object of this disclosure is to provide a thin-film transistor that efficiently ensures an effective channel length due to the gradient portions comprising a first region and a second region.

[0012] Another object of this disclosure is to provide a thin-film transistor including a conductive portion formed by doping without patterning a gate insulating film.

[0013] Another object of this disclosure is to provide a display device including such a thin-film transistor.

[0014] In addition to the purposes described above, other purposes and features of this disclosure will become apparent to those skilled in the art from the following description.

[0015] According to one aspect of this disclosure, the above and other objectives can be achieved by providing a thin-film transistor comprising: an active layer; a gate electrode spaced apart from and partially overlapping the active layer; and a gate insulating film between the active layer and the gate electrode, wherein the gate insulating film covers an upper surface of the active layer facing the gate electrode, the active layer comprising: a channel portion overlapping the gate electrode; a conductive portion not overlapping the gate electrode; and a gradient portion between the channel portion and the conductive portion, the gradient portion not overlapping the gate electrode, the conductive portion and the gradient portion being doped with a dopant, and in the gradient portion, the concentration of the dopant increasing along a direction from the channel portion toward the conductive portion.

[0016] The gradient portion may include a first region and a second region. The first region may be adjacent to the channel portion, and the second region may be adjacent to the conductive portion. The concentration gradient of the dopant in the first portion of the first region adjacent to the channel portion may be greater than the concentration gradient of the dopant in the second region, and the concentration gradient of the dopant in the second portion of the first region other than the first portion adjacent to the channel portion may be less than the concentration gradient of the dopant in the second region.

[0017] The first region may have a stepped concentration profile. For example, in the first portion of the first region adjacent to the channel portion, the dopant concentration may vary in a step manner.

[0018] The second portion of the first region, excluding the first portion, may not have a dopant concentration gradient.

[0019] The concentration gradient of the dopant in the second region can be uniform.

[0020] The dopant may include a first dopant and a second dopant, and the concentration of the second dopant may be uniform in the conductive portion and the gradient portion.

[0021] In the gradient portion, the first dopant may have a concentration gradient.

[0022] The gradient portion may include a first region and a second region, the first region being adjacent to the channel portion and the second region being adjacent to the conductive portion, and the first region may not include the first dopant.

[0023] The concentration of the second dopant can be uniform in both the first and second regions.

[0024] The resistivity of the gradient portion may be lower than that of the channel portion and higher than that of the conductive portion.

[0025] The dopant may include at least one of B, P, F and H.

[0026] The thin-film transistor may further include a substrate and a buffer layer disposed between the substrate and the active layer, wherein the buffer layer may include the dopant.

[0027] In the region overlapping with the conductive portion, the maximum dopant concentration of the buffer layer may be higher than the dopant concentration of the conductive portion and the dopant concentration of the gate insulating film.

[0028] In the region overlapping with the conductive portion, the dopant concentration of the conductive portion may be higher than the dopant concentration of the gate insulating film and the dopant concentration of the buffer layer.

[0029] The active layer may include an oxide semiconductor material.

[0030] The active layer may include: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0031] The thin-film transistor may further include a source electrode and a drain electrode spaced apart from each other and respectively connected to the active layer.

[0032] The source electrode and the drain electrode may be disposed on the same layer as the gate electrode, and may be made of the same material as the gate electrode.

[0033] According to another aspect of this disclosure, the above and other objectives can be achieved by providing a method for manufacturing a thin-film transistor, the method comprising: forming an active layer; forming a gate insulating film on the active layer; forming a gate electrode on the gate insulating film that partially overlaps with the active layer; and doping the active layer with a dopant, wherein the gate insulating film covers an upper surface of the active layer facing the gate electrode, the formation of the gate electrode comprising: forming a material layer for the gate electrode on the gate insulating film; forming a photoresist pattern on the material layer for the gate electrode; and etching the material layer for the gate electrode using the photoresist pattern as a mask, wherein the area of ​​the photoresist pattern is larger than the area of ​​the gate electrode in a plan view, the gate electrode being disposed in a region defined by the photoresist pattern in a plan view, and the doping of the active layer with a dopant comprising: a first doping using the photoresist pattern as a mask; and a second doping using the gate electrode as a mask after removing the photoresist pattern.

[0034] The photoresist pattern is formed to protrude beyond the area defined by the gate electrode, and the sum of the lengths of the photoresist patterns protruding from the gate electrode on both sides of the gate electrode can range from 1.5 μm to 3.3 μm.

[0035] The dopant may include at least one of B, P, F and H.

[0036] The dopant used for the first doping and the dopant used for the second doping can be the same as each other.

[0037] The dopant used for the first doping and the dopant used for the second doping may be different from each other.

[0038] The doping concentration of the second doping can be lower than that of the first doping.

[0039] The second doping may not make the channel portion conductive.

[0040] According to other aspects of this disclosure, the above and other objectives can be achieved by providing a display device including the aforementioned thin-film transistors. Attached Figure Description

[0041] The above and other objects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0042] Figure 1 This is a cross-sectional view illustrating a thin-film transistor according to one embodiment of the present disclosure;

[0043] Figure 2 This is a schematic diagram illustrating the comparison of dopant concentrations in different regions of the active layer.

[0044] Figure 3 This is a schematic diagram illustrating the first doping step;

[0045] Figure 4 This is a schematic diagram illustrating the second doping process;

[0046] Figure 5 This is a schematic diagram that compares the first dopant concentration, the second dopant concentration, and the total dopant concentration in each region of the active layer.

[0047] Figure 6 This is a schematic diagram illustrating the comparison of resistivity in different regions of the active layer;

[0048] Figure 7A , Figure 7B and Figure 7C This is a schematic diagram illustrating the comparison of dopant concentrations along the thickness direction of a thin-film transistor.

[0049] Figure 8 This is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present disclosure;

[0050] Figure 9 This is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present disclosure;

[0051] Figure 10 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present disclosure;

[0052] Figure 11 This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present disclosure;

[0053] Figure 12A This is a schematic diagram illustrating the conductivity method based on the comparative example. Figure 12B This is a schematic diagram illustrating the conductive penetration depth ΔL;

[0054] Figure 13 The diagram illustrates the threshold voltage value of a thin-film transistor based on the length of the channel portion.

[0055] Figures 14A to 14H This is a process diagram illustrating a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure;

[0056] Figure 15 The illustration is a schematic diagram of a display device according to another embodiment of the present disclosure;

[0057] Figure 16 yes Figure 15 The circuit diagram of any pixel in the diagram;

[0058] Figure 17 The diagram illustrates a circuit diagram of any pixel of a display device according to another embodiment of the present disclosure;

[0059] Figure 18 The diagram illustrates a circuit diagram of any pixel of a display device according to yet another embodiment of the present disclosure;

[0060] Figure 19 The diagram illustrates a circuit diagram of any pixel of a display device according to yet another embodiment of the present disclosure. Detailed Implementation

[0061] The advantages and features of this disclosure and its implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure comprehensive and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0062] The shapes, dimensions, scales, angles, and quantities disclosed in the accompanying drawings for the purpose of describing embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the details illustrated. Similar reference numerals denote similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of this disclosure.

[0063] Where the terms “comprising,” “having,” and “including” are used in this application, additional parts may be added unless “only” is used. Singular terms may include plural forms unless otherwise indicated.

[0064] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0065] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "after," one or more other parts may be arranged between the two parts, unless "immediately following" or "directly" is used.

[0066] Spatially relative terms such as “below,” “under,” “below,” “above,” and “above” may be used throughout this document to facilitate the description of the relationship between the elements shown in the figures and other elements. It will be understood that these terms are intended to cover different device locations other than those depicted in the figures. For example, if the device shown in the figure is inverted, a device described as being arranged “below” or “below” another device may be arranged “above” another device. Thus, the exemplary term “below or below” can include both “below or below” and “above” locations. Similarly, the exemplary terms “above” or “on” can include both “above” and “below or below” locations.

[0067] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “immediately after” or “directly” is used.

[0068] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0069] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, "at least one of the first, second and third items" could mean any combination of two or more items selected from the first, second and third items, as well as the first, second or third item.

[0070] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. Embodiments of this disclosure can be implemented independently of each other or together in an interdependent relationship.

[0071] In the accompanying drawings, the same or similar elements are indicated by the same reference numerals, even though they are depicted in different drawings.

[0072] In embodiments of this disclosure, for ease of description, the source electrode and drain electrode are distinguished from each other. However, the source electrode and drain electrode can be used interchangeably. A source electrode can be a drain electrode, and a drain electrode can be a source electrode. Furthermore, a source electrode in any embodiment of this disclosure can be a drain electrode in other embodiments of this disclosure, and a drain electrode in any embodiment of this disclosure can be a source electrode in other embodiments of this disclosure.

[0073] In some embodiments of this disclosure, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode. However, embodiments of this disclosure are not limited to this structure. For example, the source region may be the source electrode, and the drain region may be the drain electrode. Furthermore, the source region may be the drain electrode, and the drain region may be the source electrode.

[0074] Figure 1 This is a cross-sectional view illustrating a thin-film transistor 100 according to one embodiment of the present disclosure.

[0075] A thin-film transistor 100 according to one embodiment of the present disclosure includes an active layer 130, a gate electrode 140 spaced apart from and partially overlapping the active layer 130, and a gate insulating film 150 between the active layer 130 and the gate electrode 140. The gate insulating film 150 covers the upper surface of the active layer 130 facing the gate electrode 140. The gate insulating film 150 may cover the entire upper surface of the active layer 130.

[0076] The active layer 130 includes a channel portion 131 overlapping with the gate electrode 140, conductive portions 133a and 133b not overlapping with the gate electrode 140, and gradient portions 132a and 132b between the channel portion 131 and the conductive portions 133a and 133b. The gradient portions 132a and 132b do not overlap with the gate electrode 140, and the conductive portions 133a and 133b, as well as the gradient portions 132a and 132b, are doped with dopants.

[0077] According to one embodiment of the present disclosure, the dopant concentration in gradient portions 132a and 132b increases along the direction from channel portion 131 toward conductive portions 133a and 133b.

[0078] Reference Figure 1 The gradient portions 132a and 132b include a first gradient portion 132a and a second gradient portion 132b.

[0079] In the following text, reference will be made to Figure 1 and Figure 2 A thin-film transistor 100 according to one embodiment of the present disclosure will be described in more detail.

[0080] Reference Figure 1 and Figure 2 An active layer 130 is disposed on a substrate 110.

[0081] Glass or plastic can be used as the substrate 110. A transparent plastic with flexible properties, such as polyimide, can be used. When polyimide is used as the substrate 110, a heat-resistant polyimide with high temperature resistance can be used, taking into account the high-temperature deposition process performed on the substrate 110.

[0082] A buffer layer 120 may be provided on the substrate 110. The buffer layer 120 may include at least one of silicon oxide or silicon nitride. The buffer layer 120 may protect the active layer 130, and the planarization properties of the buffer layer 120 may be used to planarize the upper part of the substrate 110. The buffer layer 120 may be omitted.

[0083] According to one embodiment of this disclosure, the active layer 130 includes an oxide semiconductor material. The active layer 130 may be an oxide semiconductor layer.

[0084] The active layer 130 may include at least one of the following: IZO (InZnO)-based oxide semiconductor material, IGO (InGaO)-based oxide semiconductor material, ITO (InSnO)-based oxide semiconductor material, IGZO (InGaZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, ITZO (InSnZnO)-based oxide semiconductor material, IGTO (InGaSnO)-based oxide semiconductor material, GO (GaO)-based oxide semiconductor material, GZTO (GaZnSnO)-based oxide semiconductor material, and GZO (GaZnO)-based oxide semiconductor material. However, embodiments of this disclosure are not limited to this example, and the active layer 130 may be made of other oxide semiconductor materials known in the art.

[0085] The active layer 130 includes a channel portion 131, conductive portions 133a and 133b, and gradient portions 132a and 132b disposed between the channel portion 131 and the conductive portions 133a and 133b.

[0086] A gate insulating film 150 is disposed on the active layer 130. The gate insulating film 150 has insulating properties and may include at least one of silicon oxide, silicon nitride, and metal-based oxides. The gate insulating film 150 may have a single-layer film structure or a multilayer film structure.

[0087] The gate insulating film 150 can cover the entire upper surface of the active layer 130. Figure 1 In this context, the surface of the active layer 130 disposed toward the gate electrode 140 will be referred to as the upper surface. According to one embodiment of this disclosure, such as... Figure 1 and Figure 2 As shown, the gate insulating film 150 may not be patterned, but rather formed to cover the entire surface of the substrate 110, including the active layer 130.

[0088] However, the implementation of this disclosure is not limited to... Figure 1 and Figure 2 Contact holes can be formed in the gate insulating film 150. When contact holes are formed in the gate insulating film 150, the active layer 130 can be partially exposed from the gate insulating film 150 through the contact holes. According to one embodiment of the present disclosure, the gate insulating film 150 can cover the entire upper surface of the active layer 130 except for the area corresponding to the contact holes.

[0089] Furthermore, according to one embodiment of this disclosure, the gate insulating film 150 may cover the entire upper surface of the active layer 130 except for the area where the active layer 130 contacts the conductor. In this case, the conductor refers to an element made of conductive material that contacts or connects to the active layer 130, including wires, electrodes, pads, terminals, etc. As a conductor, for example, it may be the source electrode and drain electrode connected to the active layer 130.

[0090] According to one embodiment of the present disclosure, the gate insulating film 150 is configured to cover the upper surface of the channel portion 131 of the active layer 130 and the upper surfaces of the gradient portions 132a and 132b.

[0091] According to one embodiment of this disclosure, the active layer 130 can be selectively conductive by doping based on a dopant. The dopant can be doped into the active layer 130 through the gate insulating film 150. Therefore, doping can be performed on the active layer 130 even though the active layer 130 is not exposed from the gate insulating film 150. Therefore, according to one embodiment of this disclosure, the gate insulating film 150 may not be patterned.

[0092] A gate electrode 140 is disposed on a gate insulating film 150. The gate electrode 140 may include at least one of Al, an Al-based metal such as an Al alloy, Ag, an Ag-based metal such as an Ag alloy, Cu, a Cu-based metal such as a Cu alloy, Mo, a Mo-based metal such as a Mo alloy, Cr, Ta, Nd, and Ti. The gate electrode 140 may have a multilayer film structure, comprising at least two conductive films each having different physical properties from the others.

[0093] The gate electrode 140 overlaps with the channel portion 131 of the active layer 130. The portion of the active layer 130 that overlaps with the gate electrode 140 may be the channel portion 131. According to one embodiment of this disclosure, the portion of the active layer 130 that overlaps with the gate electrode 140 will be referred to as the channel portion 131.

[0094] The conductive portions 133a and 133b do not overlap with the gate electrode 140. (Refer to...) Figure 1 and Figure 2 The conductive portions 133a and 133b may include a first conductive portion 133a and a second conductive portion 133b spaced apart from each other. The first conductive portion 133a, as either conductive portion 133a or 133b, may be a source region, and the second conductive portion 133b, as the other conductive portion 133a or 133b, may be a drain region. Depending on the application, the source region 133a may be used as a source electrode, and the drain region 133b may be used as a drain electrode. The conductive portions 133a and 133b may be used as wiring.

[0095] According to one embodiment of this disclosure, conductive portions 133a and 133b can be formed by selectively making the active layer 130 conductive. For example, conductive portions 133a and 133b can be formed by doping based on a dopant. According to one embodiment of this disclosure, conductive portions 133a and 133b are doped with a dopant.

[0096] The dopant may include at least one of B, P, F, and H. For doping, at least one of B ions, P ions, and F ions may be used. H ions may also be used for doping.

[0097] The conductive portions 133a and 133b may have a higher dopant concentration than the channel portion 131 and a lower specific resistance than the channel portion 131. The conductive portions 133a and 133b may have higher conductivity than the channel portion 131 and the gradient portions 132a and 132b, or may have conductivity similar to that of a conductor.

[0098] According to one embodiment of this disclosure, gradient portions 132a and 132b are disposed between channel portion 131 and conductive portions 133a and 133b, and do not overlap with gate electrode 140. Gradient portions 132a and 132b have a dopant concentration that increases along a direction from channel portion 131 toward conductive portions 133a and 133b.

[0099] Figure 2 The diagram exemplarily illustrates the dopant concentration in each region of the active layer along the direction from the channel portion 131 toward the conductive portions 133a and 133b. More specifically, Figure 2 The dopant concentration is shown along a line in the horizontal direction connecting the first conductive portion 133a, the channel portion 131, and the second conductive portion 133b to each other in sequence. For convenience, Figure 2 The dopant concentration shown can be referred to as the "concentration in the planar direction." Furthermore, as... Figure 2 The curve shown represents the concentration distribution along the horizontal position, which can be called the "concentration profile".

[0100] According to one embodiment of this disclosure, gradient portions 132a and 132b include first regions 132a1 and 132b1 and second regions 132a2 and 132b2. The first regions 132a1 and 132b1 may be adjacent to the channel portion 131, and the second regions 132a2 and 132b2 may be adjacent to the conductive portions 133a and 133b. Specifically, the first gradient portion 132a includes the first region 132a1 and the second region 132a2, and the second gradient portion 132b includes the first region 132b1 and the second region 132b2.

[0101] Reference Figure 2 In the first portions Sa1 and Sb1 of the first regions 132a1 and 132b1 adjacent to the channel portion 131, the dopant concentration changes drastically. The rate of change of dopant concentration in the first portions Sa1 and Sb1 of the first regions 132a1 and 132b1 adjacent to the channel portion 131 is greater than the rate of change of dopant concentration in the second regions 132a2 and 132b2. According to one embodiment of the present disclosure, the dopant concentration gradient in the first portions Sa1 and Sb1 of the first regions 132a1 and 132b1 adjacent to the channel portion 131 is greater than the dopant concentration gradient in the second regions 132a2 and 132b2. According to one embodiment of the present disclosure, the rate of change of dopant concentration can be described by the dopant concentration gradient. The dopant concentration gradient can be defined as the ratio of concentration change to distance change (Δconcentration / Δdistance) based on the direction from the channel portion 131 toward the conductive portions 133a and 133b.

[0102] In the first regions 132a1 and 132b1, excluding the first portions Sa1 and Sb1 adjacent to the channel portion 131, the dopant concentration remains almost constant. According to one embodiment of this disclosure, the portions in the first regions 132a1 and 132b1 other than the first portions Sa1 and Sb1 may be referred to as "second portions Sa2 and Sb2". The rate of change of dopant concentration in the second portions Sa2 and Sb2 of the first regions 132a1 and 132b1, excluding the first portions Sa1 and Sb1 adjacent to the channel portion 131, is less than the rate of change of dopant concentration in the second regions 132a2 and 132b2. According to one embodiment of this disclosure, the dopant concentration gradient in the second portions Sa2 and Sb2 of the first regions 132a1 and 132b1, excluding the first portions Sa1 and Sb1, is less than the dopant concentration gradient in the second regions 132a2 and 132b2.

[0103] Reference Figure 2 In the first portions Sa1 and Sb1 of the first regions 132a1 and 132b1 adjacent to the channel portion 131, the dopant concentration changes in a step manner. More specifically, the first regions 132a1 and 132b1 may have a stepped concentration profile. (Refer to...) Figure 2 Due to the almost vertically varying dopant concentration in the first portions Sa1 and Sb1 adjacent to the channel portion 131 and the almost constant dopant concentration in the second portions Sa2 and Sb2 not adjacent to the channel portion 131, the first regions 132a1 and 132b1 may have a stepped concentration profile.

[0104] According to one embodiment of this disclosure, such as Figure 2As shown, the first regions 132a1 and 132b1 include regions in the second portions Sa2 and Sb2 that do not have a dopant concentration gradient. Specifically, there is no dopant concentration variation in the second portions Sa2 and Sb2 of the first regions 132a1 and 132b1, excluding the first portions Sa1 and Sb1. Therefore, the second portions Sa2 and Sb2 of the first regions 132a1 and 132b1, excluding the first portions Sa1 and Sb1, may not have a dopant concentration gradient.

[0105] Reference Figure 2 It is noted that in the second regions 132a2 and 132b2, the dopant concentration increases uniformly along the direction from the channel portion 131 toward the conductive portions 133a and 133b. Therefore, according to one embodiment of the present disclosure, the dopant concentration gradient in the second regions 132a2 and 132b2 can be uniform.

[0106] According to one embodiment of this disclosure, the active layer 130 may be doped two or more times during the manufacturing process of the thin-film transistor 100.

[0107] Figure 3 This is a schematic diagram illustrating the first doping process. (Refer to...) Figure 3 The active layer 130 is first doped by using a photoresist pattern 40 for forming the gate electrode 140 as a mask.

[0108] A dopant is used for the first doping. The dopant may include at least one of B, P, F, and H. For example, at least one of B, P, and F may be used as the dopant, or H may also be used. The dopant may be doped in an ionic state. According to one embodiment of this disclosure, the first doping can be performed by ion implantation.

[0109] During the doping process, the photoresist pattern 40 retained on the gate electrode 140 can be used as a mask to protect the channel portion 131.

[0110] Reference Figure 3 Based on the cross-sectional view, the photoresist pattern 40 may have a length longer than the gate electrode 140. Based on the planar view, the photoresist pattern 40 may have an area larger than the gate electrode 140. For example, in the planar view, the gate electrode 140 may be disposed within the area defined by the photoresist pattern 40.

[0111] According to one embodiment of this disclosure, a material layer for a gate electrode can be formed on the gate insulating film 150, and the material layer for the gate electrode can be etched using a photoresist pattern 40 as a mask to form a gate electrode 140. In this case, the material layer for the gate electrode can be etched within the edge of the photoresist pattern 40, thereby forming a gate electrode 140 with an area smaller than that of the photoresist pattern 40.

[0112] like Figure 3 As shown, doping is performed using a photoresist pattern 40 as a mask, doping is performed on regions of the active layer 130 that do not overlap with the photoresist pattern 40. As a result, conductive portions 133a and 133b are formed.

[0113] The channel portion 131, protected by the photoresist pattern 40, is not doped with dopants. As a result, the channel portion 131 retains its semiconductor properties.

[0114] Reference Figure 3 The gradient portions 132a and 132b are protected by a photoresist pattern 40. This prevents dopants from being directly implanted into the gradient portions 132a and 132b. However, dopants doped in the conductive portions 133a and 133b can diffuse into the gradient portions 132a and 132b. Therefore, the effect of partially doping the gradient portions 132a and 132b can be achieved.

[0115] As a result, Figure 3 As shown in the lower part, the concentration profile of the dopant can be formed by the first doping. Hereinafter, the dopant used for the first doping will be referred to as the "first dopant".

[0116] According to one embodiment of this disclosure, each of the first gradient portion 132a and the second gradient portion 132b may have a length corresponding to the length of the photoresist pattern 40 protruding from the gate electrode 140.

[0117] Next, a second doping process is performed on the active layer 130.

[0118] Figure 4 This is a schematic diagram illustrating the second doping step. (For example...) Figure 4 As shown, a second doping is performed after the photoresist pattern 40 is removed. In the second doping, the gate electrode 140 is used as a mask.

[0119] The ion concentration for the second doping is lower than that for the first doping. Furthermore, the acceleration energy for the second doping ions can be set lower than that for the first doping ions.

[0120] A dopant is used for the second doping. The dopant may include at least one of B, P, F, and H. For example, at least one of B, P, and F may be used as the dopant, or H may also be used. The dopant may be doped in an ionic state. According to one embodiment of this disclosure, the second doping can be performed by ion implantation.

[0121] In the second doping step, the dopant can be directly doped into the gradient regions 132a and 132b and the conductive regions 133a and 133b. Therefore, the dopant is also doped into the gradient regions 132a and 132b (see...). Figure 14G However, due to the lower ion concentration of the second doping, the dopant applied to the second doping does not diffuse into the channel portion 131, or diffuses almost not into the channel portion 131. The concentration of the dopant used in the second doping can be applied equally to the entire doped region except for the channel portion 131. According to one embodiment of this disclosure, the second doping does not make the channel portion 131 conductive.

[0122] As a result, Figure 4 As shown in the lower portion, a concentration profile of the dopant based on the second doping can be formed. Hereinafter, the dopant used for the second doping will be referred to as the "second dopant".

[0123] Figure 5 This is a schematic diagram that compares the first dopant concentration, the second dopant concentration, and the total dopant concentration in each region of the active layer.

[0124] According to one embodiment of the present disclosure, the dopant may include a first dopant and a second dopant, and the concentration of the second dopant in the conductive portions 133a and 133b and the gradient portions 132a and 132b may be kept uniform.

[0125] On the other hand, the first dopant in gradient portions 132a and 132b may have a concentration gradient. (Refer to...) Figure 3 and Figure 5 The gradient portions 132a and 132b include first regions 132a1 and 132b1 and second regions 132a2 and 132b2. The first regions 132a1 and 132b1 are adjacent to the channel portion 131, and the second regions 132a2 and 132b2 are adjacent to the conductive portions 133a and 133b. The first regions 132a1 and 132b1 may not include the first dopant. The first dopant may have a concentration gradient in the second regions 132a2 and 132b2 of the gradient portions 132a and 132b. According to one embodiment of this disclosure, the regions of the gradient portions 132a and 132b that do not include the first dopant may be defined as the first regions 132a1 and 132b1.

[0126] Furthermore, the concentration of the second dopant can be uniform in the first regions 132a1 and 132b1 and the second regions 132a2 and 132b2.

[0127] Figure 6 This is a schematic diagram illustrating the comparison of the specific resistance in different regions of the active layer 130.

[0128] According to one embodiment of this disclosure, the specific resistance of gradient portions 132a and 132b is lower than that of channel portion 131 and higher than that of conductive portions 133a and 133b.

[0129] Reference Figure 6 In the first regions 132a1 and 132b1, the resistivity changes drastically in the first portions Sa1 and Sb1 adjacent to the channel portion 131. The rate of change of resistivity in the first portions Sa1 and Sb1 of the first regions 132a1 and 132b1 adjacent to the channel portion 131 is greater than the rate of change of resistivity in the second regions 132a2 and 132b2. On the other hand, the rate of change of resistivity in the second portions Sa2 and Sb2 of the first regions 132a1 and 132b1 other than the first portions Sa1 and Sb1 is less than the rate of change of resistivity in the second regions 132a2 and 132b2.

[0130] Reference Figure 6 In the first portions Sa1 and Sb1 of the first regions 132a1 and 132b1 adjacent to the channel portion 131, the resistivity changes in a step manner.

[0131] According to one embodiment of this disclosure, such as Figure 6 As shown, the first regions 132a1 and 132b1 include regions without resistance variation, namely the second portions Sa2 and Sb2. For example, there is no resistance variation in the second portions Sa2 and Sb2 of the first regions 132a1 and 132b1 other than the first portions Sa1 and Sb1.

[0132] Reference Figure 6 It is noted that in the second regions 132a2 and 132b2, the resistivity decreases uniformly along the direction from the channel portion 131 toward the conductive portions 133a and 133b.

[0133] According to one embodiment of this disclosure, since the concentration of ions in the second doping is low, the dopant will not diffuse into the channel portion 131. In this case, the second regions 132a2 and 132b2 can be used to control or buffer the diffusion of the dopant. Therefore, the process margin of the channel portion 131 that should be set due to the diffusion of the dopant can be minimized, and a stable effective channel length can be obtained. Therefore, according to one embodiment of this disclosure, even if the channel length is designed to be short, the thin-film transistor 100 can be driven stably.

[0134] On the other hand, when the gradient portions 132a and 132b are short and only the first doping is performed, the first regions 132a1 and 132b1 are not formed. Therefore, the edge of the channel portion 131 overlapping with the gate electrode 140 is partially conductive during the conductivity process, thereby reducing the effective channel length. Therefore, a longer length L1 of the channel portion 131 must be designed to ensure a stable effective channel length, making it difficult to achieve a short channel. Furthermore, even if the channel portion 131 is directly connected to the conductivity portions 133a and 133b without having gradient portions 132a and 132b, the edge of the channel portion 131 overlapping with the gate electrode 140 is partially conductive during the conductivity process of the conductivity portions 133a and 133b, thereby reducing the effective channel length. Therefore, a longer length L1 of the channel portion 131 must be designed to ensure a stable effective channel length, making it difficult to achieve a short channel.

[0135] According to one embodiment of this disclosure, the length L2 of the gradient portions 132a and 132b is designed to prevent the edges of the channel portion 131 from becoming conductive without hindering the driving of the thin-film transistor 100.

[0136] According to one embodiment of this disclosure, the length of the first gradient portion 132a and the length of the second gradient portion 132b may be equal to or different from each other. In one embodiment of this disclosure, for convenience, the lengths of the first gradient portion 132a and the second gradient portion 132b are not distinguished from each other and are labeled as L2.

[0137] According to one embodiment of this disclosure, the sum of the lengths of the gradient portions 132a and 132b formed on both sides of the channel portion 131 can be 1.5 μm or greater. When the sum of the lengths of the gradient portions 132a and 132b formed on both sides of the channel portion 131 is less than 1.5 μm, the edge of the channel portion 131 is partially conductive. In this case, "both sides" refers to... Figure 6The term refers to the left and right sides of the channel portion 131. For example, with the channel portion 131 as a reference, the directions of the source region 133a and the drain region 133b can be referred to as the two sides of the channel portion 131. According to one embodiment of this disclosure, the length L2 of either gradient portion 132a or 132b can be 0.7 μm or greater.

[0138] According to one embodiment of this disclosure, the length L2 of each gradient portion 132a and 132b can be designed to be 2.5 μm or less. When the length L2 of each gradient portion 132a and 132b exceeds 2.5 μm, the ON current characteristics of the thin-film transistor 100 deteriorate, which is detrimental to the miniaturization of the thin-film transistor 100. According to one embodiment of this disclosure, the sum of the lengths L2 of the gradient portions 132a and 132b can be designed to be 3.3 μm or less. When the sum of the lengths L2 of the gradient portions 132a and 132b exceeds 3.3 μm, the ON current characteristics of the thin-film transistor 100 deteriorate, which is detrimental to the miniaturization of the thin-film transistor 100.

[0139] According to one embodiment of this disclosure, since gradient portions 132a and 132b, particularly first regions 132a1 and 132b1, are provided between the channel portion 131 and the conductive portions 133a and 133b, the entire channel portion 131 overlapping with the gate electrode 140 can be used as an effective channel. Therefore, even if the length L1 of the channel portion 131 is designed to be short, the thin-film transistor 100 can be effectively driven and can be miniaturized.

[0140] Furthermore, gradient portions 132a and 132b can be used as electrical buffers between conductive portions 133a and 133b and channel portion 131. Specifically, since first regions 132a1 and 132b1 with relatively high specific resistance are provided between channel portion 131 and conductive portions 133a and 133b, leakage current can be prevented from flowing between channel portion 131 and conductive portions 133a and 133b when the thin-film transistor 100 is in the OFF state.

[0141] According to one embodiment of the present disclosure, the length of the channel portion 131 may be 1 μm or greater. Furthermore, according to one embodiment of the present disclosure, the length of the channel portion 131 may be 2 μm or greater. According to one embodiment of the present disclosure, since gradient portions 132a and 132b are provided between the channel portion 131 and the conductive portions 133a and 133b, the thin-film transistor 100 can be used to effectively perform switching functions even when the length of the channel portion 131 is approximately 2 μm. In particular, due to the first regions 132a1 and 132b1 of the gradient portions 132a and 132b, the thin-film transistor 100 can be used to effectively perform switching functions even when the length L1 of the channel portion 131 is approximately 1 μm. For example, the channel portion 131 may have a length of 1 μm to 10 μm, a length of 2 μm to 10 μm, a length of 1 μm to 6 μm, a length of 2 μm to 6 μm, a length of 1 μm to 4 μm, a length of 2 μm to 4 μm, a length of 3 μm to 10 μm, a length of 3 μm to 8 μm, or a length of 3 μm to 6 μm.

[0142] According to one embodiment of the present disclosure, a buffer layer 120 may be provided between the substrate 110 and the active layer 130, and a dopant may even be doped into the buffer layer 120.

[0143] The accelerating voltage applied to the dopant during the doping process can be controlled, thereby controlling the dopant concentration of the conductive portions 133a and 133b, the dopant concentration of the gate insulating film 150, and the dopant concentration of the buffer layer 120.

[0144] To adequately dope the dopant in the conductive portions 133a and 133b, the accelerating voltage applied to the dopant can be increased. In this case, the dopant can pass through the conductive portions 133a and 133b and be doped into the buffer layer 120. As the concentration of the dopant in the buffer layer 120 increases, the dopant concentration in the buffer layer 120 can be higher than the dopant concentration in the conductive portions 133a and 133b.

[0145] However, when the accelerating voltage used for doping increases beyond the required voltage, the active layer 130 can be damaged. Therefore, according to one embodiment of this disclosure, the accelerating voltage is controlled such that the conductive portions 133a and 133b have the maximum dopant concentration or the upper portion of the buffer layer 120 has the maximum dopant concentration.

[0146] According to one embodiment of this disclosure, in the region overlapping with the conductive portions 133a and 133b, the maximum dopant concentration of the buffer layer 120 may be higher than the maximum dopant concentration of the conductive portions 133a and 133b and the maximum dopant concentration of the gate insulating film 150.

[0147] According to one embodiment of this disclosure, in the region overlapping with conductive portions 133a and 133b, the dopant concentration of conductive portions 133a and 133b may be higher than the dopant concentration of the gate insulating film 150 and the dopant concentration of the buffer layer 120.

[0148] According to one embodiment of this disclosure, when the conductive portions 133a and 133b have the maximum dopant concentration or the buffer layer 120 has the maximum dopant concentration, it is considered that effective doping has been performed on the conductive portions 133a and 133b. Furthermore, the thin-film transistor 100 can operate effectively when the conductive portions 133a and 133b have the maximum dopant concentration or the buffer layer 120 has the maximum dopant concentration.

[0149] Figure 7A , Figure 7B and Figure 7C This is a schematic diagram illustrating the comparison of dopant concentrations along the thickness direction of a thin-film transistor.

[0150] Figure 7A The diagram illustrates the depth-based dopant concentration variation in the region overlapping the first conductive portion 133a. Figure 7A In this context, the vertical distance from the upper surface of the gate insulating film 150 to the substrate 110 represents the depth. More specifically, in... Figure 7A In this context, the depth of the upper surface of the gate insulating film 150 is defined as "0", and the depth increases toward the substrate 110.

[0151] Depth-based elemental concentrations can be confirmed using the D-SIMS Ion Profile.

[0152] Reference Figure 7A In the region overlapping with the first conductive portion 133a, the dopant concentration of the first conductive portion 133a is higher than the dopant concentration of the gate insulating film 150. Furthermore, in the region overlapping with the first conductive portion 133a, the dopant concentration of the buffer layer 120 may be higher than both the dopant concentration of the first conductive portion 133a and the dopant concentration of the gate insulating film 150. In the region overlapping with the first conductive portion 133a, the upper portion of the buffer layer 120 may have the highest dopant concentration.

[0153] Figure 7B The diagram illustrates the depth-based dopant concentration variation in the region overlapping with the second region 132a2 of the first gradient portion 132a. The upper portion of the buffer layer 120 may have the highest dopant concentration in the region overlapping with the second region 132a2 of the first gradient portion 132a.

[0154] Figure 7CThe diagram illustrates the depth-based dopant concentration variation in the region overlapping with the first region 132a1 of the first gradient portion 132a. The upper portion of the buffer layer 120 may have the highest dopant concentration in the region overlapping with the first region 132a1 of the first gradient portion 132a.

[0155] Figure 8 This is a cross-sectional view illustrating a thin-film transistor 200 according to another embodiment of the present disclosure.

[0156] and Figure 1 Compared to the thin-film transistor 100 shown, Figure 8 The thin-film transistor 200 shown further includes an interlayer dielectric film 155, a source electrode 161, and a drain electrode 162. The interlayer dielectric film 155 may be disposed on the gate electrode 140 and the gate insulating film 150 and may be made of an insulating material.

[0157] Source electrode 161 and drain electrode 162 are disposed on interlayer dielectric film 155. Source electrode 161 and drain electrode 162 are spaced apart from each other and connected to active layer 130.

[0158] Reference Figure 8 The source electrode 161 is connected to the first conductive portion 133a through contact hole H1, and the drain electrode 162 is connected to the second conductive portion 133b through contact hole H2. The first conductive portion 133a connected to the source electrode 161 can be referred to as the source connection portion, and the second conductive portion 133b connected to the drain electrode 162 can be referred to as the drain connection portion.

[0159] Reference Figure 8 Contact holes H1 and H2 pass through the interlayer dielectric film 155 and the gate insulating film 150. A portion of the active layer 130 can be exposed from the gate insulating film 150 through contact holes H1 and H2. Specifically, a portion of the first conductive portion 133a and a portion of the second conductive portion 133b can be exposed from the gate insulating film 150 through contact holes H1 and H2.

[0160] Figure 9 This is a cross-sectional view illustrating a thin-film transistor 300 according to another embodiment of the present disclosure.

[0161] Reference Figure 9 According to another embodiment of the present disclosure, the thin-film transistor 300 includes a light-shielding layer 121 disposed on a substrate 110. The light-shielding layer 121 may be disposed to overlap with the active layer 130 to block light incident on the active layer 130 via the substrate 110, thereby protecting the active layer 130. In particular, the light-shielding layer 121 is disposed to overlap with the channel portion 131 of the active layer 130.

[0162] Figure 10 This is a cross-sectional view illustrating a thin-film transistor 400 according to yet another embodiment of the present disclosure.

[0163] Reference Figure 10 The active layer 130 has a multi-layer structure. According to... Figure 10 The active layer 130 of the thin-film transistor 400 includes a first oxide semiconductor layer 130a and a second oxide semiconductor layer 130b on the first oxide semiconductor layer 130a. Each of the first oxide semiconductor layer 130a and the second oxide semiconductor layer 130b includes an oxide semiconductor material. The first oxide semiconductor layer 130a and the second oxide semiconductor layer 130b may include the same oxide semiconductor material, or they may include different oxide semiconductor materials from each other.

[0164] A first oxide semiconductor layer 130a is disposed on the substrate 110 and supports a second oxide semiconductor layer 130b. Therefore, the first oxide semiconductor layer 130a can be referred to as a "support layer". A main channel is formed in the second oxide semiconductor layer 130b. Therefore, the second oxide semiconductor layer 130b can be referred to as a "channel layer". However, embodiments of the present disclosure are not limited to this case, and the channel may be formed in the first oxide semiconductor layer 130a.

[0165] like Figure 10 As shown, the structure of the active layer 130, which includes a first oxide semiconductor layer 130a and a second oxide semiconductor layer 130b, can be referred to as a two-layer structure.

[0166] The first oxide semiconductor layer 130a, used as a support layer, can exhibit excellent film stability and mechanical properties. For film stability, the first oxide semiconductor layer 130a may include Ga. Ga forms a stable bond with oxygen, and Ga oxide exhibits excellent film stability.

[0167] The first oxide semiconductor layer 130a may include, for example, at least one of the following: IGZO (InGaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, IGTO (InGaSnO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, and GO (GaO) based oxide semiconductor material.

[0168] The second oxide semiconductor layer 130b, used as the channel layer, may be made of at least one of the following: IZO (InZnO)-based oxide semiconductor material, IGO (InGaO)-based oxide semiconductor material, ITO (InSnO)-based oxide semiconductor material, IGZO (InGaZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, GZTO (GaZnSnO)-based oxide semiconductor material, and ITZO (InSnZnO)-based oxide semiconductor material. However, embodiments of this disclosure are not limited to this example, and the second oxide semiconductor layer 130b may be made of other oxide semiconductor materials known in the art.

[0169] Figure 11 This is a cross-sectional view illustrating a thin-film transistor 500 according to yet another embodiment of the present disclosure.

[0170] Figure 11 The thin-film transistor 500 shown includes an active layer 130, a gate electrode 140 spaced apart from the active layer 130 and partially overlapping the active layer 130, a gate insulating film 150 between the active layer 130 and the gate electrode 140, a source electrode 161 on the gate insulating film 150, and a drain electrode 162 spaced apart from the source electrode 161 and disposed on the gate insulating film 150.

[0171] Reference Figure 11 The gate insulating film 150 is formed to cover the upper surface of the active layer 130. The source electrode 161 and the drain electrode 162 may be disposed in the same layer as the gate electrode 140 and may be made of the same material as the gate electrode 140. Each of the source electrode 161 and the drain electrode 162 is connected to the active layer 130 through a contact hole formed in the gate insulating film 150.

[0172] Figure 12A This is a schematic diagram illustrating the conductivity method based on the comparative example.

[0173] Reference Figure 12A With the photoresist pattern 45 remaining on the gate electrode 140, conductivity is performed using the photoresist pattern 45 as a mask. (Refer to...) Figure 12A The photoresist pattern 45 protrudes partially outside the gate electrode 140.

[0174] According to the comparative example, the active layer 130 is doped using a single doping step. (Refer to...) Figure 12A After the gate electrode 140 is formed, conductivity is performed by first doping using a photoresist pattern 45 as a mask.

[0175] In addition, in order to effectively drive the thin-film transistor in the ON state, the conductive portions 133a and 133b should be in contact with the channel portion 131. To ensure stable contact between the conductive portions 133a and 133b and the channel portion 131, the photoresist pattern 45 protruding outside the gate electrode 140 has a limited length.

[0176] When the length of the photoresist pattern 45 protruding outside the gate electrode 140 is relatively long, a non-conductive portion is generated between the channel portion 131 and the conductive portions 133a and 133b. In this case, current will not flow through the thin-film transistor when it is in the ON state. To avoid this problem, for example, approximately 1 μm of photoresist pattern 45 protrudes outside the gate electrode 140 on both sides.

[0177] Since the length of the photoresist pattern 45 is designed for stable contact between the conductive portions 133a and 133b and the channel portion 131, the edge of the channel portion 131 can be partially conductive during the conductivity process.

[0178] The distance at which the channel portion 131 is conductive during the conductive process will be referred to as the conductive penetration depth ΔL.

[0179] Figure 12B This is a schematic diagram illustrating the conductive penetration depth ΔL.

[0180] Reference Figure 12B The length of the channel portion 131 of the active layer 130 overlapping with the gate electrode 140 is marked as "L". ideal ". Figure 12B The "L" ideal "This can be considered as the ideal length of the channel section 131."

[0181] In the selective conductivity process of the active layer 130, the channel portion 131 is partially conductive, and the conductive area cannot be used as a channel. The length of the conductive portion of the channel portion 131 is called the conductivity penetration depth ΔL. Furthermore, the length of the unconductive area in the channel portion 131 that can be effectively used as a channel is called the effective channel length L. eff As the conductivity penetration depth ΔL increases, the effective channel length L... eff Decrease.

[0182] In order for a thin-film transistor to perform a switching function, the effective channel length L eff It should be maintained above the predetermined value. Therefore, when considering the conductive penetration depth ΔL, the channel portion 131 should be designed to have a relatively long length to ensure the predetermined effective channel length L. eff In this case, the size of the thin-film transistor increases, making it difficult to miniaturize and integrate the device.

[0183] According to one embodiment of this disclosure, gradient portions 132a and 132b are disposed between channel portion 131 and conductive portions 133a and 133b, thereby serving as a buffer between channel portion 131 and conductive portions 133a and 133b, whereby the majority of channel portion 131 can be effectively used as a channel. In this way, according to one embodiment of this disclosure, an effective channel length L is effectively obtained. eff Therefore, the length of the channel portion 131 is easily determined and designed. Furthermore, according to one embodiment of this disclosure, even if the length of the channel portion 131, as specified by the length of the gate electrode 140, is designed to be relatively short, the effective channel length L required for driving the thin-film transistor can be obtained. eff .

[0184] Figure 13 The diagram illustrates the threshold voltage value of the thin-film transistor based on the length of the channel portion 131.

[0185] In detail, Figure 13 The comparative example 1 illustrates the process by which... Figure 12A The thin-film transistor shown is fabricated using photoresist pattern 45 doping, with a specific threshold voltage based on the length of the channel portion 131. Specifically, in the thin-film transistor fabricated in Comparative Example 1, the photoresist pattern 45 protruding beyond the gate electrode 140 has a total length of 1 μm, i.e., the sum of the lengths protruding from the left and right sides of the gate electrode 140, and the channel portion 131 has a length ranging from 3 μm to 20 μm (3 μm, 4 μm, 6 μm, 10 μm, 12 μm, 20 μm). The threshold voltage of the thin-film transistor is then measured. For conductivity, B is doped, and only the first doping based on B is performed. The accelerating voltage used for B doping is 40 kV, and the doping concentration is 1 × 10⁻⁶. 15 atom / cm 3 .

[0186] Figure 13 Example 1 illustrates the process by, as shown in Figure 3 The first doping and using photoresist pattern 40 shown Figure 4The threshold voltage of the thin-film transistor fabricated by the second doping shown is based on the length of the channel portion 131. Specifically, in the thin-film transistor fabricated in Example 1, the photoresist pattern 40 protruding beyond the gate electrode 140 has a total length of 2.0 μm, which is the sum of the lengths protruding from the left and right sides of the gate electrode 140, and the channel portion 131 has a length ranging from 2.5 μm to 20 μm (2.5 μm, 3 μm, 4 μm, 8 μm, 10 μm, 12 μm, 19 μm). The threshold voltage of the thin-film transistor is then measured. For conductivity, B is doped twice. The accelerating voltage for the first B doping is 40 kV, and the doping concentration is 1 × 10⁻⁶. 15 atom / cm 3 The accelerating voltage for the second B doping was 40 kV, and the doping concentration was 3 × 10⁻⁶. 14 atom / cm 3 .

[0187] Figure 13 Example 2 illustrates the process by, as shown in the figure Figure 3 The first doping and using photoresist pattern 40 shown Figure 4 The threshold voltage of the thin-film transistor fabricated by the second doping shown is based on the length of the channel portion 131. Specifically, in the thin-film transistor fabricated in Example 2, the photoresist pattern 40 protruding beyond the gate electrode 140 has a total length of 2.0 μm, which is the sum of the lengths protruding from the left and right sides of the gate electrode 140, and the channel portion 131 has a length ranging from 2.5 μm to 20 μm (2.5 μm, 3 μm, 4 μm, 8 μm, 10 μm, 12 μm, 19 μm). The threshold voltage of the thin-film transistor is then measured. For conductivity, B is doped twice. The accelerating voltage for the first B doping is 40 kV, and the doping concentration is 1 × 10⁻⁶. 15 atom / cm 3 The accelerating voltage for the second B doping was 40 kV, and the doping concentration was 4 × 10⁻⁶. 14 atom / cm 3 .

[0188] Figure 13 Example 3 illustrates the process by, as shown in Figure 3 The first doping and using photoresist pattern 40 shown Figure 4The threshold voltage of the thin-film transistor fabricated by the second doping shown is based on the length of the channel portion 131. Specifically, in the thin-film transistor fabricated in Example 3, the photoresist pattern 40 protruding beyond the gate electrode 140 has a total length of 2.8 μm, which is the sum of the lengths protruding from the left and right sides of the gate electrode 140, and the channel portion 131 has a length ranging from 2.5 μm to 20 μm (2.5 μm, 3 μm, 4 μm, 8 μm, 10 μm, 12 μm, 18 μm). The threshold voltage of the thin-film transistor is then measured. For conductivity, B is doped twice. The accelerating voltage for the first B doping is 40 kV, and the doping concentration is 1 × 10⁻⁶. 15 atom / cm 3 The accelerating voltage for the second B doping was 40 kV, and the doping concentration was 4 × 10⁻⁶. 14 atom / cm 3 .

[0189] Reference Figure 13 In Comparative Example 1, when the length of the channel portion 131 is 3 μm, it is noted that no threshold voltage is formed in the thin-film transistor, and the thin-film transistor becomes conductive. Therefore, in Comparative Example 1, when the length of the channel portion 131 is 3 μm, the thin-film transistor cannot effectively perform the switching function.

[0190] On the other hand, in embodiments 1, 2, and 3 according to this disclosure, it is noted that even when the length of the channel portion 131 is 2.5 μm, the thin-film transistor can still have an effective threshold voltage. In embodiments 1, 2, and 3, it is noted that the threshold voltage increases as the length of the channel portion 131 increases. However, in any case, the thin-film transistor has a specific threshold voltage, thereby enabling the thin-film transistor to effectively perform switching functions.

[0191] In the following text, reference will be made to Figures 14A to 14H A method for manufacturing a thin-film transistor 100 according to one embodiment of the present disclosure is described.

[0192] Figures 14A to 14H This is a process diagram illustrating a method for manufacturing a thin-film transistor 100 according to one embodiment of the present disclosure.

[0193] Reference Figure 14A A buffer layer 120 is formed on the substrate 110, and an active layer 130 is formed on the buffer layer 120. The active layer 130 comprises an oxide semiconductor material. More specifically, the active layer 130 may be an oxide semiconductor layer.

[0194] Reference Figure 14BA gate insulating film 150 is formed on the active layer 130. The gate insulating film 150 covers the entire upper surface of the active layer 130.

[0195] In addition, refer to Figure 14B A material layer 145 for the gate electrode is formed on the gate insulating film 150. The material layer 145 for the gate electrode may include metal.

[0196] Reference Figure 14C A photoresist pattern 40 is formed on the material layer 145 used for the gate electrode. The photoresist pattern 40 can be formed by exposure and development of the photoresist.

[0197] Reference Figure 14D The material layer 145 for the gate electrode is etched using a photoresist pattern 40 as a mask. As a result, the gate electrode 140 is formed.

[0198] like Figure 14D As shown in the plan view, the size of the photoresist pattern 40 is larger than the size of the gate electrode 140. A gate electrode 140 with a smaller size than the photoresist pattern 40 can be formed by over-etching the material layer 145 used for the gate electrode. In the plan view, the gate electrode 140 can be disposed within the area defined by the photoresist pattern 40.

[0199] like Figure 14D In the cross-sectional view shown, the photoresist pattern 40 protrudes from the gate electrode 140. More specifically, the photoresist pattern 40 is formed to protrude beyond the area defined by the gate electrode 140. For example, the photoresist pattern 40 protrudes from the edge of the gate electrode 140 along a line that sequentially connects the subsequently formed first conductive portion 133a, channel portion 131, and second conductive portion 133b to each other.

[0200] The length of the photoresist patterns 40 protruding from the gate electrode 140 on both sides of the gate electrode 140 defines the lengths of the subsequently formed first gradient portion 132a and second gradient portion 132b. According to one embodiment of this disclosure, the sum of the lengths of the photoresist patterns 40 protruding from the gate electrode 140 on both sides of the gate electrode 140 can range from 1.5 μm to 3.3 μm. According to one embodiment of this disclosure, in Figure 14D In the figure shown, "both sides" refers to the left and right sides based on the gate electrode 140. According to one embodiment of this disclosure, the length of either side of the photoresist pattern 40 protruding from the gate electrode 140 can be 0.7 μm or greater.

[0201] According to one embodiment of this disclosure, the gate insulating film 150 may not be patterned during the process of forming the gate electrode 140. Therefore, the gate insulating film 150 may cover the entire upper surface of the active layer 130.

[0202] Next, the active layer 130 is doped with a dopant. Doping is performed through at least two steps.

[0203] In detail, refer to Figure 14E The active layer 130 is doped. Figure 14E The doping shown will be referred to as the first doping.

[0204] Reference Figure 14E In the first doping, a photoresist pattern 40 is used as a mask. The regions of the active layer 130 not protected by the photoresist pattern 40 are selectively doped.

[0205] The dopant may include at least one of B, P, F, and H. The dopant used for the first doping will be referred to as the first dopant. At least one of B, P, F, and H may be used as the first dopant. The dopant may be doped in an ionic state. According to one embodiment of this disclosure, the first doping can be performed by ion implantation.

[0206] Reference Figure 14F The active layer 130 is selectively conductiveized by the first doping, thus forming conductive portions 133a and 133b.

[0207] According to one embodiment of this disclosure, the channel portion 131 of the active layer 130 is not doped. For example... Figure 14F As shown, in the first doping process, the photoresist pattern 40 retained on the gate electrode 140 can be used as a mask to protect the channel portion 131.

[0208] Reference Figure 14E and Figure 14F Based on the cross-sectional view, the photoresist pattern 40 can have a length longer than the gate electrode 140, thereby allowing the gate electrode 140 to completely overlap with the photoresist pattern 40. This effectively protects the channel portion 131 from dopants.

[0209] Dopant is not doped in the channel portion 131 protected by the photoresist pattern 40. As a result, the channel portion 131 retains its semiconductor properties.

[0210] Reference Figure 14F Gradient portions 132a and 132b are formed in the region protected by the photoresist pattern 40. During the first doping, the dopant is not directly implanted into the gradient portions 132a and 132b. However, the dopant doped in the conductive portions 133a and 133b can diffuse into the gradient portions 132a and 132b. Therefore, the effect of partially doping the gradient portions 132a and 132b is achieved.

[0211] The lengths of each gradient portion 132a and 132b correspond to the lengths by which the photoresist pattern 40 protrudes from the gate electrode 140. According to one embodiment of this disclosure, the sum of the lengths of the first gradient portion 132a and the second gradient portion 132b can range from 1.5 μm to 3.3 μm.

[0212] Reference Figure 14F In gradient portions 132a and 132b, the first dopant may have a concentration gradient. Specifically, gradient portions 132a and 132b may include first regions 132a1 and 132b1 adjacent to channel portion 131, and second regions 132a2 and 132b2 adjacent to conductive portions 133a and 133b. In the second regions 132a2 and 132b2 of gradient portions 132a and 132b, the first dopant may have a concentration gradient. The first regions 132a1 and 132b1 of gradient portions 132a and 132b may not include the first dopant. According to one embodiment of this disclosure, the regions of gradient portions 132a and 132b that do not include the first dopant are defined as first regions 132a1 and 132b1.

[0213] Reference Figure 14G After the first doping, the photoresist pattern 40 is removed, and a second doping is performed using the gate electrode 140 as a mask. In the second doping, the ion concentration is lower than that of the first doping.

[0214] As the second dopant for the second doping, at least one of B, P, F, and H can be used. According to one embodiment of this disclosure, the second doping can be performed by ion implantation. According to one embodiment of this disclosure, the second dopant used for the second doping may be the same as or different from the first dopant used for the first doping.

[0215] A second doping is performed on the entire active layer 130, excluding the region protected by the gate electrode 140. Therefore, in this second doping, the dopant can be directly doped into the gradient portions 132a and 132b. However, due to the lower ion concentration in the second doping, the second dopant does not diffuse into the channel portion 131, or diffuses almost nothing into it. Figure 14G As shown, the concentration of the second dopant is the same for the entire doped region except for the channel portion 131. According to one embodiment of this disclosure, the second doping does not make the channel portion 131 conductive.

[0216] Reference Figure 14H As a result of this doping, conductive portions 133a and 133b are formed.

[0217] According to one embodiment of this disclosure, the buffer layer 120 may also be doped with a dopant during the doping process.

[0218] The dopant concentration of the active layer 130 may be higher than the dopant concentration of the gate insulating film 150 and the dopant concentration of the buffer layer 120. Alternatively, the dopant concentration of the buffer layer 120 may be higher than the dopant concentration of the active layer 130 and the dopant concentration of the gate insulating film 150.

[0219] Formed through the first and second doping processes Figure 14H The thin-film transistor 100 is shown. The total dopant concentration of the thin-film transistor 100 is as follows: Figure 14H As shown in the figure. The total dopant concentration of the thin-film transistor 100 may be referred to as the dopant concentration of the thin-film transistor 100. Since the dopant concentration of the thin-film transistor 100 has already been described, its detailed description will be omitted.

[0220] Figure 15 The illustration is a schematic diagram of a display device 600 according to another embodiment of the present disclosure.

[0221] like Figure 15 As shown, a display device 600 according to another embodiment of the present disclosure includes a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0222] The display panel 310 includes gate lines GL, data lines DL, and pixels P disposed in the intersection area between the gate lines GL and DL. Pixel P includes a display element and a pixel driving circuit for driving the display element. Images are displayed by driving the pixels P.

[0223] The controller 340 controls the gate driver 320 and the data driver 330.

[0224] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using a synchronization signal and a clock signal provided from an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, rearranges the sampled data, and provides the rearranged digital image data (RGB) to the data driver 330.

[0225] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Additionally, the gate control signal GCS may include control signals for controlling the shift register 350.

[0226] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0227] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage, and provides a horizontal line of data voltage to the data line DL during the first horizontal period of each gate pulse supplied to the gate line GL.

[0228] The gate driver 320 includes a shift register 350.

[0229] The shift register 350 sequentially provides gate pulses to the gate line GL within a frame using a start signal and a gate clock transmitted from the controller 340. In this case, a frame refers to a period of time during which an image is output through the display panel 310. The gate pulses have an on-state voltage for turning on the switching elements (thin-film transistors) disposed in the pixel P.

[0230] In addition, shift register 350 provides a gate cut-off signal to gate line GL during other periods in a frame when no gate pulse is provided, which turns off the switching element. Hereinafter, the gate pulse and gate cut-off signal are collectively referred to as the scan signal SS or Scan.

[0231] According to one embodiment of this disclosure, the gate driver 320 may be packaged on the display panel 310. In this manner, the structure in which the gate driver 320 is directly packaged on the display panel 310 is referred to as a gate-in-panel (GIP) structure. The gate driver 320 may include at least... Figure 1 and Figures 8 to 11 One of the thin-film transistors 100, 200, 300, 400 or 500 shown.

[0232] Figure 16 yes Figure 15 The circuit diagram of any pixel P.

[0233] Figure 16 The circuit diagram is an equivalent circuit diagram of pixel P of display device 600, which includes an organic light-emitting diode (OLED) as a display element 710.

[0234] Pixel P includes display element 710 and pixel driving circuit PDC that drives display element 710.

[0235] Figure 16 The pixel driving circuit PDC includes a first thin-film transistor TR1 as a switching transistor and a second thin-film transistor TR2 as a driving transistor. Figure 1 and Figures 8 to 11 Each of the thin-film transistors 100, 200, 300, 400 and 500 shown can be used as a first thin-film transistor TR1 or a second thin-film transistor TR2.

[0236] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and the first thin-film transistor TR1 is turned on or off by the scan signal SS provided by the gate line GL.

[0237] The data line DL provides the data voltage Vdata to the pixel drive circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0238] The driving power line PL provides a driving voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the application of the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0239] When the first thin-film transistor TR1 is turned on by the scan signal SS applied through the gate line GL by the gate driver 320, the data voltage Vdata supplied through the data line DL is provided to the gate electrode of the second thin-film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in the first capacitor C1 formed between the gate electrode and the source electrode of the second thin-film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0240] The amount of current supplied to the organic light-emitting diode (OLED) 710, which serves as the display element, is controlled by the data voltage Vdata, thereby controlling the grayscale level of the light emitted from the display element 710.

[0241] Figure 17 The diagram illustrates a circuit diagram of any pixel P of a display device 700 according to another embodiment of the present disclosure.

[0242] Figure 17 The pixel P of the display device 700 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC that drives the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0243] In pixel P, there are signal lines DL, GL, PL, RL and SCL for providing signals to the pixel driving circuit PDC.

[0244] The data voltage Vdata is provided to the data line DL, the scan signal SS is provided to the gate line GL, the driving voltage Vdd for driving the pixel is provided to the driving power line PL, the reference voltage Vref is provided to the reference line RL, and the sensing control signal SCS is provided to the sensing control line SCL.

[0245] Reference Figure 17 Assume that the gate line of the nth pixel P is "GLn", and the gate line of the (n-1)th pixel P adjacent to the nth pixel P is "GLn-1". The gate line "GLn-1" of the (n-1)th pixel P is used as the sensing control line SCL of the nth pixel P.

[0246] For example, the pixel driving circuit PDC includes: a first thin-film transistor TR1 (switching transistor), which is connected to the gate line GL and the data line DL; a second thin-film transistor TR2 (driving transistor), which controls the magnitude of the current output to the display element 710 according to the data voltage Vdata transmitted through the first thin-film transistor TR1; and a third thin-film transistor TR3 (reference transistor), which senses the characteristics of the second thin-film transistor TR2.

[0247] The first capacitor C1 is disposed between the gate electrode of the second thin-film transistor TR2 and the display element 710. The first capacitor C1 is referred to as the storage capacitor Cst.

[0248] The first thin-film transistor TR1 is turned on by the scan signal SS provided to the gate line GL, thereby transmitting the data voltage Vdata provided to the data line DL to the gate electrode of the second thin-film transistor TR2.

[0249] The third thin-film transistor TR3 is connected to the first node n1 and the reference line RL. The first node n1 is between the second thin-film transistor TR2 and the display element 710. Therefore, the third thin-film transistor TR3 is turned on or off by the sensing control signal SCS, and senses the characteristics of the second thin-film transistor TR2, which is a driving transistor, during the sensing period.

[0250] A second node n2, connected to the gate electrode of the second thin-film transistor TR2, is connected to the first thin-film transistor TR1. A first capacitor C1 is formed between the second node n2 and the first node n1.

[0251] When the first thin-film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is provided to the gate electrode of the second thin-film transistor TR2. The first capacitor C1 formed between the gate electrode and the source electrode of the second thin-film transistor TR2 is charged with the data voltage Vdata.

[0252] When the second thin-film transistor TR2 is turned on, current is supplied to the display element 710 through the second thin-film transistor TR2 according to the driving voltage Vdd of the driving pixel, thereby outputting light from the display element 710.

[0253] Figure 17 At least one of the first thin-film transistor TR1, the second thin-film transistor TR2, and the third thin-film transistor TR3 may have the same characteristics as... Figure 1 and Figures 8 to 11 The thin-film transistors 100, 200, 300, 400 and 500 shown have the same structure.

[0254] Figure 18 The diagram illustrates a circuit diagram of any pixel of a display device 800 according to yet another embodiment of the present disclosure.

[0255] Figure 18 The pixel P of the display device 800 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0256] The pixel drive circuit PDC includes thin-film transistors TR1, TR2, TR3, and TR4.

[0257] In pixel P, there are signal lines DL, EL, GL, PL, SCL and RL for providing drive signals to the pixel drive circuit PDC.

[0258] and Figure 17 Compared to the pixel P, Figure 18 The pixel P further includes an emission control line EL. An emission control signal EM is provided to the emission control line EL.

[0259] In addition, with Figure 17 Compared to the pixel drive circuit PDC, Figure 18 The pixel driving circuit PDC further includes a fourth thin-film transistor TR4 as a light-emitting control transistor, which is used to control the light-emitting timing of the display element 710.

[0260] Reference Figure 18 Assume that the gate line of the nth pixel P is "GLn", and the gate line of the (n-1)th pixel P adjacent to the nth pixel P is "GLn-1". The gate line "GLn-1" of the (n-1)th pixel P is used as the sensing control line SCL of the nth pixel (P).

[0261] The first capacitor C1 is disposed between the gate electrode of the second thin-film transistor TR2 and the display element 710. The second capacitor C2 is disposed between a terminal of the fourth thin-film transistor TR4 to which the driving voltage Vdd is supplied and an electrode of the display element 710.

[0262] The first thin-film transistor TR1 is turned on by the scan signal SS provided to the gate line GL, thereby transmitting the data voltage Vdata provided to the data line DL to the gate electrode of the second thin-film transistor TR2.

[0263] The third thin-film transistor TR3 is connected to the reference line RL and is turned on or off using the sensing control signal SCS. The third thin-film transistor TR3 senses the characteristics of the second thin-film transistor TR2, which is the driving transistor, during the sensing period.

[0264] The fourth thin-film transistor TR4 transmits the driving voltage Vdd to the second thin-film transistor TR2 according to the light emission control signal EM, or blocks the driving voltage Vdd. When the fourth thin-film transistor TR4 is turned on, current is supplied to the second thin-film transistor TR2, thereby outputting light from the display element 710.

[0265] Figure 18 At least one of the first thin-film transistor TR1, the second thin-film transistor TR2, the third thin-film transistor TR3, and the fourth thin-film transistor TR4 may have the same characteristics as... Figure 1 and Figures 8 to 11 The thin-film transistors 100, 200, 300, 400 and 500 shown have the same structure.

[0266] In addition to the structures described above, the pixel driving circuit PDC according to another embodiment of the present invention can also be formed in various other structures. For example, the pixel driving circuit PDC may include five or more thin-film transistors.

[0267] Figure 19 The diagram illustrates a circuit diagram of any pixel P of a display device 900 according to yet another embodiment of the present disclosure.

[0268] Figure 19 The display device 900 is a liquid crystal display device.

[0269] Figure 19 The pixel P of the display device 900 shown includes a pixel driving circuit PDC and a liquid crystal capacitor Clc connected to the pixel driving circuit PDC. The liquid crystal capacitor Clc corresponds to the display element.

[0270] The pixel driver PDC includes a thin-film transistor TR connected to the gate line GL and the data line DL, and a storage capacitor Cst connected between the thin-film transistor TR and the common electrode 372. A liquid crystal capacitor Clc is connected in parallel with the storage capacitor Cst between the thin-film transistor TR and the common electrode 372.

[0271] The liquid crystal capacitor Clc is charged with the voltage difference between the data signal supplied to the pixel electrode via the thin-film transistor TR and the common voltage Vcom supplied to the common electrode 372, and the amount of light transmission is controlled by driving the liquid crystal according to the charged voltage. The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.

[0272] Figure 19 Thin-film transistors (TRs) can have the same characteristics as... Figure 1 and Figures 8 to 11 The thin-film transistors 100, 200, 300, 400 and 500 shown have the same structure.

[0273] According to one embodiment of this disclosure, a gradient portion can be formed between the channel portion and the conductive portion of the active layer by first doping using a photoresist pattern as a mask and second doping using a gate electrode as a mask, and due to this gradient portion, a thin-film transistor with a short channel can be designed.

[0274] According to another embodiment of this disclosure, the active layer of the thin-film transistor has a gradient portion, thereby achieving stability of the channel portion and driving stability of the thin-film transistor.

[0275] According to other embodiments of this disclosure, thin-film transistors can be manufactured in small sizes because the channel length can be reduced. Thin-film transistors can be integrated into various electronic products, and when used, high-resolution display devices can be manufactured.

[0276] It will be apparent to those skilled in the art that the above disclosure is not limited to the described embodiments and drawings, and various substitutions, modifications, and variations can be made to the disclosure without departing from its spirit or scope. Therefore, the scope of the disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of this disclosure.

Claims

1. A thin-film transistor, comprising: substrate; An active layer on the substrate, the active layer comprising an oxide semiconductor material; A buffer layer between the substrate and the active layer; A gate electrode spaced apart from and partially overlapping the active layer; as well as The gate insulating film between the active layer and the gate electrode, The active layer includes: The channel portion overlapping the gate electrode; A conductive portion that does not overlap with the gate electrode; and The gradient portion between the channel portion and the conductive portion, which does not overlap with the gate electrode. The conductive portion and the gradient portion of the active layer are doped with dopants. The gate insulating film covers the upper surface of the active layer facing the gate electrode during doping of the active layer. In the gradient portion, the dopant concentration increases along the direction from the channel portion toward the conductive portion. The buffer layer includes the dopant in the region that overlaps with the conductive portion.

2. The thin-film transistor of claim 1, wherein the gradient portion comprises a first region adjacent to the channel portion and a second region adjacent to the conductive portion. The first region includes a first portion adjacent to the channel portion and a second portion adjacent to the second region, and The concentration gradient of the dopant in the first part of the first region is greater than the concentration gradient of the dopant in the second region.

3. The thin-film transistor of claim 2, wherein the concentration gradient of the dopant in the second portion of the first region is less than the concentration gradient of the dopant in the second region.

4. The thin-film transistor of claim 3, wherein the first region has a stepped concentration profile.

5. The thin-film transistor of claim 2, wherein the second portion of the first region does not have a dopant concentration gradient.

6. The thin-film transistor of claim 2, wherein the concentration gradient of the dopant in the second region is uniform.

7. The thin-film transistor of claim 1, wherein the dopant comprises a first dopant and a second dopant, and the first dopant has a concentration gradient in the gradient portion.

8. The thin-film transistor of claim 7, wherein the concentration of the second dopant is uniform in the conductive portion and the gradient portion.

9. The thin-film transistor of claim 7, wherein the gradient portion includes a first region adjacent to the channel portion and a second region adjacent to the conductive portion, and the first region does not include the first dopant.

10. The thin-film transistor of claim 1, wherein the specific resistance of the gradient portion is lower than that of the channel portion and higher than that of the conductive portion.

11. The thin-film transistor of claim 1, wherein the dopant comprises at least one of B, P, F and H.

12. The thin-film transistor of claim 1, wherein the buffer layer includes the dopant in the region overlapping with the gradient portion.

13. The thin-film transistor according to claim 1, wherein, In the region overlapping with the conductive portion, the maximum dopant concentration of the buffer layer is higher than the dopant concentration of the conductive portion and the dopant concentration of the gate insulating film.

14. The thin-film transistor according to claim 1, wherein, In the region overlapping with the conductive portion, the maximum dopant concentration of the conductive portion is higher than the dopant concentration of the gate insulating film and the dopant concentration of the buffer layer.

15. The thin-film transistor of claim 7, wherein the first dopant is implanted into the conductive portion and diffused into the gradient portion.

16. The thin-film transistor of claim 7, wherein the second dopant is implanted into the conductive portion and the gradient portion.

17. The thin-film transistor of claim 7, wherein in the conductive portion, the concentration of the second dopant is less than the concentration of the first dopant.

18. The thin-film transistor of claim 1, wherein the active layer comprises: First oxide semiconductor layer; and A second oxide semiconductor layer on top of the first oxide semiconductor layer.

19. The thin-film transistor of claim 1, further comprising a source electrode and a drain electrode spaced apart from each other and respectively connected to the active layer.

20. The thin-film transistor of claim 19, wherein the source electrode and the drain electrode are disposed on the same layer as the gate electrode and are made of the same material as the gate electrode.

21. A method for manufacturing a thin-film transistor, the method comprising: Form a buffer layer; An active layer is formed on the buffer layer, the active layer comprising an oxide semiconductor material; A gate insulating film is formed on the active layer; A gate electrode that partially overlaps with the active layer is formed on the gate insulating film by using a photoresist patterning process; and The active layer is doped with a dopant to form a conductive portion that does not overlap with the gate electrode. The gate insulating film covers the upper surface of the active layer facing the gate electrode during the doping of the active layer. In the plan view, the gate electrode is disposed within the area defined by the photoresist pattern. The buffer layer includes the dopant in the region overlapping with the conductive portion, and The active layer doping agent includes: The first doping using the photoresist pattern as a mask; and A second doping is performed using the gate electrode as a mask after the photoresist pattern is removed.

22. The method of claim 21, wherein the sum of the lengths of the photoresist patterns protruding from the gate electrode on both sides of the gate electrode ranges from 1.5 μm to 3.3 μm.

23. The method of claim 21, wherein the dopant comprises at least one of B, P, F and H.

24. The method of claim 21, wherein the dopant used for the first doping and the dopant used for the second doping are the same as each other.

25. The method of claim 21, wherein the dopant used for the first doping and the dopant used for the second doping are different from each other.

26. The method of claim 21, wherein the doping concentration of the second doping is lower than the doping concentration of the first doping.

27. A display device comprising a thin-film transistor according to any one of claims 1 to 20.

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