Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. A semiconductor device includes a plurality of memory cells, each memory cell including: a memory layer; a first selector layer formed in an upper portion or a lower portion of the memory layer to select the memory layer; a second selector layer for selecting a memory layer; and an interface layer disposed between the first selector layer and the second selector layer, in which the first selector layer and the second selector layer include an amorphous silicon layer including one or more dopants selected from the group including Group 13 elements, Group 14 elements, and Group 15 elements of the periodic table, and wherein the interface layer is selected from the group comprising silicon oxide, silicon carbonitride, silicon carbonitride, silicon nitride, tantalum nitride, titanium nitride, aluminum nitride, and hafnium nitride.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0108390, filed on August 13, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure generally relate to semiconductor technology, and more specifically, to a semiconductor device including a memory cell having a selector, and a method of manufacturing the semiconductor device. Background Technology

[0004] In recent years, there has been a need for semiconductor devices capable of storing data in various electronic devices, such as computers and portable communication devices, to address the trends of miniaturization, low power consumption, high performance, and diversification in electronic devices. Developing such semiconductor devices requires extensive research and development work. Semiconductor devices capable of storing data by utilizing the characteristic of switching between different resistance states according to applied voltage or current can include resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electronic fuses, among others.

[0005] A memory device having a variable resistance element may include a selector as an element for selecting a specific memory cell from a plurality of memory cells arranged in an array, and the selector may be implemented as a thin layer in the memory cell, which is also referred to as a layer in this application. Summary of the Invention

[0006] Embodiments of this disclosure relate to a semiconductor device with improved selector characteristics having a memory cell, and a method of manufacturing the semiconductor device.

[0007] According to one embodiment of this disclosure, a semiconductor device includes a plurality of memory cells, wherein each memory cell includes: a memory layer; a first selector layer formed in an upper or lower portion of the memory layer to select the memory layer; a second selector layer adapted to select the memory layer; and an interface layer disposed between the first selector layer and the second selector layer, wherein the first selector layer and the second selector layer include an amorphous silicon layer, the amorphous silicon layer including one or more dopants selected from the group consisting of elements of Group 13, Group 14 and Group 15 of the periodic table, and wherein the interface layer is selected from the group consisting of silicon oxide, silicon carbonitride, silicon carbonitride oxycarbonate, silicon nitride, tantalum nitride, titanium nitride, aluminum nitride and hafnium nitride.

[0008] According to another embodiment of the disclosure, a method for manufacturing a semiconductor device including a first selector layer and a second selector layer in a memory cell to control electrical access to one of a plurality of memory cells arranged in an array, the method includes: forming an amorphous silicon layer containing a dopant as the first selector layer over a substrate; depositing an interface layer over the first selector layer, a material of the interface layer being selected from a group including silicon oxide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitride, tantalum nitride, titanium nitride, aluminum nitride, and hafnium nitride; forming an amorphous silicon layer containing a dopant as the second selector layer over the interface layer; and performing a heat treatment at a temperature equal to or lower than a temperature at which the amorphous silicon layer crystallizes. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1A and FIG. 1B A semiconductor device according to one embodiment of the disclosure is shown.

[0010] FIG. 2A and FIG. 2B A semiconductor device according to another embodiment of the disclosure is shown.

[0011] FIG. 3 is a cross-sectional view showing a structure of a selector cell according to one embodiment of the disclosure.

[0012] FIG. 4A to FIG. 4H is a cross-sectional view showing a method of manufacturing a semiconductor device according to one embodiment of the disclosure.

[0013] FIG. 5A to FIG. 5H is a cross-sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the disclosure. DETAILED DESCRIPTION

[0014] Hereinafter, various embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0015] Embodiments of the disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the disclosure to the skilled in the art. Like reference numerals refer to like elements throughout the specification and the drawings.

[0016] The drawings are not necessarily to scale and, in some instances, proportions have been exaggerated in order to clearly convey the concepts of the embodiments. When a first layer is referred to as being "on" or "under" a second layer, it can mean that the first layer is directly formed on the second layer or there can be one or more third layers between the first layer and the second layer.

[0017] FIG. 1A and FIG. 1B A semiconductor device according to one embodiment of the present disclosure is shown. FIG. 1A is a perspective view, FIG. 1B is a cross-sectional view taken along FIG. 1A line A-A' shown in FIG. 1. According to an embodiment of the present disclosure, a semiconductor device can have a structure in which an interface layer 141 is formed between a first selector layer 140 and a second selector layer 150. FIG. 1A and FIG. 1B A semiconductor memory according to an embodiment of the present disclosure can have a structure in which an interface layer 141 is formed between a first selector layer 140 and a second selector layer 150.

[0018] Referring to FIG. 1A and FIG. 1B , a semiconductor device can have a cross-point structure including a substrate 100, a plurality of first conductive lines 110 disposed over the substrate 100 and extending in a first direction, a plurality of second conductive lines 120 disposed over the first conductive lines 110 and extending in a second direction intersecting the first direction, and a plurality of memory cells MC disposed to overlap with intersection regions between the first conductive lines 110 and the second conductive lines 120. Here, the first direction and the second direction can refer to directions substantially parallel to a surface of the substrate 100. Hereinafter, a direction substantially perpendicular to the surface of the substrate 100 can be referred to as a vertical direction.

[0019] The substrate 100 can include a semiconductor material such as silicon. Further, a predetermined lower structure (not shown) can be formed in the substrate 100. For example, an integrated circuit for driving the first conductive lines 110 and / or the second conductive lines 120 can be formed in the substrate 100.

[0020] The plurality of first conductive lines 110 can be disposed at regular intervals from each other in the second direction. The first conductive lines 110 can include a variety of conductive materials such as, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or the like, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, or a combination thereof. The first conductive lines 110 can have a single-layer structure or a multi-layer structure.

[0021] The plurality of second conductive lines 120 can be disposed at regular intervals from each other in the first direction. The second conductive lines 120 can include a variety of conductive materials such as, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or the like, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, or a combination thereof. The second conductive lines 120 can have a single-layer structure or a multi-layer structure.

[0022] Each memory cell MC can include a memory unit MU, which is a portion of the memory cell MC that actually stores data, and a selector unit SU, which is a portion of the memory cell MC that controls access to the memory unit MU. Each memory cell MC can include a first electrode layer 130 disposed below the first selector layer 140 and the second selector layer 150. Each memory cell MC can also include a second electrode layer 160 and / or a third electrode layer 180 disposed above the first selector layer 140 and the second selector layer 150. In addition, each memory cell can also include an interface layer 141 disposed between the first selector layer 140 and the second selector layer 150. The interface layer 141 can include a dielectric material, such as silicon oxide, that forms As-Si-O bonds with the first selector layer 140 formed by a plasma oxidation process. In addition, the interface layer 141 can include arsenic-silicon oxide, silicon oxide, silicon carbonitride, silicon oxycarbonitride, silicon nitride, tantalum nitride, titanium nitride, aluminum nitride, or hafnium nitride, and the interface layer 141 can be formed by chemical oxidation, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), a combination of chemical deposition, atomic layer deposition (ALD), and chemical vapor deposition (CVD), and / or other suitable methods. In addition, the interface layer 141 can be a metal oxide, such as aluminum oxide (AI2O3), hafnium oxide (HfO2), titanium oxide (TiO2), yttrium oxide (Y2O3), cerium oxide (CeO2), scandium oxide (Sc2O3), zinc oxide (ZnO), niobium oxide (Nb2O5), or tin oxide (SnO2), although the inventive concept and scope of the present disclosure is not limited thereto. Each memory cell MC can include a thin layer of SiN at the interface between the first electrode layer 130 and the first selector layer 140, and a thin layer of carbon (C) at the interface between the second selector layer 150 and the second electrode layer 160. As used herein, a thin layer of SiN refers to a layer having a thickness of 1 nm to 50 nm, or more specifically, a thickness of 1 nm to 10 nm. As used herein, a thin layer of carbon (C) refers to a layer having a thickness of 0.5 nm to 20 nm, or more specifically, a thickness of 0.5 nm to 5 nm.

[0023] For example, the interface layer 141 can be SiO2, SiN, SiCN, SiON, or SiCON. The interface layer 141 can be a single layer that forms As-Si-O bonds or Si-C-O-N bonds with the first selector layer 140. The interface layer 141 can be very thin such that it does not affect the flow of current. The interface layer 141 can have a thickness that is not electrically significant. The formation of the interface layer 141 will be described in more detail later with reference to FIG. 4A to 5H FIG. 4C to FIG. 4H and FIG. 5E to FIG. 5H The interface layer 141 can be the same as the interface layer 221 shown in FIGS. 2A and 2B, which will be described later.​

[0024] For example, the memory cell MC can include a stack structure of the first electrode layer 130, the first selector layer 140, the interface layer 141, the second selector layer 150, the second electrode layer 160, the memory layer 170, and the third electrode layer 180. Here, the selector unit SU can include the first electrode layer 130, the first selector layer 140, the interface layer 141, the second selector layer 150, and the second electrode layer 160, and the memory unit MU can include the second electrode layer 160, the memory layer 170, and the third electrode layer 180. The second electrode layer 160 can be shared by the selector unit SU and the memory unit MU.

[0025] The first electrode layer 130 and the third electrode layer 180 can be disposed at both ends of the memory cell MC, i.e., at the bottom end and the top end of the memory cell MC, respectively, and can function to apply a voltage or a current required for an operation of the memory cell MC. The second electrode layer 160 can function to electrically connect the first selector layer 140 and the second selector layer 150 to the memory layer 170 to each other, and to physically separate them from each other. The first electrode layer 130, the second electrode layer 160, or the third electrode layer 180 can include a variety of conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), or the like, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, or a combination thereof. In addition, the first electrode layer 130, the second electrode layer 160, or the third electrode layer 180 can include a carbon electrode.

[0026] The memory layer 170 can function to store data in a variety of ways. For example, the memory layer 170 can include a variable resistance layer that stores different data by switching between different resistance states according to a voltage or a current supplied through the upper end and the lower end of the memory layer 170. The variable resistance layer can have a single-layer structure or a multi-layer structure, including a variety of materials used in resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), or the like, for example, a metal oxide such as a transition metal oxide, a perovskite-based material, or the like, a phase-change material such as a chalcogenide-based material, a ferroelectric material, a ferromagnetic material, or the like.

[0027] The first selector layer 140 and the second selector layer 150 can be formed as a thin layer in the memory cell. As used herein, a thin layer refers to a layer having a thickness of 1 nm to 100 nm, 1 nm to 50 nm, or 1 nm to 30 nm. The first selector layer 140 and the second selector layer 150 can prevent current leakage between memory cells MC sharing the first wire 110 or the second wire 120 and control electrical access to one of the memory cells arranged in an array. To this end, the first selector layer 140 and the second selector layer 150 can have a threshold switching characteristic, i.e., block current flow or keep current flow almost nil when a voltage level supplied to upper and lower ends of the first selector layer 140 and the second selector layer 150 is lower than a predetermined threshold voltage level, and then let current flow fast at a voltage level equal to or higher than the predetermined threshold voltage level. The first selector layer 140 and the second selector layer 150 can be turned on at a voltage level equal to or higher than the threshold voltage level and turned off at a voltage level lower than the threshold voltage level.

[0028] In general, the first selector layer 140 and the second selector layer 150 can be made of a dielectric material into which a dopant is injected. The dielectric material suitable for the first selector layer 140 and the second selector layer 150 includes, for example, a silicon oxide layer or an amorphous silicon layer. The dopant suitable for the first selector layer 140 and the second selector layer 150 includes, for example, an n-type dopant or a p-type dopant. The dopant can be introduced through an ion implantation process. The dopant can include, for example, one or more selected from the group including boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), and germanium (Ge).

[0029] The first selector layer 140 and the second selector layer 150 can include, for example, an amorphous silicon layer including one or more dopants selected from the group including a group 13 element, a group 14 element, and a group 15 element of the periodic table, and according to a preferred embodiment of the present disclosure, the first selector layer 140 and the second selector layer 150 can include, for example, an amorphous silicon layer doped with boron (B). This can increase the consistency with oxides and nitrides of the interface layer 141. According to another embodiment of the present disclosure, the interface layer 141 can be doped with arsenic (As) by additionally implanting ions into the amorphous silicon layer doped with boron. The formation of the first selector layer 140 and the second selector layer 150 will be described in detail later with reference to FIG. 2. FIG. 4A to FIG. 5H

[0030] ​According to embodiments of the present disclosure, the dopant doped into the amorphous silicon layer can be an element of Group 13 of the periodic table instead of boron (B), and can be an element of Group 14 or Group 15 of the periodic table instead of arsenic (As). The potential difference between the first selector layer 140 and the second selector layer 150 can be generated by controlling the concentration of ion-implanted elements, such as arsenic (As). By utilizing this potential difference, the formation voltage and threshold voltage can be optimized, and efficient selector operation can be performed. The potential difference between the first selector layer 140 and the second selector layer 150 can be formed by changing the formation voltage in terms of the design of the bias application direction, the presence or absence of electrode bonding, and the formation operation, or by adjusting the thickness of the base material of the selector layer or the concentration of elements ion-implanted into the first selector layer 140 and the second selector layer 150.

[0031] According to the combination of the base material of the first selector layer 140 and the second selector layer 150 or the ion concentration implanted into the first selector layer 140 and the second selector layer 150 and the base material of the interface layer 141, a potential difference can be generated between the first selector layer 140 and the second selector layer 150. For example, a P-type selector layer can be a selector layer having a high ion concentration, and an N-type selector layer can be a selector layer having a low ion concentration. Accordingly, the first selector layer 140 and the second selector 150 can function as a P-N-P diode or an N-P-N diode. For example, in the P-N-P diode, the first selector layer 140 can be an N-type selector layer, and the second selector layer 150 can be a P-type selector layer, and in the N-P-N diode, the first selector layer 140 can be a P-type selector layer, and the second selector layer 150 can be an N-type selector layer.

[0032] In general, an oxide layer such as SiO2 can be formed by mixing a source gas containing silicon (Si) and oxygen (O) through a method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Since the deposited oxide layer formed in this way has a relatively low density, when a dopant is subsequently introduced through ion implantation, a micropore can be formed inside, or a portion of the surface of the first electrode layer 130 or the second electrode layer 160 disposed at the lower portion of the deposited oxide layer can be damaged, resulting in a problem in which the interface between the first selector layer 140 and the first electrode layer 130 or the second electrode layer 160 is not clear.

[0033] The role of the selector in the memory device can be important. The selector can be used to selectively operate the memory cell, and the selector can need a high on-off ratio and low current leakage. However, a typical selector structure can not be sufficient to meet these requirements. Accordingly, embodiments of the present disclosure propose a method of forming a double selector layer using an interface layer to solve this problem.

[0034] To solve this problem, according to one embodiment of the present disclosure, an interface layer 141 can be disposed between the first selector layer 140 and the second selector layer 150, thereby enabling a dual selector layer to be formed. This can reduce current leakage and reduce the off-state current I off and semi-state current I half off by the Schottky barrier effect of the interface layer 141 according to the strength of the applied bias. In addition, by controlling the base material of the first selector layer 140, the second selector layer 150, and the interface layer 141, and the concentration of ions injected into the first selector layer 140 and the second selector layer 150, a wide potential difference can be obtained between the first selector layer 140 and the second selector layer 150, thereby enabling various electrical characteristics of the dual selector layer.

[0035] Referring back to FIG. 1A and FIG. 1B , the semiconductor device according to an embodiment of the present disclosure can have a structure in which the first selector layer 140, the interface layer 141, and the second selector layer 150 are sequentially stacked on the first electrode layer 130, and then the second electrode layer 160, the storage layer 170, and the third electrode layer 180 are sequentially stacked on the stack of the first electrode layer 130, the first selector layer 140, the interface layer 141, and the second selector layer 150. That is, a structure in which the storage layer 170 is formed in the upper portion of the dual selector layer can be formed. An interlayer dielectric material 190 can be injected between the stacked structure. In general, silicon oxide (SiO2), silicon nitride (Si3N4), a high-k material, etc. can be used for the interlayer dielectric material 190. The interlayer dielectric material 190 can be used for interlayer insulation, can prevent electrical interference, and can provide electrical insulation between elements.

[0036] Whether the storage layer 170 is disposed in the upper portion or the lower portion of the dual selector layer, there is no significant difference in the functional performance of the dual selector layer. However, when the storage layer 170 is disposed in the upper portion of the dual selector layer, by stacking the storage layer after forming the selector layer, the process can become relatively simple, and the bonding between the selector layer and the storage layer can become relatively easy. However, when the storage layer must undergo a high-temperature process after the formation of the selector layer, the thermal stability of the storage layer can become an issue.

[0037] FIG. 2A and FIG. 2B A semiconductor device according to another embodiment of the present disclosure is illustrated. FIG. 2A is an isometric view, FIG. 2B is a cross-sectional view taken along FIG. 2AA cross-sectional view taken along the line A-A' shown in FIG. 1. A semiconductor device according to another embodiment of the disclosure can have a structure in which the storage layer 170 and the second electrode layer 160 are sequentially stacked on the first electrode layer 130, and then the first selector layer 140, the interface layer 141, the second selector layer 150, and the third electrode layer 180 are sequentially stacked on the stacked structure of the first electrode layer 130, the storage layer 170, and the second electrode layer 160. A structure in which the storage layer 170 is formed in the lower portion of the dual selector layer can be formed. In this case, since the storage layer is disposed in the lower portion, the storage layer can be less affected during the heat treatment of the selector layer, and physical damage to the storage layer in the subsequent process can be avoided. However, when the selector layer is formed after the storage layer is formed, the process can become relatively complex, and the interlayer bonding between the storage layer and the selector layer can become relatively difficult.

[0038] FIG. 2A and FIG. 2B The semiconductor device shown in FIG. 1 can be similar to the semiconductor device shown in FIG. 1A and FIG. 1B The semiconductor device shown in FIG. 1 can be similar to the semiconductor device shown in FIG. 1A and FIG. 1B Detailed descriptions of parts similar to the embodiment of the disclosure shown in FIG. 1 will be omitted here. All the advantages described in the above-described embodiments of the disclosure can be obtained even with this embodiment of the disclosure.

[0039] Although FIG. 1A to FIG. 2B Although the storage cell MC is shown to have a stacked structure of the first electrode layer 130, the first selector layer 140, the interface layer 141, the second selector layer 150, the second electrode layer 160, the storage layer 170, and the third electrode layer 180, the technical idea and scope of the disclosure are not limited thereto, and the layer structure of the storage cell MC can be modified differently. For example, at least one of the first electrode layer 130, the second electrode layer 160, and the third electrode layer 180 can be omitted. For example, the storage cell MC can include the first selector layer 140 and the second selector layer 150, the first electrode layer 130 or the second electrode layer 160 disposed below the first selector layer 140, and the second electrode layer 160 or the third electrode layer 180 disposed above the second selector layer 150. For example, the first electrode layer 130 disposed below the first selector layer 140 can include titanium nitride (TiN), and the third electrode layer 180 disposed above the second selector layer 150 can include a carbon (C) electrode. Furthermore, for example, the upper and lower positions of the dual selector layer and the storage layer 170 can be switched with each other. Furthermore, for example, the storage cell MC can further include one or more layers (not shown) to enhance characteristics or improve a process.

[0040] FIG. 3 is a cross-sectional view illustrating a structure of a selector unit according to one embodiment of the present disclosure.

[0041] Referring to FIG. 3 , the selector unit SU can include a first electrode layer 130, a first selector layer 140, an interface layer 141, a second selector layer 150, and a second electrode layer 160.

[0042] As described above, the first electrode layer 130 and the second electrode layer 160 can include a variety of conductive materials, such as a metal, a metal nitride, etc. The first electrode layer 130 and the second electrode layer 160 can be formed of the same material to have the same work function. For example, the first electrode layer 130 and the second electrode layer 160 can include titanium nitride (TiN) having a work function of about 4.4 to 4.6 eV. However, the technical idea and scope of the present disclosure are not limited thereto, and the first electrode layer 130 and the second electrode layer 160 can be formed of different materials to have different work functions. As used herein, the term "about" when referring to a numerical range means within ±5% of the stated value.

[0043] The first selector layer 140 and the second selector layer 150 can include, for example, an amorphous silicon layer 142 and dopants 144 and 154 implanted into the amorphous silicon layer 142.

[0044] The amorphous silicon layer 142 can be a dielectric material having a relatively wide band gap, specifically, a dielectric material having a band gap of about 5.0 eV or more. For example, there can be deep traps in the amorphous silicon layer 142, the energy levels of which are closer to the energy level of the valence band than to the energy level of the conduction band of the thin layer. The dopants 144 can serve to create shallow traps that provide a path for conductive carriers, such as electrons or holes, to move in the amorphous silicon layer 142. The energy levels of the shallow traps can be closer to the energy level of the conduction band of the amorphous silicon layer 142 than to the energy level of the valence band.

[0045] Dopant 144 may include one or more elements selected from the group consisting of Group 13, Group 14, and Group 15 elements of the periodic table whose atomic valence differs from that of silicon (Si). For example, dopant 144 may include Group 13 elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In). For example, dopant 144 may include Group 14 elements such as carbon (C), silicon (Si), germanium (Ge), or tin (Sn), as well as Group 13 elements. For example, dopant 144 may include Group 15 elements such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb), as well as Group 13 elements. For example, dopant 144 may include boron (B), and may further include one or more of phosphorus (P) and arsenic (As) together with boron (B).

[0046] The dopant concentration and amorphous silicon ratio in a doped amorphous silicon layer can vary significantly depending on process conditions. The dopant concentration can be controlled by adjusting the concentration of diborane (B₂H₆) and silane gas (Si). x H y The flow rate and hydraulic pressure are used to regulate the dopant concentration. For example, increasing the flow rate of diborane (B₂H₆) can increase the dopant concentration, while increasing the flow rate of silane gas (SiO₂) can decrease it. x H y The flow rate can increase the ratio of amorphous silicon. When a doped amorphous silicon layer is generated by reacting diborane and silane gases at a temperature of about 300°C, the dopant 144 in the doped amorphous silicon layer can have a concentration of about 10 wt% to 30 wt%, and the amorphous silicon can have a concentration of about 90 wt% to 70 wt%. When a doped amorphous silicon layer is generated by reacting diborane and silane gases at a temperature of about 400°C, the diffusion of the dopant can become more active, and the dopant can be more easily doped into the amorphous silicon layer. Therefore, in this case, the dopant 144 in the doped amorphous silicon layer can have a concentration of about 30 wt% to 90 wt%, and the amorphous silicon can have a concentration of about 70 wt% to 10 wt%.

[0047] FIG. 4A to FIG. 4H This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0048] Reference FIG. 4A A substrate 200 having a predetermined lower structure formed thereon can be provided. The substrate 200 may include various circuits. For example, the substrate 200 may include circuits similar to those described above. FIG. 1A and FIG. 2A The first conductor 110.

[0049] Subsequently, a first electrode layer 210 can be formed over the substrate 200. The first electrode layer 210 can be formed as a TiN thin layer. As used herein, a TiN thin layer refers to a layer having a thickness of 5 nm to 100 nm, or more specifically, a thickness of 5 nm to 50 nm.

[0050] Subsequently, an initial first selector layer 220 can be formed over the first electrode layer 210. The initial first selector layer 220 can include a silicon oxide layer or an amorphous silicon layer doped with a first dopant as a silicon (Si) containing layer. Here, a method of forming the silicon oxide layer or the amorphous silicon layer doped with the first dopant can be implemented as a method of depositing the silicon oxide layer or the amorphous silicon layer doped with the first dopant. The first dopant can include at least one selected from a group including boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), and germanium (Ge).

[0051] The amorphous silicon layer containing the first dopant can be formed by a low pressure chemical vapor deposition (LPCVD) process using a catalyst containing the first dopant and a silicon source gas. For example, the amorphous silicon layer containing the first dopant can be formed by a low pressure chemical vapor deposition (LPCVD) process using silane gas (SixHy) (e.g., SiH4) and diborane (B2H6). The low pressure chemical vapor deposition (LPCVD) process can provide a uniform thin layer and a low defect rate, thereby improving the performance of a semiconductor device.

[0052] When boron (B) is used as the first dopant, a boron-containing catalyst can be selected from a group including trimethyl borate (B(Ome)3), boron trichloride (BCl3), boron tribromide (BBr3), boron dibromide (BBr2), boron trifluoride (BF3), or diborane (B2H6). In the case of a boron (B)-containing catalyst that does not contain hydrogen in itself, it can be supplied together with hydrogen (H2).

[0053] Subsequently, with reference to FIG. 4BA second dopant (e.g., arsenic (As)) ions can be implanted into an amorphous silicon layer containing a first dopant. Besides arsenic (As), the second dopant may also include elements from Group 14 of the periodic table, such as carbon (C), silicon (Si), germanium (Ge), or tin (Sn), or elements from Group 15 of the periodic table, such as nitrogen (N), phosphorus (P), or antimony (Sb). According to one embodiment of this disclosure, the first dopant may include boron (B), while the second dopant may include one or more selected from the group consisting of carbon (C), silicon (Si), germanium (Ge), phosphorus (P), and arsenic (As). Ion implantation of the second dopant can be performed in a direction substantially perpendicular to the surface of the substrate 200. However, angular ion implantation can also be performed. The ion implantation process can be repeated several times. Electrical properties can be imparted to semiconductor devices fabricated by implanting second dopant ions, such as arsenic (As), into the amorphous silicon layer. The characteristics of the semiconductor device can be suitably altered by varying the concentration of the second dopant implanted. For example, the concentration can be adjusted in the range of about 10% to 50% depending on the implantation conditions.

[0054] It is easy to ensure that the second dopant is implanted into the amorphous silicon layer with additional ions, and the conductive path in the amorphous silicon layer can be easily ensured due to the influence of the second dopant during the ion implantation process.

[0055] This ion implantation process can be performed at high energy and high ion implantation rates, and because ions such as arsenic (As) are heavy components with large mass, the ion implantation process can be performed under conditions that the layer material cannot withstand. According to embodiments of this disclosure, a second dopant can be absorbed into the vacancies between silicon (Si) and hydrogen (H) in an amorphous silicon layer containing the first dopant. Therefore, the layer material can withstand these harsh conditions during the ion implantation process. This prevents the formation of defects such as micropores internally.

[0056] Subsequently, referring to FIG. 4C ,because FIG. 4B The ion implantation process shown allows for the formation of a first selector layer 225 from an initial first selector layer 220, wherein a second dopant is ion-implanted into an amorphous silicon layer containing the first dopant, and an interface layer 221 can be deposited on the first selector layer 225. The interface layer 221 can be formed via chemical oxidation, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical deposition, a combination of ALD and CVD, and / or other suitable methods. The base material and deposition method of the interface layer 221 can be appropriately selected considering the electrical characteristics of the dual selector layer.

[0057] Subsequently, referring to FIG. 4DAn initial second selector layer 230 can be formed on the interface layer 221. The base material of the initial second selector layer 230 can be the same as that of the initial first selector layer 220, and thus can include a silicon oxide layer or an amorphous silicon layer doped with a first dopant as a silicon (Si) containing layer. Referring to FIG. 4E A second dopant (e.g., arsenic (As)) can be ion implanted into the amorphous silicon layer containing the first dopant as shown in FIG. 4B Referring to FIG. 4F The second selector layer 235 can be formed from the initial second selector layer 230 by the ion implantation process of FIG. 4E wherein the second dopant is ion implanted into the amorphous silicon layer containing the first dopant.

[0058] Referring to FIG. 4G A second electrode layer 240 can be formed on the second selector layer 235. The second electrode layer 240 can be formed by a method of depositing a conductive material. The second electrode layer 240 can be formed as a single TiN thin layer, or the second electrode layer 240 can be formed by stacking a carbon (C) thin layer and a TiN layer. In this case, the carbon (C) thin layer can be formed at an interface between the amorphous silicon layer and the TiN layer.

[0059] Referring to FIG. 4H A storage layer 250 can be deposited on the second electrode layer 240 to manufacture a semiconductor device in which the storage layer 250 is formed on the dual selector layers. According to one embodiment of the disclosure, the amorphous silicon layer containing the first and / or second dopant as the first selector layer 225 and the second selector layer 235 can have to exist in an amorphous state in the final manufactured result of the semiconductor device. Generally, in the manufacture of a variable resistance storage element, a high-temperature process of about 400°C or higher can not be followed. Thus, in the semiconductor device of the final result manufactured according to one embodiment of the disclosure, the amorphous silicon layer as the dual selector can exist in an un-crystallized amorphous state. The semiconductor device according to the embodiment of the disclosure can be manufactured by the above-described processes.

[0060] Referring back to FIG. 4H The semiconductor device according to the embodiment of the disclosure can have a structure including a substrate 200, a first electrode layer 210 on the substrate 200, a first selector layer 225, an interface layer 221, and a second selector layer 235 sequentially stacked on the first electrode layer 210, to produce a stack of the substrate 200, the first electrode layer 210, and the first selector layer 225, the interface layer 221, and the second selector layer 235. The structure can further include a second electrode layer 240 and a storage layer 250 sequentially stacked on the stack of the substrate 200, the first electrode layer 210, the first selector layer 225, the interface layer 221, and the second selector layer 235.

[0061] FIG. 5A to FIG. 5H This is a cross-sectional view illustrating a method for manufacturing a semiconductor device in which a memory layer 250 is formed on the underside of a dual selector layer, according to another embodiment of the present disclosure. FIG. 5A to FIG. 5H The method for manufacturing semiconductor devices shown can be compared with... FIG. 4A to FIG. 4H The method for manufacturing semiconductor devices shown is similar, except that the memory layer 250 is formed below the dual selector layer. For... FIG. 4A to FIG. 4H The similar portions of the embodiments shown in this disclosure will be omitted here in their detailed description.

[0062] Reference FIG. 5A A substrate 200 in which a predetermined lower structure is formed can be provided, and a first electrode layer 210 and a storage layer 250 can be sequentially formed on the substrate 200.

[0063] Subsequently, referring to FIG. 5B to FIG. 5D A second electrode layer 240 and an initial first selector layer 220 can be formed on top of the storage layer 250, and a second dopant, such as arsenic (As), can be implanted into the amorphous silicon layer containing the first dopant.

[0064] Subsequently, referring to FIG. 5E and FIG. 5F ,pass FIG. 5D The ion implantation process allows for the formation of a first selector layer 225 from an initial first selector layer 220, wherein a second dopant is ion implanted into an amorphous silicon layer containing the first dopant. Subsequently, with... FIG. 4C to FIG. 4F In the same manner shown, interface layer 221 can be deposited and initial second selector layer 230 can be formed.

[0065] Reference FIG. 5G The second selector layer 235 can be formed from the initial second selector layer 230 by an ion implantation process, wherein the second dopant is ion implanted into the amorphous silicon layer containing the first dopant.

[0066] Subsequently, referring to FIG. 5H This allows for the fabrication of semiconductor devices in which the memory layer 250 is formed beneath the dual selector layer. Semiconductor devices according to embodiments of this disclosure can be fabricated using the processes described above.

[0067] Return to reference FIG. 5HThe semiconductor device according to embodiments of this disclosure may have the following structure: including a substrate 200, a first electrode layer 210 on the substrate 200, a memory layer 250 and a second electrode layer sequentially stacked on the first electrode layer 210, to form a stack of substrate 200, first electrode layer 210, memory layer 250 and second electrode layer. A first selector layer 225, an interface layer 221 and a second selector layer 235 are also sequentially stacked on the stack of substrate 200, first electrode layer 210, memory layer 250 and second electrode layer.

[0068] According to embodiments of the present disclosure, a semiconductor device and a method for manufacturing the same can have improved selector characteristics by forming a dual selector layer in a memory cell.

[0069] While embodiments of the present disclosure have been described with respect to specific examples, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical concept and scope of the present disclosure as defined in the following claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: Multiple storage units, each of the storage units comprising: Storage layer; A first selector layer is formed in the upper or lower part of the storage layer to select the storage layer; A second selector layer is used to select the storage layer; and An interface layer is positioned between the first selector layer and the second selector layer. The first selector layer and the second selector layer include an amorphous silicon layer, the amorphous silicon layer comprising one or more dopants selected from the group consisting of elements of Group 13, Group 14 and Group 15 of the periodic table, and The interface layer is selected from the group consisting of silicon oxide, silicon carbonitride, silicon carbonitride, silicon nitride, tantalum nitride, titanium nitride, aluminum nitride, and hafnium nitride.

2. The semiconductor device according to claim 1, wherein, The dopant includes elements from group 13 of the periodic table.

3. The semiconductor device according to claim 1, wherein, The dopants include elements from Group 13 and Group 14 of the periodic table.

4. The semiconductor device according to claim 1, wherein, The dopants include elements from Group 13 and Group 15 of the periodic table.

5. The semiconductor device according to claim 1, wherein, The dopant includes boron (B).

6. The semiconductor device according to claim 1, wherein, The dopant includes at least one of phosphorus (P) and arsenic (As), and boron (B).

7. The semiconductor device according to claim 1, wherein, The dopant includes at least one selected from the group consisting of carbon (C), silicon (Si), and germanium (Ge), and boron (B).

8. The semiconductor device according to claim 1, wherein, The concentration of the dopant in the doped amorphous silicon layer is about 10 wt% to 30 wt%.

9. The semiconductor device according to claim 1, wherein, The storage unit further includes: A first electrode layer is disposed below the first selector layer or the second selector layer; and A second electrode layer is disposed above the first selector layer or the second selector layer.

10. The semiconductor device according to claim 9, wherein, The first electrode layer and the second electrode layer comprise a thin TiN layer.

11. The semiconductor device according to claim 9, further comprising: A SiN thin layer is located at the interface between the first electrode layer and the first selector layer or the second selector layer; as well as A thin layer of carbon C is located at the interface between the first selector layer or the second selector layer and the second electrode layer.

12. A method for manufacturing a semiconductor device, the semiconductor device including a first selector layer and a second selector layer in a memory cell to control electrical access to one of a plurality of memory cells arranged in an array, the method comprising: An amorphous silicon layer containing dopants is formed on the substrate as the first selector layer; An interface layer is deposited on the first selector layer, the material of which is selected from the group consisting of silicon oxide, silicon carbonitride, silicon carbonitride oxycarbonate, silicon nitride, tantalum nitride, titanium nitride, aluminum nitride and hafnium nitride. An amorphous silicon layer containing dopants is formed on the interface layer as the second selector layer; and Heat treatment is performed at a temperature equal to or lower than the temperature at which the amorphous silicon layer crystallizes.

13. The method according to claim 12, wherein, Forming the amorphous silicon layer includes: An amorphous silicon layer doped with a first dopant is deposited.

14. The method according to claim 13, wherein, The concentration of the first dopant in the doped amorphous silicon layer is about 10 wt% to 30 wt%.

15. The method of claim 12, further comprising: An electrode layer is formed on top of the second selector layer.

16. The method according to claim 12, wherein, Forming the amorphous silicon layer includes: Deposited amorphous silicon layer doped with a first dopant; and The second dopant ions are implanted into the amorphous silicon layer doped with the first dopant.

17. The method according to claim 16, wherein, The first dopant includes elements from group 13 of the periodic table, and The second dopant includes a Group 14 or Group 15 element of the periodic table.

18. The method according to claim 16, wherein, The first dopant includes boron (B), and The second dopant includes at least one selected from the group consisting of carbon (C), silicon (Si), germanium (Ge), phosphorus (P), and arsenic (As).

19. The method according to claim 12, wherein, The heat treatment is performed at a temperature of about 400°C or lower.

20. The method according to claim 13, wherein, The deposition of the amorphous silicon layer containing the first dopant is performed using a low-pressure chemical vapor deposition (LPCVD) process with SiH4 and diborane (B2H6).

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