Amplifier arrangement with duplexer circuit

Abstract

An amplifier device and a duplexer circuit. The amplifier device includes a first differential amplification circuit and a controller. The first differential amplification circuit includes first and second radio frequency input terminals, first and second transistors, first and second adjustable capacitance circuits, and first and second radio frequency output terminals. The controller adjusts capacitance values of the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit based on at least one of a characteristic related to a first radio frequency input signal of the first differential amplification circuit, a characteristic related to a second radio frequency input signal of the first differential amplification circuit, a mismatch error between the first transistor and the second transistor of the first differential amplification circuit, and a characteristic of the amplifier device.

Description

Technical Field

[0001] This invention relates to a circuit structure for a wireless communication system, and more particularly to an amplifier device and a multiplexer circuit. Background Technology

[0002] With the increasing prevalence of wireless communication devices using dual-ended / differential antennas, radio frequency (RF) amplifiers designed to match these antennas are under research and development. However, RF amplifiers with dual-ended / differential circuit topologies suffer from issues such as matching errors between transistor differential pairs and signal power loss. Therefore, mitigating these problems remains a key area of ​​research in the field of wireless communication. Summary of the Invention

[0003] The amplifier device of the present invention includes a first differential amplifier circuit and a controller. The first differential amplifier circuit includes a first RF input terminal, a second RF input terminal, a first transistor, a second transistor, a first adjustable capacitor circuit, a second adjustable capacitor circuit, a first RF output terminal, and a second RF output terminal. The first RF input terminal is used to input a first RF input signal. The second RF input terminal is used to input a second RF input signal. The first transistor has a first terminal and a control terminal coupled to the first RF input terminal, wherein the control terminal obtains the first RF input signal through the first RF input terminal, the first transistor amplifies the first RF input signal, and generates a first amplified RF signal at the first terminal. The second transistor has a first terminal and a control terminal coupled to the second RF input terminal, wherein the control terminal obtains the second RF input signal through the second RF input terminal, the second transistor amplifies the second RF input signal, and generates a second amplified RF signal at the first terminal. The first adjustable capacitor circuit is coupled between the control terminal of the first transistor and the first terminal of the second transistor to couple the first RF input signal to the first terminal of the second transistor. A second adjustable capacitor circuit is coupled between the control terminal of the second transistor and the first terminal of the first transistor to couple the second RF input signal to the first terminal of the first transistor. A first RF output terminal is coupled to the first terminal of the first transistor to output a first RF output signal. A second RF output terminal is coupled to the first terminal of the second transistor to output a second RF output signal. The first amplified RF signal and the coupled second RF input signal are combined to form the first RF output signal, and the second amplified RF signal and the coupled first RF input signal are combined to form the second RF output signal. The controller is coupled to the first adjustable capacitor circuit and the second adjustable capacitor circuit of the first differential amplifier circuit, and is used to adjust the capacitance values ​​of the first adjustable capacitor circuit and the second adjustable capacitor circuit of the first differential amplifier circuit according to at least one of the characteristics related to the first radio frequency input signal of the first differential amplifier circuit, the characteristics related to the second radio frequency input signal of the first differential amplifier circuit, the matching error between the first transistor and the second transistor of the first differential amplifier circuit, and the characteristics of the amplifier device.

[0004] The amplifier device of the present invention includes a first differential amplifier circuit. The first differential amplifier circuit includes a first radio frequency (RF) input terminal, a second RF input terminal, a first transistor, a second transistor, a first adjustable capacitor circuit, and a second adjustable capacitor circuit. The first RF input terminal is used to input a first RF input signal. The second RF input terminal is used to input a second RF input signal. The control terminal of the first transistor receives the first RF input signal through the first RF input terminal, amplifies the first RF input signal, and generates a first amplified RF signal at its first terminal. The control terminal of the second transistor receives the second RF input signal through the second RF input terminal, amplifies the second RF input signal, and generates a second amplified RF signal at its first terminal. The first terminal of the first adjustable capacitor circuit is coupled to the control terminal of the first transistor to receive a first voltage, and its second terminal is coupled to the first terminal of the second transistor to receive a second voltage. The first adjustable capacitor circuit is used to couple the first RF input signal to the first terminal of the second transistor. The capacitance value of the first adjustable capacitor circuit is controlled by the first voltage and the second voltage. The first terminal of the second adjustable capacitor circuit is coupled to the control terminal of the second transistor to receive a third voltage, and its second terminal is coupled to the first terminal of the first transistor to receive a fourth voltage. The second adjustable capacitor circuit is used to couple the second RF input signal to the first terminal of the first transistor, and the capacitance value of the second adjustable capacitor circuit is controlled by the third voltage and the fourth voltage. The first amplified RF signal and the coupled second RF input signal are combined to form a first RF output signal, and the second amplified RF signal and the coupled first RF input signal are combined to form a second RF output signal. The first voltage is related to the first RF input signal, the second voltage is related to the second RF output signal, the third voltage is related to the second RF input signal, and the fourth voltage is related to the first RF output signal.

[0005] The duplexer circuit of the present invention is coupled to an antenna. The duplexer circuit includes a duplexer, a power amplifier, a low-noise amplifier, and an amplifier device. The duplexer includes an antenna terminal, a signal transmitting terminal, and a signal receiving terminal. The power amplifier is coupled to the signal receiving terminal of the duplexer. The low-noise amplifier is coupled to the signal transmitting terminal of the duplexer. The amplifier device is disposed on the power amplifier or the low-noise amplifier. The amplifier device includes a first differential amplifier circuit. The first differential amplifier circuit includes a first RF input terminal, a second RF input terminal, a first transistor, a second transistor, a first adjustable capacitor circuit, and a second adjustable capacitor circuit. The first RF input terminal is used to input a first RF input signal. The second RF input terminal is used to input a second RF input signal. The first transistor has a first terminal and a control terminal coupled to the first RF input terminal, wherein the control terminal obtains the first RF input signal through the first RF input terminal, the first transistor amplifies the first RF input signal, and generates a first amplified RF signal at the first terminal. The second transistor has a first terminal and a control terminal coupled to the second RF input terminal, wherein the control terminal obtains the second RF input signal through the second RF input terminal, and the second transistor amplifies the second RF input signal and generates a second amplified RF signal at the first terminal. A first adjustable capacitor circuit is coupled between the control terminal of the first transistor and the first terminal of the second transistor to couple the first RF input signal to the first terminal of the second transistor. A second adjustable capacitor circuit is coupled between the control terminal of the second transistor and the first terminal of the first transistor to couple the second RF input signal to the first terminal of the first transistor. A first RF output terminal is coupled to the first terminal of the first transistor to output a first RF output signal. A second RF output terminal is coupled to the first terminal of the second transistor to output a second RF output signal. The first amplified RF signal and the coupled second RF input signal are combined to form the first RF output signal, and the second amplified RF signal and the coupled first RF input signal are combined to form the second RF output signal. The controller is coupled to the first adjustable capacitor circuit and the second adjustable capacitor circuit of the first differential amplifier circuit, and is used to adjust the capacitance values ​​of the first adjustable capacitor circuit and the second adjustable capacitor circuit of the first differential amplifier circuit according to at least one of the characteristics related to the first radio frequency input signal of the first differential amplifier circuit, the characteristics related to the second radio frequency input signal of the first differential amplifier circuit, the matching error between the first transistor and the second transistor of the first differential amplifier circuit, and the characteristics of the amplifier device. Attached Figure Description

[0006] Figure 1 A circuit diagram of an amplifier device according to a first embodiment of the present invention is shown.

[0007] Figure 2 A circuit diagram of an amplifier device according to a second embodiment of the present invention is shown.

[0008] Figure 3 A circuit diagram of an amplifier device according to a third embodiment of the present invention is shown.

[0009] Figure 4 A first circuit structure diagram of the adjustable capacitor circuit in various embodiments of the present invention is shown.

[0010] Figure 5 A second circuit structure diagram of the adjustable capacitor circuit in various embodiments of the present invention is shown.

[0011] Figure 6 A cross-sectional schematic diagram of a capacitor transistor TCX in one embodiment of the present invention is shown.

[0012] Figure 7 A circuit diagram of an amplifier device according to a fourth embodiment of the present invention is shown.

[0013] Figure 8 A block diagram illustrating the duplexer circuit in various embodiments of the present invention is shown.

[0014] Main illustrations :

[0015] 100, 200, 300, 600: Amplifier devices

[0016] 110-1~110-N: Differential amplifier circuit

[0017] 120, 220, 320: Controller

[0018] 231, 232: Through-hole wafers

[0019] 610: Well Area

[0020] 620-1, 620-2: Heavily doped regions

[0021] 630: Dielectric layer

[0022] 640: Gate material layer

[0023] 700: Duplexer Circuit

[0024] 710: Antenna

[0025] 720: Duplexer

[0026] 730: Power Amplifier

[0027] 740: Low Noise Amplifier

[0028] T11~TN1, T12~TN2, T21, T22, Tn1, Tn2, T410: Transistors

[0029] CX11~CXN1, CX12~CXN2, CXn3, CXN3, CXn4, CXN4, CX11-1, CX11-2, CX12-2, TCX: Adjustable capacitor circuit

[0030] RFin11, RFin12, RFin21, RFin22: Radio frequency input terminals

[0031] RFamp11, RFamp12: Amplify radio frequency signals

[0032] RFout11, RFout12, RFout21, RFout22: RF output terminals

[0033] CN11, CN12, CN21, CN22: Control terminals of the transistor

[0034] DN11, DN12, DN21, DN22: The first terminal of the transistor

[0035] SN11, SN12, SN21, SN22: The second terminal of the transistor

[0036] VREF: Reference voltage terminal

[0037] C1, C2: Capacitors

[0038] R1, R2: Resistors

[0039] G: Gate terminal of transistor

[0040] D: Drain terminal of the transistor

[0041] S: Source terminal of transistor

[0042] V1~V4: Voltage

[0043] RC1, RC2: Resistor-capacitor circuit

[0044] TXN: Signal Transmission End

[0045] RXN: Signal receiver Detailed Implementation

[0046] Figure 1A circuit diagram illustrating an amplifier device 100 according to a first embodiment of the present invention is shown. The amplifier device 100 of this embodiment can be applied to a duplexer circuit in a wireless communication system. The amplifier device 100 can serve as a low-noise amplifier (LNA) in a duplexer circuit for receiving antenna signals. The amplifier device 100 can also serve as a power amplifier (PA) in a duplexer circuit for transmitting antenna signals. This embodiment can also be applied to amplifier circuits in other technical fields as needed.

[0047] Amplifier device 100 includes a differential amplifier circuit 110-1 and a controller 120. The differential amplifier circuit 110-1 includes RF input terminals RFin11 and RFin12, transistors T11 and T12, adjustable capacitor circuits CX11 and CX12, and RF output terminals RFout111 and RFout112. RF input terminal RFin11 is used to input the RF input signal Sin11, and RF input terminal RFin12 is used to input the RF input signal Sin12. The differential amplifier circuit 110-1 in this embodiment can also be referred to as a first-stage differential amplifier circuit.

[0048] Transistor T11 has a first terminal DN11 (e.g., the drain terminal of transistor T11) and a control terminal CN11 (e.g., the gate terminal of transistor T11). The control terminal CN11 is coupled to the RF input terminal RFin11. The control terminal CN11 obtains the RF input signal Sin11 through the RF input terminal RFin11. Transistor T11 amplifies the RF input signal Sin11 and generates an amplified RF signal RFamp11 at its first terminal DN1. Transistor T12 has a first terminal DN12 (e.g., the drain terminal of transistor T12) and a control terminal CN12 (e.g., the gate terminal of transistor T12). The control terminal CN12 is coupled to the RF input terminal RFin12. The control terminal CN12 obtains the RF input signal Sin12 through the RF input terminal RFin12. Transistor T12 amplifies the RF input signal Sin12 and generates an amplified RF signal RFamp12 at its first terminal DN12.

[0049] Adjustable capacitor circuit CX11 is coupled between the control terminal CN11 of transistor T11 and the first terminal DN12 of transistor T12 to couple the RF input signal Sin11 to the first terminal DN12 of transistor T12. Adjustable capacitor circuit CX12 is coupled between the control terminal CN12 of transistor T12 and the first terminal DN11 of transistor T11 to couple the RF input signal Sin12 to the first terminal DN11 of transistor T11. RF output terminal RFout11 is coupled to the first terminal DN11 of transistor T11 to output the RF output signal Sout11. RF output terminal RFout12 is coupled to the first terminal DN12 of transistor T12 to output the RF output signal Sout12. The amplified RF signal RFamp11 and the coupled RF input signal Sin12 are combined to form the RF output signal Sout11, and the amplified RF signal RFamp12 and the coupled RF input signal Sin11 are combined to form the RF output signal Sout12.

[0050] In the differential amplifier circuit 110-1 of this embodiment, the radio frequency input signals Sin11 and Sin12 are out of phase, the radio frequency input signal Sin11 and the amplified radio frequency signal RFamp11 are out of phase, and the radio frequency input signal Sin12 and the amplified radio frequency signal RFamp12 are out of phase.

[0051] Amplifier device 100 is used to input an input signal Sin and output an output signal Sout. The radio frequency input signals Sin11 and Sin12 are generated from the input signal Sin, and the output signal Sout is generated from the radio frequency output signals Sout11 and Sout12. In other words, amplifier device 100 is a differential amplifier circuit, where the input signal Sin is divided into two input signals Sin11 and Sin12, and the output signal Sout is also composed of the two radio frequency output signals Sout11 and Sout12.

[0052] Adjustable capacitor circuits CX11 and CX12 are mainly used to at least partially cancel the parasitic capacitance between the control terminal CN11 and the first terminal DN11 of transistor T11, and at least partially cancel the parasitic capacitance between the control terminal CN12 and the first terminal DN12 of transistor T12. By reducing / canceling the parasitic capacitance between the control terminals and the first terminals of transistors T11 and T12, the power gain, gain linearity (e.g., second-order intercept point (IIP2), third-order intercept point (IIP3), error vector magnitude (EVM), adjacent channel leakage ratio (ACLR), etc.), and the matching error of the differential pair in the semiconductor process can be improved in the differential amplifier circuit 110-1.

[0053] In this embodiment, the controller 120 is coupled to the adjustable capacitor circuits CX11 and CX12 of the differential amplifier circuit 110-1. The controller 120 adjusts the capacitance values ​​of the adjustable capacitor circuits CX11 and CX12 of the differential amplifier circuit 110-1 based on at least one of the characteristics related to the radio frequency input signal Sin11 of the differential amplifier circuit 110-1, the characteristics related to the radio frequency input signal Sin12 of the differential amplifier circuit 110-1, the matching error between transistors T11 and T12 of the differential amplifier circuit 110-1, and the characteristics of the amplifier device 100.

[0054] For example, the characteristics of the aforementioned amplifier device 100 may include the signal amplification linearity of the amplifier device 100. Specifically, the controller 120 may adjust the capacitance values ​​in the adjustable capacitor circuits CX11 and CX12 based on the second-order intercept point (IIP2) related to the signal amplification linearity of the amplifier device 100. The characteristics of the aforementioned amplifier device 100 may also include the operating current of the amplifier device 100 during current operation and the current power gain of the amplifier device 100.

[0055] For example, characteristics related to the RF input signal Sin11 could be: the frequency of the RF input signal Sin11, the frequency of the RF output signal Sout11, the power of the RF input signal Sin11, or the power of the RF output signal Sout11. Characteristics related to the RF input signal Sin12 could be: the frequency of the RF input signal Sin12, the frequency of the RF output signal Sout12, the power of the RF input signal Sin12, or the power of the RF output signal Sout12.

[0056] In various embodiments of the present invention, the controller may be additionally coupled to appropriate conventional detection circuits such as process error detection circuit, current detection circuit, power detection circuit, frequency detection circuit, etc., to obtain relevant characteristic parameters such as characteristics and / or matching errors related to various radio frequency signals in various embodiments of the present invention, which can be used as the basis for adjusting the capacitance value of each adjustable capacitor circuit.

[0057] In this embodiment, the controller 120 can adjust the capacitance value in the adjustable capacitor circuits CX11 or CX12 in various ways. For example, the controller 120 can use a lookup table, based on one or more of the aforementioned characteristics (e.g., characteristics related to the RF input signal Sin11 of the differential amplifier circuit 110-1, characteristics related to the RF input signal Sin12 of the differential amplifier circuit 110-1, the matching error between transistors T11 and T12 of the differential amplifier circuit 110-1, and at least one or a combination of the characteristics of the amplifier device 100) as input, to find the corresponding capacitance value in the adjustable capacitor circuits CX11 or CX12 in the lookup table, and adjust the capacitance value in the adjustable capacitor circuits CX11 or CX12 in a digital or analog control manner. In this embodiment, the power gain of the amplifier circuit 100 can be improved by adjusting the adjustable capacitor circuits CX11 and CX12 through circuit design. However, since the value of the parasitic capacitance in the amplifier circuit 100 is not necessarily linear, but may have different values ​​under different conditions, this embodiment is designed to use the controller 120 or other means to adaptively adjust the capacitance values ​​of the adjustable capacitor circuits CX11 and CX12 according to one or more of the aforementioned characteristics, thereby improving the function of the amplifier circuit 100, such as improving power gain, improving gain linearity, balancing the matching error of the differential pair, etc.

[0058] The second terminal SN11 of transistor T11 (e.g., the source terminal of transistor T11) and the second terminal SN12 of transistor T12 (e.g., the source terminal of transistor T12) are coupled to the reference voltage terminal VREF. In this embodiment, the reference voltage terminal VREF can be a common terminal or a ground terminal, and users of this embodiment can adjust the voltage value of this reference voltage terminal according to their needs.

[0059] In this embodiment, the components in the amplifier device 100 can be made of group III-V compound materials, such as gallium arsenide (GaAs) or gallium nitride (GaN). Furthermore, the amplifier device 100 is manufactured using high electron mobility transistor (HEMT) technology. Users of this embodiment can, according to their needs and current technology, use other materials to manufacture the components in the amplifier device 100, for example, using silicon and corresponding semiconductor processes.

[0060] Figure 2 A circuit diagram illustrating an amplifier device 200 according to a second embodiment of the present invention is shown. First embodiment ( Figure 1 ) and the second embodiment ( Figure 2 The main difference between them is that, Figure 2In addition to the first-stage differential amplifier circuit (differential amplifier circuit 110-1), a second-stage differential amplifier circuit (i.e., differential amplifier circuit 110-2) is also included. Similar to the circuit structure of differential amplifier circuit 110-1, differential amplifier circuit 110-2 includes RF input terminals RFin21 and RFin22, transistors T21 and T22, adjustable capacitor circuits CX21 and CX22, and RF output terminals RFout21 and RFout22. In other words, the amplifier device 200 has a two-stage differential amplifier circuit.

[0061] The RF input terminal RFin21 is coupled to the RF output terminal RFout11 of the differential amplifier circuit 110-1, and is used to input the RF input signal Sin21 (i.e., the RF output signal Sout11 of the differential amplifier circuit 110-1). The RF input terminal RFin22 is coupled to the RF output terminal RFout12 of the differential amplifier circuit 110-1, and is used to input the RF input signal Sin22 (i.e., the RF output signal Sout12 of the differential amplifier circuit 110-1). Transistor T21 has a first terminal DN21, a second terminal SN21, and a control terminal CN21, and the second terminal SN21 is coupled to the RF input terminal RFin21. Transistor T22 has a first terminal DN22, a second terminal SN22, and a control terminal CN22, and the second terminal SN22 is coupled to the RF input terminal RFin22. The adjustable capacitor circuit CX21 is coupled between the control terminal CN21 of transistor T21 and the first terminal DN22 of transistor T22. The adjustable capacitor circuit CX22 is coupled between the control terminal CN22 of transistor T22 and the first terminal DN21 of transistor T21. The RF output terminal RFout21 is coupled to the first terminal DN21 of transistor T21 to output the RF output signal Sout21. The RF output terminal RFout22 is coupled to the first terminal DN22 of transistor T22 to output the RF output signal Sout22.

[0062] In addition to having Figure 1 In addition to its original functions, the controller 220 can also be coupled to the adjustable capacitor circuits CX21 and CX22 of the differential amplifier circuit 110-2. The controller 220 is also used to adjust the capacitance values ​​of the adjustable capacitor circuits CX21 and CX22 of the differential amplifier circuit 110-2 based on at least one of the characteristics related to the RF input signal Sin21 of the differential amplifier circuit 110-2, the characteristics related to the RF input signal Sin22, the matching error between transistors T21 and T22 of the differential amplifier circuit 110-2, and the characteristics of the amplifier device 200.

[0063] For example, a characteristic related to the RF input signal Sin21 could be the power of the RF input signal Sin21 or the power of the RF output signal Sout21. A characteristic related to the RF input signal Sin22 could be the power of the RF input signal Sin22 or the power of the RF output signal Sout22.

[0064] For example, the characteristic of the amplifier device can be the signal amplification linearity of amplifier device 200. Controller 220 is used to adjust the capacitance values ​​of adjustable capacitor circuits CX11 and CX22 of differential amplifier circuit 110-1 based on characteristics related to the RF input signal Sin21 or Sin22. Similarly, controller 200 is used to adjust the capacitance values ​​of adjustable capacitor circuits CX11 and CX12 of differential amplifier circuit 110-2 based on the characteristics of amplifier device 200.

[0065] The differential amplifier circuit 110-2 may also optionally include adjustable capacitor circuits CX23 and CX24. Adjustable capacitor circuit CX23 is coupled between the control terminal CN21 of transistor T21 and the reference voltage terminal (e.g., VREF). Adjustable capacitor circuit CX24 is coupled between the control terminal CN22 of transistor T22 and the reference voltage terminal (e.g., VREF).

[0066] The controller 220 is also coupled to the adjustable capacitor circuits CX23 and CX24 of the differential amplifier circuit 110-2. The controller 220 is also used to adjust the capacitance values ​​of the adjustable capacitor circuits CX23 and CX24 of the differential amplifier circuit 110-2 according to at least one of the characteristics related to the RF input signal RFin21 of the differential amplifier circuit 110-2, the characteristics related to the RF input signal RFin22 of the differential amplifier circuit 110-2, the matching error between the transistors T21 and T22 of the differential amplifier circuit 110-2, and the characteristics of the amplifier device 200.

[0067] The differential amplifier circuits 110-1 to 110-2 in this embodiment can adjust the adjustable capacitor circuits for different purposes. For example, the adjustable capacitor circuits CX11 and CX12 in differential amplifier circuit 110-1 can be used to adjust the overall power gain of amplifier circuit 200; the adjustable capacitor circuits CX21 and CX22 in differential amplifier circuit 110-2 are used to adjust the linearity of amplifier circuit 200. Users of this embodiment can adjust the capacitance values ​​of the adjustable capacitor circuits in differential amplifier circuits 110-1 to 110-2 using controller 220 according to their needs and different purposes.

[0068] To reduce the adverse effects of the parasitic capacitance to ground of transistors T11 and T12, the second terminals SN11 and SN12 of transistors T11 and T12 in the differential amplifier circuit 110-1 of this embodiment can be coupled to the reference voltage terminal VREF through through-wafer vias 231 and 232, respectively. Figure 1 and Figure 2 As shown.

[0069] Figure 3 A circuit diagram illustrating the amplifier device 300 according to a third embodiment of the present invention is shown. Second embodiment ( Figure 2 ) and the third embodiment ( Figure 3 The main difference between them is that, Figure 3 In addition to the first-stage differential amplifier circuit (differential amplifier circuit 110-1), it also includes multiple stages of differential amplifier circuits, such as an nth-stage differential amplifier circuit (i.e., differential amplifier circuit 110-n) and an Nth-stage differential amplifier circuit (i.e., differential amplifier circuit 110-N) as the last stage. In this embodiment, N is a positive integer greater than or equal to 3, and n is a positive integer greater than or equal to 2 and less than or equal to N. Figure 3 The circuit structures of the intermediate differential amplifier circuit 110-n and the differential amplifier circuit 110-N are similar. Figure 2 The circuit structure of the differential amplifier circuit 110-2 is the same, and will not be described again here. However, when N equals 2, the amplifier device 300 is essentially the same as... Figure 2 The circuit structure of the amplifier device 200 is the same.

[0070] The first and second RF input terminals of the nth differential amplifier circuit 110-n are respectively coupled to the first and second RF output terminals of the (n-1)th differential amplifier circuit 110-(n-1). The controller 320 is also coupled to the adjustable capacitor circuits CX(n-1)1 and CX(n-1)2 of the (n-1)th differential amplifier circuit 110-(n-1). The controller 320 is also used to adjust the capacitance values ​​of the adjustable capacitor circuits CX(n-1)1 and CX(n-1)2 of the (n-1)th differential amplifier circuit 110-(n-1) according to at least one of the characteristics related to the first RF input signal of the (n-1)th differential amplifier circuit, the characteristics related to the second RF input signal of the (n-1)th differential amplifier circuit, the matching error between transistors T(n-1)1 and T(n-1)2 of the (n-1)th differential amplifier circuit, and the characteristics of the amplifier device 300.

[0071] For example, the controller 320 is used to adjust the capacitance values ​​of the adjustable capacitor circuits CXn1 and CXn2 of the nth differential amplifier circuit according to the signal amplification linearity of the amplifier device 300.

[0072] In this embodiment, the differential amplifier circuits 110-1 to 110-N can be used to adjust the adjustable capacitor circuits of different stages of the differential amplifier circuit for different purposes. For example, assuming that the amplifier circuit 300 has a fourth-order differential amplifier circuit (i.e., N=4), the first-order differential amplifier circuit 110-1 can be used to adjust the overall power gain of the amplifier circuit 300; the second-order differential amplifier circuit 110-2 can be used to adjust the RF signal reliability of the amplifier circuit 300; the third-order differential amplifier circuit 110-3 can be used to adjust the DC power stability of the amplifier circuit 300; and the fourth-order differential amplifier circuit 110-4 is used to adjust the linearity of the amplifier circuit 300. Users of this embodiment can adjust the capacitance value of the adjustable capacitor circuit in each stage of the differential amplifier circuit according to their needs and different purposes.

[0073] Figure 4 A first circuit structure diagram of the adjustable capacitor circuit CX11-1 in various embodiments of the present invention is shown. The adjustable capacitor circuits in the foregoing embodiments (e.g., adjustable capacitor circuits CX11-CXN1, CX12-CXN2, CXn3, CX4) can be transmitted through... Figure 4 This is achieved using the adjustable capacitor circuit CX11-1 described above. Figure 4 The adjustable capacitor circuit CX11-1 mainly includes capacitor C1, capacitive coupling switch 410, and capacitor C2. The first terminal of capacitor C1 is coupled to one end of the adjustable capacitor circuit CX11-1 (e.g., coupled to the control terminal CN11 of transistor T11). The second terminal of capacitor C1 is coupled to the first terminal N410-1 of capacitive coupling switch 410. Capacitive coupling switch 410 is controlled by a controller (e.g., ...). Figure 1 The controller 120 changes its on state or its off state. The first terminal of capacitor C2 is coupled to the second terminal N410-2 of capacitor-coupled switch 410.

[0074] The capacitive coupling switch 410 may include a transistor T410, whose control terminal G is controlled by a controller. In this embodiment, when the transistor T410 in the capacitive coupling switch 410 is turned off by the controller, the control terminal CN11 of transistor T11 and the first terminal DN12 of transistor T12 have a capacitance value equal to the sum of capacitor C1, the cutoff capacitor Coff in the capacitive coupling switch 410, and capacitor C2. When the transistor T410 in the capacitive coupling switch 410 is turned on by the controller, the control terminal CN11 of transistor T11 and the first terminal DN12 of transistor T12 have a capacitance value equal to the sum of capacitor C1 and capacitor C2. Furthermore, the controller can change the capacitance value of the cutoff capacitor Coff in the capacitive coupling switch 410 by controlling the voltage value on the control terminal G. The equivalent capacitance value of the adjustable capacitor circuit CX11-1 can be controlled digitally or analogfully. For example, the transistor T410 in the capacitive coupling switch 410 can be digitally controlled by the controller to turn its terminals on or off, while the transistor T410 in the capacitive coupling switch 410 can be analog controlled by the controller to change the voltage value at the control terminal G, thereby continuously changing the capacitance value of the cutoff capacitor Coff in the capacitive coupling switch 410. In other embodiments of the present invention, capacitors C1 and C2 may also be omitted.

[0075] Figure 4 The capacitively coupled switch 410 may also include control voltage terminals V1 and V2, and resistors R1 and R2 respectively coupled to the control voltage terminals V1 and V2. Control voltage terminal V1 is connected to the first terminal of transistor T410 in the capacitively coupled switch 410 through resistor R1, and control voltage terminal V2 is connected to the second terminal of transistor T410 in the capacitively coupled switch 410 through resistor R2. Therefore, in this embodiment, the controller can not only change the capacitance value of the cutoff capacitor Coff in the capacitively coupled switch 410 by controlling the voltage value at the control terminal G, but also change the capacitance value of the cutoff capacitor Coff in the capacitively coupled switch 410 by adjusting the voltages at the control voltage terminals V1 and V2.

[0076] The capacitive coupling switch 410 can also automatically adjust its on or off state without the control of the controller. For example, when the power of the RF output signal Sout11 or Sout12 is higher than a preset power value, the aforementioned capacitive coupling switch 410 will automatically turn on or be turned on by the controller; when the power of the RF output signal Sout11 or Sout12 is lower than the preset power value, the aforementioned capacitive coupling switch 410 will automatically turn off or be turned off by the controller.

[0077] In this embodiment, the voltage value within the adjustable capacitor circuit CX11-1 can also be adjusted using voltages V1 and V2. This adjustment can be achieved automatically using logic circuits or other automatic control technologies instead of a controller, utilizing voltages V1 and V2. For example, Figure 4 Voltages V1 and V2 can be used to adjust the voltage values ​​within the adjustable capacitor circuit CX11-1, and voltages V3 and V4 can be used to adjust the voltage values ​​within the adjustable capacitor circuit CX12. In this embodiment, the voltage values ​​of V1, V2, V3, and V4 are all related to the RF input signal Sin11 and the RF output signal Sout12, respectively. This allows the differential amplifier circuit to adjust the voltage values ​​within the adjustable capacitor circuits CX11-1 and CX12 using V1-V4. The adjustable capacitor circuit CX12 can also be implemented using the same or a similar circuit architecture as the adjustable capacitor circuit CX11-1.

[0078] Figure 5 A second circuit structure diagram of the adjustable capacitor circuits CX11-2 and CX12-2 in various embodiments of the present invention is shown. The adjustable capacitor circuits in the aforementioned embodiments (e.g., adjustable capacitor circuits CX11-CXN1, CX12-CXN2, CXn3, CX4) can be... Figure 5 This is achieved using the adjustable capacitor circuits CX11-2 and CX12-2 described above. Figure 5 The adjustable capacitor circuit CX11-2 mainly includes a capacitor transistor TCX11. The control terminal (e.g., gate terminal G) of transistor TCX11 serves as one of the first and second terminals of the adjustable capacitor circuit CX11-2, for example, the first terminal. The first terminal (e.g., source terminal S) and the second terminal (e.g., drain terminal D) of transistor TCX11 are interconnected to serve as the other of the first and second terminals of the adjustable capacitor circuit CX11-2, for example, the second terminal, and are also connected to the RF input terminal RFin11. In this way, transistor TCX11 can be considered as a diode with a capacitance value. The RF input signal Sin11 in the RF input terminal RFin11 can be coupled to the first terminal DN12 of transistor T12 through transistor TCX11. The adjustable capacitor circuit CX11-2 also includes a resistor-capacitor circuit RC1, coupled between the first terminal (source terminal S) of capacitor transistor TCX11 and the second terminal of the adjustable capacitor circuit CX11-2, to increase bandwidth. The resistor-capacitor circuit RC1 includes, for example, a resistor and a capacitor connected in series.

[0079] Figure 5The adjustable capacitor circuit CX12-2 mainly includes a transistor TCX12. The gate G of transistor TCX12 is connected to the first terminal DN11 of transistor T11. The source terminal S and drain terminal D of transistor TCX12 are interconnected and also connected to the RF input terminal RFin12. In this way, transistor TCX12 can be regarded as a diode with capacitance. The RF input signal Sin12 in the RF input terminal RFin12 can be coupled to the first terminal DN11 of transistor T11 through transistor TCX12. The adjustable capacitor circuit CX12-2 also includes a resistor-capacitor circuit RC2, which is coupled between the first terminal (source terminal S) of capacitor transistor TCX12 and the second terminal of adjustable capacitor circuit CX12-2 to increase bandwidth. In this embodiment, by changing the voltage difference across capacitor transistors TCX11 and TCX12, the capacitance value of capacitor transistors TCX11 and TCX12 can be changed accordingly.

[0080] Those who apply this embodiment may also Figure 5 In this embodiment, the capacitor transistors TCX11 and TCX12 are replaced with appropriate diodes. The first terminal of the diode serves as the first terminal of the adjustable capacitor circuits CX11-2 and CX12-2, and the second terminal of the diode serves as the second terminal of the adjustable capacitor circuits CX11-2 and CX12-2. In other embodiments, the diode may also include a transistor connected in a diode configuration.

[0081] Figure 6 A cross-sectional schematic diagram of the capacitor transistor TCX is shown in one embodiment of the present invention. The adjustable capacitor circuits (e.g., adjustable capacitor circuits CX11-CXN1, CX12-CXN2, CXn3, CX4) in various embodiments of the present invention can be seen through… Figure 6 It is implemented using the capacitor transistor TCX described in the document. Figure 6The capacitor transistor TCX mainly includes a well region 610, two heavily doped regions 620-1 and 620-2 forming the source terminal S and drain terminal D, a dielectric layer 630, and a gate material layer 640. The dielectric layer 630 is disposed on the well region 610 and connects the two heavily doped regions 620-1 and 620-2. The gate material layer 640 is used to form the gate terminal G and is disposed on the dielectric layer 630. The source terminal S and the drain terminal D are interconnected. In this embodiment, the well region 610 may be a type I well region, such as an n-well; the heavily doped regions 620-1 and 620-2 may be type I heavily doped regions, such as n+; the dielectric layer 630 may be a gate oxide layer; and the gate material layer 640 may be a polysilicon gate. The first type well region 610 and the heavily doped regions 620-1 and 620-2 of the first type well region can also be p-well and p+, respectively. In this embodiment, since the well region 610 and the heavily doped regions 620-1 and 620-2 are all made of the same type of material, the capacitor transistor TCX can provide a better capacitance tuning range compared to embodiments where the well region 610 and the heavily doped regions 620-1 and 620-2 are made of different types of materials. For example, when the voltage difference across the capacitor transistor TCX (source terminal S / drain terminal D and gate terminal G) varies by 0.5V, other embodiments where the well region and the heavily doped region are made of different types of materials only provide a capacitance tuning range of about 0.1pF, but this embodiment where the well region and the heavily doped region are made of the same type of material can provide a capacitance tuning range of about 2.8pF.

[0082] Figure 7 A circuit diagram of the amplifier device 600 according to the fourth embodiment of the present invention is shown. The amplifier device 600 of the fourth embodiment and... Figure 2 The amplifier device 200 in the second embodiment is similar to that in the second embodiment, except that... Figure 7 The control terminal CN21 of transistor T21 in differential amplifier circuit 110-2 is also coupled to the control terminal CN12 of transistor T12 in differential amplifier circuit 110-1, and the control terminal CN22 of transistor T22 in differential amplifier circuit 110-2 is also coupled to the control terminal CN11 of transistor T11 in differential amplifier circuit 110-1. In this way, the signal amplified and output from the first terminal DN22 of transistor T22 in differential amplifier circuit 110-2 can be fed back to the control terminal CN12 of transistor T12 in differential amplifier circuit 110-1, and the signal amplified and output from the first terminal DN21 of transistor T21 in differential amplifier circuit 110-2 can also be fed back to the control terminal CN11 of transistor T11 in differential amplifier circuit 110-1, thereby increasing the signal amplification linearity of amplifier device 600.

[0083] Figure 8 A block diagram illustrating a duplexer circuit 700 in various embodiments of the present invention is shown. The duplexer circuit 700 is coupled to an antenna 710. The duplexer circuit 700 includes a duplexer 720, a power amplifier 730, and a low-noise amplifier 740. The duplexer 720 includes an antenna terminal AN1, a signal transmission terminal TXN, and a signal receiving terminal RXN. The power amplifier 730 is coupled to the signal transmission terminal TXN of the duplexer 720. The low-noise amplifier 740 is coupled to the signal receiving terminal RXN of the duplexer 720. The amplifier devices 100, 200, 300, and 600 described in the first to fourth embodiments can be disposed within the power amplifier 730 or the low-noise amplifier 740. In particular, amplifier devices 200, 300, and 600 having multi-stage differential amplifier circuits are more suitable for being disposed within the low-noise amplifier 740; amplifier device 100 is more suitable for being disposed within the power amplifier 730 or the low-noise amplifier 740. The detailed circuit structure and actuation method of amplifier devices 100, 200, 300, and 600 are described in the foregoing embodiments.

[0084] In summary, the amplifier device and duplexer circuit of this invention are implemented using one or more stages of differential amplifier circuits in conjunction with adjustable capacitor circuits located in each stage of the differential amplifier circuit. By adaptively adjusting the capacitance values ​​in the adjustable capacitor circuits, the amplifier device and duplexer circuit achieve better power gain, better signal conversion efficiency, higher reliability, increased manufacturing yield, and reduced cost. If multiple stages of differential amplifier circuits are provided, the adjustable capacitor circuits of different stages of the differential amplifier circuit can be adjusted separately for different purposes (e.g., power gain, gain linearity, differential pair matching error, second-order intercept point (IIP2), etc.). Furthermore, the components in the aforementioned amplifier device and duplexer circuit can be manufactured using III-V compound materials to enhance the performance of the amplifier device from a material perspective.

Claims

1. An amplifier arrangement, characterized by The amplifier device comprises: a first differential amplifier circuit comprising: a first radio frequency input terminal for inputting a first radio frequency input signal; a second radio frequency input terminal for inputting a second radio frequency input signal; a first transistor having a first terminal and a control terminal coupled to the first radio frequency input terminal, wherein the control terminal obtains the first radio frequency input signal through the first radio frequency input terminal, the first transistor amplifies the first radio frequency input signal and generates a first amplified radio frequency signal at the first terminal; a second transistor having a first terminal and a control terminal coupled to the second radio frequency input terminal, wherein the control terminal obtains the second radio frequency input signal through the second radio frequency input terminal, the second transistor amplifies the second radio frequency input signal and generates a second amplified radio frequency signal at the first terminal; a first adjustable capacitance circuit coupled between the control terminal of the first transistor and the first terminal of the second transistor for coupling the first radio frequency input signal to the first terminal of the second transistor; and a second adjustable capacitance circuit coupled between the control terminal of the second transistor and the first terminal of the first transistor for coupling the second radio frequency input signal to the first terminal of the first transistor; a first radio frequency output terminal coupled to the first terminal of the first transistor for outputting a first radio frequency output signal; and a second radio frequency output terminal coupled to the first terminal of the second transistor for outputting a second radio frequency output signal, wherein the first amplified radio frequency signal and the coupled second radio frequency input signal combine to become the first radio frequency output signal, and the second amplified radio frequency signal and the coupled first radio frequency input signal combine to become the second radio frequency output signal; and a controller coupled to the first adjustable capacitance circuit of the first differential amplifier circuit and the second adjustable capacitance circuit of the first differential amplifier circuit for adjusting capacitance values of the first adjustable capacitance circuit of the first differential amplifier circuit and the second adjustable capacitance circuit of the first differential amplifier circuit according to at least one of characteristics related to the first radio frequency input signal of the first differential amplifier circuit, characteristics related to the second radio frequency input signal of the first differential amplifier circuit, a mismatch error between the first transistor and the second transistor of the first differential amplifier circuit, and a characteristic of the amplifier device, the first adjustable capacitance circuit of the first differential amplifier circuit and the second adjustable capacitance circuit of the first differential amplifier circuit being used to at least partially cancel parasitic capacitances between the control terminal of the first transistor and the first terminal of the first transistor, and between the control terminal of the second transistor and the first terminal of the second transistor, respectively.

2. The amplifier arrangement of claim 1, wherein The characteristic of the amplifier device is signal amplification linearity of the amplifier device, and the controller adjusts the capacitance values in the first adjustable capacitance circuit and the second adjustable capacitance circuit according to a second order truncation point related to the signal amplification linearity of the amplifier device.

3. The amplifier arrangement of claim 1, wherein The characteristic of the amplifier device includes operating current of the amplifier device and gain of the amplifier device.

4. The amplifier arrangement of claim 1, wherein wherein the characteristic associated with the first radio frequency input signal is a frequency of the first radio frequency input signal, a frequency of the first radio frequency output signal, a power of the first radio frequency input signal, or a power of the first radio frequency output signal, and the characteristic associated with the second radio frequency input signal is a frequency of the second radio frequency input signal, a frequency of the second radio frequency output signal, a power of the second radio frequency input signal, or a power of the second radio frequency output signal.

5. The amplifier arrangement of claim 1, wherein wherein the components in the amplifier device are made of III-V compound materials.

6. An amplifier arrangement characterized by comprising: a first differential amplification circuit, comprising: a first radio frequency input terminal for inputting a first radio frequency input signal; a second radio frequency input terminal for inputting a second radio frequency input signal; a first transistor having a first terminal and a control terminal coupled to the first radio frequency input terminal, wherein the control terminal obtains the first radio frequency input signal through the first radio frequency input terminal, the first transistor amplifies the first radio frequency input signal and generates a first amplified radio frequency signal at the first terminal; a second transistor having a first terminal and a control terminal coupled to the second radio frequency input terminal, wherein the control terminal obtains the second radio frequency input signal through the second radio frequency input terminal, the second transistor amplifies the second radio frequency input signal and generates a second amplified radio frequency signal at the first terminal; a first adjustable capacitance circuit coupled between the control terminal of the first transistor and the first terminal of the second transistor for coupling the first radio frequency input signal to the first terminal of the second transistor; and a second adjustable capacitance circuit coupled between the control terminal of the second transistor and the first terminal of the first transistor for coupling the second radio frequency input signal to the first terminal of the first transistor; a first radio frequency output terminal coupled to the first terminal of the first transistor for outputting a first radio frequency output signal; and a second radio frequency output terminal coupled to the first terminal of the second transistor for outputting a second radio frequency output signal, wherein the first amplified radio frequency signal and the coupled second radio frequency input signal combine to become the first radio frequency output signal, and the second amplified radio frequency signal and the coupled first radio frequency input signal combine to become the second radio frequency output signal; and a controller coupled to the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit for adjusting capacitance values of the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit according to at least one of a characteristic associated with the first radio frequency input signal of the first differential amplification circuit, a characteristic associated with the second radio frequency input signal of the first differential amplification circuit, a matching error between the first transistor and the second transistor of the first differential amplification circuit, and a characteristic of the amplifier device; a second differential amplification circuit, comprising: a first radio frequency input terminal coupled to the first radio frequency output terminal of the first differential amplification circuit for inputting a first radio frequency input signal; a second radio frequency input terminal coupled to the second radio frequency output terminal of the first differential amplification circuit for inputting a first radio frequency input signal; a first transistor having a first terminal, a control terminal, and a second terminal coupled to the first radio frequency input terminal; a second transistor having a first terminal, a control terminal, and a second terminal coupled to the second radio frequency input terminal; a first adjustable capacitance circuit coupled between the control terminal of the first transistor and the first terminal of the second transistor; a second adjustable capacitance circuit coupled between the control terminal of the second transistor and the first terminal of the first transistor; a first radio frequency output terminal coupled to the first terminal of the first transistor for outputting a first radio frequency output signal; and a second radio frequency output terminal coupled to the first terminal of the second transistor for outputting a second radio frequency output signal, wherein the controller is further coupled to the first adjustable capacitance circuit of the second differential amplification circuit and the second adjustable capacitance circuit of the second differential amplification circuit, and is further configured to adjust capacitance values of the first adjustable capacitance circuit of the second differential amplification circuit and the second adjustable capacitance circuit of the second differential amplification circuit according to at least one of a characteristic related to the first radio frequency input signal of the second differential amplification circuit, a characteristic related to the second radio frequency input signal of the second differential amplification circuit, a matching error between the first transistor and the second transistor of the second differential amplification circuit, and a characteristic of the amplifier device.

7. The amplifier arrangement of claim 6, wherein wherein the characteristic related to the first radio frequency input signal is a power of the first radio frequency input signal or a power of the first radio frequency output signal, and the characteristic related to the second radio frequency input signal is a power of the second radio frequency input signal or a power of the second radio frequency output signal, and the characteristic of the amplifier device is a signal amplification linearity of the amplifier device; wherein the controller is configured to adjust the capacitance values of the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit according to the characteristic related to the first radio frequency input signal or the characteristic related to the second radio frequency input signal, and the controller is configured to adjust the capacitance values of the first adjustable capacitance circuit of the second differential amplification circuit and the second adjustable capacitance circuit of the second differential amplification circuit according to the characteristic of the amplifier device.

8. The amplifier arrangement of claim 6, wherein wherein the second differential amplification circuit further comprises: a third adjustable capacitance circuit coupled between the control terminal of the first transistor and a reference voltage terminal; and a fourth adjustable capacitance circuit coupled between the control terminal of the second transistor and the reference voltage terminal; The controller is further coupled to the third adjustable capacitance circuit of the second differential amplification circuit and the fourth adjustable capacitance circuit of the second differential amplification circuit, and is used to adjust capacitance values of the third adjustable capacitance circuit of the second differential amplification circuit and the fourth adjustable capacitance circuit of the second differential amplification circuit according to at least one of a characteristic related to the first radio frequency input signal of the second differential amplification circuit, a characteristic related to the second radio frequency input signal of the second differential amplification circuit, a matching error between the first transistor and the second transistor of the second differential amplification circuit, and a characteristic of the amplifier device.

9. The amplifier arrangement of claim 6, wherein The control terminal of the first transistor of the second differential amplification circuit is coupled to the control terminal of the second transistor of the first differential amplification circuit, and the control terminal of the second transistor of the second differential amplification circuit is coupled to the control terminal of the first transistor of the first differential amplification circuit.

10. An amplifier arrangement characterized by The first differential amplification circuit comprises: A first differential amplification circuit comprises: A first radio frequency input terminal for inputting a first radio frequency input signal; A second radio frequency input terminal for inputting a second radio frequency input signal; A first transistor having a first terminal and a control terminal coupled to the first radio frequency input terminal, wherein the control terminal obtains the first radio frequency input signal through the first radio frequency input terminal, the first transistor amplifies the first radio frequency input signal and generates a first amplified radio frequency signal at the first terminal; A second transistor having a first terminal and a control terminal coupled to the second radio frequency input terminal, wherein the control terminal obtains the second radio frequency input signal through the second radio frequency input terminal, the second transistor amplifies the second radio frequency input signal and generates a second amplified radio frequency signal at the first terminal; A first adjustable capacitance circuit coupled between the control terminal of the first transistor and the first terminal of the second transistor, for coupling the first radio frequency input signal to the first terminal of the second transistor; and A second adjustable capacitance circuit coupled between the control terminal of the second transistor and the first terminal of the first transistor, for coupling the second radio frequency input signal to the first terminal of the first transistor; A first radio frequency output terminal coupled to the first terminal of the first transistor, for outputting a first radio frequency output signal; and A second radio frequency output terminal coupled to the first terminal of the second transistor, for outputting a second radio frequency output signal, Wherein the first amplified radio frequency signal and the coupled second radio frequency input signal are combined to become the first radio frequency output signal, and the second amplified radio frequency signal and the coupled first radio frequency input signal are combined to become the second radio frequency output signal; and a controller coupled to the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit to adjust capacitance values of the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit according to at least one of a characteristic related to the first radio frequency input signal of the first differential amplification circuit, a characteristic related to the second radio frequency input signal of the first differential amplification circuit, a mismatch error between the first transistor and the second transistor of the first differential amplification circuit, and a characteristic of the amplifier device; wherein a second end of the first transistor of the first differential amplification circuit is coupled to a reference voltage terminal through a first through-wafer via, and a second end of the second transistor of the first differential amplification circuit is coupled to the reference voltage terminal through a second through-wafer via.

11. An amplifier arrangement characterized by comprising: a first differential amplification circuit comprising: a first radio frequency input terminal to input a first radio frequency input signal; a second radio frequency input terminal to input a second radio frequency input signal; a first transistor having a first end and a control end coupled to the first radio frequency input terminal, wherein the control end obtains the first radio frequency input signal through the first radio frequency input terminal, the first transistor amplifies the first radio frequency input signal and generates a first amplified radio frequency signal at the first end; a second transistor having a first end and a control end coupled to the second radio frequency input terminal, wherein the control end obtains the second radio frequency input signal through the second radio frequency input terminal, the second transistor amplifies the second radio frequency input signal and generates a second amplified radio frequency signal at the first end; a first adjustable capacitance circuit coupled between the control end of the first transistor and the first end of the second transistor to couple the first radio frequency input signal to the first end of the second transistor; and a second adjustable capacitance circuit coupled between the control end of the second transistor and the first end of the first transistor to couple the second radio frequency input signal to the first end of the first transistor; a first radio frequency output terminal coupled to the first end of the first transistor to output a first radio frequency output signal; and a second radio frequency output terminal coupled to the first end of the second transistor to output a second radio frequency output signal, wherein the first amplified radio frequency signal and the coupled second radio frequency input signal combine to become the first radio frequency output signal, and the second amplified radio frequency signal and the coupled first radio frequency input signal combine to become the second radio frequency output signal; and a controller coupled to the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit to adjust capacitance values of the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit according to at least one of a characteristic related to the first radio frequency input signal of the first differential amplification circuit, a characteristic related to the second radio frequency input signal of the first differential amplification circuit, a matching error between the first transistor and the second transistor of the first differential amplification circuit, and a characteristic of the amplifier device; wherein the first adjustable capacitance circuit and the second adjustable capacitance circuit each include at least one switch to be controlled to adjust capacitance values in the first adjustable capacitance circuit and the second adjustable capacitance circuit; wherein the at least one switch is turned on when a power of the first radio frequency output signal or the second radio frequency output signal is higher than a preset power value, and the at least one switch is turned off when the power of the first radio frequency output signal or the second radio frequency output signal is lower than the preset power value.

12. An amplifier device, characterized by comprising: a first differential amplification circuit comprising: a first radio frequency input terminal to input a first radio frequency input signal; a second radio frequency input terminal to input a second radio frequency input signal; a first transistor having a first terminal and a control terminal coupled to the first radio frequency input terminal, wherein the control terminal obtains the first radio frequency input signal through the first radio frequency input terminal, the first transistor amplifies the first radio frequency input signal and generates a first amplified radio frequency signal at the first terminal; a second transistor having a first terminal and a control terminal coupled to the second radio frequency input terminal, wherein the control terminal obtains the second radio frequency input signal through the second radio frequency input terminal, the second transistor amplifies the second radio frequency input signal and generates a second amplified radio frequency signal at the first terminal; a first adjustable capacitance circuit coupled between the control terminal of the first transistor and the first terminal of the second transistor to couple the first radio frequency input signal to the first terminal of the second transistor; and a second adjustable capacitance circuit coupled between the control terminal of the second transistor and the first terminal of the first transistor to couple the second radio frequency input signal to the first terminal of the first transistor; a first radio frequency output terminal coupled to the first terminal of the first transistor to output a first radio frequency output signal; and a second radio frequency output terminal coupled to the first terminal of the second transistor to output a second radio frequency output signal, wherein the first amplified radio frequency signal and the coupled second radio frequency input signal combine to become the first radio frequency output signal, and the second amplified radio frequency signal and the coupled first radio frequency input signal combine to become the second radio frequency output signal; and a controller coupled to the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit for adjusting capacitance values of the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit according to at least one of characteristics related to the first radio frequency input signal of the first differential amplification circuit, characteristics related to the second radio frequency input signal of the first differential amplification circuit, a matching error between the first transistor and the second transistor of the first differential amplification circuit, and characteristics of the amplifier device; further comprising: N-1 differential amplification circuits, N being a positive integer greater than 2, wherein each differential amplification circuit comprises: a first radio frequency input terminal for inputting a first radio frequency input signal; a second radio frequency input terminal for inputting a first radio frequency input signal; a first transistor having a first terminal, a control terminal, and a second terminal coupled to the first radio frequency input terminal; a second transistor having a first terminal, a control terminal, and a second terminal coupled to the second radio frequency input terminal; a first adjustable capacitance circuit coupled between the control terminal of the first transistor and the first terminal of the second transistor; a second adjustable capacitance circuit coupled between the control terminal of the second transistor and the first terminal of the first transistor; a first radio frequency output terminal coupled to the first terminal of the first transistor for outputting a first radio frequency output signal; and a second radio frequency output terminal coupled to the first terminal of the second transistor for outputting a second radio frequency output signal; wherein the first radio frequency input terminal of an nth differential amplification circuit is coupled to the first radio frequency output terminal of an (n-1)th differential amplification circuit, the second radio frequency input terminal of the nth differential amplification circuit is coupled to the second radio frequency output terminal of the (n-1)th differential amplification circuit, the controller is further coupled to the first adjustable capacitance circuit of the (n-1)th differential amplification circuit and the second adjustable capacitance circuit of the (n-1)th differential amplification circuit, and the controller is further for adjusting capacitance values of the first adjustable capacitance circuit of the (n-1)th differential amplification circuit and the second adjustable capacitance circuit of the (n-1)th differential amplification circuit according to at least one of characteristics related to the first radio frequency input signal of the (n-1)th differential amplification circuit, characteristics related to the second radio frequency input signal of the (n-1)th differential amplification circuit, a matching error between the first transistor and the second transistor of the (n-1)th differential amplification circuit, and characteristics of the amplifier device, wherein n is a positive integer greater than or equal to 2 and n is less than or equal to N.

13. The amplifier arrangement of claim 12, wherein wherein the controller is further for adjusting capacitance values of the first adjustable capacitance circuit of the nth differential amplification circuit and the second adjustable capacitance circuit of the nth differential amplification circuit according to signal amplification linearity of the amplifier device.

14. An amplifier arrangement characterized by comprising: a first differential amplification circuit comprising: a first radio frequency input terminal for inputting a first radio frequency input signal; a second radio frequency input terminal for inputting a second radio frequency input signal; a first transistor having a first end and a control end coupled to the first radio frequency input end, wherein the control end obtains the first radio frequency input signal through the first radio frequency input end, the first transistor amplifies the first radio frequency input signal and generates a first amplified radio frequency signal at the first end; a second transistor having a first end and a control end coupled to the second radio frequency input end, wherein the control end obtains the second radio frequency input signal through the second radio frequency input end, the second transistor amplifies the second radio frequency input signal and generates a second amplified radio frequency signal at the first end; a first adjustable capacitance circuit coupled between the control end of the first transistor and the first end of the second transistor for coupling the first radio frequency input signal to the first end of the second transistor; and a second adjustable capacitance circuit coupled between the control end of the second transistor and the first end of the first transistor for coupling the second radio frequency input signal to the first end of the first transistor; a first radio frequency output end coupled to the first end of the first transistor for outputting a first radio frequency output signal; and a second radio frequency output end coupled to the first end of the second transistor for outputting a second radio frequency output signal, wherein the first amplified radio frequency signal and the coupled second radio frequency input signal combine to become the first radio frequency output signal, and the second amplified radio frequency signal and the coupled first radio frequency input signal combine to become the second radio frequency output signal; and a controller coupled to the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit for adjusting capacitance values of the first adjustable capacitance circuit of the first differential amplification circuit and the second adjustable capacitance circuit of the first differential amplification circuit according to at least one of characteristics related to the first radio frequency input signal of the first differential amplification circuit, characteristics related to the second radio frequency input signal of the first differential amplification circuit, a matching error between the first transistor and the second transistor of the first differential amplification circuit, and characteristics of the amplifier device; the first adjustable capacitance circuit comprises: a first capacitor having a first end coupled to one end of the first adjustable capacitance circuit; a capacitance coupling switch controlled by the controller to change its on state or to change its off capacitance, having a first end coupled to a second end of the first capacitor; and a second capacitor having a first end coupled to a second end of the capacitance coupling switch, and having a second end coupled to another end of the first adjustable capacitance circuit; or the second adjustable capacitance circuit further comprises: a first capacitor having a first end coupled to one end of the second adjustable capacitance circuit; a capacitance coupling switch controlled by the controller to change its on state or to change its off capacitance, having a first end coupled to a second end of the first capacitor; and a second capacitor having a first end coupled to a second end of the capacitance coupling switch, and having a second end coupled to another end of the second adjustable capacitance circuit.

15. An amplifier arrangement characterized by comprises: a first differential amplification circuit comprising: a first radio frequency input end for inputting a first radio frequency input signal; a second radio frequency input terminal for receiving a second radio frequency input signal; a first transistor having a control terminal coupled to receive the first radio frequency input signal, the first transistor amplifying the first radio frequency input signal and generating a first amplified radio frequency signal at a first terminal of the first transistor; a second transistor having a control terminal coupled to receive the second radio frequency input signal, the second transistor amplifying the second radio frequency input signal and generating a second amplified radio frequency signal at a first terminal of the second transistor; a first adjustable capacitor circuit having a first terminal coupled to receive a first voltage at the control terminal of the first transistor and a second terminal coupled to receive a second voltage at the first terminal of the second transistor, the first adjustable capacitor circuit coupling the first radio frequency input signal to the first terminal of the second transistor, the capacitance of the first adjustable capacitor circuit being controlled by the first voltage and the second voltage; and a second adjustable capacitor circuit having a first terminal coupled to receive a third voltage at the control terminal of the second transistor and a second terminal coupled to receive a fourth voltage at the first terminal of the first transistor, the second adjustable capacitor circuit coupling the second radio frequency input signal to the first terminal of the first transistor, the capacitance of the second adjustable capacitor circuit being controlled by the third voltage and the fourth voltage. wherein the first amplified radio frequency signal and the coupled second radio frequency input signal combine to form a first radio frequency output signal and the second amplified radio frequency signal and the coupled first radio frequency input signal combine to form a second radio frequency output signal; wherein the first voltage is related to the first radio frequency input signal, the second voltage is related to the second radio frequency output signal, the third voltage is related to the second radio frequency input signal and the fourth voltage is related to the first radio frequency output signal.

16. The amplifier arrangement of claim 15, wherein wherein the first adjustable capacitor circuit or the second adjustable capacitor circuit comprises: a capacitor transistor having a control terminal, a first terminal and a second terminal, the control terminal of the capacitor transistor being one of a first terminal and a second terminal of the first adjustable capacitor circuit, the first terminal and the second terminal of the capacitor transistor being the other of the first terminal and the second terminal of the first adjustable capacitor circuit. wherein the capacitor transistor comprises: a first type well region; two first type heavily doped regions forming the first terminal and the second terminal of the capacitor transistor, the two first type heavily doped regions being disposed on the first type well region; a dielectric layer connecting the two first type heavily doped regions; and a gate material forming the control terminal of the capacitor transistor, the gate material being disposed on the dielectric layer.

17. The amplifier arrangement of claim 16, wherein wherein the first adjustable capacitor circuit or the second adjustable capacitor circuit further comprises: a resistor capacitor circuit coupled between the first terminal of the capacitor transistor and the second terminal of the first adjustable capacitor circuit.

18. A diplexer circuit, characterized by The duplexer circuit is coupled to an antenna, and the duplexer circuit comprises: a duplexer having an antenna terminal, a signal transmission terminal and a signal reception terminal; a power amplifier coupled to the signal transmission terminal of the duplexer; a low noise amplifier coupled to the signal reception terminal of the duplexer; and a first transistor having a control terminal coupled to receive the first radio frequency input signal, the first transistor amplifying the first radio frequency input signal and generating a first amplified radio frequency signal at a first terminal of the first transistor; a second transistor having a control terminal coupled to receive the second radio frequency input signal, the second transistor amplifying the second radio frequency input signal and generating a second amplified radio frequency signal at a first terminal of the second transistor; a first adjustable capacitor circuit having a first terminal coupled to receive a first voltage at the control terminal of the first transistor and a second terminal coupled to receive a second voltage at the first An amplifier device is provided in the power amplifier or the low noise amplifier. The amplifier device includes: a first differential amplifier circuit including: a first radio frequency input terminal for inputting a first radio frequency input signal; a second radio frequency input terminal for inputting a second radio frequency input signal; a first transistor having a first terminal and a control terminal coupled to the first radio frequency input terminal, wherein the control terminal obtains the first radio frequency input signal through the first radio frequency input terminal, the first transistor amplifies the first radio frequency input signal and generates a first amplified radio frequency signal at the first terminal; a second transistor having a first terminal and a control terminal coupled to the second radio frequency input terminal, wherein the control terminal obtains the second radio frequency input signal through the second radio frequency input terminal, the second transistor amplifies the second radio frequency input signal and generates a second amplified radio frequency signal at the first terminal; a first adjustable capacitor circuit coupled between the control terminal of the first transistor and the first terminal of the second transistor for coupling the first radio frequency input signal to the first terminal of the second transistor; and a second adjustable capacitor circuit coupled between the control terminal of the second transistor and the first terminal of the first transistor for coupling the second radio frequency input signal to the first terminal of the first transistor; a first radio frequency output terminal coupled to the first terminal of the first transistor for outputting a first radio frequency output signal; and a second radio frequency output terminal coupled to the first terminal of the second transistor for outputting a second radio frequency output signal, wherein the first amplified radio frequency signal and the coupled second radio frequency input signal combine to become the first radio frequency output signal, and the second amplified radio frequency signal and the coupled first radio frequency input signal combine to become the second radio frequency output signal; and a controller coupled to the first adjustable capacitor circuit of the first differential amplifier circuit and the second adjustable capacitor circuit of the first differential amplifier circuit for adjusting the capacitance values of the first adjustable capacitor circuit of the first differential amplifier circuit and the second adjustable capacitor circuit of the first differential amplifier circuit according to at least one of the characteristics related to the first radio frequency input signal of the first differential amplifier circuit, the characteristics related to the second radio frequency input signal of the first differential amplifier circuit, the matching error between the first transistor and the second transistor of the first differential amplifier circuit, and the characteristics of the amplifier device.

19. The duplexer circuit of Claim 18 wherein, Wherein the amplifier device is provided in the low noise amplifier, the characteristics of the amplifier device are the signal amplification linearity of the amplifier device, and the controller adjusts the capacitance values in the first adjustable capacitor circuit and the second adjustable capacitor circuit according to the second order truncation point related to the signal amplification linearity of the amplifier device.

20. The duplexer circuit of Claim 18 wherein, Wherein the amplifier device is provided in the power amplifier, further including: a second differential amplifier circuit including: a first radio frequency input terminal coupled to the first radio frequency output terminal of the first differential amplifier circuit for inputting a first radio frequency input signal; a second radio frequency input terminal coupled to the second radio frequency output terminal of the first differential amplifier circuit for inputting a first radio frequency input signal; a first transistor having a first terminal, a control terminal, and a second terminal coupled to the first radio frequency input terminal; a second transistor having a first terminal, a control terminal, and a second terminal coupled to the second radio frequency input terminal; a first adjustable capacitance circuit coupled between the control terminal of the first transistor and the first terminal of the second transistor; a second adjustable capacitance circuit coupled between the control terminal of the second transistor and the first terminal of the first transistor; a first radio frequency output terminal coupled to the first terminal of the first transistor for outputting a first radio frequency output signal; and a second radio frequency output terminal coupled to the first terminal of the second transistor for outputting a second radio frequency output signal, wherein the controller is further coupled to the first adjustable capacitance circuit of the second differential amplification circuit and the second adjustable capacitance circuit of the second differential amplification circuit for adjusting capacitance values of the first adjustable capacitance circuit of the second differential amplification circuit and the second adjustable capacitance circuit of the second differential amplification circuit.

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