Root monitoring on FPGA using satellite ADCs

Abstract

Systems and methods for monitoring a plurality of operating conditions of a programmable device are disclosed. In some embodiments, the system can include a root monitor including circuitry configured to generate a reference voltage; a plurality of sensors and satellite monitors distributed across the programmable device; and an interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each satellite monitor can be proximate a respective one of the plurality of sensors and coupled to the respective one of the plurality of sensors via a local interconnect. The interconnect system can include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors and can include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors as data packets to the root monitor.

Description

Technical Field

[0001] This invention generally relates to integrated circuit devices, and more specifically, to monitoring one or more operating conditions of an integrated circuit. Background Technology

[0002] A programmable logic device (PLD) is a device that can be programmed by a user to implement various user-specified circuit designs. An example of a PLD is a field-programmable gate array (FPGA). An FPGA may include a set of configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), input / output blocks (IOBs), a digital signal processor (DSP), multiple processing cores, and other subsystems (e.g., memory controllers, device management resources, and configuration circuitry), which can be selectively connected together via programmable interconnect structures. User-specified circuit designs can be implemented within the programmable device by loading configuration data representing the user-specified circuit design into configuration registers, which collectively determine the functions and operations performed by the various blocks, interconnect structures, and subsystems of the programmable device.

[0003] Electrical components within a programmable device typically operate under specified conditions. For example, components may be designed to operate within a defined temperature range and can be disabled or powered off if the operating temperature rises above a certain level. Similarly, the power supply voltage is typically maintained between a minimum and a maximum voltage level to provide a relatively constant operating voltage to other electrical components within the programmable device. As the size and complexity of programmable devices increase, while simultaneously using lower power supply voltages and smaller device geometries, the accuracy of monitoring their operating conditions becomes increasingly important. Summary of the Invention

[0004] The summary of this invention provides a simplified description of the selection of concepts further described in the following specific embodiments. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Furthermore, the systems, methods, and apparatus of this disclosure have several innovative aspects, none of which alone is responsible for the desired attributes disclosed herein.

[0005] One innovative aspect of the subject matter described in this disclosure can be implemented to monitor the operating conditions of various circuits and components distributed across a programmable device. In some embodiments, the programmable device may include a plurality of configurable logic resources, a root monitor, a plurality of sensors distributed at various locations of the programmable device, a plurality of satellite monitors distributed at various locations of the programmable device, and a network interconnection system coupled to each of the configurable logic resources, the root monitor, and the plurality of satellite monitors. Each of the sensors may be configured to measure the operating conditions of associated circuitry at a corresponding location in the respective locations and may provide an analog signal indicative of the measured operating conditions to a corresponding satellite monitor in the satellite monitors. In some aspects, the operating conditions may include at least one of temperature or voltage level of the associated circuitry.

[0006] Each satellite monitor may include an analog-to-digital converter (ADC) having an input for receiving analog signals from one or more associated sensors and an output for providing digital data to a network interconnect system. The ADC can convert the analog signals into digital data indicating the operating conditions of one or more associated sensors and can provide the digital data to the root monitor via the network interconnect system.

[0007] The root monitor may include circuitry configured to generate a reference voltage and may include a memory configured to store digital data received from a plurality of satellite monitors. In some embodiments, the root monitor may include a bandgap reference circuitry for compensating for temperature variations in the reference voltage. Additionally, or alternatively, the root monitor may include a controller configured to determine whether the measured operating conditions of associated circuitry are within a range. In some aspects, the controller may also be configured to generate an alarm based on a determination indicating that the measured operating conditions are not within that range.

[0008] A network interconnection system can be configured to distribute a reference voltage from a root monitor to each of a plurality of satellite monitors, and can be configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor. In some embodiments, the network interconnection system may include one or more analog channels configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route data from the satellite monitors to the root monitor. In some aspects, the digital data may be routed through the network interconnection system as individually addressable data packets. In other aspects, the digital data may be routed through the network interconnection system as non-packetized digital signals.

[0009] In some embodiments, each satellite monitor may include a switch configured to selectively couple a reference voltage allocated by an interconnect system to the satellite monitor based on control signals. These control signals may be generated by a root monitor and allocated to the respective satellite monitors via a network interconnect system (or other suitable signal interconnect). In some aspects, the root monitor may selectively assert the control signals based on a timing table that allows only one satellite monitor to timely access the allocated reference voltage from the network interconnect system at any given time.

[0010] An example system for monitoring multiple operating conditions of a programmable device may include a root monitor, multiple sensors distributed across the programmable device, multiple satellite monitors distributed across the programmable device, and a network interconnection system coupled to at least the root monitor and each of the multiple satellite monitors. The root monitor may include circuitry configured to generate a reference voltage that can be used to perform analog-to-digital conversion. In some embodiments, the root monitor may include a bandgap reference circuitry that compensates for temperature variations in the reference voltage. Furthermore, or alternatively, the root monitor may include a controller configured to determine whether the operating conditions measured by the associated circuitry are within a range. In some aspects, the controller may also be configured to generate an alarm based on a determination indicating that the measured operating conditions are not within that range.

[0011] Each sensor can be configured to generate an analog signal indicating the operating conditions of the associated circuitry, and each satellite monitor can be configured to convert the analog signals generated by one or more associated sensors into digital data that can be routed to the root monitor via a network interconnection system.

[0012] The network interconnection system may include one or more analog channels configured to distribute a reference voltage to each of a plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to a root monitor. In some aspects, the digital data may be routed through the network interconnection system as individually addressable data packets. In other aspects, the digital data may be routed through the network interconnection system as unpacked digital signals.

[0013] Each satellite monitor may include an analog-to-digital converter (ADC) configured to convert analog signals into digital data. In some embodiments, each satellite monitor may include a switch configured to selectively couple a reference voltage allocated by an interconnect system to the satellite monitor based on control signals. These control signals may be generated by a root monitor and may be allocated to the respective satellite monitors via a network interconnect system (or other suitable signal interconnect). In some aspects, the root monitor may selectively assert the control signals based on a timing table that allows only one satellite monitor to timely access the allocated reference voltage from the network interconnect system at any given time.

[0014] The example methods disclosed herein can be used to monitor multiple operating conditions of a programmable device. The methods may include generating a reference voltage using a voltage generator associated with a root monitor provided within the programmable device, and distributing the reference voltage to each of a plurality of satellite monitors using one or more analog channels of a network interconnect system integrated within the programmable device. In some embodiments, distributing the reference voltage may include selectively coupling each of the plurality of satellite monitors to the network interconnect system based on corresponding control signals. The control signals may be generated by the root monitor and distributed to the plurality of satellite monitors via the network interconnect system. In some aspects, the root monitor may selectively assert the control signals based on a timing table that allows only one satellite monitor to timely access the allocated reference voltage from the network interconnect system at any given time.

[0015] The method may further include generating an analog signal indicating the operating conditions of the associated circuitry using each of a plurality of sensors, and providing the analog signal to a corresponding monitor among a plurality of satellite monitors. The analog signal can be converted into digital data using the multiple satellite monitors, and the digital data can be selectively routed from the multiple satellite monitors to the root monitor using one or more digital channels of the network interconnection system. In some aspects, the digital data can be routed through the network interconnection system as individually addressable data packets. In other aspects, the digital data can be routed through the network interconnection system as non-packetized digital signals.

[0016] The method may further include determining whether the operating conditions of the associated circuits are within a range, and selectively generating one or more alarms based on the determination. In some embodiments, an alarm may be generated when the operating conditions of at least one associated circuit in the associated circuits are not within the range, which may indicate that at least one associated circuit in the associated circuits is operating outside of specific conditions.

[0017] One innovative aspect of the subject matter described in this disclosure can be implemented to monitor the operating conditions of various circuits and components distributed across a programmable device. In some embodiments, the programmable device may include programmable logic comprising a plurality of configurable logic resources, a root monitor, a plurality of sensors distributed at various locations of the programmable device, and a plurality of satellite monitors distributed at various locations of the programmable device. Each sensor may be configured to generate an analog signal indicating the measured operating conditions of one or more associated circuits near a corresponding location in the various locations, and may provide the analog signal to a relevant satellite monitor via one or more local signal lines. In some aspects, the operating conditions may include at least one of temperature or voltage levels of the associated circuits.

[0018] The root monitor may include a bandgap voltage generator configured to generate a temperature-independent reference voltage, and may include memory for storing digital data received from multiple satellite monitors. The root monitor may also include a controller configured to determine whether the measured operating conditions of the associated circuitry are within a range. In some aspects, the controller may also be configured to generate an alarm based on a determination indicating that the measured operating conditions are not within that range.

[0019] Each satellite monitor may include a relatively small local voltage source configured to generate a local reference voltage, an analog-to-digital converter (ADC), calibration circuitry, and correction circuitry. The ADC may include a reference terminal for receiving the local reference voltage and may be configured to convert analog signals generated by one or more associated sensors into digital codes indicating the measured operating conditions. The calibration circuitry may be configured to generate a correction factor indicating errors in the digital codes, and the correction circuitry may be configured to correct the digital codes generated by the ADC based on the correction factor.

[0020] In some embodiments, each satellite monitor may include a switch comprising a first input coupled to receive a temperature-independent reference voltage, a second input coupled to receive analog signals generated by one or more associated sensors, a control terminal coupled to receive control signals, and an output terminal coupled to the input of an ADC within the satellite monitor. During calibration operations, the switch may provide the temperature-independent reference voltage as an input signal to the ADC, and the ADC may sample the temperature-independent reference voltage to generate a reference code. Calibration circuitry may generate a correction factor based on the difference between the reference code generated by the ADC and a predetermined digital code indicating the temperature-independent reference. During monitoring operations, the switch may provide analog signals from sensors as input signals to the ADC, the ADC may sample the analog signals from one or more associated sensors to generate a digital code, and calibration circuitry may use the correction factor to correct the digital code.

[0021] The root monitor may generate control signals based at least in part on a timing table used to calibrate multiple satellite monitors. In some embodiments, the timing table may be configured to sequentially enable calibration of each of the multiple satellite monitors by allowing only one satellite monitor at a time to access a temperature-independent reference voltage.

[0022] In some embodiments, the programmable device may include an on-chip network (NoC) interconnect system coupled to configurable logic resources, a root monitor, and each of a plurality of satellite monitors. The NoC interconnect system may be configured to route control signals from the root monitor to each of the plurality of satellite monitors, and may be configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor. Additionally, or alternatively, the programmable device may include one or more analog channels configured to distribute a temperature-independent reference voltage from the root monitor to each of the plurality of satellite monitors.

[0023] The example methods disclosed herein can be used to monitor the operating conditions of multiple circuits distributed at various locations of a programmable device. In some embodiments, the method may include generating an analog signal indicating the operating conditions of each of the multiple circuits using a corresponding sensor among multiple sensors distributed at various locations of the programmable device; providing each analog signal to a corresponding satellite monitor among multiple satellite monitors distributed at various locations of the programmable device; generating a local reference voltage in each of the multiple satellite monitors using a local voltage source; converting a corresponding analog signal among the multiple analog signals into a digital code using an analog-to-digital converter (ADC) based on the local reference voltage in each of the multiple satellite monitors; allocating a temperature-independent reference voltage from a root monitor to each of the multiple satellite monitors; correcting the digital code generated by the ADC in each of the multiple satellite monitors based at least in part on the allocated temperature-independent reference voltage; and selectively routing the corrected digital code from each of the multiple satellite monitors to the root monitor. In some embodiments, allocating the temperature-independent reference voltage may include sequentially enabling each of the multiple satellite monitors to access the temperature-independent reference voltage based on corresponding multiple control signals generated by the root monitor.

[0024] In some embodiments, a network-on-chip (NoC) interconnect system spanning programmable logic can be used to selectively route the corrected digital code from multiple satellite monitors to a root monitor, and a temperature-independent reference voltage can be distributed from the root monitor to the multiple satellite monitors using one or more analog channels spanning programmable logic. In some embodiments, the corrected digital code may include providing the temperature-independent reference voltage as an input signal to an ADC; converting the temperature-independent reference voltage into a reference code using the ADC; generating a correction factor based on the difference between the reference code and a predetermined digital code indicating the temperature-independent reference voltage; and adjusting the digital code according to the correction factor.

[0025] One innovative aspect of the subject matter described in this disclosure can be implemented to monitor the operating conditions of various circuits and components distributed across a programmable device. In some embodiments, the programmable device may include programmable logic comprising a plurality of configurable logic resources, a root monitor, a plurality of sensors distributed at various locations of the programmable device, and a plurality of satellite monitors distributed at various locations of the programmable device. Each sensor may be configured to generate an analog signal indicating measured operating conditions of one or more associated circuits near a corresponding location in the various locations, and may provide the analog signal to a corresponding satellite monitor via one or more local signal lines. In some aspects, the operating conditions may include at least one of temperature or voltage levels of the associated circuits.

[0026] The root monitor may include a bandgap voltage generator configured to generate a temperature-independent reference voltage, and may include memory for storing digital data received from multiple satellite monitors. The root monitor may also include a controller configured to determine whether the operating conditions of the measured associated circuitry are within a range. In some aspects, the controller may also be configured to generate an alarm based on a determination indicating that the measured operating conditions are not within that range.

[0027] Each satellite monitor may include a voltage memory configured to store a local reference voltage based on a temperature-independent reference voltage generated by a bandgap voltage generator, an analog-to-digital converter (ADC), calibration circuitry, and correction circuitry. The ADC may include a reference terminal for receiving the local reference voltage and may be configured to convert analog signals generated by one or more associated sensors into digital codes indicating the measured operating conditions. The calibration circuitry may be configured to generate a correction factor indicating errors in the digital codes, and the correction circuitry may be configured to correct the digital codes generated by the ADC based on the correction factor.

[0028] In some embodiments, each satellite monitor may include a first switch and a second switch. The first switch may include a first input coupled to receive a temperature-independent reference voltage, a second input coupled to receive analog signals generated by one or more associated sensors, a control terminal coupled to receive control signals, and an output terminal coupled to the input of an ADC within the satellite monitor. The second switch may include an input coupled to receive a temperature-independent reference voltage, a control terminal coupled to receive control signals, and an output terminal coupled to a voltage memory.

[0029] During calibration, a first switch can provide a temperature-independent reference voltage as an input signal to the ADC, a second switch can isolate the voltage memory from the temperature-independent reference voltage, and the ADC can sample the temperature-independent reference voltage to generate a reference code. The calibration circuit can generate a correction factor based on the difference between the reference code generated by the ADC and a predetermined digital code indicating the temperature-independent reference. During monitoring, the first switch can provide an analog signal from a sensor as an input signal to the ADC, the second switch can provide a temperature-independent reference voltage to the voltage memory, and the ADC can sample analog signals from one or more associated sensors to generate a digital code. The calibration circuit can then use the correction factor to correct the digital code.

[0030] The root monitor may generate control signals based at least in part on a timing table used to calibrate multiple satellite monitors. In some embodiments, the timing table may be configured to sequentially enable calibration of each of the multiple satellite monitors by allowing only one satellite monitor at a time to access a temperature-independent reference voltage.

[0031] In some implementations, the programmable device may include an on-chip network (NoC) interconnect system coupled to a configurable logic resource, a root monitor, and each of a plurality of satellite monitors. The NoC interconnect system may be configured to route control signals from the root monitor to each of the plurality of satellite monitors, and may be configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor. Additionally, or alternatively, the programmable device may include one or more analog channels configured to distribute a temperature-independent reference voltage from the root monitor to each of the plurality of satellite monitors.

[0032] The example methods disclosed herein can be used to monitor the operating conditions of multiple circuits distributed across various locations of a programmable device. In some embodiments, the method may include generating an analog signal indicative of the operating conditions of each of a plurality of sensors distributed across various locations of the programmable device; providing each analog signal to a corresponding satellite monitor among a plurality of satellite monitors distributed across various locations of the programmable device; storing a local reference voltage in each of the plurality of satellite monitors based on a temperature-independent reference voltage; converting a corresponding analog signal among the plurality of analog signals into a digital code using an analog-to-digital converter (ADC) based on the local reference voltage in each of the plurality of satellite monitors; distributing the temperature-independent reference voltage from a root monitor to each of the plurality of satellite monitors; correcting the digital code generated by the ADC in each of the plurality of satellite monitors based at least in part on the distributed temperature-independent reference voltage; and selectively routing the corrected digital code from each of the plurality of satellite monitors to the root monitor. In some embodiments, the voltage memory may be a capacitor, and the local reference voltage may be relatively inaccurate compared to the temperature-independent reference voltage. In some embodiments, allocating a temperature-independent reference voltage may include sequentially enabling each of the plurality of satellite monitors to access the temperature-independent reference voltage based on a plurality of corresponding control signals generated by the root monitor.

[0033] A corrected digital code can be selectively routed from multiple satellite monitors to a root monitor using a network-on-chip (NoC) interconnect system spanning programmable logic, and a temperature-independent reference voltage can be distributed from the root monitor to multiple satellite monitors using one or more analog channels spanning programmable logic. In some embodiments, correcting the digital code may include providing a temperature-independent reference voltage as an input signal to an ADC; converting the temperature-independent reference voltage into a reference code using the ADC; generating a correction factor based on the difference between the reference code and a predetermined digital code indicating the temperature-independent reference voltage; and adjusting the digital code according to the correction factor. Attached Figure Description

[0034] Exemplary embodiments are shown by way of example and are not intended to be limited to the figures in the accompanying drawings. Throughout the drawings and specification, the same reference numerals denote the same elements. It should be noted that the relative dimensions of the following figures may not be drawn to scale.

[0035] Figure 1 This is a block diagram of an exemplary programmable device that can implement the various aspects disclosed herein.

[0036] Figure 2Illustrations are shown according to some embodiments Figure 1 A functional block diagram of a portion of a programmable device.

[0037] Figure 3 A block diagram of an exemplary programmable structure according to some embodiments is shown.

[0038] Figure 4 A functional block diagram of a monitoring system according to some embodiments is shown.

[0039] Figure 5 A block diagram of an exemplary root monitor according to some embodiments is shown.

[0040] Figure 6 A block diagram of an exemplary satellite monitor according to some embodiments is shown.

[0041] Figure 7 This is an illustrative flowchart depicting exemplary operations for monitoring multiple operating conditions of a programmable device, according to some embodiments.

[0042] Figure 8 This is a block diagram of an exemplary programmable device that can implement the various aspects disclosed herein.

[0043] Figure 9 Illustrations are shown according to some embodiments Figure 8 A functional block diagram of a portion of a programmable device.

[0044] Figure 10 A block diagram of an exemplary programmable structure according to some embodiments is shown.

[0045] Figure 11 A functional block diagram of a monitoring system according to some embodiments is shown.

[0046] Figure 12 A block diagram of an exemplary root monitor according to some embodiments is shown.

[0047] Figure 13 A block diagram of an exemplary satellite monitor according to some embodiments is shown.

[0048] Figure 14 This is an illustrative flowchart depicting exemplary operations for monitoring multiple operating conditions of a programmable device, according to some embodiments.

[0049] Figure 15 This is an illustrative flowchart depicting exemplary operations for correcting digital codes, according to some embodiments.

[0050] Figure 16 A block diagram of an exemplary satellite monitor according to some embodiments is shown. Detailed Implementation

[0051] Embodiments of the subject matter described in this disclosure can be used to monitor multiple operating conditions of a programmable device. Operating conditions can be any suitable measure of the operating characteristics or parameters of the device, including, for example, the temperature of circuitry or components provided within the programmable device, the temperature of circuitry or devices external to the programmable device, power supply voltage, etc. According to some aspects disclosed herein, a monitoring system can be implemented in a programmable device that includes programmable logic, dedicated circuitry such as processors and DSPs, and a network interconnection system that can route information between the programmable logic, dedicated circuitry, and other circuitry or components of the programmable device using individually addressable data packets.

[0052] The monitoring system may include a root monitor, multiple sensors distributed across various locations of the programmable device, and multiple satellite monitors distributed across various locations of the programmable device. Each sensor may generate an analog signal indicating one or more operating conditions of associated circuitry and may provide the analog signal to a corresponding satellite monitor among the multiple satellite monitors. Each satellite monitor may include an ADC for converting the analog signal into digital data, and a network interconnection system may route the digital data from each satellite monitor to the root monitor. In some embodiments, for example, each satellite monitor may be located near the corresponding sensor such that the analog signal generated by the corresponding sensor is not routed across the programmable device to the root monitor for conversion into digital data, but is instead routed a relatively short distance via local signal lines to the corresponding satellite monitor for conversion into digital data.

[0053] In other embodiments, digital data generated by the satellite monitor can be routed to the root monitor using other suitable routing resources provided within the device, including (but not limited to) clock distribution networks, programmable interconnect structures, and / or routing resources provided within each programmable logic patch in the device.

[0054] The root monitor can receive digital data generated by each satellite monitor via a network interconnect system and can analyze the digital data to determine whether one or more monitored circuits are operating outside a specified operating range. In some embodiments, the root monitor can generate an adjusted and temperature-compensated reference voltage, and the network interconnect system can distribute the adjusted and temperature-compensated reference voltage to each satellite monitor located throughout the device.

[0055] Conventional systems for monitoring the operating conditions of various circuits distributed across a programmable device typically consist of a central system monitor and multiple sensors located near the circuits to be monitored. Each sensor generates an analog signal indicating the operating conditions of the associated circuitry, and these analog signals are routed from each sensor to the system monitor for conversion into digital data. Since the sensors are typically distributed throughout the device, the analog signals generated by at least some of them may need to traverse a significant portion of the device's path to reach the system monitor. Because the analog signals indicating operating conditions can be particularly susceptible to noise and interference, some programmable devices utilize dedicated metal layer routing resources with shielding properties to route these analog signals from the individual sensors to the system monitor for conversion into digital data.

[0056] While the shielding properties of such dedicated metal layer routing resources can reduce signal attenuation and data loss, they are expensive and consume a significant amount of device metal layers. Furthermore, because programmable logic is typically implemented as multiple repeatable tiles arranged in multiple rows or columns, the signal routing resources embedded in each repeatable tile are often based on worst-case routing scenarios (e.g., for tiles placed in locations with the highest device density). Therefore, many repeatable tiles are over-configured with signal routing resources, which can lead to unused routing resources and / or potentially limit the scalability of programmable devices.

[0057] Specific embodiments of the subject matter described herein can be implemented to achieve one or more of the following potential advantages. By deploying multiple satellite monitors with analog-to-digital conversion capabilities throughout the programmable device close to the location of sensors monitoring the operating conditions of various circuits, the monitoring system disclosed herein can convert analog signals generated by the sensors into digital data using local satellite monitors, and then route the digital data from various locations throughout the device to a root monitor. Therefore, instead of routing analog signals over a large area of ​​the device and then converting them to digital data, the analog signals are transmitted over a relatively short distance to the nearest satellite monitor for conversion to digital data, and then routed to the root monitor using a network interconnect system. In some aspects, the digital data generated by the satellite monitors can be routed to the root monitor as individually addressable data packets. In other aspects, the digital data generated by the satellite monitors can be routed to the root monitor as unpacked data. By using satellite monitors located near the sensors to convert analog signals to digital data, rather than performing analog-to-digital conversion in the root monitor, the monitoring system disclosed herein eliminates the need for metal layer routing resources, which in turn reduces costs while increasing the scalability of the programmable device. Furthermore, performing analog-to-digital conversion locally (e.g., near the sensor) and routing the resulting digital data from the satellite monitor to the root monitor allows the root monitor to collect and analyze more sensor data (compared to existing techniques that route analog signals from individual sensors located throughout the device to an ADC provided within the system monitor), for example, because ADCs distributed throughout the programmable device can perform analog-to-digital conversion in parallel (e.g., simultaneously).

[0058] In the following description, numerous specific details, such as examples of specific components, circuits, and processes, are set forth to provide a thorough understanding of the document. As used herein, the term “coupled” means directly coupled to or coupled through one or more intermediary components or circuits. Furthermore, specific terms and / or details are set forth in the following description for purposes of explanation to provide a thorough understanding of the exemplary embodiments. However, these specific details will be obvious to those skilled in the art and may not be necessary for practicing the exemplary embodiments. In other instances, well-known circuits and devices are shown in block diagram form to avoid obfuscation with the document. Any signals provided by the various buses described herein may be time-multiplexed with other signals and provided via one or more common buses. Furthermore, interconnections between circuit elements or software blocks may be shown as buses or single signal lines. Each bus may be replaced by a single signal line, and each single signal line may be replaced by a bus, and a single line or bus may represent any one or more of a multitude of physical or logical mechanisms for communication between components. Exemplary embodiments should not be construed as limited to the specific examples described herein, but rather all embodiments as defined in the appended claims are included within their scope.

[0059] Figure 1 A block diagram of an exemplary programmable device 100 that can implement the various aspects disclosed herein is shown. Device 100 may include multiple subsystems, such as programmable logic (PL) 110, network interconnect system 120, processing and management resources (PMR) 130, CCIX and PCIe modules (CPM) 140, transceiver block 150, input / output (I / O) block 160, memory controller 170, configuration logic 180, root monitor 190, multiple satellite monitors 192(1)-192(19), and multiple sensors (S). In one or more embodiments, device 100 may include... Figure 1 Other subsystems or components not shown. Furthermore, although not shown for simplicity, device 100 may be coupled to multiple peripheral components (e.g., high-performance memory devices) and / or other devices or chips (e.g., another programmable device).

[0060] The PL 110 includes programmable circuitry that can be configured or programmed to perform a variety of different user-defined functions or operations. For example, such as Figure 1 As shown, in some embodiments, PL 110 may include a plurality of programmable circuit blocks implemented as repeatable tiles arranged in columns within the programmable device 100. The programmable circuit blocks may also be referred to as programmable structure sub-regions (FSRs), and each programmable circuit block may include programmable interconnect circuitry and programmable logic circuitry. In some embodiments, the programmable circuit blocks may include (but are not limited to) configurable logic blocks (CLBs), random access memory blocks (BRAMs), digital signal processing blocks (DSPs), clock managers, delay-locked loops (DLLs), and / or other logic or circuitry that can be programmed or configured to implement a user-specified circuit design.

[0061] Each programmable interconnect circuit within a programmable block or patch may include multiple interconnects of varying lengths, interconnected via programmable interconnect points (PIPs). These interconnects can be configured to provide connectivity between components within a specific programmable patch, between components in different programmable patches, and between components of a programmable patch and other subsystems or devices. Programmable interconnect circuits and programmable blocks can be programmed or configured by loading configuration data into configuration registers, which define how programmable elements are configured and operated to achieve a corresponding user-specified circuit design. In some aspects, the programmable interconnect circuit within each of multiple programmable blocks may form part of a programmable interconnect structure (not shown for simplicity) that provides block-level and / or device-level signal routing resources for device 100.

[0062] Network interconnection system 120 may be manufactured as part of device 100 and may include any number of horizontal and vertical segments (and / or diagonal segments) connected together to enable a high-speed, high-bandwidth programmable signal routing network that can selectively interconnect various device resources (e.g., PL 110, PMR 130, CPM 140, transceiver block 150, I / O block 160, memory controller 170, configuration logic 180, root monitor 190, and satellite monitors 192(1)–192(19)) and interconnect with other components not shown for simplicity. Figure 1 In an exemplary embodiment, the network interconnect system 120 is shown to include two horizontal segments and four vertical segments. A first horizontal segment extending across the width of device 100 is arranged along the bottom boundary of device 100, and a second horizontal segment extending across the width of device 100 is arranged along the top boundary of device 100. The four vertical segments extend across the height of device 100 and connect to the first and second horizontal segments of the network interconnect system 120. In some aspects, the horizontal segments may allow the network interconnect system 120 to exchange signals and data with I / O block 160 and memory controller 170 without any intermediate circuitry or interfaces, and the vertical segments may allow the network interconnect system 120 to exchange signals and data with transceiver block 150, processing and management resources (PMR) 130, and CPM 140 without any intermediate circuitry or interfaces. In other exemplary embodiments, the network interconnect system 120 may include other numbers of horizontal and vertical segments, which in turn may occupy other locations on device 100. Thus, Figure 1 The specific layout, shape, size, orientation and other physical characteristics of the exemplary network interconnection system 120 depicted herein are merely illustrative of the various embodiments disclosed herein.

[0063] Network interconnect system 120 can be configured to transmit information as data packets among various device resources. These data packets can be individually addressed and routed from source locations to destination locations. In some aspects, data packets transmitted on network interconnect system 120 can be dynamically addressable. In one or more embodiments, network interconnect system 120 can employ a suitable data packet protocol (e.g., token ring protocol) and / or use memory-mapped addresses to route data packets from any number of source locations to any number of destination locations. Data packets may include header information (e.g., source address, destination address, and protocol information) that network interconnect system 120 can use to route data packets to their indicated destinations.

[0064] In some embodiments, data packets may include Quality of Service (QoS) information that allows data packet transmission over network interconnect system 120 to be prioritized, for example, based on assigned priority, service type, service flow, and / or other criteria. In such embodiments, network interconnect system 120 may include priority logic that can determine the priority or service class of received data packets and use the determined priority or service class when queuing data packets for transmission. As individually addressable data packets, by transmitting information between various device resources, network interconnect system 120 can provide connectivity between various device resources, regardless of a particular user-specified circuit design, thereby significantly increasing the signal routing capability of device 100 (compared to conventional programmable devices). For example, while the programmable interconnect structure of device 100 and other surface-mount-based signal routing structures are typically configured to provide point-to-point signaling connections between specified circuits, network interconnect system 120 can simultaneously route each of multiple data packets from any source address on device 100 to any destination address, thereby providing system-level connectivity for device 100.

[0065] Although not shown for simplicity, the network interconnect system 120 may also include a scheduler and decision-making logic. The scheduler can be used to schedule packets from a source address to a destination address using one or more physical and / or virtual channels of the network interconnect system 120. The decision-making logic can be used to decide access to the network interconnect system 120, for example, minimizing collisions and other contention-related latency. In embodiments where the device 100 is fabricated using Stacked Silicon Interconnect (SSI) technology, column portions of the network interconnect system 120 may provide signaling connections between adjacent Super Logic Regions (SLRs), for example, to allow configuration data to be routed between the master SLR and slave SLRs.

[0066] Network interconnect system 120 can be programmed by loading configuration data into appropriate configuration registers that define how various switches, interfaces, and routers within or associated with network interconnect system 120 are configured to implement a specific user-specified circuit design. In some embodiments, network interconnect system 120 may include multiple nodes, ports, or other interfaces (not shown for simplicity) that provide selective connectivity between network interconnect system 120 and various resources, subsystems, circuits, and other components of device 100. For example, network interconnect system 120 may allow multiple subsystems of device 100 to share access to on-chip memory (OCM) resources, processing resources, I / O resources, and / or transceiver block 150. The nodes, ports, or other interfaces of network interconnect system 120 can be programmed to implement specific connectivity profiles by loading configuration data into multiple associated configuration registers.

[0067] By selectively interconnecting various resources, subsystems, circuits, and other components of device 100 that may require and use large amounts of data, network interconnect system 120 can alleviate the signal routing burden on local interconnect resources, thereby improving device performance and allowing for better configuration flexibility than other programmable devices. Furthermore, by providing a high-performance signal routing network with higher data transfer rates and lower error rates than device-level and block-level programmable interconnects, network interconnect system 120 can increase the processing power and data throughput of device 100 (compared to other programmable devices).

[0068] The Processing and Management Resource (PMR) 130 can provide dedicated data processing capabilities and platform management resources for the device 100. The PMR 130 may include a Processing System (PS) and a Platform Management Controller (PMC), as shown in reference... Figure 2 A more detailed description follows. In some embodiments, the PS may include multiple processor cores, a cache, a memory controller, and unidirectional and / or bidirectional interfaces configured to be directly coupled to I / O pins of device 100. In some aspects, each processor core may include a central processing unit (CPU) or a scalar processor that can be used for sequential data processing. The PMC may be used to boot and configure device 100 based on configuration data (e.g., configuration bitstream) provided by external memory. The PMC may also be used to configure PL 110 and control various encryption, authentication, root monitoring, and debugging capabilities of device 100.

[0069] CCIX and PCIe Module (CPM) 140 may include multiple interfaces that provide connectivity between device 100 and multiple peripheral components (e.g., external devices or chips). In some embodiments, CPM 140 may include multiple peripheral high-speed interconnect (PCIe) interfaces and cache coherent interconnect (CCIX) interfaces for accelerators, which provide connectivity to other devices or chips via transceiver block 150. In some aspects, the PCIe and CCIX interfaces may be implemented as part of transceiver block 150. An exemplary embodiment of CPM 140 is... Figure 2 Described.

[0070] Transceiver block 150 can provide signal connectivity to one or more other devices or chips (not shown for simplicity) connected to device 100. Transceiver block 150 may include multiple different serial transceivers, such as gigabit serial transceivers (GT). In some embodiments, transceiver block 150 may be implemented as multiple repeatable patches positioned at different locations along the right and left sides of device 100, such as... Figure 1As shown. In other embodiments, transceiver block 150 may be located at other suitable locations within device 100. In one or more embodiments, each transceiver block 150 may be coupled to one or more associated voltage sources (not shown for simplicity). In some aspects, for example, each set of transceiver circuitry within a given transceiver block 150 may include or may be coupled to a corresponding voltage source, such that each set of transceiver circuitry can be powered using a separate voltage source.

[0071] I / O block 160 is coupled to the I / O pins of the device (not shown for simplicity) and can provide I / O capabilities to device 100. For example, I / O block 160 can receive data from one or more other devices and can drive the received data to multiple destinations within device 100. I / O block 160 can also receive data from multiple sources within device 100 and can drive the received data to one or more other devices via the device's I / O pins. In some embodiments, I / O block 160 can be implemented as a repeatable patch. Device 100 can include any suitable number of I / O blocks 160, and therefore Figure 1 The exemplary embodiments depicted are merely illustrative.

[0072] I / O block 160 may include any number of suitable I / O circuits or devices. In some embodiments, I / O block 160 may include ultra-high performance I / O (XPIO) circuitry, high-density I / O (HDIO) circuitry, and multiplexed I / O (MIO) circuitry. XPIO circuitry may be optimized for high-performance communication, such as providing a high-speed, low-latency interface to memory controller 170. In one or more embodiments, XPIO circuitry may include dedicated memory resources that can be accessed by other subsystems of device 100 without using memory controller 170. HDIO circuitry may provide a cost-effective solution (compared to XPIO circuitry) that supports lower speed and higher voltage I / O capabilities. MIO circuitry may provide general-purpose I / O resources that can be accessed by various subsystems, such as PL 110, PMR 130, and CPM 140.

[0073] The memory controller 170 can be used to control access to various memory resources provided internally and / or externally to the device 100. In some embodiments, the memory controller 170 can be used to access dedicated memory residing in one or more I / O blocks 160. The memory controller 170 may include a Double Data Rate v4 (DDR4) memory controller, a High Bandwidth Memory (HBM) controller, and / or other suitable memory controllers. In one or more embodiments, some or all of the memory controllers 170 may include a scheduler with transaction reordering capabilities that can improve memory access efficiency. Furthermore, or alternatively, the repeatable patches implementing the memory controller 170 may differ from each other. For example, a first number of memory controllers 170 may implement a DDR4 memory controller, a second number of memory controllers 170 may implement an LPDDR4 memory controller, and a third number of memory controllers 170 may implement an HBM controller.

[0074] Device 100 may include any number of I / O blocks 160 and memory controller 170, therefore, Figure 1 The number and location of the I / O blocks 160 and memory controllers 170 depicted are merely illustrative. In some embodiments, the first row of I / O blocks 160 and memory controllers 170 may be implemented as repeatable patches positioned along the bottom edge of the device 100, and the second row of I / O blocks 160 and memory controllers 170 may be implemented as repeatable patches positioned along the top edge of the device 100. In some embodiments, the I / O blocks 160 and memory controllers 170 may be alternately positioned or distributed relative to each other, for example, as shown in the diagram. Figure 1 As depicted in the example. In other embodiments, a pair of I / O blocks 160 and a storage controller 170 may be implemented within the same repeatable patch.

[0075] In some embodiments, a first row of I / O blocks 160 and a memory controller 170 positioned along the bottom of device 100 may be coupled to a first horizontal segment of network interconnect system 120, and a second row of I / O blocks 160 and a memory controller 170 positioned along the top of device 100 may be coupled to a second horizontal segment of network interconnect system 120. In this way, network interconnect system 120 can provide connectivity between the programmable resources of device 100 and its I / O pins (not shown for simplicity).

[0076] In some embodiments, device 100 may include one or more columns of connection structures (not shown for simplicity) that extend vertically through the height of device 100 and are positioned near transceiver block 150. The connection structures may include multiple hardwired circuits including (but not limited to) a USB controller, an Ethernet MAC, a Multi-Rate (MR) Ethernet MAC (MRMAC), a PCIe controller, a CCIX controller, and / or other components providing a connection between transceiver block 150 and PL 110.

[0077] Configuration logic 180 can be used to load configuration data (e.g., a configuration bit stream) from external memory and route portions of the configuration data (e.g., frames, words, bytes, and / or bits) to suitable configuration registers that define how device 100 is configured. Configuration logic 180 can also be used for partial reconfiguration of device 100 and / or internal reconfiguration of one or more portions of device 100. In some embodiments, configuration logic 180 may include configuration registers, boundary scan test circuitry (e.g., TAP controller circuitry), encryption circuitry for encrypting the bit stream of configuration data read from device 100, and decryption circuitry for decrypting the bit stream of configuration data loaded into device 100.

[0078] Although not shown for simplicity, device 100 may include an interface between the programmable structure and each row of I / O blocks 160, and a memory controller 170 located at the boundary of device 100. This interface, referred to herein as a boundary logic interface (BLI), allows large and complex external devices (e.g., HBMs) to appear as smaller blocks (e.g., CLBs) within the programmable structure of device 100. In some embodiments, the BLI may be arranged in rows at the top and bottom boundaries or edges of the programmable structure. In this way, the BLI can be used to route signals between columnar logic structures (e.g., CLB columns or DSP columns) and I / O resource rows (e.g., I / O blocks 160).

[0079] According to various aspects disclosed herein, for example, programmable device 100 may include a monitoring system that can monitor one or more operating conditions of a plurality of selected circuits provided by programmable device 100 to ensure that the selected circuits operate within a specified range of operating parameters. The monitoring system disclosed herein can measure any suitable operating conditions of the selected circuits, including, for example, temperature, voltage levels, and current levels. As used herein, the term "selected circuit" can refer to any circuit, component, power supply voltage, structure, or device that can be selected for monitoring one or more operating conditions to ensure proper operation of device 100. In some embodiments, the monitoring system may generate a single alarm (or multiple alarms) when the measured operating conditions of one or more selected circuits do not fall within a specified range of operating conditions. In some aspects, the alarm may be used to de-energize multiple circuits or components of device 100. In other aspects, the alarm may be used to de-energize the entire device 100.

[0080] The monitoring system may include (or may be formed from) at least a portion of the following components: a root monitor 190, satellite monitors 192(1)-192(19), sensors (S), and a network interconnection system 120. Monitor 190 is coupled to the network interconnection system 120 and may include circuitry configured to generate a reference voltage. The reference voltage generated by the root monitor 190 may be a trimmed and temperature-compensated voltage suitable for analog-to-digital conversion. In some embodiments, the root monitor 190 may be located within the processor system of device 100, for example, as... Figure 1 As shown. In other embodiments, the root monitor 190 may be located in other suitable locations within the device 100.

[0081] A reference voltage can be distributed to each satellite monitor 192(1)–192(19) via the network interconnection system 120, thereby eliminating the need to place multiple voltage generators at various locations of device 100 to provide a reference voltage to each satellite monitor 192(1)–192(19). In some embodiments, the network interconnection system 120 may include one or more analog channels for distributing the reference voltage from the root monitor 190 to each of the satellite monitors 192(1)–192(19), and may also include one or more digital channels for selectively routing digital data from the satellite monitors 192(1)–192(19) to the root monitor 190.

[0082] The sensor (S) can be any suitable sensing circuit or device that can generate an electrical signal indicating one or more operating conditions of at least one selected circuit, and may include (but is not limited to) a temperature sensor, a voltage sensor, and / or a current sensor. In some embodiments, each sensor (S) can measure the operating conditions of one or more selected circuits and can provide an analog signal indicating the measured operating conditions to a corresponding satellite monitor among satellite monitors 192(1)-192(19).

[0083] Satellite monitors 192(1)-192(19) can be any suitable circuit or device capable of converting analog signals generated by sensors (S) into digital data indicating the operating conditions of the measured quantity of a selected circuit. Although not detailed in the provided text... Figure 1 As shown, in some embodiments, each of the satellite monitors 192(1)-192(19) may include at least an analog-to-digital converter (ADC) and a memory. The ADC may be any suitable circuit capable of converting analog signals into digital data, and may include one or more inputs for receiving analog signals generated by a plurality of associated sensors (S); one or more outputs for providing indications of operating conditions measured by the associated sensors (S); and one or more references for receiving a local reference voltage. In some embodiments, the local reference voltage may be at least partially based on a reference voltage generated by the root monitor and distributed to the satellite monitors 192(1)-192(19) by the network interconnection system 120. The memory may store the digital data generated by the ADC and may provide the digital data to the network interconnection system 120 for routing to the root monitor.

[0084] For example, sensors (S) and satellite monitors 192(1)-192(19) can be distributed throughout the programmable device 100 and located at various locations near selected circuits so that analog signals indicating the operating conditions of the selected circuits can be converted into digital signals at each distributed location (instead of being transmitted to a central hub and then converted into digital data). In some embodiments, for example, each sensor (S) can be located near the corresponding selected circuit, such that the sensor (S) and the corresponding selected circuit can be coupled together using local signal lines. Similarly, for example, each of the satellite monitors 192(1)-192(19) can be located near one or more associated sensors (S), such that satellite monitor 192 and one or more associated sensors (S) can be coupled together using local signal lines. In some aspects, the term "nearby," as used herein, can refer to the distance over which analog signals indicating operating conditions are transmitted with minimal signal degradation via relatively short local signal lines.

[0085] For example, for Figure 1 For example, the first set of sensors (S) located within transceiver block 150 may be placed in the vicinity of a voltage source (not shown for simplicity) associated with transceiver block 150, and the first set of satellite monitors 192(1)–192(6) may be placed in the vicinity of the first set of sensors (S), such that each sensor in the first set of sensors (S) can be coupled to the corresponding power supply voltage and the corresponding satellite monitor 190 via a relatively short local signal line. In some embodiments, each sensor in the first set of sensors (S) may be configured to generate an analog signal indicating one or more operating conditions of the corresponding voltage power supply, and the first set of satellite monitors 192(1)–192(6) may be configured to convert the analog signals generated by the associated sensors (S) into digital data, which can be transmitted to the root monitor 190 via network interconnection system 120.

[0086] For example, a second set of sensors (S) located within PL 110 may be located within PL 110 or near a plurality of corresponding selected circuits (not shown for simplicity) associated with PL 110, and a second set of satellite monitors 192(7)–192(19) may be located near the second set of sensors (S) such that each sensor in the second set of sensors (S) can be coupled to the corresponding selected circuit and a corresponding satellite monitor in the second set of satellite monitors 192(7)–192(19) via a relatively short local signal line. In some embodiments, each sensor in the second set of sensors (S) may be configured to generate an analog signal indicating one or more operating conditions of the corresponding selected circuit, and each satellite monitor in the second set of satellite monitors 192(7)–192(19) may be configured to convert the analog signals generated by the associated sensors (S) into digital data, which can be transmitted to the root monitor 190 via the network interconnection system 120.

[0087] Each of the satellite monitors 192(1)-192(19) can be coupled to any suitable number of sensors (S) via a local signal line. For example, satellite monitor 192(1) can be coupled to a single sensor (S) located within transceiver block 150 and can generate digital signals indicating one or more operating conditions of the corresponding voltage power supply associated with transceiver block 150. As another example, satellite monitor 192(16) can be coupled to two sensors (S) located within PL 110 and can generate digital signals indicating one or more operating conditions of selected circuits associated with the two sensors (S) located within PL 110. As another example, satellite monitor 192(17) can be coupled to four sensors (S) located within PL 110 and can generate digital signals indicating one or more operating conditions of selected circuits associated with the four sensors (S) located within PL 110. Moreover, although Figure 1 The display includes 18 satellite monitors 192(1)-192(19), but the programmable device 100 may include other numbers of satellite monitors 192 located at other suitable locations within the programmable device 100.

[0088] As described above, satellite monitors 192(1)-192(19) can be placed close enough to the sensors (S) that each sensor (S) can be coupled to the corresponding satellite monitor 192 using a relatively short local signal line, instead of using a central system monitor to transmit analog signals over a relatively long distance for conversion to digital data. In this way, the implementation of the monitoring system disclosed herein eliminates the need for metal layer signal routing resources to route these analog signals from various locations distributed throughout device 100 to the central monitor for conversion to digital data, which reduces device complexity and cost while also increasing the scalability of the monitoring system. Furthermore, by using multiple satellite monitors 192(1)-192(19) distributed throughout device 100 to perform analog-to-digital conversion of the analog sensor data, and then routing the digital data to the root monitor 190 for analysis, the number of sensors that can be measured simultaneously is not limited by the number of ADC input channels provided within the satellite monitors. In contrast, the number of sensors that can be measured simultaneously by the conventional solution of routing analog sensor data to the central system monitor for conversion to digital data is limited by the number of ADC input channels associated with the system monitor. Therefore, by distributing the conversion of analog sensor data to digital information throughout the device 100 via satellite monitors 192(1)–192(19), the number of sensors that can be simultaneously measured by the monitoring system disclosed herein is based on the number of satellite monitors 192(1)–192(19), rather than the number of input channels of any particular ADC. As a result, the monitoring system disclosed herein can simultaneously measure far more sensors than the conventional solutions described above.

[0089] Root monitor 190 can receive digital data routed from each of the satellite monitors 192(1)-192(19) via network interconnection system 120, and can process the received digital data to determine the operating conditions of selected circuits monitored by sensors. In some embodiments, root monitor 190 can compare the measured operating conditions with one or more reference values ​​to determine whether each of the selected circuits is operating within its specified operating range.

[0090] It is important to note that Figure 1 This is intended to illustrate only one example architecture of the programmable device 100. For example, Figure 1 The number of logical blocks in the columns (or rows) shown, the relative width of the columns (or rows), the number and order of the columns (or rows), the types of logical blocks contained in the columns (or rows), the relative size of the logical blocks, and other architectural aspects are merely illustrative of various embodiments of the subject matter of the invention disclosed herein.

[0091] Figure 2A functional block diagram of a programmable device 200 according to some embodiments is shown. The programmable device 200 may be... Figure 1 An example of a programmable device 100. Device 200 is shown as including a transceiver block 150, a programmable logic (PL) 210, a CPM 220, a processing system (PS) 230, a platform management controller (PMC) 240, and an I / O block + memory controller 260. PL 210 may be... Figure 1 One embodiment of PL 110 can be adjacent to and directly connected to transceiver block 150, CPM 220, PMC 240, and network interconnect system 120. I / O block + storage controller 260 can be... Figure 1 One embodiment of the I / O block 160 and memory controller 170 can be implemented as a plurality of repeatable patches arranged along the bottom edge of the programmable device 200. Although Figure 2 For simplicity, it is not shown, but the I / O block + memory controller 260 can also be implemented as a plurality of repeatable patches arranged along the top edge of the programmable device 200. Alternatively, the I / O block + memory controller 260 can be implemented as a plurality of repeatable patches arranged along the right and left edges of the programmable device 200.

[0092] CPM 220 can be Figure 1 One embodiment of the CPM 140 provides interface capabilities for many different bus standards. In some embodiments, the CPM 220 may include a peripheral high-speed interconnect (PCIe) interface 222, direct memory access (DMA) circuitry 224, and a cache coherent interconnect (CCIX) interface 226 for accelerators. Data can be exchanged between the PS 230 and one or more other devices or chips via transceiver block 150 using the PCIe interface 222 according to the PCI protocol. Similarly, the CCIX interface 226 can be used to exchange data between the PS 230 and one or more other devices or chips via transceiver block 150 according to the CCIX protocol.

[0093] PS 230 can provide dedicated data processing capabilities for device 200 and is shown as including an application processing unit (APU) 232, a real-time processing unit (RPU) 234, a cache memory 236, and a system-on-a-chip (SoC) interface 238. Although not shown for simplicity, PS 230 may also include peripherals for communication standards (e.g., Ethernet and USB 2.0 interfaces) and various controllers (e.g., SPI, I2C, UART, and CAN-FD controllers). Each of APU 232 and RPU 234 may include one or more processing cores (e.g., a CPU) that can provide dedicated scalar processing capabilities for device 200. In some aspects, PS 230 can be selectively connected to other subsystems of device 200 via a programmable interconnect structure and network interconnect system 120.

[0094] In some embodiments, APU 232 may include a multi-core ARM processor supporting hardware virtualization and may have a built-in interrupt controller and monitoring control unit. The interrupt controller may support virtual interrupts and the monitoring control unit may be used to maintain consistency between one or more caches used and / or shared by APU 232 and RPU 234. APU 232 may communicate with other components of PS 230 via an AXI Coherence Extension (ACE) port and with PL 210 via an Accelerator Coherence Port (ACP). In some embodiments, RPU 234 may include a multi-core ARM processor supporting real-time data processing, may include a tightly coupled memory (TCM) interface for real-time single-cycle access, and may have a dedicated interrupt controller and floating-point unit. RPU 234 may communicate with other components of PS 230 and / or with PL 210 via an AXI port.

[0095] The cache memory 236 can be any suitable cache that allows shared access by the APU 232 and RPU 234. The SoC interface 238 can provide connectivity between the PS 230 and various resources of the network interconnect system 120.

[0096] PMC 240 may include Figure 1 The system includes a security circuit 242, a boot and reconfiguration circuit 244, an analog circuit 246, and a root monitor 190. The security circuit 242 can provide data encryption / decryption capabilities and other security features. The boot and reconfiguration circuit 244 can provide a multi-stage boot process supporting both insecure and secure boots. The analog circuit 246 can include any suitable analog circuit components. Furthermore, although for simplicity, [details omitted]. Figure 2As shown, PMC 240 may include test and debug resources (e.g., JTAG circuitry), external flash memory interfaces, and other components or circuitry. In some embodiments, PMC 240 may allow a portion of PL 210 to be reconfigured using a partial reconfiguration operation. For example, a new configuration bitstream for a portion of PL 210 may be loaded from PS 230 via a primary or secondary boot interface (e.g., PCIe or Ethernet) and then stored in a configuration register associated with the portion of PL 210 that needs to be reconfigured. The ability to allow partial reconfiguration of one or more portions of PL 210 allows users to reconfigure device 200 more quickly to reflect changes or updates to user-specified circuit designs (e.g., compared to other programmable devices).

[0097] Figure 3 A block diagram of an exemplary programmable structure 300 according to some embodiments is shown. In some embodiments, the programmable structure 300 may be Figure 1 PL 110, Figure 2 PL 210, or both. The programmable structure 300 is shown as comprising multiple different programmable circuit blocks or patches that can be arranged in columns (or rows). The programmable circuit blocks may include (but are not limited to) programmable interconnect elements (INTs) 310, configurable logic elements (CLEs) 320, DSPs 330, and block RAM (BRAM) 340 arranged in a columnar architecture. For Figure 3 For example, programmable structure 300 is shown as including eleven columns of programmable interconnect elements 310, five columns of CLEs 320, two columns of DSPs 330, and two columns of BRAMs 340. In other embodiments, programmable structure 300 may include other numbers of columns of programmable interconnect elements 310, CLEs 320, DSPs 330, and BRAMs 340. Programmable structure 300 may also include, for simplicity, […]. Figure 3 Several other subsystems or components (e.g., processing core, programmable interconnect structure, etc.) are not shown.

[0098] Programmable interconnect elements 310, CLE 320, DSP 330, and BRAM 340 can be implemented as repeatable patches across programmable structure 300. Each patch may include at least one programmable interconnect element 310 that can provide local signal interconnects to programmable logic elements within the same patch, to programmable interconnect elements 310 in adjacent patches, and / or to other signal routing resources. Programmable interconnect elements 310 may collectively form at least a portion of the programmable interconnect structure (or other suitable block-level and / or device-level signal routing structures).

[0099] In some embodiments, the programmable structure 300 may include a columnar hard block 350 extending vertically across the height of the programmable structure 300. The hard block 350 may include multiple hardwired circuits, such as a USB controller, an Ethernet MAC, a multi-rate (MR) Ethernet MAC, a PCIe controller, a CCIX controller, and / or other suitable circuitry or components implementing the physical layer, data link layer, and transaction layer of the PCIe protocol. In some embodiments, the hard block 350 may be as described above regarding... Figure 1 An embodiment of the described connection structure.

[0100] Figure 4 A functional block diagram of a monitoring system 400 according to some embodiments is shown. It can be... Figure 1 The monitoring system 400 implemented in the programmable device 100 is shown as including a root monitor 410, multiple satellite monitors SAT1-SAT15, multiple power supply voltage sensors SV1-SV4, multiple temperature sensors T5-T15, and multiple selected circuits CKT5-CKT15. The root monitor 410 may be... Figure 1 One embodiment of the root monitor 190 is coupled to the network interconnect system 120 and may include generating a reference voltage (V). REF The circuitry for generating a temperature-compensated reference voltage V. In some embodiments, the root monitor 410 may include a circuit for generating a temperature-compensated reference voltage V. REF The bandgap reference circuit (not shown for simplicity).

[0101] Satellite monitors SAT1-SAT15 can be distributed on device 100 and arranged such that each of the satellite monitors SAT1-SAT15 is located near a corresponding sensor among sensors SV1-SV4 and T5-T15. For Figure 4In an example embodiment, satellite monitors SAT1-SAT4 are coupled to their respective power supply voltage sensors SV1-SV4 via local signal lines, and satellite monitors SAT5-SAT15 are coupled to their respective temperature sensors T5-T15 via local signal lines. In this way, analog signals generated by power supply voltage sensors SV1-SV4 can be provided to each satellite monitor SAT1-SAT4 via local signal lines, and analog signals generated by temperature sensors T5-T15 can be provided to each satellite monitor SAT5-SAT15 via local signal lines. By placing satellite monitors SAT5-SAT15 close to (e.g., in the vicinity of) the associated sensors SV1-SV4 and T5-T15, the analog signals generated by sensors SV1-SV4 and T5-T15 do not need to be routed across most of device 100 to the root monitor 410, thereby minimizing the signal degradation associated with the relatively small amount of analog signal routing across the metal layer interconnects of device 100. Furthermore, because the analog signals generated by each sensor SV1-SV4 and T5-T15 can be locally converted into digital data using a nearby satellite monitor SAT1-STA15, there is no need for expensive metal layer routing resources in programmable devices (e.g., Figure 1 The monitoring system 400 is implemented within the programmable device 100.

[0102] For example, sensor SV1 can monitor the operating conditions of the associated power supply voltage by generating an analog signal indicating the voltage level of the associated power supply voltage. By placing the corresponding satellite monitor SAT1 near sensor SV1, the analog signal generated by sensor SV1 does not need to be routed through device 100 to root monitor 410, but can reach satellite monitor SAT1 over a relatively short distance via local signal lines. As another example, sensor T5 can monitor the operating conditions of associated circuit CKT5 by generating an analog signal indicating the temperature of associated circuit CKT5. By placing the corresponding satellite monitor SAT5 near sensor T5, the analog signal generated by sensor T5 does not need to be routed through device 100 to root monitor 410, but can reach satellite monitor SAT5 over a relatively short distance via local signal lines.

[0103] Reference voltage V REF The data can be distributed across device 100 and made accessible to each satellite monitor SAT1-STA15 via one or more dedicated analog channels of network interconnection system 120, and digital data can be selectively routed from each satellite monitor SAT1-STA15 to root monitor 410 via one or more digital channels of network interconnection system 120. In some embodiments, the one or more analog channels can be physically separated from the one or more digital channels.

[0104] Figure 5 A block diagram of an exemplary root monitor 500 according to some embodiments is shown. The root monitor 500 may be... Figure 1 Root monitor 190 or Figure 4 One embodiment of the root monitor 410 (or both) is shown as including a voltage generator 510, a memory 520, and a controller 530. The voltage generator 510 may be capable of generating a voltage V suitable for use as a reference voltage. REF Any suitable circuitry or device for fine-tuning the voltage, including one or more analog channels 121 coupled to the output of the network interconnect system 120. (Continue referring to...) Figure 1 In some embodiments, the reference voltage V generated by the voltage generator 510 can be transmitted via one or more analog channels 121 of the network interconnection system 120. REF Each of the satellite monitors 192(1)-192(19) located throughout the device 100 is assigned a reference voltage V. The satellite monitors 192(1)-192(19) can access the reference voltage V from the network interconnection system 120. REF And the assigned reference voltage V can be used. REF To perform analog-to-digital conversion (or for other appropriate operations).

[0105] In some embodiments, for example, voltage generator 510 may include bandgap circuit 512 capable of generating a temperature-compensated voltage to adjust the reference voltage V for temperature variations. REF Additionally, or alternatively, voltage generator 510 can provide positive and negative reference voltages to one or more analog channels 121 of network interconnect system 120. In some aspects, the reference voltage V REF It can be equal to 1.25 volts, although other suitable voltages can also be used as V. REF .

[0106] Memory 520 includes data inputs coupled to one or more digital channels 122 of network interconnect system 120, control inputs coupled to controller 530, data outputs coupled to controller 530, and one or more outputs from which a user can access the data stored therein via one or more of a JTAG interface, a multiplexed input / output (MIO) block, or an AXI interface. In some embodiments, memory 520 may include a plurality of status registers 521 and a plurality of alarm registers 522. Status registers 521 may store digital data indicating operating conditions of selected circuitry provided throughout device 100, and alarm registers 522 may store a plurality of reference values ​​defining a plurality of specified operating ranges. Status registers 521 may be loaded with digital data routed from satellite monitors 192(1)-192(19) to root monitor 500 via network interconnect system 120, and alarm registers 522 may be loaded with reference values ​​during configuration (or reconfiguration) of programmable device 100.

[0107] The controller 530 can control various operations of the root monitor 500, analyze digital data received from satellite monitors 192(1)-192(19) to determine if any selected circuit is not operating within its specified operating range, and generate result data accessible to the user. In some embodiments, the controller 530 can determine whether a selected circuit is operating within its specified operating range by comparing a measured operating condition stored in the status register 521 with a corresponding reference value stored in the alarm register 522. If the selected circuit is determined to be operating outside its specified operating range, the controller 530 can generate an alarm. For example, in some aspects, the alarm may disable or power down the selected circuit until the operating conditions of the selected circuit are within its specified operating range. For example, in other aspects, the alarm may power down or operate the programmable device 100 at a low power level until the operating conditions of the selected circuit are within its specified operating range.

[0108] Some specified operating ranges stored in alarm register 522 may be defined by minimum and maximum reference values. In some embodiments, the specified voltage range may include a minimum voltage value and a maximum voltage value. In these embodiments, controller 530 may compare the measured voltage of a selected circuit with the minimum and maximum voltage values ​​stored in alarm register 522 and may generate one or more alarms based on the comparison results. For example, if the measured voltage is between the minimum and maximum voltage values, controller 530 may instruct the selected circuit to operate within its specified voltage range. Conversely, if the measured voltage is less than the minimum voltage value or greater than the maximum voltage value, controller 530 may generate an alarm to indicate that the selected circuit is not operating within its specified voltage range.

[0109] Other specified operating ranges stored in alarm register 522 may include reference values ​​that define the upper limit of operation. In some embodiments, a specified temperature range for the selected circuit may be defined by a reference temperature value. In these embodiments, controller 530 may compare the measured temperature of the selected circuit with the reference temperature value stored in alarm register 522 and may generate one or more alarms based on the comparison result. For example, if the measured temperature is less than (or equal to) the reference temperature value, controller 530 may instruct the selected circuit to operate within its specified temperature range. Conversely, if the measured temperature is greater than the reference temperature value, controller 530 may generate an alarm to indicate that the selected circuit is too hot or overheated.

[0110] Figure 6 A block diagram of an example satellite monitor 600 according to some embodiments is shown. The satellite monitor 600 may be... Figure 1 Any number of satellite monitors 192(1)-192(19) or Figure 4 An example of a satellite monitor SAT1-SAT15 (or both) includes data inputs coupled to one or more sensors 20, outputs coupled to a network interconnection system 120, and a reference terminal coupled to the network interconnection system 120 via a first switch SW1. (Continue to the previous section) Figure 1 and Figure 5 In some embodiments, the satellite monitor 600 may receive a reference voltage V generated by the root monitor 500 and distributed via a first switch SW1 by one or more analog channels 121 of the network interconnection system 120. REF In some aspects, sensor 20 may include (but is not limited to) a temperature sensor 21, a power supply voltage sensor 22, and an external sensor 23.

[0111] exist Figure 6 In the example, satellite monitor 600 is shown to include ADC circuitry 610, memory 620, and local reference circuitry 630. ADC circuitry 610 includes an input coupled to one or more sensors 20 via a second switch SW2, an output coupled to memory 620, and one or more references coupled to local reference circuitry 630. ADC circuitry 610 can be (or may include) any suitable ADC that can convert analog signals generated by one or more sensors 20 into digital signals or digital data. In some embodiments, ADC circuitry 610 may utilize a scaling architecture to digitize analog sensing data provided by the sensors 20.

[0112] The memory 620 can be any suitable storage device, including an input coupled to the output of the ADC circuit 610 and an output coupled to the network interconnect system 120. The memory 620 can store digital data generated by the ADC circuit 610 in response to analog signals provided by one or more sensors 20, and can provide the digital data to one or more digital channels 122 of the network interconnect system 120 for routing. Figure 5 The root monitor 500. In some embodiments, the memory 620 may be or may include multiple registers, each for storing digital data indicating the operating conditions of a corresponding circuit among a plurality of circuits selected for monitoring. In this way, the satellite monitor 600 can receive analog signals from the sensor 20 indicating the operating conditions of a corresponding circuit among the selected circuits, convert the analog signals into digital data, and provide the digital data indicating the operating conditions of the selected circuit to one or more digital channels 122 of the network interconnection system 120.

[0113] The local reference circuit 630, coupled between the first switch SW1 and one or more reference terminals of the satellite monitor 600, can be capable of providing a local reference voltage (V) to the ADC circuit 610. REF_LOCAL Any suitable device or component. In some embodiments, the local reference voltage V REF_LOCAL It can be based at least in part on the reference voltage V allocated by the network interconnection system 120. REF It can be used by the ADC circuit 610 to perform analog-to-digital conversion.

[0114] The first switch SW1 can be configured to distribute the reference voltage V allocated by the network interconnection system 120 based on the first control signal (CTRL1). REF Selectively coupled to satellite monitor 600. In some embodiments, when the first control signal CTRL1 is in an assertion state (e.g., logic high), the first switch SW1 can couple the reference terminal of satellite monitor 600 to network interconnect system 120, and when the first control signal CTRL1 is in a deassertion state (e.g., logic low), the first switch SW1 can isolate satellite monitor 600 from network interconnect system 120. In this way, the first switch SW1 can be used to control when (and for how long) satellite monitor 600 acquires the reference voltage V allocated by network interconnect system 120. REF .

[0115] The first control signal CTRL1 can be generated by Figure 5 The root monitor 500 is generated and can be routed to the satellite monitor 600 via the network interconnection system 120 (or via other suitable signal interconnection). See also... Figure 1 and Figure 5In some embodiments, the root monitor 500 may assert a first control signal CTRL1 for each of a plurality of satellite monitors 600 distributed on a programmable device based on, for example, a timing table, such that only one satellite monitor 600 can acquire the assigned reference voltage V via the network interconnection system 120 at any given time. REF In this way, the root monitor 500 can prevent the assigned reference voltage V from being acquired simultaneously by more than one satellite monitor 600. REF The resulting distributed reference voltage V REF decline.

[0116] The second switch SW2 can selectively couple one of the sensors 21-23 to the input of the ADC circuit 610 based on a second control signal (CTRL2). In some embodiments, the second control signal CTRL2 can be generated by... Figure 5 The root monitor 500 is generated and can be routed to the satellite monitor 600 via the network interconnection system 120 (or via other suitable signal interconnection).

[0117] Figure 7 This is an illustrative flowchart depicting an exemplary operation 700 for monitoring multiple operating conditions of a programmable device according to some embodiments. The following is for... Figure 1 Programmable device 100 Figure 4 400 surveillance system Figure 5 Root monitor 500, and Figure 6 The satellite monitor 600 describes exemplary operation 700 for illustrative purposes only. It should be understood that exemplary operation 700 can be performed by other programmable devices and / or other suitable devices disclosed herein.

[0118] Operation 700 can generate a reference voltage (V) by using a voltage generator 510 associated with a root monitor 190 provided within the programmable device 100. REF It begins at block 701. For example, in some embodiments, the root monitor 190 can be configured using... Figure 5 The bandgap circuit 512 generates a trimmed and temperature-compensated reference voltage V. REF .

[0119] Operation 700 can use one or more analog channels 121 of interconnect system 120 to transmit the reference voltage V from root monitor 190. REF The assignment to each of the multiple satellite monitors 192 is performed at block 702. In some embodiments, a reference voltage V is assigned. REFThis may include selectively coupling each of the multiple satellite monitors 192(1)-192(19) to the interconnect system 120 based on the corresponding control signal CTRL1 generated by the root monitor 190. In some aspects, Figure 6 The first switch SW1 allows the satellite monitor 600 to acquire a reference voltage V from the network interconnection system 120 based on the first state of CTRL1. REF Furthermore, the first switch SW1 can isolate the satellite monitor 600 from the network interconnection system 120 based on the second state of CTRL1.

[0120] Operation 700 can be performed at block 703 by generating an analog signal indicating the operating conditions of the associated circuit using each of the plurality of sensors 20. In some embodiments, each of the plurality of sensors 20 may be located near the associated circuit. In some aspects, the sensor 20 may be (or may include) at least one of a temperature sensor 21, a power supply voltage sensor 22, or an external sensor 23.

[0121] Operation 700 can be performed at block 704 by providing analog signals generated by the multiple sensors 20 to the respective satellite monitors among the multiple satellite monitors 192(1)-192(19). For example, in some embodiments, the analog signals generated by the sensors 20 can be provided to the respective satellite monitors 192(1)-192(19) using relatively short local signal lines, compared to conventional programmable devices that route analog signals indicating the operating conditions of various circuits across the device and provide them to the central monitor using a metal layer signal routing structure.

[0122] Operation 700 can be performed at block 705 by using multiple satellite monitors 192(1)-192(19) to convert analog signals into digital data. See also... Figure 6 An ADC circuit 610 provided in each satellite monitor 192(1)-192(19) can convert analog signals into digital data (19) that can be stored in a memory 620 in each satellite monitor 192(1)-192. The memory 620 can selectively provide the stored digital data to the interconnect system 120 for routing to the root monitor 190.

[0123] Operation 700 can be performed at block 706 by selectively routing digital data from multiple satellite monitors 192(1)-192(19) to the root monitor 190 using one or more digital channels 122 of the interconnection system 120. (Continue to reference) Figure 4Digital channel 122 may be physically separated from analog channel 121 of interconnect system 120. For example, in some embodiments, satellite monitors 192(1)-192(19) may provide digital data to interconnect system 120 in response to a signal (e.g., a trigger signal) generated by root monitor 190 for scheduling or prioritizing the transmission of digital data from multiple satellite monitors 192(1)-192(19) to root monitor 190. In other embodiments, satellite monitors 192(1)-192(19) may provide digital data to interconnect system 120 without prompting and / or without control of root monitor 190.

[0124] Operation 700 can be performed at block 707 by determining whether the operating conditions of at least one circuit in the associated circuit are within range, and can be performed at block 708 by selectively generating alarms based on this determination. (Continue to refer to...) Figure 5 The root monitor 500 may receive digital data from one of the satellite monitors 192(1)-192(19) and may compare the received digital data with one or more reference values ​​to determine whether the operating conditions of the associated circuit are within range. In some embodiments, the root monitor 500 may generate an alarm and / or may shut down one or more portions of the programmable device 100 (or the entire programmable device 100 if multiple different circuits, blocks and subsystems do not remain within their specified operating parameters).

[0125] For embodiments where an analog signal indicates the voltage of an associated circuit (e.g., a voltage supply), root monitor 500 can compare the measured voltage of the associated circuit with a minimum reference voltage level and a maximum reference voltage level. If the measured voltage of the associated circuit is between the minimum and maximum reference voltage levels, root monitor 190 can determine that the associated circuit is operating within the specified voltage range. Conversely, if the measured voltage of the associated circuit is less than the minimum reference voltage level or greater than the maximum reference voltage level, root monitor 190 can determine that the associated circuit is not operating within the specified voltage range.

[0126] In embodiments where an analog signal indicates the temperature of the associated circuit, root monitor 500 can compare the measured temperature of the associated circuit with a reference temperature value. If the measured temperature of the associated circuit is not greater than the reference temperature value, root monitor 190 can determine that the associated circuit is operating within its specified temperature range. Conversely, if the measured temperature of the associated circuit is greater than the reference temperature value, root monitor 190 can determine that the associated circuit is not operating within the specified temperature range.

[0127] Embodiments of the subject matter described herein can be used to monitor multiple operating conditions of a programmable device. Operating conditions can be any suitable measure of the device's operating characteristics or parameters, including, for example, the temperature of circuitry or components provided within the programmable device, the temperature of circuitry or components external to the programmable device, power supply voltage, etc. According to some aspects of the disclosure herein, the monitoring system may include a root monitor, multiple sensors distributed at various locations of the programmable device, and multiple satellite monitors distributed at various locations of the programmable device. The root monitor may include a bandgap voltage generator configured to generate a highly accurate and temperature-independent reference voltage, and the temperature-independent reference voltage can be distributed from the root monitor to each satellite monitor via one or more analog channels spanning the programmable logic.

[0128] Each sensor can generate an analog signal indicating one or more operating conditions of associated circuitry, and can provide the analog signal to a corresponding satellite monitor via one or more local signal lines. For example, each satellite monitor may include an ADC for converting the analog signal into digital data, and may be placed near one or more associated sensors such that the analog signal generated by the one or more associated sensors can be routed via local signal lines over a relatively short distance to the corresponding satellite monitor for conversion into digital data. In some embodiments, the programmable device may include a network-on-chip (NoC) interconnect system that can selectively route digital data from each satellite monitor to a root monitor for processing, and can route control signals and other information from the root monitor to each satellite monitor. Furthermore, or alternatively, other suitable routing resources provided within the device can be used to route the digital data generated by each satellite monitor to the root monitor; these resources include (but are not limited to) clock distribution networks, programmable interconnect structures, and / or routing resources provided within repeatable patches of programmable logic forming the device.

[0129] The accuracy of thermal and voltage monitoring by multiple sensors distributed across a programmable device depends on the accurate analog-to-digital conversion (ADC) of each of the multiple satellite monitors distributed across the programmable device. The accuracy of the ADC can be based, at least in part, on the accuracy of the reference voltage supplied to the ADC within each satellite monitor. While bandgap voltage generators can be used to generate highly accurate and temperature-independent reference voltages, they consume significant circuit area and require expensive and time-consuming trimming during the fabrication of the programmable device.

[0130] To avoid the silicon cost of providing an accurate reference voltage for each of multiple satellite monitors distributed across devices, and to eliminate the need to trim the corresponding multiple voltage generators, each satellite monitor may include a relatively small voltage source (e.g., an area-efficient voltage source) configured to generate a local reference voltage for the corresponding ADC. The local voltage source may be relatively small compared to the bandgap voltage generator provided in the root monitor, and therefore "area-efficient." In some embodiments, the local voltage source may include fewer than a dozen transistors and may consume at least an order of magnitude less circuit area than a bandgap voltage generator. In some embodiments, each satellite monitor may include a local voltage memory configured to store the local reference voltage of the corresponding ADC. The local voltage memory may consist of capacitors coupled to a switch (e.g., a transistor).

[0131] Compared to the high-precision, temperature-independent reference voltage generated by the bandgap voltage generator, the local reference voltage may be relatively inaccurate and may cause errors in the digital code generated by the ADC provided in the respective satellite monitor. In some embodiments, each satellite monitor may include calibration circuitry configured to generate a correction factor indicating errors in the digital code, and may also include correction circuitry configured to correct the digital code based on the correction factor. The ADCs provided in multiple satellite monitors can be periodically calibrated relative to the high-precision, temperature-independent reference voltage by their respective calibration and correction circuitry, as described in more detail below.

[0132] Conventional systems for monitoring the operating conditions of various circuits distributed across a programmable device typically consist of a central system monitor and multiple sensors located near the circuits to be monitored. Each sensor generates an analog signal indicating the operating conditions of the associated circuitry, and these analog signals are routed from each sensor to the system monitor for conversion into digital data. Since the sensors are typically distributed throughout the device, the analog signals generated by at least some of them can be routed across a large portion of the device to the system monitor. Because the analog signals indicating operating conditions can be particularly susceptible to noise and interference, some programmable devices can utilize dedicated metal layers with shielding properties to route these analog signals from the various sensors to the system monitor for conversion into digital data.

[0133] While the shielding properties of dedicated metal layer routing resources can reduce signal attenuation and data loss, these resources are expensive and consume significant amounts of device metal layers. Furthermore, because programmable logic is typically implemented as multiple repeatable tiles arranged in multiple rows or columns, the signal routing resources embedded in each repeatable tile are often based on worst-case routing scenarios (e.g., for tiles placed in locations with the highest device density). As a result, many repeatable tiles are over-configured with signal routing resources, which can lead to unused routing resources and / or potentially limit the scalability of programmable devices.

[0134] By deploying multiple satellite monitors close to sensors monitoring the operating conditions of various circuits throughout the programmable device, the monitoring system disclosed herein can convert analog signals generated by the sensors into digital data using local satellite monitors, and then route the digital data from various locations throughout the device to the root monitor. Therefore, instead of routing analog signals across a large area of ​​the device and then converting them to digital data, the analog signals are transmitted over a relatively short distance to the nearest satellite monitor for conversion to digital data, and then routed to the root monitor using a NoC interconnect system. In some aspects, the digital data generated by the satellite monitors can be routed to the root monitor as individually addressable data packets. In other aspects, the digital data generated by the satellite monitors can be routed to the root monitor as unpacked data. By using satellite monitors located near the sensors to convert analog signals to digital data, instead of performing analog-to-digital conversion in the root monitor, the monitoring system disclosed herein eliminates the need for metal layer routing resources, which in turn reduces costs while increasing the scalability of the programmable device. Furthermore, performing analog-to-digital conversion locally (e.g., near the sensor) and routing the resulting digital data from the satellite monitor to the root monitor can allow the root monitor to collect and analyze more sensor data (compared to existing techniques that route analog signals from various sensors located throughout the device to an ADC provided within the system monitor), because the ADC distributed throughout the programmable device can perform analog-to-digital conversion in parallel (e.g., simultaneously).

[0135] In the following description, numerous specific details, such as examples of specific components, circuits, and processes, are set forth to provide a thorough understanding of this disclosure. As used herein, the term “coupled” means directly coupled to or coupled through one or more intermediary components or circuits. Furthermore, specific nomenclature and / or details are set forth in the following description and for illustrative purposes to provide a thorough understanding of exemplary embodiments. However, these specific details will be apparent to those skilled in the art and may not be necessary for practicing the exemplary embodiments. In other instances, well-known circuits and devices are shown in block diagram form to avoid obfuscation with this disclosure. Any signal provided via the various buses described herein may be time-multiplexed with other signals and provided via one or more common buses. Furthermore, interconnections between circuit elements or software blocks may be shown as buses or single signal lines. Each bus may be replaced by a single signal line, and each single signal line may be replaced by a bus, and a single line or bus may represent any one or more of a multitude of physical or logical mechanisms for communication between components. Exemplary embodiments should not be construed as limited to the specific examples described herein, but rather all embodiments defined by the appended claims are included within their scope.

[0136] Figure 8 A block diagram of an exemplary programmable device 800 in which various aspects of the present disclosure may be implemented is shown. Device 800 may include multiple subsystems, such as programmable logic (PL) 810, a network-on-chip (NoC) interconnect system 820 spanning PL 810, one or more analog channels 821 spanning PL 810, dedicated circuitry 830, CCIX and PCIe modules (CPM) 840, transceiver block 850, input / output (I / O) block 860, memory controller 870, configuration logic 880, root monitor 890, multiple satellite monitors 892(1)-892(19), and multiple sensors (S). In one or more embodiments, device 800 may include... Figure 8 Other subsystems or components not shown. Furthermore, although not shown for simplicity, device 800 may be coupled to multiple peripheral components (e.g., high-performance memory devices) and / or other devices or chips (e.g., another programmable device).

[0137] PL 810 includes programmable circuitry that can be configured or programmed to perform a variety of different user-defined functions or operations. In some embodiments, such as... Figure 8As described herein, PL 810 may include a plurality of programmable circuit blocks implemented as repeatable patches arranged in columns within programmable device 800. The programmable circuit blocks may also be referred to as programmable structure sub-regions (FSRs), each of which may include programmable interconnect circuitry and programmable logic circuitry. In some embodiments, the programmable circuit blocks may include (but are not limited to) configurable logic blocks (CLBs), random access memory blocks (BRAMs), digital signal processing blocks (DSPs), clock managers, delay phase-locked loops (DLLs), and / or other logic or circuitry that can be programmed or configured to implement a user-specified circuit design.

[0138] Each programmable interconnect circuit within a programmable block or patch may include multiple interconnects of varying lengths, interconnected via programmable interconnect points (PIPs). These interconnects can be configured to provide connectivity between components within a specific programmable patch, between components in different programmable patches, and between components of a programmable patch and other subsystems or devices. Programmable interconnect circuits and programmable blocks can be programmed or configured by loading configuration data into configuration registers, which define how programmable elements are configured and operated to implement a corresponding user-specified circuit design. In some aspects, the programmable interconnect circuitry within each of multiple programmable blocks may form part of a programmable interconnect structure (not shown for simplicity) that provides block-level and / or device-level signal routing resources for device 800.

[0139] The NoC interconnect system 820 can be manufactured as part of device 800 and may include any number of horizontal and vertical segments (and / or diagonal segments) connected together to enable a high-speed, high-bandwidth programmable signal routing network that can selectively interconnect various device resources (e.g., PL 810, dedicated circuitry 830, CPM 840, transceiver block 850, I / O block 860, memory controller 870, configuration logic 880, root monitor 890, and satellite monitors 892(1)–892(19)) with each other and with other components not shown for simplicity. Figure 8In an example embodiment, the NoC interconnect system 820 is shown to include two horizontal segments and four vertical segments. A first horizontal segment extending across the width of device 800 is positioned along the bottom boundary of device 800, and a second horizontal segment extending across the width of device 800 is positioned along the top boundary of device 800. Four vertical segments extend across the height of device 800 and connect to the first and second horizontal segments of the NoC interconnect system 820. In some aspects, the horizontal segments may allow the NoC interconnect system 820 to exchange signals and data with I / O block 860 and memory controller 870 without any intermediate circuitry or interfaces, and the vertical segments may allow the NoC interconnect system 820 to exchange signals and data with transceiver block 850, dedicated circuitry 830, and CPM 840 without any intermediate circuitry or interfaces. In other embodiments, the NoC interconnect system 820 may include other numbers of horizontal and vertical segments, which in turn may occupy other locations on device 800. Therefore, Figure 8 The specific layout, shape, size, orientation, and other physical characteristics of the example NoC interconnect system 820 depicted herein are merely illustrative of the various embodiments disclosed herein.

[0140] The NoC interconnect system 820 can be configured to transmit information as data packets between various device resources, and these data packets can be individually addressed and routed from source locations to destination locations. In some aspects, data packets transmitted on the NoC interconnect system 820 can be dynamically addressable. In one or more embodiments, the NoC interconnect system 820 can employ a suitable data packet protocol (e.g., token ring protocol) and / or use memory-mapped addresses to route data packets from any number of source locations to any number of destination locations. Data packets may include header information (e.g., source address, destination address, and protocol information) that can be used by the NoC interconnect system 820 to route data packets to their indicated destinations.

[0141] In some embodiments, data packets may include priority quality of service (QoS) information that allows data packet transmission via the NoC interconnect system 820, such as based on assigned priority, service type, service flow, and / or other criteria. In these embodiments, the NoC interconnect system 820 may include priority logic that can determine the priority or service class of received data packets and use the determined priority or service class when queuing data packets for transmission. As individually addressable data packets, the NoC interconnect system 820 can provide connectivity between various device resources by transmitting information between them, regardless of a specific user-specified circuit design, thereby significantly improving the signal routing capability of device 800 (compared to conventional programmable devices). For example, while the programmable interconnect structure of device 800 and other surface-mount-based signal routing structures are typically configured to provide point-to-point signaling connections between specified circuits, the NoC interconnect system 820 can simultaneously route each of multiple data packets from any source address on device 800 to any destination address, thereby providing system-level connectivity for device 800.

[0142] Although not shown for simplicity, the NoC interconnect system 820 may also include a scheduler and decision-making logic. The scheduler can be used to schedule packet transmissions from a source address to a destination address using one or more physical and / or virtual channels of the NoC interconnect system 820. The decision-making logic can be used to decide access to the NoC interconnect system 820, for example, minimizing collisions and other contention-related latency. In embodiments where the device 800 is fabricated using Stacked Silicon Interconnect (SSI) technology, the column portions of the NoC interconnect system 820 may provide signaling connections between adjacent Super Logic Regions (SLRs), for example, to allow configuration data to be routed between the master SLR and slave SLRs.

[0143] The NoC interconnect system 820 can be programmed by loading configuration data into appropriate configuration registers, which define how various switches, interfaces, and routers within or associated with the NoC interconnect system 820 are configured to implement a specific user-specified circuit design. In some embodiments, the NoC interconnect system 820 may include multiple nodes, ports, or other interfaces (not shown for simplicity) that provide selective connectivity between the NoC interconnect system 820 and various resources, subsystems, circuits, and other components of device 800. For example, the NoC interconnect system 820 may allow multiple subsystems of device 800 to share access to on-chip memory (OCM) resources, processing resources, I / O resources, and / or transceiver block 850. The nodes, ports, or other interfaces of the NoC interconnect system 820 can be programmed to implement specific connectivity profiles by loading configuration data into one or more associated configuration registers.

[0144] By selectively interconnecting various resources, subsystems, circuits, and other components of device 800 that may require and use large amounts of data, the NoC interconnect system 820 can alleviate the signal routing burden on local interconnect resources, thereby improving device performance and allowing for greater configuration flexibility than other programmable devices. Furthermore, by providing a high-performance signal routing network with higher data transfer rates and lower error rates than device-level and block-level programmable interconnects, the NoC interconnect system 820 can improve the processing power and data throughput of device 800 (as compared to other programmable devices).

[0145] An analog channel 821 spanning the programmable device 800 can be used to distribute a high-precision, temperature-independent reference voltage from the root monitor 890 to each of the plurality of satellite monitors 892(1)-892(19). In some embodiments, the analog channel 821 may be adjacent to (or integrated therein) a corresponding segment of the NoC interconnect system 820. In other embodiments, the analog channel 821 may be separate from the NoC interconnect system 820. In some other embodiments, the analog channel 821 may be part of a clock distribution network or some other suitable signal interconnect system provided within the device 800.

[0146] The dedicated circuit 830 may include any suitable hardwired circuitry, including (but not limited to) a processor, serial transceiver, digital signal processor (DSP), analog-to-digital converter (ADC), digital-to-analog converter (DAC), device management resources, device monitoring resources, device test management resources, etc. In some embodiments, the dedicated circuit 830 may include, for example, Figure 9 The described processing system (PS) and platform management controller (PMC) are described. In some embodiments, the PS may include one or more processor cores, cache memory, a memory controller, and unidirectional and / or bidirectional interfaces configurable to be directly coupled to I / O pins of device 800. In some aspects, each processor core may include a central processing unit (CPU) or a scalar processor that can be used for sequential data processing. The PMC may boot and configure device 800 based on configuration data (e.g., configuration bitstream) provided from external memory. The PMC may also be used to configure PL 810 and control various encryption, authentication, root monitoring, and debugging capabilities of device 800.

[0147] The CCIX and PCIe module (CPM) 840 may include multiple interfaces providing connectivity between device 800 and multiple peripheral components (e.g., external devices or chips). In some embodiments, the CPM 840 may include multiple peripheral high-speed interconnect (PCIe) interfaces and cache coherent interconnect (CCIX) interfaces for accelerators that provide connectivity to other devices or chips via transceiver block 850. In some aspects, the PCIe and CCIX interfaces may be implemented as part of transceiver block 850. An exemplary embodiment of the CPM 840 is as follows: Figure 9 As described.

[0148] Transceiver block 850 can provide signal connectivity to one or more other devices or chips (not shown for simplicity) connected to device 800. Transceiver block 850 may include many different serial transceivers, such as gigabit serial transceivers (GTs). In some embodiments, transceiver block 850 may be implemented as multiple repeatable patches placed at various locations along the right and left sides of device 800, such as... Figure 8 As shown. In other embodiments, transceiver block 850 may be located at other suitable locations within device 800. In one or more embodiments, each transceiver block 850 may be coupled to one or more associated voltage sources (not shown for simplicity). In some aspects, for example, each set of transceiver circuitry within a given transceiver block 850 may include or may be coupled to a corresponding voltage power supply, such that each set of transceiver circuitry can be powered using a separate voltage power supply.

[0149] I / O block 860 is coupled to the I / O pins of the device (not shown for simplicity) and can provide I / O capabilities to device 800. For example, I / O block 860 can receive data from one or more other devices and can drive the received data to multiple destinations within device 800. I / O block 860 can also receive data from multiple sources within device 800 and can drive the received data to one or more other devices via the device's I / O pins. In some embodiments, I / O block 860 can be implemented as a repeatable patch. Device 800 can include any suitable number of I / O blocks 860, therefore Figure 8 The exemplary embodiments depicted are merely illustrative.

[0150] I / O block 860 may include any number of suitable I / O circuits or devices. In some embodiments, I / O block 860 may include ultra-high performance I / O (XPIO) circuitry, high-density I / O (HDIO) circuitry, and multiplexed I / O (MIO) circuitry. XPIO circuitry may be optimized for high-performance communication, such as providing a high-speed, low-latency interface to memory controller 870. In one or more embodiments, XPIO circuitry may include dedicated memory resources accessible to other subsystems of device 800 without using memory controller 870. HDIO circuitry may provide a cost-effective solution (compared to XPIO circuitry) that supports lower speed and higher voltage I / O capabilities. MIO circuitry may provide general-purpose I / O resources accessible by various subsystems, such as PL 810, dedicated circuitry 830, and CPM 840.

[0151] The memory controller 870 can be used to control access to various memory resources provided internally and / or externally to the device 800. In some embodiments, the memory controller 870 can be used to access dedicated memory residing in one or more I / O blocks 860. The memory controller 870 may include a Double Data Rate v4 (DDR4) memory controller, a High Bandwidth Memory (HBM) controller, and / or other suitable memory controllers. In one or more embodiments, some or all of the memory controllers 870 may include a scheduler with transaction reordering capabilities that can improve memory access efficiency. Furthermore, or alternatively, repeatable patches implementing the memory controllers 870 can be different from each other. For example, a first number of memory controllers 870 may be implemented as DDR4 memory controllers, a second number of memory controllers 870 may be implemented as LPDDR4 memory controllers, and a third number of memory controllers 870 may be implemented as HBM controllers.

[0152] Device 800 may include any number of I / O blocks 860 and memory controller 870, therefore Figure 8 The number and location of the I / O blocks 860 and memory controllers 870 depicted are merely illustrative. In some embodiments, the I / O blocks 860 and memory controllers 870 in the first row may be implemented as repeatable patches disposed along the bottom edge of the device 800, and the I / O blocks 860 and memory controllers 870 in the second row may be implemented as repeatable patches disposed along the top edge of the device 800. In some embodiments, the I / O blocks 860 and memory controllers 870 may be alternately arranged or distributed relative to each other, for example, as shown in the diagram. Figure 8 As depicted in the example. In other embodiments, a pair of I / O blocks 860 and a memory controller 870 may be implemented within the same repeatable patch.

[0153] In some embodiments, a first row of I / O blocks 860 and memory controller 870 disposed along the bottom of device 800 may be coupled to a first horizontal segment of NoC interconnect system 820, and a second row of I / O blocks 860 and memory controller 870 disposed along the top of device 800 may be coupled to a second horizontal segment of NoC interconnect system 820. In this way, NoC interconnect system 820 can provide connectivity between the programmable resources of device 800 and its I / O pins (not shown for simplicity).

[0154] In some embodiments, device 800 may include one or more columns of connection structures (not shown for simplicity) extending vertically through the height of device 800 and located near transceiver block 850. The connection structures may include one or more hardwired circuits, including (but not limited to) a USB controller, an Ethernet MAC, a multi-rate (MR) Ethernet MAC (MRMAC), a PCIe controller, a CCIX controller, and / or other components used to provide a connection between transceiver block 850 and PL 810.

[0155] Configuration logic 880 can be used to load configuration data (e.g., a configuration bitstream) from external memory and route portions of the configuration data (e.g., frames, words, bytes, and / or bits) to appropriate configuration registers that define how to configure various programmable resources of device 800. Configuration logic 880 can also be used to partially reconfigure device 800 and / or internally reconfigure one or more portions of device 800. In some embodiments, configuration logic 880 may include configuration registers, boundary scan test circuitry (e.g., TAP controller circuitry), encryption circuitry for encrypting the bitstream of configuration data read from device 800, and decryption circuitry for decrypting the bitstream of configuration data loaded into device 800.

[0156] Although not shown for simplicity, device 800 may include an interface between the programmable structure and each row of I / O blocks 860, and a memory controller 870 located at the boundary of device 800. This interface may be referred to herein as a boundary logic interface (BLI), which allows large and complex external devices (e.g., HBMs) to appear as smaller blocks (e.g., CLBs) within the programmable structure of device 800. In some embodiments, the BLI may be arranged in rows at the top and bottom boundaries or edges of the programmable structure. In this way, the BLI can be used to route signals between columnar logic structures (e.g., CLB columns or DSP columns) and I / O resource rows (e.g., I / O blocks 860).

[0157] According to various aspects of this disclosure, programmable device 800 may include a monitoring system capable of monitoring one or more operating conditions across a plurality of selected circuits provided by programmable device 800, for example, to ensure that the selected circuits operate within a specified range of operating parameters. The monitoring system disclosed herein can measure any suitable operating conditions of the selected circuits, including, for example, temperature, voltage levels, and current levels. As used herein, the term "selected circuit" can refer to any circuit, component, power supply voltage, structure, or device that can be selected for monitoring one or more operating conditions to ensure proper operation of device 800. In some embodiments, the monitoring system may generate an alarm (or multiple alarms) when the measured operating conditions of one or more selected circuits do not fall within a specified range of operating conditions. In some aspects, the alarm may be used to de-energize one or more circuits or components of device 800. In other aspects, the alarm may be used to de-energize the entire device 800.

[0158] The monitoring system may include (or may consist of) a root monitor 890, satellite monitors 892(1)-892(19), and sensors (S). The root monitor 890 is coupled to the NoC interconnect system 820 and the analog channel 821, and may include circuitry configured to generate a high-precision, temperature-independent reference voltage. The temperature-independent reference voltage can be distributed to each satellite monitor 892(1)-892(19) via one or more analog channels 821, thereby eliminating the need for each satellite monitor 892(1)-892(19) to generate its own high-precision, temperature-independent reference voltage. For example, as... Figure 8 As shown, in some embodiments, the root monitor 890 may be located within the processor system of the device 800. In other embodiments, the root monitor 890 may be located in other suitable locations within the device 800.

[0159] The sensor (S) can be any suitable sensing circuit or device capable of generating an electrical signal indicating one or more operating conditions of at least one circuit in the selected circuits, and may include (but is not limited to) a temperature sensor, a voltage sensor, and / or a current sensor. In some embodiments, each sensor (S) can measure the operating conditions of one or more selected circuits and can provide an analog signal indicating the measured operating conditions to a corresponding satellite monitor in satellite monitors 892(1)-892(19).

[0160] Satellite monitors 892(1)-892(19) can be any suitable circuit or device that can convert analog signals generated by a sensor (S) into digital data indicating the measurement operating conditions of a selected circuit. Although not in Figure 8As shown, but for simplicity, in some embodiments, each of the satellite monitors 892(1)-892(19) may include at least one analog-to-digital converter (ADC), a local voltage source having a relatively small size (e.g., compared to a bandgap voltage generator), calibration circuitry, and correction circuitry. The ADC may be any suitable circuitry capable of converting analog signals into digital data, and may include one or more inputs for receiving analog signals generated by one or more associated sensors (S), one or more outputs for providing digital data indicating operating conditions measured by the associated sensors (S), and one or more references for receiving a local reference voltage. In some embodiments, each of the satellite monitors 192(1)-192(19) may include at least an analog-to-digital converter (ADC), a local voltage memory configured to store the local reference voltage of the respective ADC, calibration circuitry, and correction circuitry. For the local voltage memory, it may be a capacitor or, in some embodiments employing capacitors, the local voltage memory has a relatively small size compared to a bandgap voltage generator. In some embodiments, the circuit area consumed by the local voltage memory may be at least an order of magnitude smaller than that consumed by the bandgap voltage generator. The voltage memory can be selectively coupled to one or more analog channels to charge the voltage memory to a value approximately equal to a temperature-independent reference voltage. The charge generated in the voltage memory can be a local reference voltage supplied to the reference terminal of the ADC.

[0161] A local voltage source can generate a local reference voltage, which may be relatively inaccurate compared to a highly accurate and temperature-independent reference voltage provided by the root monitor 890. In some embodiments, the local reference voltage may be at least an order of magnitude less accurate than a temperature-independent reference voltage generated by a bandgap voltage generator. In one or more embodiments, the local reference voltage may have approximately 5% accuracy within a target voltage, while the temperature-independent reference voltage may have approximately 0.5% accuracy within the target voltage. A calibration circuit can generate a correction factor indicating the error in the digital code generated by the ADC, and the calibration circuit can correct the digital code based on the correction factor.

[0162] For example, sensors (S) and satellite monitors 892(1)-892(19) may be distributed throughout the programmable device 800 and located at various locations near selected circuits so that analog signals indicating the operating conditions of the selected circuits can be converted into digital signals at the respective distributed locations (instead of being transmitted to a central hub and then converted into digital data). For example, in some embodiments, each sensor (S) may be located near the corresponding selected circuit, such that the sensor (S) and the corresponding selected circuit can be coupled together using local signal lines. Similarly, for example, each of the satellite monitors 892(1)-892(19) may be located near one or more associated sensors (S), such that the satellite monitor 892 and one or more associated sensors (S) can be coupled together using local signal lines. In some aspects, the term "nearby," as used herein, may refer to the distance over which analog signals indicating operating conditions can be transmitted with minimal signal degradation via relatively short local signal lines.

[0163] for Figure 8 For example, the first set of sensors (S) located within transceiver block 850 may be located at various proximate points of a power supply (not shown for simplicity) associated with transceiver block 850, and the first set of satellite monitors 892(1)–892(6) may be located near the first set of sensors (S), such that each sensor in the first set of sensors (S) can be coupled to the corresponding power supply voltage and the corresponding satellite monitor 890 via a relatively short local signal line. In some embodiments, each sensor in the first set of sensors (S) may be configured to generate an analog signal indicating one or more operating conditions of the corresponding power supply, and each of the first set of satellite monitors 892(1)–892(6) may be configured to convert the analog signal generated by the associated sensor (S) into digital data, which can be transmitted to the root monitor 890 via the NoC interconnect system 820.

[0164] For example, a second set of sensors (S) located within PL 810 may be located within PL 810 or near one or more corresponding selected circuits (not shown for simplicity) associated with PL 810, and a second set of satellite monitors 892(7)–892(19) may be located near the second set of sensors (S) such that each sensor in the second set of sensors (S) can be coupled to the corresponding selected circuit and a corresponding sensor in the second set of satellite monitors 892(7)–892(19) via a relatively short local signal line. In some embodiments, each sensor in the second set of sensors (S) may be configured to generate an analog signal indicating one or more operating conditions of the corresponding selected circuit, and each satellite monitor in the second set of satellite monitors 892(7)–892(19) may be configured to convert the analog signal generated by the associated sensor (S) into digital data, which can be transmitted to the root monitor 890 via the NoC interconnect system 820.

[0165] Each of the satellite monitors 892(1)-892(19) can be coupled to any suitable number of sensors (S) via a local signal line. For example, satellite monitor 892(1) can be coupled to a single sensor (S) located within transceiver block 850 and can generate digital signals indicating one or more operating conditions of the corresponding power supply associated with transceiver block 850. As another example, satellite monitor 892(16) can be coupled to two sensors (S) located within PL 810 and can generate digital signals indicating one or more operating conditions of selected circuits associated with the two sensors (S) located within PL 810. As another example, satellite monitor 892(17) can be coupled to four sensors (S) located within PL 810 and can generate digital signals (S) indicating one or more operating conditions of selected circuits associated with the four sensors located within PL 810. Furthermore, although in Figure 8 The diagram shows 19 satellite monitors 892(1)-892(19), but the programmable device 800 may include other numbers of satellite monitors 892 located at other suitable locations within the programmable device 800.

[0166] As described above, satellite monitors 892(1)-892(19) can be positioned close enough to the sensors (S) that each sensor (S) can be coupled to the corresponding satellite monitor 892 using relatively short local signal lines, rather than transmitting analog signals over considerable distances for conversion to digital data using a central system monitor. Thus, embodiments of the monitoring system disclosed herein eliminate the need for metal layer signal routing resources to route these analog signals from various locations distributed throughout the device 800 to the central monitor for conversion to digital data, reducing device complexity and cost while increasing the scalability of the monitoring system. Furthermore, by using multiple satellite monitors 892(1)-892(19) distributed throughout the device 800 to perform analog-to-digital conversion of the sensor data, and then routing the digital data to the root monitor 890 for analysis, the number of sensors that can be measured simultaneously is not limited by the number of ADC input channels provided within the satellite monitors. In contrast, the number of sensors that can be measured simultaneously by the conventional solution of routing analog sensor data to the central system monitor for conversion to digital data is limited by the number of ADC input channels associated with the system monitor. Therefore, by distributing the conversion of analog sensor data to digital information at various locations throughout the device 800 via satellite monitors 892(1)–892(19), the number of sensors that can be simultaneously measured by the monitoring system disclosed herein can be based on the number of satellite monitors 892(1)–892(19), rather than on the number of input channels of the centrally located ADC that receives analog signals from sensors distributed across the device. Thus, the monitoring system disclosed herein can simultaneously measure far more sensors than the conventional solutions described above.

[0167] The root monitor 890 can receive digital data routed from each of the satellite monitors 892(1)-892(19) by the NoC interconnect system 820, and can process the received digital data to determine the operating conditions of selected circuits monitored by the sensors. In some embodiments, the root monitor 890 can compare the measured operating conditions with one or more reference values ​​to determine whether each of the selected circuits is operating within its specified operating range.

[0168] It should be pointed out that, Figure 8 This is merely intended to illustrate an exemplary architecture of the programmable device 800. Examples include, for instance, the number of logic blocks in a column (or row), the relative width of the column (or row), the number and order of the columns (or rows), the type of logic blocks contained in the column (or row), the relative size of the logic blocks, and... Figure 8 The other architectural aspects shown are merely illustrative of various embodiments of the inventive subject matter disclosed herein.

[0169] Figure 9 A functional block diagram of a programmable device 900 according to some embodiments is shown. The programmable device 900 may be... Figure 8 An example of a programmable device 800. Device 900 is shown as including a transceiver block 850, a programmable logic (PL) 910, a CPM 920, a processing system (PS) 930, a platform management controller (PMC) 940, and an I / O block + memory controller 960. PL910 may be Figure 8 One embodiment of the PL 810 can be adjacent to and directly connected to the transceiver block 850, CPM 920, PMC 940, and NoC interconnect system 820. The I / O block + memory controller 960 can be... Figure 8 One embodiment of the I / O block 860 and memory controller 870 can be implemented by arranging a plurality of repeatable patches along the bottom edge of the programmable device 900. Although in Figure 9 For simplicity, the I / O block + memory controller 960 may not be shown, but it can also be implemented as a plurality of repeatable patches arranged along the top edge of the programmable device 900. Alternatively, the I / O block + memory controller 960 may be implemented as a plurality of repeatable patches arranged along the left and right edges of the programmable device 900.

[0170] CPM 920 can be Figure 8 One embodiment of the CPM 840 provides interface capabilities for a variety of different bus standards. In some embodiments, the CPM 920 may include a Peripheral High-Speed ​​Interconnect (PCIe) interface 922, Direct Memory Access (DMA) circuitry 924, and a Cache Interconnect Coherence (CCIX) interface 926 for accelerators. The PCIe interface 922 can be used to exchange data between the PS 930 and one or more other devices or chips via transceiver block 850 according to the PCI protocol. Similarly, the CCIX interface 926 can be used to exchange data between the PS 930 and one or more other devices or chips via transceiver block 850 according to the CCIX protocol.

[0171] PS 930 can provide dedicated data processing capabilities for device 900 and is shown as including an application processing unit (APU) 932, a real-time processing unit (RPU) 934, a cache memory 936, and a system-on-a-chip (SoC) interface 938. Although not shown for simplicity, PS 930 may also include peripherals for communication standards (e.g., Ethernet and USB 2.0 interfaces) and various controllers (e.g., SPI, I2C, UART, and CAN-FD controllers). APU 932 and RPU 934 may each include one or more processing cores (e.g., CPUs) that can provide dedicated scalar processing capabilities for device 900. In some respects, PS 930 can be selectively connected to other subsystems of device 900 via a programmable interconnect structure and NoC interconnect system 820.

[0172] In some embodiments, the APU 932 may include a multi-core ARM processor supporting hardware virtualization and may have a built-in interrupt controller and monitoring control unit. The interrupt controller may support virtual interrupts and the monitoring control unit may be used to maintain consistency between one or more caches used and / or shared by the APU 932 and RPU 934. The APU 932 may communicate with other components of the PS 930 via the AXI Coherence Extension (ACE) port and with the PL 910 via the Accelerator Coherence Port (ACP). In some embodiments, the RPU 934 may include a multi-core ARM processor supporting real-time data processing, may include a tightly coupled memory (TCM) interface for real-time single-cycle access, and may have a dedicated interrupt controller and floating-point unit. The RPU 934 may communicate with other components of the PS 930 and / or with the PL 910 via the AXI port.

[0173] The cache memory 936 can be any suitable cache that can be shared by the APU 932 and RPU 934. The SoC interface 938 can provide connectivity between the PS 930 and the various resources of the NoC interconnect system 820.

[0174] The PMC 940 may include a safety circuit 942, a startup and reconfiguration circuit 944, an analog circuit 946, and... Figure 8 The root monitor 890. Security circuitry 942 can provide data encryption / decryption capabilities and other security features. Boot and reconfiguration circuitry 944 can support a multi-stage boot process that supports both insecure and secure boot. Analog circuitry 946 can include any suitable analog circuitry components. Furthermore, although for simplicity... Figure 9As not shown, the PMC 940 may include test and debug resources (e.g., JTAG circuitry), an external flash memory interface, and other components or circuitry. In some embodiments, the PMC 940 may allow partial reconfiguration operations to reconfigure portions of the PL 910. For example, a new configuration bitstream for a portion of the PL 910 may be loaded from the PS 930 via a primary or secondary boot interface (e.g., PCIe or Ethernet) and then stored in a configuration register associated with the portion of the PL 910 that needs to be reconfigured. The ability to allow partial reconfiguration of one or more portions of the PL 910 allows users to reconfigure the device 900 more quickly to reflect changes or updates to a user-specified circuit design (e.g., compared to other programmable devices).

[0175] Figure 10 A block diagram of an exemplary programmable structure 1000 according to some embodiments is shown. In some embodiments, the programmable structure 1000 may be Figure 8 PL 810, Figure 9 The PL 910, or both. The programmable structure 1000 is shown as including multiple different programmable circuit blocks or patches that can be arranged in columns (or rows). The programmable circuit blocks may include (but are not limited to) programmable interconnect elements (INTs) 1010, configurable logic elements (CLEs) 1020, DSPs 1030, and block RAM (BRAM) 1040 arranged in a columnar architecture. For Figure 10 For example, programmable structure 1000 is shown as including eleven columns of programmable interconnect elements 1010, five columns of CLEs 1020, two columns of DSPs 1030, and two columns of BRAMs 1040. In other embodiments, programmable structure 1000 may include other numbers of columns of programmable interconnect elements 1010, CLEs 1020, DSPs 1030, and BRAMs 1040. Programmable structure 1000 may also include Figure 10 For simplicity, many other subsystems or components (e.g., processing core, programmable interconnect structure, etc.) are not shown.

[0176] Programmable interconnect elements 1010, CLE 1020, DSP 1030, and BRAM 1040 can be implemented as repeatable patches on the programmable structure 1000. Each patch may include at least one programmable interconnect element 1010 that provides local signal interconnects to programmable logic elements within the same block, provides local signal interconnects to programmable interconnect elements 1010 in adjacent blocks, and / or provides local signal interconnects to other signal routing resources. The programmable interconnect elements 1010 may collectively form at least a portion of the programmable interconnect structure (or other suitable block-level and / or device-level signal routing structures).

[0177] In some embodiments, the programmable structure 1000 may include a columnar hard block 1050 extending vertically through the height of the programmable structure 1000. The hard block 1050 may include multiple hardwired circuits, such as a USB controller, an Ethernet MAC, a multi-rate (MR) Ethernet MAC, a PCIe controller, a CCIX controller, and / or other suitable circuitry or components implementing the physical layer, data link layer, and transaction layer of the PCIe protocol. In some embodiments, the hard block 1050 may be as described above regarding... Figure 8 An embodiment of the described connection structure.

[0178] Figure 11 A functional block diagram of a monitoring system 1100 according to some embodiments is shown. It can be... Figure 8 The monitoring system 1100 implemented in the programmable device 800 is shown as including a root monitor 1110, multiple satellite monitors SAT1-SAT15, multiple power supply voltage sensors SV1-SV4, multiple temperature sensors T5-T15, and multiple selected circuits CKT5-CKT15. The root monitor 1110 may be... Figure 8 One embodiment of the root monitor 890 is coupled to a NoC interconnect system 820 and one or more analog channels 821. In some embodiments, the root monitor 1110 may include a bandgap voltage generator (not shown for simplicity) to generate a temperature-independent reference voltage V. REF .

[0179] Satellite monitors SAT1-SAT15 can be distributed on device 800 and arranged such that each of the satellite monitors SAT1-SAT15 is located near a corresponding sensor among sensors SV1-SV4 and T5-T15. For Figure 11In an exemplary embodiment, satellite monitors SAT1-SAT4 are coupled to their respective power supply voltage sensors SV1-SV4 via local signal lines, and satellite monitors SAT5-SAT15 are coupled to their respective temperature sensors T5-T15 via local signal lines. In this way, analog signals generated by power supply voltage sensors SV1-SV4 can be provided to each satellite monitor SAT1-SAT4 via local signal lines, and analog signals generated by temperature sensors T5-T15 can be provided to each satellite monitor SAT5-SAT15 via local signal lines. By placing satellite monitors SAT5-SAT15 close to (e.g., in the vicinity of) their associated sensors V1-SV4 and T5-T15, the analog signals generated by sensors SV1-SV4 and T5-T15 do not need to be routed across a large portion of device 800 to reach root monitor 1110, thereby minimizing signal degradation associated with the relatively small amount of analog signal routed across the metal layer interconnects of device 800. Furthermore, because each sensor SV1-SV4 and T5-T15 can be locally converted into digital data using a nearby satellite monitor SAT1-STA15, expensive metal layer routing resources are not required to realize programmable devices (e.g., Figure 8 The monitoring system 1100 is located within the programmable device 800.

[0180] For example, sensor SV1 can monitor the operating conditions of the associated power supply voltage by generating an analog signal indicating the voltage level of the associated power supply voltage. By placing the corresponding satellite monitor SAT1 near sensor SV1, the analog signal generated by sensor SV1 does not need to be routed through device 800 to root monitor 1110, but can be routed to satellite monitor SAT1 over a relatively short distance via local signal lines. As another example, sensor T5 can monitor the operating conditions of associated circuit CKT5 by generating an analog signal indicating the temperature of associated circuit CKT5. By placing the corresponding satellite monitor SAT5 near sensor T5, the analog signal generated by sensor T5 does not need to be routed through device 800 to root monitor 1110, but can be routed to satellite monitor SAT5 over a relatively short distance via local signal lines.

[0181] Temperature-independent reference voltage V REFThe analog channels 821 can be distributed across device 800 and can be accessed through one or more analog channels 821 for each satellite monitor SAT1-STA15. Digital data can be selectively routed from each satellite monitor SAT1-STA15 to the root monitor 1110 via the NoC interconnect system 820. In some embodiments, the one or more analog channels 821 may extend along a corresponding portion of the NoC interconnect system 820. In other embodiments, the one or more analog channels 821 may be separate from the NoC interconnect system 820.

[0182] Figure 12 A block diagram of an exemplary root monitor 1200 according to some embodiments is shown. The root monitor 1200 may be... Figure 8 Root monitor 890 or Figure 11 The root monitor 1110 (or both) is shown as including a bandgap voltage generator 1210, a memory 1220, and a controller 1230. The bandgap voltage generator 1210 can generate a high-precision, temperature-independent reference voltage V. REF Any suitable circuit or device, including outputs coupled to one or more analog channels 821. In some embodiments, the bandgap voltage generator 1210 can generate a temperature-independent reference voltage V. REF Provided as a differential voltage (e.g., including a positive reference voltage and a negative reference voltage) to one or more analog channels 821. In some respects, the temperature-independent reference voltage V... REF It can be equal to 1.25 volts, although other suitable voltages can also be used as V. REF .

[0183] Refer again Figure 8 In some embodiments, the temperature-independent reference voltage V generated by the bandgap voltage generator 1210 REF One or more analog channels 821 can be distributed to each of the satellite monitors 892(1)-892(19) located throughout the device 800. For example, satellite monitors 892(1)-892(19) can selectively access a temperature-independent reference voltage V from one or more analog channels 821. REF This is to charge their respective voltage memories and periodically calibrate their ADCs, in order to use a relatively inaccurate local reference voltage (instead of using a high-precision and temperature-independent reference voltage V). REF This is used to compensate for analog-to-digital conversion errors associated with the sampled analog signal.

[0184] Memory 1220 includes data inputs coupled to NoC interconnect system 820, control inputs coupled to controller 1230, data outputs coupled to controller 1230, and one or more outputs through which a user can access data stored therein via one or more of a JTAG interface, a multiplexed input / output (MIO) block, or an AXI interface. In some embodiments, memory 1220 may include a plurality of status registers 1221 and a plurality of alarm registers 1222. Status registers 1221 may store digital data indicating operating conditions of selected circuitry provided throughout device 800, and alarm registers 1222 may store a plurality of reference values ​​defining a plurality of specified operating ranges. Status registers 1221 may be loaded with digital data routed from satellite monitors 892(1)-892(19) to root monitor 1200 via NoC interconnect system 820, and alarm registers 1222 may be loaded with reference values ​​during programmable device 800 configuration (or reconfiguration).

[0185] The controller 1230 can control various operations of the root monitor 1200, analyze digital data received from satellite monitors 892(1)-892(19) to determine if any selected circuits are not operating within their specified operating range, and generate result data accessible to the user. In some embodiments, the controller 1230 can determine whether a selected circuit is operating within its specified operating range by comparing measured operating conditions stored in the status register 1221 with corresponding reference values ​​stored in the alarm register 1222. If it is determined that a selected circuit is operating outside its specified operating range, the controller 1230 can generate an alarm. For example, in some aspects, an alarm can disable or power down the selected circuit until the operating conditions of the selected circuit are within its specified operating range. For example, in other aspects, an alarm can power down the programmable device 800 or operate it at a reduced power level until the operating conditions of the selected circuit are within its specified operating range.

[0186] Some specified operating ranges stored in alarm register 1222 may be defined by minimum and maximum reference values. In some embodiments, the specified voltage range may include a minimum voltage value and a maximum voltage value. In these embodiments, controller 1230 may compare the measured voltage of a selected circuit with the minimum and maximum voltage values ​​stored in alarm register 1222 and may generate one or more alarms based on the comparison result. For example, if the measured voltage is between the minimum and maximum voltage values, controller 1230 may indicate that the selected circuit is operating within its specified voltage range. Conversely, if the measured voltage is less than the minimum voltage value or greater than the maximum voltage value, controller 1230 may generate an alarm to indicate that the selected circuit is not operating within its specified voltage range.

[0187] Other specified operating ranges stored in alarm register 1222 may include reference values ​​that define the upper limit of operation. In some embodiments, a specified temperature range for the selected circuit may be defined by a reference temperature value. In these embodiments, controller 1230 may compare the measured temperature of the selected circuit with the reference temperature value stored in alarm register 1222 and may generate one or more alarms based on the comparison result. For example, if the measured temperature is less than (or equal to) the reference temperature value, controller 1230 may instruct the selected circuit to operate within its specified temperature range. Conversely, if the measured temperature is greater than the reference temperature value, controller 1230 may generate an alarm to indicate that the selected circuit is too hot or overheated.

[0188] In some embodiments, controller 1230 may be configured to generate control signal CTRL[1:19], which may be used by the respective satellite monitors 892(1)-892(19) to operate in calibration mode or monitoring mode. When operating in calibration mode, the respective satellite monitor 892 may access a temperature-independent reference voltage V from one or more analog channels 821. REF And can use V REF To generate an indication due to the inaccuracy of the relatively inaccurate local reference voltage (e.g., as... Figure 13 The correction factor for analog-to-digital conversion errors caused by (as described). When operating in surveillance mode, the corresponding satellite monitor 892 can convert analog signals generated by one or more sensors (S) into digital codes, and can correct the digital codes based on the correction factor (e.g., as described). Figure 13 (As described). In some embodiments, controller 1230 may selectively assert control signal CTRL[1:19] based on a timing table, such that only one of the satellite monitors 892(1)-892(19) can simultaneously access V from one or more analog channels 821. REF In this way, the root monitor 1200 can prevent multiple satellite monitors 892(1)-892(19) from simultaneously accessing the temperature-independent reference voltage V. REF The resulting temperature-independent reference voltage V REF decline.

[0189] For example, the timing table that can be stored in memory 1220 may also include a method for using V REFThe timetable for each satellite monitor 892(1)-892(19) is periodically calibrated to ensure that any periodic drift of the local reference voltage used by and / or stored in each satellite monitor 892(1)-892(19) is compensated for by corresponding updates to the correction factor. For example, in one or more embodiments, the controller 1230 may assert the control signal CTRL[1:19] sequentially every N milliseconds, such that a calibration operation is performed once every N milliseconds in the satellite monitors 892(1)-892(19), where N can be any suitable number. For example, the timetable may also include the use of V REF The voltage memory within each satellite monitor 192(1)-192(19) is periodically charged to maintain the local reference voltage held by the voltage memory within a range (e.g., within a temperature-independent reference voltage value).

[0190] Figure 13 A block diagram of an exemplary satellite monitor 1300 according to some embodiments is shown. The satellite monitor 1300 can be any number of... Figure 8 Satellite monitors 892(1)-892(19) or Figure 11 The satellite monitors SAT1-SAT15 (or both) are shown to include an ADC 1310, a memory 1320, a local voltage source 1330, a calibration circuit 1340, a correction circuit 1345, and a switch SW. The switch SW includes components coupled to receive a temperature-independent reference voltage V from one or more analog channels 821. REF The ADC 1310 has a first input terminal, a second input terminal coupled to receive analog signals generated by one or more associated sensors 20, a control terminal coupled to receive a corresponding control signal CTRL generated by the root monitor 1200, and an output terminal coupled to the input terminal of the ADC 1310. In some aspects, the sensor 20 may include (but is not limited to) a temperature sensor 21, a power supply voltage sensor 22, and an external sensor 23.

[0191] ADC 1310 includes an output coupled to memory 1320 and one or more reference terminals coupled to a local voltage source 1330. ADC 1310 can be (or can include) any suitable ADC that can convert analog signals generated by one or more sensors 20 into digital data or digital codes. In some embodiments, ADC 1310 can utilize a scaling architecture to digitize analog sensor data provided by sensor 20.

[0192] Memory 1320 can be any suitable storage device, including an input coupled to the output of ADC 1310 and an output coupled to NoC interconnect system 820. Memory 1320 can store digital data generated by ADC 1310 in response to analog signals provided by one or more sensors 20, and can provide the digital data to NoC interconnect system 820 for routing. Figure 12 The root monitor 1200. In some embodiments, the memory 1320 may be or may include a plurality of registers, each register for storing digital data indicating the operating conditions of a corresponding circuit among a plurality of circuits selected for monitoring. In this way, the satellite monitor 1300 can receive analog signals from the sensor 20 indicating the operating conditions of a corresponding circuit among the selected circuits, convert the analog signals into digital data, and provide the digital data indicating the operating conditions of the selected circuit to the root monitor 1200 via the NoC interconnect system 820.

[0193] The local voltage source 1330 can be any suitable, relatively small, or area-efficient voltage source that can generate a local reference voltage V suitable for use by the ADC 1310. REF_LOCAL (And no trimming is required during manufacturing). The local voltage source 1330 can be constructed using fewer than 10 transistors, and with... Figure 12 Compared to the bandgap voltage generator 1210, it occupies a significantly reduced circuit area. In some embodiments, the local voltage source 1330 can occupy a larger area than... Figure 12 The bandgap voltage generator 1210 has at least an order of magnitude less circuit area. For example, in one or more embodiments, the circuit area occupied by the local voltage source can be on the order of tens of square micrometers.

[0194] The temperature-independent reference voltage V generated by the bandgap voltage generator 1210 REF In comparison, the local reference voltage V REF_LOCAL This may be relatively inaccurate and could lead to errors in the digital code generated by the ADC 1310. In some embodiments, the accuracy of the local reference voltage provided by the local voltage source 1330 may be at least an order of magnitude lower than that of the temperature-independent reference voltage generated by the bandgap voltage generator 1210. In one or more embodiments, the local reference voltage may have an accuracy of approximately 5% over the target voltage range, while the temperature-independent reference voltage may have an accuracy of approximately 0.5% over the target voltage range.

[0195] The calibration circuit 1340 may include an input coupled to receive digital codes from the output of the ADC 1310, an output providing a correction factor to the calibration circuit 1345, and a control terminal receiving a corresponding control signal CTRL from the root monitor 1200. The calibration circuit 1345, which may be coupled between the ADC 1310 and the memory 1320, includes a terminal for receiving the correction factor provided by the calibration circuit 1340. In some embodiments, the calibration circuit 1340 may be configured to generate a correction factor to compensate for errors in the digital codes generated by the ADC 1310, and the calibration circuit 1345 may be configured to correct the digital codes generated by the ADC 1310 based on the correction factor.

[0196] For example, during a calibration operation, the assertion state of the control signal CTRL can cause the switch SW to apply a temperature-independent reference voltage V. REF The input signal is provided to the ADC 1310, and the calibration circuit 1340 can also be enabled. The ADC 1310 can sample a temperature-independent reference voltage V. REF To generate a reference code, and the calibration circuit 1340 can use the reference code generated by the ADC 1310 and the indication V REF The correction factor is generated by the difference between the predetermined digital codes of the known values. During monitoring operation, the deassertion state of the control signal CTRL allows the switch SW to provide the analog signal from sensor 20 as an input signal to the ADC 1310, and can connect the satellite monitor 1300 with V REF The interconnect system 820 is isolated from the NoC interconnect system. The ADC 1310 can sample the analog signal provided by the sensor 20 and generate a digital code. The correction circuit 1345 can correct the digital code using a correction factor, for example, by adjusting the digital code based on the correction factor. In this way, the satellite monitor 1300 can compensate for the relatively inaccurate local reference voltage V. REF_LOCAL The inaccuracy of the analog-to-digital conversion leads to the error.

[0197] Figure 14 This is an illustrative flowchart depicting an exemplary operation 1400 for monitoring the operating conditions of multiple circuits distributed at various locations of a programmable device, according to some embodiments. The operation 1400 described below is for... Figure 8 Programmable devices 800 Figure 11 The monitoring system 1100 Figure 12 Root monitor 1200 and Figure 13 The operation is performed by satellite monitor 1300 and is for illustrative purposes only. It should be understood that exemplary operation 1400 can be performed by other programmable devices and / or other suitable devices disclosed herein.

[0198] Operation 1400 may begin at block 1401 by generating an analog signal indicating the operating conditions of each of a plurality of circuits using a corresponding sensor among a plurality of sensors distributed at various locations of the programmable device. In some embodiments, each of the plurality of sensors 20 may be located near an associated circuit. In some aspects, sensor 20 may be (or may include) at least one of a temperature sensor 21, a power supply voltage sensor 22, or an external sensor 23. For example, in some embodiments, root monitor 890 may be used Figure 12 The bandgap circuit 1212 generates a trimmed and temperature-independent reference voltage V. REF .

[0199] Operation 1400 can be performed at block 1402 by providing each analog signal to a corresponding satellite monitor among a plurality of satellite monitors distributed at various locations of the programmable device. For example, in some embodiments, the analog signals generated by sensor 20 can be provided to the respective satellite monitors 892(1)-892(19) using relatively short local signal lines, compared to conventional programmable devices that route analog signals indicating the operating conditions of various circuits through the device and provide them to a central monitor using a metal layer signal routing structure.

[0200] Operation 1400 can be performed at block 1403 by generating a local reference voltage in each of the plurality of satellite monitors 892(1)-892(19) using a local voltage source 1330 (e.g., based on a temperature-independent reference voltage). The local voltage source 1330 can be considerably smaller and “area-efficient” compared to the bandgap voltage generator 1210 provided in the root monitor 1200. In some embodiments, the local voltage source 1330 may comprise fewer than a dozen transistors and may consume at least an order of magnitude less circuit area than the bandgap voltage generator 1210. In one or more embodiments, the circuit area occupied by the local voltage source 1330 may be on the order of tens of square micrometers, while the circuit area occupied by the bandgap voltage generator 1210 may be on the order of hundreds of square micrometers (or even a thousand square micrometers).

[0201] The local reference voltage may be relatively inaccurate compared to the temperature-independent reference voltage generated by the bandgap voltage generator 1210. In some embodiments, the local reference voltage provided by and / or stored in the local voltage source 1330 may be at least an order of magnitude less accurate than the temperature-independent reference voltage generated by the bandgap voltage generator 1210. In one or more embodiments, the local reference voltage may have an accuracy of approximately 5% over the target voltage range, while the temperature-independent reference voltage may have an accuracy of approximately 0.5% over the target voltage range.

[0202] Operation 1400 can be performed at block 1404 by using an analog-to-digital converter (ADC) to convert the corresponding analog signal from each of the multiple satellite monitors 892(1)-892(19) into digital code based on the local reference voltage. (Continue to refer to...) Figure 13 The ADC circuit 1310 provided in each satellite monitor 892(1)-892(19) can convert analog signals into digital data (19) that can be stored in the memory 1320 of each satellite monitor 892(1)-892. The memory 1320 can selectively provide the stored digital data to the interconnect system 820 for routing to the root monitor 890.

[0203] Operation 1400 can be performed at block 1405 by distributing a temperature-independent reference voltage from root monitor 890 to each of the plurality of satellite monitors 892(1)-892(19). In some embodiments, the temperature-independent reference voltage can be distributed to each of the plurality of satellite monitors 892(1)-892(19) using one or more analog channels 821 spanning the programmable structure.

[0204] Operation 1400 can be performed at block 1406 by correcting the digital code generated by the ADC 1310 within each of the plurality of satellite monitors 892(1)-892(19) based at least in part on an assigned temperature-independent reference voltage. In some embodiments, the digital code can be adjusted based on a correction factor indicating the analog-to-digital conversion error caused by inaccuracies in the local reference voltage.

[0205] Operation 1400 can be performed at block 1407 by selectively routing corrected digital codes from a plurality of satellite monitors 892(1)-892(19) to root monitor 890. The corrected digital codes can be selectively routed from the plurality of satellite monitors 892(1)-892(19) to root monitor 890 using NoC interconnect system 820. In some embodiments, each of the satellite monitors 892(1)-892(19) can provide corrected digital codes to NoC interconnect system 820 in response to a signal (e.g., a trigger signal) generated by root monitor 890, for example, scheduling or prioritizing the transmission of digital data from satellite monitors 892(1)-892(19) to root monitor 890. In other embodiments, satellite monitors 892(1)-892(19) can provide digital data to NoC interconnect system 820 without prompting and / or without control of root monitor 890.

[0206] Figure 15This is an illustrative flowchart depicting exemplary operation 1500 for correcting digital codes generated by an ADC provided within each satellite monitor. For illustrative purposes, exemplary operation 1500 is described below regarding... Figure 8 Programmable device 800, Figure 11 The monitoring system 1100, Figure 12 The root monitor 1200, and Figure 13 The satellite monitor 1300. It should be understood that exemplary operation 1500 can be performed by other programmable devices and / or other suitable devices disclosed herein. In some embodiments, exemplary operation may be as described above regarding... Figure 14 Example of procedure 1408 described in operation 1400.

[0207] Operation 1500 can begin at block 1501 by providing a temperature-independent reference voltage as an input signal to ADC 1310. Operation 1500 can be performed at block 1502 by using ADC 1310 to convert the temperature-independent reference voltage into a reference code. Operation 1500 can be performed at block 1503 by generating a correction factor based on the difference between the reference code and a predetermined digital code indicating the temperature-independent reference voltage. Operation 1500 can be performed at block 1504 by adjusting the digital code based on the correction factor.

[0208] Figure 16 A block diagram of an exemplary satellite monitor 1600 according to some embodiments is shown. The satellite monitor 1600 may be... Figure 8 Any number of satellite monitors 892(1)-892(19) or Figure 4 The satellite monitors SAT1-SAT15 (or both) are shown to include an ADC 1610, a memory 1620, a voltage memory 1630, a calibration circuit 1640, a correction circuit 1645, a first switch SW1, and a second switch SW2. The first switch SW1 includes components coupled to receive a temperature-independent reference voltage V from one or more analog channels 821. REF The first input terminal, a second input terminal coupled to receive analog signals generated by one or more associated sensors 20, a control input terminal coupled to receive a corresponding control signal in the first control signal CTRL1, and an output terminal coupled to the input terminal of the ADC 1610. The second switch SW2 includes an input terminal coupled to receive a temperature-independent reference voltage from one or more analog channels, a control terminal coupled to receive a corresponding control signal in the second control signal CTRL2, and an output terminal coupled to the voltage memory 1630. In some aspects, the sensor 20 may include (but is not limited to) a temperature sensor 21, a power supply voltage sensor 22, and an external sensor 23.

[0209] ADC 1610 includes an output coupled to memory 1620 and one or more reference terminals coupled to voltage memory 1630. ADC 1610 can be (or can include) any suitable ADC capable of converting analog signals generated by one or more sensors 20 into digital data or digital codes. In some embodiments, ADC 1610 can utilize a scaling architecture to digitize analog sensing data provided by sensor 20.

[0210] The memory 1620 can be any suitable storage device, including an input coupled to the output of the ADC 1610 and an output coupled to the NoC interconnect system 820. The memory 1620 can store digital data generated by the ADC 1610 in response to analog signals provided by one or more sensors 20, and can also provide the digital data to the NoC interconnect system 820 for routing. Figure 12 The root monitor 1200. In some embodiments, the memory 1620 may be or may include multiple registers, each register for storing digital data indicating the operating conditions of a corresponding circuit among a plurality of selected circuits for monitoring. In this way, the satellite monitor 1600 may receive an analog signal from the sensor 20 indicating the operating conditions of a corresponding circuit among the selected circuits, convert the analog signal into digital data, and provide the digital data indicating the operating conditions of the selected circuit to the root monitor 1200 via the NoC interconnect system 820.

[0211] The voltage memory 1630 can store a local reference voltage V suitable for use with the ADC 1610. REF_LOCAL Any suitable device or component. In some embodiments, such as... Figure 16 As shown, the voltage memory 1630 can be a capacitor. More specifically, in some embodiments, the voltage memory 1630 can be implemented as a capacitor C1, and the second switch SW2 can be implemented as a CMOS transistor M1. The capacitor C1 is coupled between the transistor M1 (used as the second switch SW2) and the reference terminal of the ADC 1610, and can be compared with... Figure 12 The bandgap voltage generator 1210 occupies significantly less circuit area. Furthermore, for example, capacitors do not need to be trimmed during manufacturing, as do precise voltage reference values ​​such as the bandgap voltage generator 1210. In some embodiments, the voltage memory 1630 can occupy a much smaller area than... Figure 12 The bandgap voltage generator 1210 has a circuit area at least an order of magnitude smaller. For example, in one or more embodiments, the local voltage memory 1630 occupies a circuit area that can be on the order of tens of square micrometers.

[0212] The temperature-independent reference voltage V generated by the bandgap voltage generator 1210 REF In comparison, the local reference voltage V REF_LOCAL This may be relatively inaccurate and could lead to errors in the digital code generated by the ADC 1610. In some embodiments, the local reference voltage 1630 provided by the local voltage memory may be at least an order of magnitude less accurate than the temperature-independent reference voltage generated by the bandgap voltage generator 1210. In one or more embodiments, the local reference voltage may have an accuracy of approximately 5% over the target voltage range, while the temperature-independent reference voltage may have an accuracy of approximately 0.5% over the target voltage range.

[0213] The calibration circuit 1640 may include an input coupled to receive digital codes from the output of the ADC 1610, an output providing a correction factor to the calibration circuit 1645, and a control terminal receiving a corresponding first control signal CTRL1 from the root monitor 1200. The calibration circuit 1645, which may be coupled between the ADC 1610 and the memory 1620, includes a terminal for receiving the correction factor provided by the calibration circuit 1640. In some embodiments, the calibration circuit 1640 may be configured to generate a correction factor to compensate for errors in the digital codes generated by the ADC 1610, and the calibration circuit 1645 may be configured to correct the digital codes generated by the ADC 1610 based on the correction factor.

[0214] For example, during a calibration operation, a first control signal CTRL1 can be asserted (e.g., logic high), and a second control signal CTRL2 can be asserted (e.g., logic high). The assertion state of the first control signal CTRL1 allows the first switch SW1 to provide a temperature-independent reference voltage V to the ADC 1610. REF As an input signal, it can also enable the calibration circuit 1640. The assertion state CTRL2 of the second control signal can open the second switch SW2 and couple the voltage memory 1630 to one or more analog channels 821, thereby allowing the voltage memory 1630 to be charged to a value approximately equal to a temperature-independent reference voltage (so that the stored charge can be used by the ADC 1610 as a local reference voltage V). REF_LOCAL The conduction state of switches SW1 and SW2 may cause disturbances to temperature-independent reference voltages (e.g., sags), for example, by the V voltage coupled to the input of ADC 1610 and coupled to voltage memory 1630. REF cause.

[0215] Once the voltage memory 1630 is fully charged and stores the local reference voltage V REF_LOCALThe second control signal CTRL2 can be deasserted (e.g., to logic low). The deasserted state of the second control signal CTRL2 can close the second switch SW2 and prevent the voltage memory 1630 from accessing a temperature-independent reference voltage from one or more analog channels 821. The deassertion of the second control signal CTRL2 may also be possible at a temperature-independent reference voltage V. REF This can cause interference (e.g., a sudden drop). In some embodiments, the first control signal CTRL1 can be held in an assertion state until the temperature-independent reference voltage V... REF The interference is stabilized. Afterwards, the first control signal CTRL1 can be contacted and asserted (e.g., to logic low), and the ADC 1610 can be stabilized against a temperature-independent reference voltage V. REF Sampling is performed to generate a reference code. The calibration circuit 1640 can then use the reference code generated by the ADC 1610 and the indication V... REF The correction factor is generated by the difference between the known values ​​and predetermined digital codes. The correction factor can be provided to (and stored in) the correction circuit 1645.

[0216] During monitoring operations, the first control signal CTRL1 can be held in a deasserted state, allowing the first switch SW1 to provide the analog signal generated by sensor 20 as an input signal to ADC 1610 (and also disabling calibration circuit 1640). ADC 1610 can sample the analog signal provided by sensor 20 and generate a digital code representing the sampled analog signal. Calibration circuit 1645 can correct the digital code using a correction factor generated during calibration operations, for example, by adjusting the digital code based on the correction factor. In this way, satellite monitor 1600 can compensate for the relatively inaccurate local reference voltage V. REF_LOCAL The inaccuracy of the analog-to-digital conversion leads to the error.

[0217] In some embodiments, the calibration operation may be performed periodically (e.g., every N milliseconds, where N is any suitable number greater than zero) to maintain the minimum voltage level (e.g., V) stored by the voltage memory 1630. REF_LOCAL And ensure that the satellite monitor 1600 remains correctly calibrated.

[0218] Example

[0219] Example 1: A programmable device includes: a plurality of configurable logic resources; a root monitor including circuitry configured to generate a reference voltage; a plurality of sensors distributed at various locations of the programmable device, each sensor configured to measure operating conditions of associated circuitry at a corresponding location at each location; a plurality of satellite monitors distributed at various locations of the programmable device, each satellite monitor being coupled to one or more associated sensors located near a corresponding satellite monitor; and an interconnect system coupled to each of the configurable logic resources, the root monitor, and each of the multiple satellite monitors, wherein the interconnect system is configured to: distribute the reference voltage from the root monitor to each of the multiple satellite monitors; and selectively route digital data from each of the multiple satellite monitors to the root monitor, wherein the digital data indicates the measured operating conditions.

[0220] Example 2: The programmable device of Example 1, wherein the operating conditions include at least one of temperature or voltage level.

[0221] Example 3: The programmable device of Example 1, wherein the root monitor includes a bandgap circuit configured to compensate for a reference voltage in response to temperature variations.

[0222] Example 4: The programmable device of Example 1, wherein each satellite monitor includes: an analog-to-digital converter (ADC) including an input for receiving an analog signal indicating operating conditions measured by one or more associated sensors, an output for providing digital data to an interconnect system, and a reference for receiving a local reference voltage.

[0223] Example 5: The programmable device of Example 4, wherein the local reference voltage is at least partially based on a reference voltage assigned by the interconnect system.

[0224] Example 6: The programmable device of Example 4, wherein each satellite monitor further includes: a memory having an input coupled to the output of the ADC, an output coupled to the interconnect system, and configured to store digital data provided by the ADC.

[0225] Example 7: The programmable device of Example 4, wherein each satellite monitor further includes a switch configured to selectively couple a reference voltage assigned by the interconnect system to the satellite monitor based on a control signal generated by the root monitor.

[0226] Example 8: The programmable device of Example 7, wherein control signals are configured to simultaneously couple a reference voltage assigned to an interconnect system to a single satellite monitor.

[0227] Example 9: The programmable device of Example 1, wherein at least some of the multiple satellite monitors are integrated within an interconnect system.

[0228] Example 10: A programmable device of Example 1, wherein the interconnect system further includes: one or more analog channels configured to distribute a reference voltage from a root monitor to each of a plurality of satellite monitors; and one or more digital channels configured to selectively route digital data from the satellite monitors to the root monitor as individually addressable data packets.

[0229] Example 11: The programmable device of Example 1, wherein the root monitor further includes: a memory configured to store digital data received from each of a plurality of satellite monitors; and a controller configured to determine whether the operating conditions of at least one associated circuit being measured are within a range.

[0230] Example 12: A system for monitoring multiple operating conditions of a programmable device, the system comprising: a root monitor including circuitry configured to generate a reference voltage; a plurality of sensors distributed on the programmable device, each sensor configured to generate an analog signal indicating operating conditions of associated circuitry; a plurality of satellite monitors distributed on the programmable device, each satellite monitor configured to convert the analog signals generated by one or more corresponding sensors into digital data; and an interconnect system at least coupled to the root monitor and each of the plurality of satellite monitors, the interconnect system comprising: one or more analog channels configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors; and one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.

[0231] Example 13: The system of Example 12, wherein the operating conditions include at least one of temperature or voltage level.

[0232] Example 14: The system of Example 12, wherein each satellite monitor includes an analog-to-digital converter (ADC) configured to convert analog signals generated by one or more associated sensors into digital data.

[0233] Example 15: The system of Example 14, wherein each satellite monitor further includes a switch configured to selectively couple a reference voltage assigned to the interconnect system to the satellite monitor based on a control signal generated by the root monitor.

[0234] Example 16: The system of Example 15, wherein control signals are configured to simultaneously couple a reference voltage assigned to the interconnected system to a single satellite monitor.

[0235] Example 17: A method for monitoring multiple operating conditions of a programmable device, the method comprising: generating a reference voltage using a voltage generator associated with a root monitor provided within the programmable device; distributing the reference voltage to each of a plurality of satellite monitors using one or more analog channels of an interconnect system integrated within the programmable device; generating an analog signal indicating operating conditions of an associated circuit using each of a plurality of sensors; providing the analog signals generated by the plurality of sensors to a corresponding satellite monitor among the plurality of satellite monitors; converting the analog signals into digital data using the plurality of satellite monitors; and selectively routing the digital data from the plurality of satellite monitors to the root monitor using one or more digital channels of the interconnect system.

[0236] Example 18: The method of Example 17, wherein the operating conditions include at least one of temperature or voltage level.

[0237] Example 19: The method of Example 17, wherein allocating the reference voltage further includes: selectively coupling each of the plurality of satellite monitors to the interconnect system based on a corresponding control signal generated by the root monitor.

[0238] Example 20: The method of Example 19, wherein control signals are configured to simultaneously couple a reference voltage assigned to the interconnect system to a single satellite monitor.

[0239] Example 21: A programmable device includes: programmable logic including a plurality of configurable logic resources; a root monitor including a bandgap voltage generator configured to generate a temperature-independent reference voltage; a plurality of sensors distributed at various locations of the programmable device, each sensor configured to generate an analog signal indicating a measured operating condition of one or more associated circuits near a corresponding location at each location; and a plurality of satellite monitors distributed on the programmable device at various locations, each satellite monitor being coupled to one or more associated sensors via one or more local signal lines, and includes: a relatively small local voltage source configured to generate a local reference voltage; an analog-to-digital converter (ADC) including a reference terminal for receiving the local reference voltage and configured to convert the analog signal generated by the one or more associated sensors into a digital code indicating the measured operating condition; a calibration circuit configured to generate a correction factor indicating an error in the digital code; and a correction circuit configured to correct the digital code based on the correction factor.

[0240] Example 22: A programmable device of Example 21, wherein the local voltage source consists of fewer than a dozen transistors and consumes at least an order of magnitude less circuit area than a bandgap voltage generator.

[0241] Example 23: A programmable device of Example 21, wherein the error in the digital code is associated with a deviation between a local reference voltage and a temperature-independent reference voltage.

[0242] Example 24: A programmable device of Example 21, wherein the correction factor is based on the difference between a reference code generated by the ADC in response to sampling the temperature-independent reference voltage and a predetermined digital code indicating the temperature-independent reference voltage.

[0243] Example 25: The programmable device of Example 21 further includes: a network-on-chip (NoC) interconnect system that spans programmable logic and is configured to selectively route digital data from each of a plurality of satellite monitors to a root monitor.

[0244] Example 26: A programmable device of Example 25, wherein the root monitor further includes: a memory configured to store digital data received from a plurality of satellite monitors via a NoC interconnect system; and a controller configured to determine whether the operating conditions of the measurement embodied in the digital data are within range.

[0245] Example 27: The programmable device of Example 25 further includes: one or more analog channels configured to distribute a temperature-independent reference voltage from the root monitor to each of the plurality of satellite monitors.

[0246] Example 28: A programmable device of Example 27, wherein the NoC interconnect system includes one or more analog channels.

[0247] Example 29: The programmable device of Example 27, wherein each satellite monitor further includes: a switch comprising a first input coupled to receive a temperature-independent reference voltage from one or more analog channels, a second input coupled to receive analog signals generated by one or more associated sensors, a control terminal coupled to receive control signals, and an output terminal coupled to the input of an ADC within the satellite monitor.

[0248] Example 30: A programmable device of Example 29, wherein: during calibration operation, the switch provides a temperature-independent reference voltage as an input signal to the ADC; during monitoring operation, the switch provides an analog signal from a sensor as an input signal to the ADC.

[0249] Example 31: A programmable device of Example 30, wherein: during a calibration operation, the ADC samples a temperature-independent reference voltage to generate a reference code; and during a monitoring operation, the ADC samples analog signals from one or more associated sensors to generate a digital code.

[0250] Example 32: A programmable device of Example 31, wherein the calibration circuitry is configured to generate a correction factor based on the difference between a reference code generated by the ADC and a predetermined digital code indicating a temperature-independent reference voltage.

[0251] Example 33: A programmable device of Example 29, wherein the root monitor is configured to generate control signals for calibrating multiple satellite monitors, at least in part based on a timing table.

[0252] Example 34: A programmable device of Example 33, wherein the timing table is configured to sequentially enable calibration of each of a plurality of satellite monitors by providing a temperature-independent reference voltage to only one satellite monitor at a time.

[0253] Example 35: A method for monitoring the operating conditions of multiple circuits distributed at various locations of a programmable device, the method comprising: generating an analog signal indicative of the operating conditions of each of the multiple circuits using a corresponding sensor among a plurality of sensors distributed at various locations of the programmable device; providing each analog signal to a corresponding satellite monitor among a plurality of satellite monitors distributed at different locations of the programmable device; generating a local reference voltage in each of the multiple satellite monitors using a relatively small local voltage source; converting a corresponding one of the multiple analog signals into a digital code based on the local reference voltage using an analog-to-digital converter (ADC) in each of the multiple satellite monitors; distributing a temperature-independent reference voltage from a root monitor to each of the multiple satellite monitors; correcting the digital code generated by the ADC in each of the multiple satellite monitors based at least in part on the distributed temperature-independent reference voltage; and selectively routing the corrected digital code from each of the multiple satellite monitors to the root monitor.

[0254] Example 36: The method of Example 35, wherein the local voltage source consists of fewer than a dozen transistors and consumes at least an order of magnitude less circuit area than the bandgap voltage generator.

[0255] Example 37: The method of Example 35, wherein: a corrected digital code is selectively routed from multiple satellite monitors to a root monitor using a network-on-chip (NoC) interconnect system spanning the programmable device; and a temperature-independent reference voltage is distributed from the root monitor to the multiple satellite monitors using one or more analog channels spanning the programmable device.

[0256] Example 38: The method of Example 35, wherein the assigned temperature-independent reference voltage further includes: sequentially enabling each of the plurality of satellite monitors to access the temperature-independent reference voltage based on a plurality of corresponding control signals generated by the root monitor.

[0257] Example 39: The method of Example 35, wherein the correction includes: providing a temperature-independent reference voltage as an input signal to an ADC; converting the temperature-independent reference voltage into a reference code using the ADC; generating a correction factor based on the difference between the reference code and a predetermined digital code indicating the temperature-independent reference voltage; and adjusting the digital code according to the correction factor.

[0258] Example 40: The method of Example 39, wherein the correction factor is configured to compensate for errors in the digital code associated with the local reference voltage and the deviation from the temperature-independent reference voltage.

[0259] Example 41: A programmable device includes: programmable logic including a plurality of configurable logic resources; a root monitor including a bandgap voltage generator configured to generate a temperature-independent reference voltage; a plurality of sensors distributed at various locations of the programmable device, each sensor configured to generate an analog signal indicating measurement operating conditions of one or more associated circuits near a corresponding location at each location; and a plurality of satellite monitors distributed at various locations of the programmable device, each satellite monitor coupled to one or more associated sensors via one or more local signal lines, and includes: a voltage memory configured to store a local reference voltage based on the temperature-independent reference voltage generated by the bandgap voltage generator; an analog-to-digital converter (ADC) including a reference terminal for receiving the local reference voltage and configured to convert the analog signal generated by the one or more associated sensors into a digital code indicating the measured operating conditions; a calibration circuit configured to generate a correction factor indicating an error in the digital code; and a correction circuit configured to correct the digital code based on the correction factor.

[0260] Example 42: A programmable device of Example 41, wherein the local reference voltage is at least an order of magnitude less accurate than the temperature-independent reference voltage generated by the bandgap voltage generator.

[0261] Example 43: A programmable device of Example 41, wherein the voltage memory includes a capacitor.

[0262] Example 44: A programmable device of Example 41, wherein the error in the digital code is associated with the deviation of the local reference voltage from a temperature-independent reference voltage.

[0263] Example 45: A programmable device of Example 41, wherein the correction factor is based on the difference between a reference code generated by the ADC in response to sampling the temperature-independent reference voltage and a predetermined digital code indicating the temperature-independent reference voltage.

[0264] Example 46: The programmable device of Example 41 further includes: a network-on-chip (NoC) interconnect system that spans programmable logic and is configured to selectively route digital data from each of a plurality of satellite monitors to a root monitor.

[0265] Example 47: A programmable device of Example 46, wherein the root monitor further includes: a memory configured to store digital data received from a plurality of satellite monitors via a NoC interconnect system; and a controller configured to determine whether the measured operating conditions embodied in the digital data are within range.

[0266] Example 48: The programmable device of Example 46 further includes: one or more analog channels configured to distribute a temperature-independent reference voltage from the root monitor to each of the plurality of satellite monitors.

[0267] Example 49: A programmable device of Example 48, wherein the NoC interconnect system includes one or more analog channels.

[0268] Example 50: A programmable device of Example 48, wherein each satellite monitor further includes: a first switch comprising a first input coupled to receive a temperature-independent reference voltage from one or more analog channels, a second input coupled to receive analog signals generated by one or more associated sensors, a control terminal coupled to receive control signals, and an output terminal coupled to the input of an ADC within the satellite monitor.

[0269] Example 51: A programmable device of Example 50, wherein each satellite monitor further includes: a second switch comprising an input coupled to receive a temperature-independent reference voltage from one or more analog channels, a control terminal coupled to receive control signals, and an output terminal coupled to a voltage memory.

[0270] Example 52: A programmable device of Example 51, wherein during a calibration operation: a first switch provides a temperature-independent reference voltage as an input signal to an ADC; a second switch charges a voltage memory and then isolates the voltage memory from the temperature-independent reference voltage; and the ADC samples the temperature-independent reference voltage to generate a reference code.

[0271] Example 53: A programmable device of Example 52, wherein during monitoring operation, a first switch provides an analog signal from a sensor as an input signal to an ADC; a second switch periodically provides a temperature-independent reference voltage to a voltage memory; and the ADC samples analog signals from one or more associated sensors to generate digital codes.

[0272] Example 54: The programmable device of Example 51, wherein the root monitor is configured to generate control signals based at least in part on a timing arrangement for calibrating a plurality of satellite monitors.

[0273] Example 55: The programmable device of Example 54, wherein the timing table is configured to sequentially enable calibration of each of the plurality of satellite monitors by providing the temperature-independent reference voltage to only one of the satellite monitors at a time.

[0274] Example 56: A method for monitoring the operating conditions of a plurality of circuits distributed at various locations of a programmable device, the method comprising: generating an analog signal indicating the operating conditions of each of the plurality of circuits using a corresponding sensor among a plurality of sensors distributed at various locations of the programmable device; providing each analog signal to a corresponding satellite monitor among a plurality of satellite monitors distributed at various locations of the programmable device; storing a local reference voltage in each of the plurality of satellite monitors based on a temperature-independent reference voltage; converting a corresponding analog signal among the plurality of analog signals into a digital code using an analog-to-digital converter (ADC) in each of the plurality of satellite monitors based on the local reference voltage; distributing the temperature-independent reference voltage from a root monitor to each of the plurality of satellite monitors; correcting the digital code generated by the ADC in each of the plurality of satellite monitors based at least in part on the distributed temperature-independent reference voltage; and selectively routing the corrected digital code from each of the plurality of satellite monitors to the root monitor.

[0275] Example 57: The method of Example 56, wherein: a corrected digital code is selectively routed from multiple satellite monitors to a root monitor by using an on-chip network (NoC) interconnect system spanning the programmable device; and a temperature-independent reference voltage is distributed from the root monitor to the multiple satellite monitors by using one or more analog channels spanning the programmable device.

[0276] Example 58: The method of Example 57, wherein the storage includes: selectively charging a capacitor disposed within a respective satellite monitor by using a temperature-independent reference voltage allocated by the one or more analog channels.

[0277] Example 59: The method of Example 56, wherein assigning a temperature-independent reference voltage further includes: sequentially enabling each of the plurality of satellite monitors to access the temperature-independent reference voltage based on a plurality of corresponding control signals generated by the root monitor.

[0278] Example 60: The method of Example 56, wherein the correction includes: providing the temperature-independent reference voltage as an input signal to the ADC; using the ADC to convert the temperature-independent reference voltage into a reference code; generating a correction factor based on the difference between the reference code and a predetermined digital code indicating the temperature-independent reference voltage; and adjusting the digital code according to the correction factor.

[0279] Those skilled in the art will understand that information and signals can be represented using any of a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0280] Furthermore, those skilled in the art will understand that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally according to their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as a departure from the scope of this disclosure.

[0281] The methods, sequences, or algorithms described in conjunction with the aspects disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module can reside in a RAM latch, flash latch, ROM latch, EPROM latch, EEPROM latch, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. Example storage media are coupled to the processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor.

[0282] In the foregoing specification, exemplary embodiments have been described with reference to specific examples. However, it will be apparent that various modifications and changes can be made therein without departing from the broader scope of the disclosure set forth in the appended claims. Therefore, the specification and drawings are to be considered illustrative rather than restrictive.

Claims

1. A programmable device, characterized in that, The programmable device includes: Multiple configurable logical resources; A root monitor, the root monitor including circuitry configured to generate a reference voltage; Multiple sensors are distributed at multiple locations on the programmable device, each sensor being configured to measure the operating conditions of an associated circuit at a corresponding location among the multiple locations; A plurality of satellite monitors are distributed at multiple locations on the programmable device. Each satellite monitor is coupled to one or more associated sensors located in the vicinity of the respective satellite monitor. Each satellite monitor includes an analog-to-digital converter (ADC) comprising an input, an output, and a reference terminal. The input is used to receive an analog signal indicating operating conditions measured by the one or more associated sensors. The output is used to provide digital data to an interconnect system. The reference terminal is used to receive a local reference voltage, wherein the local reference voltage is at least partially based on a reference voltage assigned by the interconnect system. The interconnect system, coupled to the configurable logical resource, the root monitor, and each of the plurality of satellite monitors, wherein the interconnect system is configured to: Distribute the reference voltage from the root monitor to each of the plurality of satellite monitors; and The digital data from each of the plurality of satellite monitors is selectively routed to the root monitor, wherein the digital data indicates the operating conditions of the measurement.

2. The programmable device according to claim 1, characterized in that, The root monitor includes at least one of the following: A bandgap circuit configured to compensate the reference voltage for temperature variations; A memory configured to store the digital data received from each of the plurality of satellite monitors; as well as A controller configured to determine whether the operating conditions of the at least one associated circuit being measured are within a range.

3. The programmable device according to claim 1, characterized in that, Each of the satellite monitors includes at least one of the following: A memory, the memory including an input coupled to the output of the analog-to-digital converter and an output coupled to the interconnect system, the memory being configured to store the digital data provided by the analog-to-digital converter; as well as A switch configured to selectively couple the reference voltage allocated by the interconnect system to the satellite monitor based on a control signal generated by the root monitor, wherein the control signal is configured to simultaneously couple the reference voltage allocated by the interconnect system to only one of the satellite monitors.

4. The programmable device according to claim 1, characterized in that, The interconnection system also includes: One or more analog channels, the analog channels being configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors; and One or more digital channels configured to selectively route the digital data from the satellite monitor as individually addressable data packets to the root monitor.

5. The programmable device according to claim 4, characterized in that, Each of the satellite monitors is connected to one or more associated sensors via one or more local signal lines, and the satellite monitors also include: Local voltage source; An analog-to-digital converter, the analog-to-digital converter including a reference terminal for receiving a local reference voltage and configured to convert analog signals generated by the one or more associated sensors into digital codes indicating the operating conditions of the measurement; A calibration circuit, configured to generate a correction factor indicating an error in the digital code; and A correction circuit configured to correct the digital code based on the correction factor.

6. The programmable device according to claim 5, characterized in that, The local voltage source is configured as follows: Generate the local reference voltage; or The local reference voltage is stored based on a temperature-independent reference voltage generated by a bandgap voltage generator.

7. The programmable device according to claim 5, characterized in that, Also includes: An on-chip network interconnect system, which spans programmable logic and is configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.

8. The programmable device according to claim 5, characterized in that, Each of the satellite monitors also includes: A first switch, comprising: a first input terminal coupled to receive a temperature-independent reference voltage from the one or more analog channels; a second input terminal coupled to receive analog signals generated by one or more associated sensors; a control terminal coupled to receive control signals; and an output terminal coupled to the input terminal of the analog-to-digital converter within the satellite monitor.

9. The programmable device according to claim 8, characterized in that, During the calibration operation, the first switch provides the temperature-independent reference voltage as the input signal to the analog-to-digital converter; as well as During monitoring operations, the first switch provides the analog signal from the sensor as an input signal to the analog-to-digital converter.

10. The programmable device according to claim 9, characterized in that, During the calibration operation, the analog-to-digital converter samples the temperature-independent reference voltage to generate a reference code; as well as During the monitoring operation, the analog-to-digital converter samples analog signals from the one or more associated sensors to generate the digital code.

11. The programmable device according to claim 8, characterized in that, Each of the satellite monitors also includes: A second switch includes an input terminal coupled to receive the temperature-independent reference voltage from the one or more analog channels; a control terminal coupled to receive the control signal; and an output terminal coupled to a voltage memory.

12. The programmable device according to claim 11, characterized in that, During calibration operations: The second switch charges the voltage memory and isolates the voltage memory from the temperature-independent reference voltage; and The analog-to-digital converter samples the temperature-independent reference voltage to generate reference code.

13. A system for monitoring multiple operating conditions of a programmable device, characterized in that, The system includes: A root monitor, the root monitor including circuitry configured to generate a reference voltage; Multiple sensors are distributed on the programmable device, each of which is configured to generate an analog signal indicating the operating conditions of the associated circuitry; A plurality of satellite monitors are distributed on the programmable device, each satellite monitor being configured to convert analog signals generated by one or more corresponding sensors into digital data, and each satellite monitor comprising: a local voltage source; an analog-to-digital converter (ADC) including a reference terminal receiving a local reference voltage and configured to convert analog signals generated by one or more of the plurality of sensors into digital codes indicating operating conditions of the measurement; a calibration circuit configured to generate a correction factor indicating an error in the digital codes; and a correction circuit configured to correct the digital codes based on the correction factor; and An interconnection system, said interconnection system being coupled at least to the root monitor and each of the plurality of satellite monitors, said interconnection system comprising: One or more analog channels, the analog channels being configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors; and One or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.

14. The system according to claim 13, characterized in that, Each of the satellite monitors includes: A switch configured to selectively couple the reference voltage allocated by the interconnect system to the satellite monitor based on control signals generated by the root monitor; The control signal is configured to simultaneously couple the reference voltage, which is distributed by the interconnect system, to a single satellite monitor among the satellite monitors.

15. A method for monitoring multiple operating conditions of a programmable device, characterized in that, The method includes: A reference voltage is generated by using a voltage generator associated with a root monitor provided within the programmable device; The reference voltage is distributed to each of a plurality of satellite monitors by using one or more analog channels of an interconnect system integrated within the programmable device. Each satellite monitor includes an analog-to-digital converter, an output, and a reference terminal. The output is used to provide digital data to the interconnect system, and the reference terminal is used to receive a local reference voltage, wherein the local reference voltage is based at least in part on the reference voltage distributed by the interconnect system. An analog signal indicating the operating conditions of the associated circuit is generated by using each of a plurality of sensors; The analog signal generated by the plurality of sensors is provided to a corresponding satellite monitor among the plurality of satellite monitors; The analog signals are converted into digital data using the plurality of satellite monitors; and Digital data from the plurality of satellite monitors is selectively routed to the root monitor using one or more digital channels of the interconnection system.

16. The method according to claim 15, characterized in that, Allocating the reference voltage also includes: Based on a corresponding control signal generated by the root monitor, each of the plurality of satellite monitors is selectively coupled to the interconnect system, wherein the control signal is configured to simultaneously couple the reference voltage allocated by the interconnect system to one of the satellite monitors.

17. The method according to claim 15, characterized in that, The method further includes: The digital codes generated by the analog-to-digital converter within each of the plurality of satellite monitors are corrected at least in part based on the reference voltage.

18. The method of claim 17, wherein the reference voltage is a temperature-independent reference voltage.

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