Memory device with dual transistor vertical memory cell and common plate

Abstract

Some embodiments include apparatuses and methods of forming the same. One of the apparatuses includes a substrate, a conductive plate over the substrate to couple a ground connection, a data line between the substrate and the conductive plate, a memory cell, and a wire. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate and a charge storage structure electrically separate from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The wire is electrically separate from the first and second regions and spans portions of the first region of the first transistor and the second region of the second transistor and forms gates of the first and second transistors.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Provisional Application No. 62 / 892,988, filed on August 28, 2019, which is incorporated herein by reference in its entirety. Background Technology

[0003] Memory devices are widely used in computers and many other electronic devices to store information. They are generally classified into two types: volatile memory devices and non-volatile memory devices. Memory devices typically have numerous memory cells for storing information. In volatile memory devices, if the power supply is disconnected from the memory device, the information stored in the memory cells is lost. In non-volatile memory devices, the information stored in the memory cells is retained even if the power supply is disconnected.

[0004] The description in this article relates to volatile memory devices. Most conventional volatile memory devices store information as electrical charge in a capacitor structure contained within the memory cell. As the demand for device storage density increases, many conventional techniques offer methods for reducing the size of memory cells to increase the device storage density for a given device area. However, if the memory cell size needs to be reduced to a certain size, physical limitations and manufacturing constraints can pose challenges to such conventional techniques. Unlike some conventional memory devices, the memory device described in this article incorporates features that overcome the challenges faced by conventional techniques. Attached Figure Description

[0005] Figure 1 A block diagram illustrating a device in the form of a memory device including volatile memory cells, according to some embodiments described herein.

[0006] Figure 2 A schematic diagram showing a portion of a memory device according to some embodiments described herein, the memory device comprising a memory array of dual-transistor (2T) memory cells.

[0007] Figure 3 Demonstrating some embodiments according to the description herein Figure 2 The memory device includes the instance voltage used during read operations of the memory device.

[0008] Figure 4 Demonstrating some embodiments according to the description herein Figure 2 The memory device includes the instance voltage used during write operations of the memory device.

[0009] Figure 5and Figure 6 Demonstrating some embodiments according to the description herein Figure 2 Different views of the structure of the memory device.

[0010] Figures 7 to 21 The process of forming a memory device according to some embodiments described herein is illustrated.

[0011] Figures 22 to 26 This document demonstrates a process for forming another memory device according to some embodiments described herein.

[0012] Figure 27A , Figure 27B and Figure 27C Different views illustrating the structure of a memory device according to some embodiments described herein, the memory device comprising multiple stacks of memory cells. Detailed Implementation

[0013] The memory device described herein includes volatile memory cells, each of which may include two transistors (2T). One of the two transistors has a charge storage structure that forms a memory element of the memory cell to store information. The memory device described herein may have a structure that allows the size of the memory device to be relatively smaller than that of a similar conventional memory device (e.g., a 4F2 cell occupying an area). The described memory device may include a single access line (e.g., a word line) to control the two transistors of the memory cell. This can result in reduced power dissipation and improved processing. Each of the memory cells of the described memory device may include a cross-point gain cell structure (and cross-point operation) such that the memory cell can be accessed using a single access line (e.g., a word line) and a single data line (e.g., a bit line) during operation of the memory device (e.g., a read or write operation). See below. Figures 1 to 27C Discuss other improvements and benefits of the described memory device and its variations.

[0014] Figure 1This diagram illustrates a device in the form of a memory device 100 comprising volatile memory cells, according to some embodiments described herein. The memory device 100 includes a memory array 101, which may contain memory cells 102. The memory device 100 may include volatile memory devices such that memory cells 102 may be volatile memory cells. Examples of the memory device 100 include dynamic random access memory (DRAM) devices. If power supply (e.g., supply voltage Vcc) is disconnected from the memory device 100, information stored in the memory cells 102 of the memory device 100 may be lost (e.g., invalidated). Hereinafter, the supply voltage Vcc is referred to as representing some voltage level; however, it is not limited to the supply voltage (e.g., Vcc) of the memory device (e.g., memory device 100). For example, if the memory device (e.g., memory device 100) has an internal voltage generator that generates an internal voltage based on the supply voltage Vcc... Figure 1 If (not shown in the text), then this internal voltage can be used instead of the supply voltage Vcc.

[0015] In the physical structure of the memory device 100, each of the memory cells 102 may include transistors (e.g., two transistors) vertically formed (e.g., stacked on different layers) in different layers above a substrate (e.g., a semiconductor substrate) of the memory device 100. The memory device 100 may also include multiple layers (e.g., multiple stacks) of memory cells, wherein one layer (e.g., one stack) of memory cells may be formed above (e.g., another stack) of additional memory cells (e.g., stacked on another layer). The structure of the memory array 101 including the memory cells 102 may include, as described below. Figures 2 to 27C The structure of the memory array and memory cell described.

[0016] like Figure 1 As shown, memory device 100 may include access lines 104 (e.g., "word lines") and data lines (e.g., bit lines) 105. Memory device 100 may use signals on access lines 104 (e.g., word line signals) to access memory cells 102, and use signals on data lines 105 to provide information (e.g., data) to be stored (e.g., written) in or read from memory cells (e.g., sensed).

[0017] Memory device 100 may include an address register 106 for receiving address information ADDR (e.g., row address signals and column address signals) on lines (e.g., address lines) 107. Memory device 100 may include a row access circuitry (e.g., an X decoder) 108 and a column access circuitry (e.g., a Y decoder) 109 operable to decode the address information ADDR from address register 106. Based on the decoded address information, memory device 100 may determine which memory cells 102 to access during memory operations. Memory device 100 may perform write operations to store information in memory cells 102 and read operations to read (e.g., sense) information in memory cells 102 (e.g., previously stored information). Memory device 100 may also perform operations to refresh the values ​​of information stored in memory cells 102 (e.g., keep the values ​​valid) (e.g., refresh operations). Each of the memory cells 102 can be configured to store information that may represent a single bit (e.g., a single bit with binary 0 ("0") or binary 1 ("1")) or more than one bit (e.g., multiple bits with a combination of at least two binary bits).

[0018] The memory device 100 may receive supply voltages, including supply voltages Vcc and Vss on lines 130 and 132, respectively. The supply voltage Vss may operate at ground potential (e.g., having a value of approximately zero volts). The supply voltage Vcc may include an external voltage supplied to the memory device 100 from an external power source, such as a battery or an AC-to-DC converter circuitry.

[0019] like Figure 1 As shown, memory device 100 may include a memory control unit 118, which includes circuitry (e.g., hardware components) for controlling memory operations (e.g., read and write operations) of memory device 100 based on control signals on line (e.g., control line) 120. Examples of signals on line 120 include row access strobe signal RAS*, column access strobe signal CAS*, write enable signal WE*, chip select signal CS*, clock signal CK, and clock enable signal CKE. These signals may be part of the signals provided to the DRAM device.

[0020] like Figure 1As shown, memory device 100 may include lines (e.g., global data lines) 112 capable of carrying signals DQ0 to DQN. During a read operation, the value (e.g., "0" or "1") of information provided to line 112 (read from memory cell 102) (in the form of signals DQ0 to DQN) may be based on the value of a signal on data line 105. During a write operation, the value (e.g., "0" or "1") of information provided to data line 105 (to be stored in memory cell 102) may be based on the value of signals DQ0 to DQN on line 112.

[0021] Memory device 100 may include sensing circuitry 103, selection circuitry 115, and input / output (I / O) circuitry 116. Column access circuitry 109 may selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Selection circuitry 115 may respond to signals on line 114 to select signals on data line 105. Signals on data line 105 may represent the value of information to be stored in memory cell 102 (e.g., during a write operation) or the value of information read from memory cell 102 (e.g., sensed) (e.g., during a read operation).

[0022] I / O circuitry 116 is operable to provide information read from memory cell 102 to line 112 (e.g., during a read operation) and to provide information from line 112 (e.g., provided by an external device) to data line 105 for storage in memory cell 102 (e.g., during a write operation). Line 112 may contain nodes within memory device 100 or pins (or solder balls) on a package in which memory device 100 may reside. Other devices external to memory device 100 (e.g., a hardware memory controller or hardware processor) may communicate with memory device 100 via lines 107, 112, and 120.

[0023] The memory device 100 may include other components, said components in Figure 1 Examples of embodiments not shown herein are not illustrated to avoid confusion with those described herein. At least a portion of memory device 100 (e.g., a portion of memory array 101) may contain components similar to or identical to those described below. Figures 2 to 27C The structure and operation of any of the described memory devices.

[0024] Figure 2 This is a schematic diagram illustrating a portion of a memory device 200 comprising a memory array 201 containing 2T memory cells according to some embodiments described herein. The memory device 200 may correspond to... Figure 1 The memory device 100. For example, the memory array 201 may be formed Figure 1 A portion of the memory array 101. For example... Figure 2 As shown, memory device 200 may include memory cells 210 to 215, which are volatile memory cells (e.g., DRAM cells). For simplicity, similar or identical elements in memory cells 210 to 215 are given the same designation.

[0025] Each of memory cells 210 to 215 may include two transistors T1 and T2. Therefore, each of memory cells 210 to 215 may be referred to as a 2T memory cell (e.g., a 2T gain cell). Each of transistors T1 and T2 may include a field-effect transistor (FET). As an example, transistor T1 may be a p-channel FET (PFET), and transistor T2 may be an n-channel FET (NFET). A portion of transistor T1 may include the structure of a p-channel metal-oxide-semiconductor (PMOS) transistor FET (PFET). Therefore, transistor T1 may operate similarly to a PMOS transistor. A portion of transistor T2 may include the structure of an n-channel metal-oxide-semiconductor (NMOS). Therefore, transistor T2 may operate similarly to an NMOS transistor.

[0026] The transistor T1 of the memory device 200 may include a charge memory-based structure (e.g., based on a floating gate). Figure 2 As shown, each of memory cells 210 to 215 may include a charge storage structure 202, which may include a floating gate of transistor T1. The charge storage structure 202 may form a memory element of a respective memory cell among memory cells 210 to 215. The charge storage structure 202 may store charge. The value of information stored in a particular memory cell among memory cells 210 to 215 (e.g., "0" or "1") may be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0027] like Figure 2 As shown, the transistor T2 (e.g., the channel region of transistor T2) of a particular memory cell among memory cells 210 to 215 can be electrically coupled (e.g., directly coupled to) the charge storage structure 202 of that particular memory cell. Therefore, during operation of the memory device 200 (e.g., a write operation), a circuit path (e.g., a current path) can be directly formed between the transistor T2 of the particular memory cell and the charge storage structure 202 of that particular memory cell.

[0028] Memory cells 210 to 215 may be arranged in memory cell groups 2010 and 2011. Figure 2Two memory cell groups (e.g., 2010 and 2011) are shown as examples. However, memory device 200 may include more than two memory cell groups. Memory cell groups 2010 and 2011 may contain the same number of memory cells. For example, memory cell group 2010 may include memory cells 210, 212, and 214, and memory cell group 2011 may include memory cells 211, 213, and 215. Figure 2 Three memory cells are shown as examples in each of memory cell groups 2010 and 2011. The number of memory cells in memory cell groups 2010 and 2011 may be different from three.

[0029] The memory device 200 can perform write operations to store information in memory cells 210 to 215 and read operations to read (e.g., sense) information from memory cells 210 to 215. The memory device 200 can be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in a structure such as a capacitor, the memory device 200 can store information in the form of a charge in a charge storage structure 202 (which may be a floating gate structure). As mentioned above, the charge storage structure 202 may be the floating gate of transistor T1. During operation of the memory device 200 (e.g., read or write operations), access lines (e.g., single access lines) and data lines (e.g., single data lines) can be used to access selected memory cells (e.g., target memory cells).

[0030] like Figure 2 As shown, memory device 200 may include access lines (e.g., word lines) 241, 242, and 243 that can carry corresponding signals (e.g., word line signals) WL1, WL2, and WLn. Access lines 241, 242, and 243 can be used to access two memory cell groups 2010 and 2011. Each of access lines 241, 242, and 243 may be structured as at least one conductor (one conductor or multiple conductors electrically coupled (e.g., shorted) to each other). Access lines 241, 242, and 243 may be selectively activated (e.g., one at a time) during operation of memory device 200 (e.g., read or write operation) to access selected memory cells (or multiple selected memory cells) among memory cells 210 to 215. The selected cell may be referred to as the target cell. In a read operation, information can be read from the selected memory cell (or multiple selected memory cells). During a write operation, information can be stored in selected memory cells (or multiple selected memory cells).

[0031] In memory device 200, a single access line (e.g., a single word line) can be used to control (e.g., turn on or off) transistors T1 and T2 of a corresponding memory cell during read or write operations of memory device 200. Some conventional memory devices may use multiple (e.g., two separate) access lines to control access to a corresponding memory cell during read and write operations. Compared to such conventional memory devices (which use multiple access lines for the same memory cell), memory device 200 uses a single access line (e.g., a shared access line) in memory device 200 to control two transistors T1 and T2 of a corresponding memory cell, thereby accessing the corresponding memory cell. This technique saves space and simplifies the operation of memory device 200. Additionally, some conventional memory devices may use multiple data lines to access selected memory cells (e.g., during read operations) to read information from selected memory cells. In memory device 200, a single data line (e.g., data line 221 or 222) can be used to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. This simplifies the structure, operation, or both of memory device 200 compared to conventional memory devices that use multiple data lines to access selected memory cells.

[0032] In memory device 200, the gate of each of transistors T1 and T2 may be a portion of a corresponding access line (e.g., a corresponding word line). Figure 2 As shown, the gate of each of transistors T1 and T2 in memory cell 210 may be a portion of access line 241. Similarly, the gate of each of transistors T1 and T2 in memory cell 211 may be a portion of access line 241. For example, in the structure of memory device 200, four different portions of the conductive material (or multiple materials) forming access line 241 may respectively form the gates of transistors T1 and T2 in memory cell 210 and the gates of transistors T1 and T2 in memory cell 211 (e.g., four gates).

[0033] The gate of each of transistors T1 and T2 in memory cell 212 may be a portion of access line 242. The gate of each of transistors T1 and T2 in memory cell 213 may be a portion of access line 242. For example, in the structure of memory device 200, four different portions of the conductive material (or multiple materials) forming access line 242 may respectively form the gates of transistors T1 and T2 in memory cell 212 and the gates of transistors T1 and T2 in memory cell 213 (e.g., four gates).

[0034] The gate of each of transistors T1 and T2 in memory cell 214 may be a portion of access line 243. The gate of each of transistors T1 and T2 in memory cell 215 may be a portion of access line 243. For example, in the structure of memory device 200, four different portions of the conductive material (or multiple materials) forming access line 243 may respectively form the gates of transistors T1 and T2 in memory cell 214 and the gates of transistors T1 and T2 in memory cell 215 (e.g., four gates).

[0035] Memory device 200 may include data lines (e.g., bit lines) 221 and 222 capable of carrying corresponding signals (e.g., bit line signals) BL1 and BL2. During a read operation, memory device 200 may use data line 221 to obtain information read (e.g., sensed) from selected memory cells of memory cell group 2010, and use data line 222 to read information from selected memory cells of memory cell group 2011. During a write operation, memory device 200 may use data line 221 to provide information to be stored in selected memory cells of memory cell group 2010, and use data line 222 to provide information to be stored in selected memory cells of memory cell group 2011.

[0036] Memory device 200 may include a ground connection (e.g., a ground plane) 297 coupled to each of memory cells 210 to 215. Ground connection 297 may be structured by a conductive plate (e.g., a layer of conductive material) that can be coupled to a ground terminal of memory device 200. As an example, ground connection 297 may be a common conductive plate of memory device 200 (e.g., formed over memory cells (e.g., memory cells 210 to 215)). In this example, the common conductive plate may be formed over elements (e.g., transistors T1 and T2) of each of the memory cells (e.g., memory cells 210 to 215) of memory device 200.

[0037] like Figure 2 As shown, the transistor T1 (e.g., the channel region of transistor T1) of a specific memory cell among memory cells 210 to 215 can be electrically coupled (e.g., directly coupled to) ground connection 297 and electrically coupled (e.g., directly coupled to) the corresponding data line (e.g., data line 221 or 222). Therefore, during an operation performed on the selected memory cell (e.g., a read operation), a circuit path (e.g., a current path) can be formed between the corresponding data line (e.g., data line 221 or 222) and ground connection 297 via the transistor T1 of the selected memory cell.

[0038] Memory device 200 may include a read path (e.g., a circuit path). Information read from a selected memory cell during a read operation may be obtained via a read path coupled to the selected memory cell. In memory cell group 2010, the read path of a particular memory cell (e.g., memory cells 210, 212, or 214) may include a current path (e.g., a read current path) through the channel region of transistor T1 of that particular memory cell, data line 221, and ground connection 297. In memory cell group 2011, the read path of a particular memory cell (e.g., memory cells 211, 213, or 215) may include a current path (e.g., a read current path) through the channel region of transistor T1 of that particular memory cell, data line 222, and ground connection 297. In an example where transistor T1 is a PFET (e.g., PMOS), the current in the read path (e.g., during a read operation) may include hole conduction (e.g., hole conduction in the direction from data line 221 through the channel region of transistor T1 to ground connection 297). Since transistor T1 can be used in the read path to read information from the corresponding memory cell during a read operation, transistor T1 can be called a read transistor and the channel region of transistor T1 can be called a read channel region.

[0039] Memory device 200 may include write paths (e.g., circuit paths). Information to be stored in a selected memory cell during a write operation may be provided to the selected memory cell via a write path coupled to the selected memory cell. In memory cell group 2010, the write path of a particular memory cell may include a transistor T2 of that particular memory cell (e.g., a write current path may be included through the channel region of transistor T2) and a data line 221. In memory cell group 2011, the write path of a particular memory cell (e.g., memory cells 211, 213, or 215) may include a transistor T2 of that particular memory cell (e.g., a write current path may be included through the channel region of transistor T2) and a data line 222. In an example where transistor T2 is an NFET (e.g., NMOS), the current in the write path (e.g., during a write operation) may include electronic conduction through the channel region of transistor T2 (e.g., electronic conduction in the direction from data line 221 to charge storage structure 202). Since transistor T2 can be used in the write path to store information in the corresponding memory cell during a write operation, transistor T2 can be called a write transistor and the channel region of transistor T1 can be called a write channel region.

[0040] Each of transistors T1 and T2 may include a threshold voltage (Vt). Transistor T1 has a threshold voltage Vt1. Transistor T2 has a threshold voltage Vt2. The values of the threshold voltages Vt1 and Vt2 may be different (unequal). For example, the value of the threshold voltage Vt2 may be greater than the value of the threshold voltage Vt1. The difference between the values of the threshold voltages Vt1 and Vt2 allows information stored in the charge storage structure 202 of transistor T1 on the read path to be read (e.g., sensed) during a read operation without affecting (e.g., turning on) transistor T2 on the write path (e.g., the path through transistor T2). This may prevent charge from leaking from the charge storage structure 202 through transistor T2 of the write path (e.g., during a read operation).

[0041] In the structure of memory device 200, transistors T1 and T2 may be formed (e.g., engineered) such that the threshold voltage Vt1 of transistor T1 may be less than zero volts (e.g., Vt1 < 0V), regardless of the value of the information stored in the charge storage structure 202 of transistor T1 (e.g., "0" or "1"), and Vt1 < Vt2. When information having a value of "0" is stored in the charge storage structure 202, the charge storage structure 202 may be in state "0". When information having a value of "1" is stored in the charge storage structure 202, the charge storage structure 202 may be in state "1". Thus, in this structure, the relationship between the values of the threshold voltages Vt1 and Vt2 may be expressed as follows: Vt1 for state "0" < Vt1 for state "1" < 0V, and Vt2 = 0V (or alternatively, Vt2 > 0V).

[0042] In an alternative structure of memory device 200, transistors T1 and T2 may be formed (e.g., engineered) such that Vt1 for state "0" < Vt1 for state "1", where Vt1 for state "0" < 0V (or alternatively, Vt1 for state "0" = 0V), Vt1 for state "1" > 0V, and Vt1 < Vt2.

[0043] In another alternative structure, transistors T1 and T2 may be formed (e.g., engineered) such that Vt1 (for state "0") < Vt1 (for state "1"), where Vt1 for state "0" = 0V (or alternatively, Vt1 for state "0" > 0V) and Vt1 < Vt2.

[0044] During a read operation of memory device 200, only one memory cell from the same memory cell group can be selected at a time to read information from the selected memory cell. For example, memory cells 210, 212, and 214 of memory cell group 2010 can be selected one at a time during a read operation to read information from a selected memory cell (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of memory cell group 2011 can be selected one at a time during a read operation to read information from a selected memory cell (e.g., one of memory cells 211, 213, and 215 in this example).

[0045] During a read operation, memory cells from different memory cell groups (e.g., memory cell groups 2010 and 2011) sharing the same access line (e.g., access lines 241, 242, or 243) can be selected simultaneously (or alternatively, sequentially). For example, memory cells 210 and 211 can be selected simultaneously during a read operation to read (e.g., read information simultaneously) from memory cells 210 and 211. Memory cells 212 and 213 can be selected simultaneously during a read operation to read (e.g., read information simultaneously) from memory cells 212 and 213. Memory cells 214 and 215 can be selected simultaneously during a read operation to read (e.g., read information simultaneously) from memory cells 214 and 215.

[0046] The value of information read from a selected memory cell in memory cell group 2010 during a read operation can be determined based on the value of a current detected (e.g., sensed) from a read path (described above), which includes data line 221, transistor T1 of the selected memory cell (e.g., memory cell 210, 212, or 214), and ground connection 297. The value of information read from a selected memory cell in memory cell group 2011 during a read operation can be determined based on the value of a current detected (e.g., sensed) from a read path, which includes data line 222, transistor T1 of the selected memory cell (e.g., memory cell 211, 213, or 215), and ground connection 297.

[0047] Memory device 200 may include a detection circuitry (not shown) operable during a read operation to detect (e.g., sense) a current (e.g., current I1, not shown) on a read path including data line 221 and a current (e.g., current I2, not shown) on a read path including data line 222. The value of the detected current may be based on the value of information stored in selected memory cells. For example, depending on the value of information stored in selected memory cells of memory cell group 2010, the value of the detected current on data line 221 (e.g., the value of current I1) may be zero or greater than zero. Similarly, depending on the value of information stored in selected memory cells of memory cell group 2011, the value of the detected current on data line 222 (e.g., the value of current I2) may be zero or greater than zero. Memory device 200 may include a circuitry (not shown) for translating the value of the detected current into a value of information stored in the selected memory cells (e.g., a combination of "0", "1", or multiple bit values).

[0048] During a write operation of memory device 200, only one memory cell from the same memory cell group can be selected at a time to store information in the selected memory cell. For example, memory cells 210, 212, and 214 of memory cell group 2010 can be selected one at a time during a write operation to store information in selected memory cells (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of memory cell group 2011 can be selected one at a time during a write operation to store information in selected memory cells (e.g., one of memory cells 211, 213, and 215 in this example).

[0049] During a write operation, memory cells from different memory cell groups (e.g., memory cell groups 2010 and 2011) sharing the same access line (e.g., access lines 241, 242, or 243) can be selected simultaneously. For example, memory cells 210 and 211 can be selected simultaneously during a write operation to store information (e.g., simultaneously stored) in memory cells 210 and 211. Memory cells 212 and 213 can be selected simultaneously during a write operation to store information (e.g., simultaneously stored) in memory cells 212 and 213. Memory cells 214 and 215 can be selected simultaneously during a write operation to store information (e.g., simultaneously stored) in memory cells 214 and 215.

[0050] Information to be stored in selected memory cells of memory cell group 2010 during a write operation may be provided via a write path (described above) comprising data line 221 and transistor T2 of the selected memory cell (e.g., memory cell 210, 212, or 214). Information to be stored in selected memory cells of memory cell group 2011 during a write operation may be provided via a write path (described above) comprising data line 222 and transistor T2 of the selected memory cell (e.g., memory cell 211, 213, or 215). As described above, the value (e.g., binary value) of information stored in a particular memory cell among memory cells 210 to 215 may be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0051] During a write operation, the amount of charge in the charge storage structure 202 of a selected memory cell (reflecting the value of the information stored in the selected memory cell) can be changed by applying a voltage along the write path, which includes a transistor T2 of that specific memory cell and a data line coupled to that specific memory cell (e.g., data line 221 or 222). For example, if the information to be stored in the selected memory cells 210, 212, and 214 has a value (e.g., "0"), a voltage with a value (e.g., 0V) can be applied to data line 221 (e.g., providing 0V to signal BL1). In another example, if the information to be stored in the selected memory cells 210, 212, and 214 has another value (e.g., "1"), a voltage with another value (e.g., a positive voltage) can be applied to data line 221 (e.g., providing a positive voltage to signal BL1). Therefore, information can be stored (e.g., directly stored) in the charge storage structure 202 of a particular memory cell by providing the information to be stored (e.g., in the form of a voltage) on the write path (including transistor T2) of a particular memory cell.

[0052] Figure 3 Demonstrating some embodiments according to the description herein Figure 2 The memory device 200 includes instance voltages V1, V2, and V3 used during read operations of the memory device 200. Figure 3 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) during a read operation to read (e.g., sense) information stored (e.g., previously stored) in memory cells 210 and 211. It is assumed that memory cells 212 to 215 are unselected memory cells. This means that in Figure 3In this example, memory cells 212 to 215 are not accessed, and the information stored in memory cells 212 to 215 is not read, but information is read from memory cells 210 and 211.

[0053] exist Figure 3 In this specification, voltages V1, V2, and V3 represent different voltages applied to the corresponding access lines 241, 242, and 243 and data lines 221 and 222 during a read operation of the memory device 200. As examples, voltages V1, V2, and V3 may have values ​​of -1V, 0V, and 0.5V, respectively. The specific voltage values ​​used in this specification are merely example values. Different values ​​may be used. For example, voltage V1 may have a negative range (e.g., the value of voltage V1 may be from -3V to -1V).

[0054] exist Figure 3 In the read operation illustrated, voltage V1 may have a value (voltage value) to turn on transistor T1 of each of memory cells 210 and 211 (selected memory cells in this example) and turn off (disable) transistor T2 of each of memory cells 210 and 211. This allows information to be read from memory cells 210 and 211. Voltage V2 may have a value such that transistors T1 and T2 of each of memory cells 212 to 215 (unselected memory cells in this example) are turned off (e.g., disabled). Voltage V3 may have a value such that current (e.g., read current) can be formed on the read path of transistor T1 containing data line 221 and memory cell 210 and the read path of transistor T1 containing data line 222 and memory cell 212 (separate read paths). This allows the current coupled to the read paths of memory cells 210 and 211 to be detected separately. The detection circuitry system (not shown) of memory device 200 is operable to translate the value of the detected current (during information reading from a selected memory cell) into the value of the information read from the selected memory cell (e.g., a combination of "0", "1", or multiple bit values). Figure 3 In the example, the values ​​of the detected currents on data lines 221 and 222 can be translated into the values ​​of information read from memory units 210 and 211, respectively.

[0055] exist Figure 3In the read operation illustrated, in addition to transistor T1 in each of memory cells 210 and 211 (selected memory cells), the voltages applied to the corresponding access lines 241, 242, and 243 can turn off (or remain off) transistors T1 and T2 in each of memory cells 212 to 215. Depending on the value of the threshold voltage Vt1 of transistor T1 in memory cell 210 (selected memory cell), transistor T1 in memory cell 210 may or may not be turned on. Depending on the value of the threshold voltage Vt1 of transistor T1 in memory cell 211 (selected memory cell), transistor T1 in memory cell 211 may or may not be turned on. For example, if the transistor T1 of each of the memory cells (e.g., 210 to 215) of the memory device 200 is configured (e.g., structured) such that the threshold voltage of the transistor T1 is less than zero (e.g., Vt1 < -1V) without regard to the value (e.g., state) of the information stored in the corresponding memory cell 210, then in this example, the transistor T1 of the memory cell 210 can be turned on and conduct current on the data line 221 (via the transistor T1 of the memory cell 210). In this example, the transistor T1 of the memory cell 211 can also be turned on and conduct current on the data line 222 (via the transistor T1 of the memory cell 211). The memory device 200 can determine the value of the information stored in the memory cells 210 and 211 based on the values ​​of the currents on the data lines 221 and 222, respectively. As described above, the memory device 200 may include a detection circuitry system to measure the values ​​of the currents on the data lines 221 and 222 during a read operation.

[0056] Figure 4 Demonstrating some embodiments according to the description herein Figure 2 The memory device 200 includes instance voltages V4, V5, V6 and V7 used during write operations of the memory device 200. Figure 4 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) during a write operation to store information in memory cells 210 and 211. It is assumed that memory cells 212 to 215 are unselected memory cells. This means that in Figure 4 In the example, memory cells 212 to 215 are not accessed, and information is not stored in memory cells 212 to 215, but in memory cells 210 and 211.

[0057] exist Figure 4In this context, voltages V4, V5, V6, and V7 represent different voltages applied to the corresponding access lines 241, 242, and 243, and data lines 221 and 222, during a write operation of the memory device 200. As an example, voltages V4 and V5 may have values ​​of 3V and 0V, respectively. These are example values; different values ​​may be used.

[0058] Depending on the value of the information to be stored in memory cells 210 and 211 (e.g., "0" or "1"), the values ​​of voltages V6 and V7 may be the same or different. For example, if memory cells 210 and 211 are to store information with the same value, then the values ​​of voltages V6 and V7 may be the same (e.g., V6 = V7). As an example, if the information to be stored in each memory cell 210 and 211 is "0", then V6 = V7 = 0V, and if the information to be stored in each memory cell 210 and 211 is "1", then V6 = V7 = 1V to 3V.

[0059] In another example, if memory cells 210 and 211 are to store information with different values, then the values ​​of voltages V6 and V7 can be different (e.g., V6 ≠ V7). For example, if "0" is to be stored in memory cell 210 and "1" is to be stored in memory cell 211, then V6 = 0V and V7 = 1V to 3V. For another example, if "1" is to be stored in memory cell 210 and "0" is to be stored in memory cell 211, then V6 = 1V to 3V and V7 = 0V.

[0060] A voltage range of 1V to 3V is used here as an example. Different voltage ranges can be used. Alternatively, instead of applying 0V (e.g., V6 = 0V or V7 = 0V) to a specific write data line (e.g., data line 221 or 222) to store information with a value of "0" into a memory cell (e.g., memory cell 210 or 211) coupled to that specific write data line, a positive voltage (e.g., V6 > 0V or V7 > 0V) can be applied to that specific data line.

[0061] exist Figure 4During a write operation of the memory device 200, voltage V5 may have a value that turns off (e.g., disables) transistors T1 and T2 of each of memory cells 212 to 215 (unselected memory cells in this example). Voltage V4 may have a value that turns on transistor T2 of each of memory cells 210 and 211 (selected memory cells in this example), forming a write path between the charge storage structure 202 of memory cell 210 and the data line 221, and a write path between the charge storage structure 202 of memory cell 211 and the data line 222. A current (e.g., a write current) may be formed between the charge storage structure 202 of memory cell 210 (selected memory cell) and the data line 221. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of memory cell 210 to reflect the value of the information to be stored in memory cell 210. A current (e.g., another write current) may be formed between the charge storage structure 202 of memory cell 211 (selected memory cell) and the data line 222. This current can affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 211 to reflect the value of the information to be stored in the memory cell 211.

[0062] exist Figure 4 In the instance write operation, the value of voltage V6 can cause the charge storage structure 202 of memory cell 210 to discharge or be charged, such that the resulting charge on the charge storage structure 202 of memory cell 210 (e.g., the charge remaining after the discharge or charge operation) reflects the value of the information stored in memory cell 210. Similarly, in this example, the value of voltage V7 can cause the charge storage structure 202 of memory cell 211 to discharge or be charged, such that the resulting charge on the charge storage structure 202 of memory cell 211 (e.g., the charge remaining after the discharge or charge operation) reflects the value of the information stored in memory cell 211.

[0063] Figure 5 and Figure 6 Demonstrating some embodiments described herein with respect to the X, Y, and Z directions Figure 2 Different views of the structure of the memory device 200. Figure 5 A side view (e.g., cross-sectional view) of the memory device 200 relative to the XZ direction is shown. Figure 6 Display along Figure 5 The view taken by line 6-6 (e.g., a cross-sectional view).

[0064] For simplicity, Figure 5 and Figure 6 The structure of memory cells 210 and 211 is shown. Figure 2The structure of other memory cells (e.g., memory cells 212 to 215) of the memory device 200 may be similar to or the same as that of the memory device 200. Figure 5 and Figure 6 The structure of memory cells 210 and 211 is shown in the figure. Figure 2 , Figure 5 and Figure 6 In this context, identical components are given the same reference number.

[0065] See the following description Figure 5 and Figure 6 For simplicity, in Figure 5 and Figure 6 The description of the same component will not be repeated in detail. Also, for simplicity, from... Figure 5 and Figure 6 And other diagrams in the schemata described herein (e.g., Figures 7 to 27C Most of the elements shown in the drawings omit cross-sectional lines (e.g., shaded lines). Some elements of the memory device 200 may be omitted from specific drawings to avoid confusion in the description of elements (or elements) depicted in that particular drawing. The dimensions (e.g., physical structures) of the elements shown in the drawings described herein are not drawn to scale.

[0066] like Figure 5 As shown, memory device 200 may include a substrate 599, and memory cells 210 and 211 (and other memory cells of memory device 200 (not shown)) may be formed on said substrate. Transistors T1 and T2 of each of memory cells 210 and 211 may be formed perpendicular to substrate 599. Substrate 599 may be a semiconductor substrate (e.g., a silicon-based substrate) or other types of substrate. The Z-direction (e.g., the vertical direction) is a direction perpendicular to substrate 599 (e.g., extending outward from the substrate). The Z-direction is also perpendicular to the X and Y directions (e.g., extending perpendicularly from the X and Y directions). The X and Y directions are perpendicular to each other.

[0067] like Figure 5 and Figure 6 As shown, ground connection 297 may include a material structure (e.g., a sheet (e.g., a layer)) located above the elements (described below) of memory cells 201 and 211 and above data lines 221 and 222. Example materials for ground connection 297 include metal sheets, conductive doped polysilicon, or other conductive materials. Ground connection 297 may be coupled to a ground terminal (not shown) of memory device 200. Therefore, as... Figure 5 As shown, the elements of memory cells 210 and 211, as well as data lines 221 and 222, may be located between the substrate 599 and the material (e.g., metal) forming the ground connection 297 (e.g., in the respective layers).

[0068] like Figure 5 As shown, memory device 200 may include dielectric 590 formed over a portion of substrate 599. Dielectric 590 may comprise silicon oxide. Dielectric 590 electrically separates the elements of memory cells 210 and 211, as well as data lines 221 and 222, from substrate 599.

[0069] like Figure 5 and Figure 6 As shown, data line 221 (associated with signal BL1) may have a length in the Y direction ( Figure 6 Width in the X direction ( Figure 5 ) and thickness in the Z direction ( Figure 5 Similarly, data line 222 (associated with signal BL2) may have a length in the Y direction ( Figure 6 (not shown in the image), width in the X direction ( Figure 5 ) and thickness in the Z direction ( Figure 5 Each of data lines 221 and 222 may contain a conductive material (or combination of materials) that can be structured into wires (e.g., conductive regions). Examples of materials used for data lines 221 and 222 include metals, conductive doped polysilicon, or other conductive materials.

[0070] Access line 241 (associated with signal WL1) can be structured (may include) by a combination of portions 541F and 541B (e.g., front and rear conductive portions relative to the Y direction). Each of portions 541F and 541B may contain a conductive material (or combination of materials) that can be structured as a conductor (e.g., a conductive region) having a length that extends continuously in the X direction. Thus, portions 541F and 541B may be portions of conductors that are opposite each other (e.g., opposite each other in the Y direction).

[0071] Each of portions 541F and 541B may comprise a structure (e.g., a sheet, layer) of a conductive material (e.g., a metal, conductive doped polysilicon, or other conductive material). Each of portions 541F and 541B may have a length in the X direction ( Figure 5 (as shown in the image), width in the Z direction ( Figure 5 (as shown in the image) and thickness in the Y direction ( Figure 6 (As shown in the image).

[0072] Parts 541F and 541B may be electrically coupled to each other. For example, memory device 200 may include conductive material (e.g., not shown) that is accessible (e.g., electrically coupled to) parts 541F and 541B, such that parts 541F and 541B (which are portions of a single access line 241) may be simultaneously subjected to the same signal (e.g., signal WL1).

[0073] In an alternative configuration of the memory device 200, portion 541F or portion 541B can be omitted, allowing access line 241 to contain only portion 541F or portion 541B. Figure 5 The structure shown includes two parts, 541F and 541B, which can help to preferably control the transistor T1 in each of the memory cells 210 and 211 during read operations (e.g., Figure 2 Transistor T1 is shown schematically in the diagram.

[0074] The charge storage structure 202 may include a charge storage material (or a combination of materials), which may comprise a semiconductor material (e.g., polysilicon) wafer (e.g., a layer), a metal wafer (e.g., a layer), or a material (or multiple materials) wafer capable of capturing charge. The materials used for portions 541F and 541B of the charge storage structure 202 and access line 241 may be the same or different. Figure 5 As shown, the charge storage structure 202 may include a portion (e.g., a top portion) that is further away from the substrate 599 (e.g., extends further away from the substrate in the Z direction) than each of the portions 541F and 541B of the access line 241.

[0075] Figure 5 and Figure 6 The top edge of the charge storage structure 202 is separated from the edge (e.g., the top edge) of each of the portions 541F and 541B of the access line 241 by a specific distance (e.g., Figure 5 Examples of distances shown in the diagram. However, the distance between the bottom edge of the charge storage structure 202 and the edge (e.g., the top edge) of each of portions 541F and 541B can vary.

[0076] Figure 5 and Figure 6 Examples are shown where portions of 541F and 541B overlap with charge storage structure 202 (in the Z direction). However, portions of 541F and 541B may not overlap with charge storage structure 202.

[0077] The memory device 200 may include material 520 located between the data line 221 and the charge storage structure 202. For example... Figure 5 As shown, material 520 can be electrically coupled to data line 221 and charge storage structure 202 of memory cell 210. As described above, charge storage structure 202 of memory cell 210 can form a memory element of memory cell 210. Therefore, as Figure 5As shown, memory cell 210 may be contained in material 520 positioned between memory element (which is charge storage structure 202) and substrate 599 and relative to the Z direction, and memory element contact (e.g., directly coupled to) material 520.

[0078] Material 520 can form the source (e.g., source terminal), drain (e.g., drain terminal), and channel region (e.g., write channel region) between the source and drain of the transistor T2 of the memory cell 210. Therefore, as... Figure 5 As shown, the source, channel region, and drain of transistor T2 in memory cell 210 can be formed from a single piece of the same material (or alternatively, a single piece of the same combination of materials) of material 520. Therefore, the source, drain, and channel region of transistor T2 in memory cell 210 can be formed from the same material (e.g., material 520) of the same conductivity type (e.g., n-type or p-type).

[0079] like Figure 5 As shown, the memory device 200 may include material 521, which may form the source (e.g., source terminal), drain (e.g., drain terminal), and channel region (e.g., write channel region) between the source and drain of the transistor T2 of the memory cell 211. Therefore, as Figure 5 As shown, the source, channel region and drain of transistor T2 in memory cell 211 can be formed from a single piece of the same material as material 521 (or alternatively, a single piece of the same combination of materials).

[0080] Materials 520 and 521 may be the same. For example, each of materials 520 and 521 may comprise a semiconductor material structure (e.g., a wafer (e.g., a layer)). In an example where transistor T2 is an NFET (as described above), materials 520 and 521 may comprise an n-type semiconductor material (e.g., n-type silicon).

[0081] In another example, the semiconductor material forming material 520 or material 521 may comprise a sheet of oxide material. Examples of oxide materials used for materials 520 and 521 include semiconductive oxide materials, transparent conductive oxide materials, and other oxide materials.

[0082] As an example, each of materials 520 and 521 may include at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO). x Indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO) x In₂O₃), tin oxide (SnO₂), titanium oxide (TiO₂), zinc oxide (ZnO₂) x Oy N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O z Indium gallium zinc oxide (In) x Ga y Zn z O a Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf) x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ), silicon indium zinc (Si) x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum oxide zinc tin (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconia zinc tin (Zr) x Zn y Sn z O a Indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

[0083] The use of the materials listed above in memory device 200 provides improvements and benefits to memory device 200. For example, during a read operation, in order to read information from a selected memory cell (e.g., memory cell 210 or 211), charge from the charge storage structure 202 of the selected memory cell may leak to the transistor T2 of the selected memory cell. Using the materials listed above in the channel region of transistor T2 (e.g., materials 520 or 521) can reduce or prevent this leakage. This improves the accuracy of information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory device (e.g., memory device 200) described herein.

[0084] The materials listed above are examples of materials 520 and 521. However, other materials different from those listed above (e.g., materials with relatively high band gaps) may be used.

[0085] exist Figure 5 In one embodiment, the material 520 of the memory cell 210 and the charge storage structure 202 are electrically coupled (e.g., directly coupled) to each other, such that the material 520 can contact the charge storage structure 202 of the memory cell 210 without any intermediate material (e.g., no conductive material) between the charge storage structure 202 of the memory cell 210 and the material 520. In another embodiment, the material 520 is electrically coupled to the charge storage structure 202 of the memory cell 210, such that the material 520 is not directly coupled to (does not contact) the charge storage structure 202 of the memory cell 210, but is connected via an intermediate material (e.g., conductive material) between the material 520 and the charge storage structure 202 of the memory cell 210. Figure 5 The charge storage structure 202 (not shown) is coupled to (e.g., indirectly contacted) the memory cell 210.

[0086] like Figure 5 As shown, memory device 200 may include a portion 580 electrically coupled to data line 221. The portion 580 may include a structure of silicon, polysilicon or other semiconductor material (e.g., a wafer (e.g., a layer)) and may include a doped region (e.g., a p-type doped region).

[0087] Memory cell 210 may include portion 510A electrically coupled to portion 580, data line 221, and ground connection 297. Portion 510A may include a semiconductor material structure (e.g., a wafer (e.g., a layer)). Examples of materials used for portion 510A include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon-germanium or other semiconductor materials, and semiconducting oxide materials (oxide semiconductors, such as SnO or other oxide semiconductors).

[0088] See above. Figure 2As described, the transistor T1 of the memory cell 210 includes a channel region (e.g., a read channel region). In Figure 5 In the memory cell 210, the channel region of transistor T1 may include a portion 510A (e.g., may be formed by said portion). See above. Figure 2 As described, memory cell 210 may include a read path. Figure 5 In this configuration, portion 510A (e.g., the read channel region of transistor T1 in memory cell 210) may be a portion of the read path of memory cell 210, which may carry current (e.g., read current) during a read operation to read information from memory cell 210. For example, during a read operation, in order to read information from memory cell 210, portion 510A may conduct current (e.g., read current) between data line 221 and ground connection 297 (via a portion of portion 580). The direction of the read current may be from data line 221 to ground connection 297. In an example where transistor T1 is a PFET and transistor T2 is an NFET, the material forming portion 510A may have a different conductivity type than materials 520 or 521. For example, portion 510A may include a p-type semiconductor material (e.g., p-type silicon) region, and materials 520 and 521 may include an n-type semiconductor material (e.g., n-type gallium phosphide (GaP)) region.

[0089] like Figure 5 As shown, memory cell 210 may include a dielectric 515B for electrically separating the respective charge storage 202 of memory cells 210 and 211 from ground connection 297. Memory cell 210 may include dielectric 515A. Dielectric 515A may be a gate oxide region that electrically separates charge storage structure 202 from portion 510A and material 520 from portion 510A. Example materials for dielectric 515A include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials. In example structures of memory device 200, dielectric 515A comprises a high-k dielectric material (e.g., a dielectric material having a dielectric constant greater than that of silicon dioxide). Using this high-k dielectric material (instead of silicon dioxide) can improve the performance of memory device 200 (e.g., reduce current leakage, increase the drive capability of transistor T1, or both).

[0090] like Figure 5 As shown, a portion of 541F may span (e.g., overlap in the X direction) a portion of 510A and a portion of material 520. As described above, portion 510A may form a portion of the read channel region of transistor T1, and material 520 may form a portion of the write channel region of transistor T2. Therefore, as Figure 5As shown, portions of 541F may respectively span (e.g., overlap) portions of both the read and write channels of transistors T1 and T2 (e.g., on one side (e.g., the front side) in the Y direction). Although from Figure 5 The view shown in the image is hidden (but in...) Figure 6 (As can be seen), but a portion of 541B may cross (e.g., overlap in the X direction) a portion of 510A (e.g., on the other side in the Y direction (e.g., the rear side opposite the front side)) and a portion of material 520. Figure 5 As shown, access line 241 may also cross (e.g., overlap in the X direction) a portion of portion 511A (e.g., a portion of the read channel region of transistor T1 of memory cell 211) and a portion of material 521 (e.g., a portion of the write channel region of transistor T2 of memory cell 211).

[0091] Access line 241, spanning (e.g., overlapping) portion 510A and material 520, allows access line 241 (a single access line) to control (e.g., turn on or off) two transistors T1 and T2 of memory cell 210 and two transistors of memory cell 211. Similarly, access line 241, spanning (e.g., overlapping) portion 511A and material 521, allows access line 241 (a single access line) to control (e.g., turn on or off) two transistors T1 and T2 of memory cell 211.

[0092] like Figure 5 As shown, the memory device 200 may include dielectric portions 531 and 532, wherein memory cells 210 and 211 may be located between dielectric portions 531 and 532. Dielectric portion 531 can electrically isolate memory cell 210 from another memory cell (e.g., a memory cell to the left of memory cell 210 (not shown)). Dielectric portion 532 can electrically isolate memory cell 211 from another memory cell (e.g., a memory cell to the right of memory cell 211 (not shown)).

[0093] like Figure 5 As shown, memory device 200 may include a dielectric (e.g., a dielectric material) 526, which may be formed to electrically separate (e.g., isolate) portions of two adjacent (in the X direction) memory cells of memory device 200. For example, dielectric 526 may electrically separate a material portion 510A (e.g., the read channel region of transistor T1 in memory cell 210) from a portion 521 (e.g., the read channel region of transistor T2 in memory cell 211). Figure 5As shown, dielectric 526 may include one side (e.g., the left side in the X direction) of a portion 510A (read channel region) that contacts memory cell 210 and one side (e.g., the right side in the X direction) of a portion 511A (read channel region) that contacts memory cell 211.

[0094] The dashed line 526D can indicate the imaginary boundary (e.g., the boundary between adjacent cells) of each memory cell 210 and 211. Figure 5 As shown, a portion 510A of memory cell 210 (e.g., a read channel region) is located outside memory cell 210 (near an imaginary boundary). Therefore, memory cell 210 can be said to include an external read channel region. Similarly, a portion 511A of memory cell 211 (e.g., a read channel region) is located outside memory cell 211 (near an imaginary boundary). Therefore, memory cell 211 can be said to include an external read channel region.

[0095] like Figure 5 As shown, portions (e.g., materials) of memory cells 210 and 211 may be formed adjacent to (e.g., on) the respective sidewalls of dielectric portions 531 and 532 (e.g., the portion perpendicular to the Z direction). For example, as Figure 5 As shown, a portion 510A of the memory cell 210 (e.g., a semiconductor material portion) may be formed adjacent to (e.g., formed on) the sidewall (not labeled) of the dielectric portion 531. In another example, as... Figure 5 As shown, a portion 511A of the memory cell 210 (e.g., a semiconductor material portion) may be formed adjacent to (e.g., on) the sidewall (not labeled) of the dielectric portion 532.

[0096] like Figure 6 As shown, memory device 200 may include dielectrics 518F and 518B (e.g., oxide regions) to electrically separate portions 541F and 541B of access lines 241 from other elements of memory cells 210 and 211 (e.g., portions 510A and 511A (e.g., read channel regions), charge storage structure 202, and materials 520 and 521). The materials (or materials) used for dielectrics 518F and 518B may be the same as (or alternatively, different from) the materials (or materials) used for dielectric 515A. Examples of materials used for portions 518F and 518B may include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

[0097] like Figure 6As shown, portions 541F and 541B may be adjacent to corresponding sides of the material 520 and charge storage structure 202 of memory cell 210. For example, portion 541F may be adjacent to one side of a portion of each of the material 520 and charge storage structure 202 (e.g., in...). Figure 6 In the view, on the right side in the X direction). In another example, portion 541B may be adjacent to the other side of a portion of each of material 520 and charge storage structure 202 (e.g., in Figure 6 In the view, on the left side in the X direction (opposite to the right side)).

[0098] The above description focuses on the structure of memory cell 210. Memory cell 211 may contain elements structured in a manner similar to or identical to the elements of memory cell 210 described above. For example, such as Figure 5 As shown, memory cell 211 may include charge storage structure 202, channel region (e.g., write channel region) 521, portion 581 (which is similar to portion 580), and portion 511A (e.g., read channel region). The material (or multiple materials) used for dielectrics 525A and 525B may be the same as the material (or multiple materials) used for dielectric 515A.

[0099] See above. Figures 2 to 6 As described, the connectivity and structure of memory device 200 allow cross-point operation because a single access line (e.g., access line 241) and a single data line (e.g., data line 221) can be used to access memory cells (e.g., memory cell 210) during operation of memory device 200 (e.g., read or write operations). This cross-point operation can be achieved in part by coupling the terminals (e.g., source terminals) of transistor T1 in each of the memory cells (e.g., memory cells 210 to 215) to a ground connection. This ground connection allows the voltage level at the terminals (e.g., source terminals) of transistor T1 in the selected memory cell to remain constant (e.g., remain at 0V without switching), thereby allowing cross-point operation. Compared to some conventional volatile memory devices (e.g., DRAM devices), the cross-point operation and structure of memory device 200 provide superior memory performance.

[0100] Figures 7 to 19 Different views of elements during the process of forming memory device 700 according to some embodiments described herein are shown. Some or all of the processes used to form memory device 700 can be used to form the above-described memory device 700. Figures 2 to 6 The memory device 200 described.

[0101] Figure 7The memory device 700 is shown after different material levels (e.g., layers) are formed on the substrate 799 in the Z direction of the memory device 700. The different material levels include dielectric material 790, semiconductor material 780, conductive material 782, material 720, material 702 and dielectric 715. Figure 7 The material layers shown can be formed on the substrate 799 in a sequential manner, one material following another. For example, Figure 7 The process used may include: forming (e.g., depositing) a dielectric material 790 over a substrate 799; forming (e.g., depositing) a semiconductor material 780 over the dielectric material 790; forming (e.g., depositing) a conductive material 782 over the semiconductor material 780; forming (e.g., depositing) a material 720 over the conductive material 782; forming (e.g., depositing) a material 702 over the material 720; and forming (e.g., depositing) a dielectric material 715 over the material 702.

[0102] Substrate 799 may be similar to or the same as Figure 5 The substrate 599 of the memory device 200. Dielectric materials 790 and 715 may comprise the same dielectric material or different dielectric materials. Each of dielectric materials 790 and 715 may comprise a nitride material (e.g., silicon nitride (e.g., Si3N4)), an oxide material (e.g., SiO2)) or other dielectric materials.

[0103] Semiconductor material 780 may contain and Figure 5 The materials 780 and 781 are the same. For example, semiconductor material 780 may comprise silicon, polysilicon, or other semiconductor materials, and may include doped regions (e.g., p-type doped regions). Conductive material 782 may comprise the same material as data lines 221 and 222 (e.g., metal, conductive doped polysilicon, or other conductive materials).

[0104] Material 702 may contain and Figure 5 The charge storage structure 202 of the memory cell 210 is made of the same material. For example, material 702 may comprise a charge storage material (or a combination of materials), which may comprise a semiconductor material (e.g., polysilicon), a metal, or other material capable of trapping charge.

[0105] Material 720 may include and Figure 5 The write channel region (e.g., material 520) of the transistor T2 in memory cell 210 is made of the same material. For example, material 720 may comprise a semiconductive material. The semiconductive material may comprise an oxide material. Examples of oxide materials include semiconductive oxide materials, transparent conductive oxide materials, and other oxide materials.

[0106] Figure 8 A memory device 700 is shown after trenches (e.g., openings) 801 and 802 have been formed. The formation of trenches 801 and 802 may include a portion of each of semiconductor material 780, conductive material 782, material 720, material 702, and dielectric material 715 removed (e.g., by patterning) at portions of trenches 801 and 802. The remaining portions of semiconductor material 780, conductive material 782, material 720, material 702, and dielectric material 715 are included in structures (e.g., device structures) 811, 812, and 813, such as... Figure 8 As shown in the image.

[0107] Each of trenches 801 and 802 may have a length in the Y direction, a width in the X direction (shorter than the length), and a bottom (not labeled) resting on a corresponding portion of the dielectric material 790 (e.g., defined by the corresponding portion). Structures 811, 812, and 813 may include corresponding sidewalls (e.g., opposite vertical sidewalls) 861, 862, 863, and 864, which also form the sidewalls of the corresponding trenches 801 and 802. For example, structure 811 may include sidewall 861, structure 812 may include sidewalls 862 and 863, and structure 813 may include sidewall 864. Sidewalls 861 and 862 may form the sidewalls of trench 801. Sidewalls 863 and 864 may form the sidewalls of trench 802.

[0108] Figure 9 A memory device 700 is shown after materials (e.g., sacrificial materials) 951 and 952 are formed in trenches 801 and 802, respectively. Examples of materials 951 and 952 include dielectric materials (e.g., silicon nitride).

[0109] Figure 10 A memory device 700 is shown after dielectric materials (e.g., dielectrics) 1015, 1025, 1015', and 1025' are formed on the respective sidewalls 861, 862, 863, and 864 of trenches 801 and 802. Figure 10 As shown, each of the dielectric materials (e.g., dielectrics) 1015, 1025, 1015' and 1025' is formed on a portion (not all) of the respective sidewalls 861, 862, 863 and 864, because another portion of each of the sidewalls 861, 862, 863 and 864 is occupied (e.g., blocked) by the dielectric material 951 or 952.

[0110] Figure 11The memory device 700 is shown after materials 951 and 952 have been removed. The removal of materials 951 and 952 exposes portions (sidewall portions) 1161, 1162, 1161', and 1162' of the sidewalls 863, 864, 861, and 862 in the corresponding trenches 801 and 802, respectively. Figure 11 As shown, portions 1161, 1162, 1161' and 1162' can be formed from corresponding portions of material 780.

[0111] Figure 12 A memory device 700 is shown after semiconductor materials 1210, 1211, 1210', and 1211' are formed adjacent to dielectric materials 1015, 1025, 1015', and 1025', respectively. The semiconductor materials 1210, 1211, 1210', and 1211' are electrically separated from each other. Figure 12 As shown, each of the semiconductor materials 1210, 1211, 1210', and 1211' is accessible (e.g., electrically coupled to) a portion of a corresponding sidewall among sidewalls 861, 862, 863, and 864 (e.g., portions of 1161, 1162, 1161', and 1162'). Therefore, Figure 12 Each of the semiconductor materials 1210, 1211, 1210', and 1211' can be contacted (e.g., electrically coupled to) 1161, 1162, 1161', and 1162'. Figure 11 The materials of structures 811, 812, and 813 exposed at ( ). For example, such as Figure 12 As shown, semiconductor material 1210 has semiconductor material 780 and conductive material 782 in contact with portion 812. Semiconductor material 1211 has semiconductor material 780 and conductive material 782 in contact with portion 813. Semiconductor material 1210' has semiconductor material 780 and conductive material 782 in contact with structure 811. Semiconductor material 1211' has semiconductor material 780 and conductive material 782 in contact with portion 812.

[0112] Figure 13 A memory device 700 is shown after trenches (e.g., openings) 1301, 1302, and 1303 have been formed. Forming trenches 1301, 1302, and 1303 may include removing (e.g., by patterning) portions of each of a semiconductor material 780, a conductive material 782, a material 720, a material 702, and a dielectric material 715 at locations within the trenches 1301, 1302, and 1303. Figure 13As shown, data lines 1318, 1319, 1320, 1321, 1322, and 1323 can be formed from the remaining portions of the conductive material 782 of structures 811, 812, and 813, respectively. Data lines 1318, 1319, 1320, 1321, 1322, and 1323 are electrically separated from each other. Each of data lines 1318, 1319, 1320, 1321, 1322, and 1323 can have a length in the Y direction (from...). Figure 13 (View hidden in the middle). Data lines 1321 and 1322 may correspond to memory device 200 respectively. Figure 2 and Figure 5 Data cables 221 and 222.

[0113] Figure 14 A memory device 700 is shown after the formation of dielectric materials (dielectrics) 1431, 1432, 1433, 1426, and 1426'. Dielectric materials 1431, 1432, and 1433 may be formed (e.g., deposited) in trenches 1301, 1302, and 1303, respectively. Figure 13 (indicated by the Chinese character). Dielectric material 1426 may be formed between semiconductor materials 1210 and 1211. Dielectric material 1426' may be formed between semiconductor materials 1210' and 1211'. Dielectric materials 1431, 1432, 1433, 1426 and 1426' may form a dielectric (e.g., cell isolation structure) between adjacent memory cells in the X direction.

[0114] Dielectric materials 1431, 1432, and 1433 may be formed simultaneously (e.g., in the same deposition process). Dielectric materials 1426 and 1426' may be formed simultaneously (e.g., in the same deposition process).

[0115] Dielectric materials 1431, 1432, and 1433 may be formed simultaneously with dielectric materials 1426 and 1426' (e.g., formed in the same deposition process). Alternatively, dielectric materials 1431, 1432, and 1433 may be formed at different times when dielectric materials 1426 and 1426' are formed (e.g., before or after the formation of dielectric materials).

[0116] Figure 12 , Figure 13 and Figure 14 Displayed in the formation of trenches 1301, 1302 and 1303 ( Figure 13 Examples of dielectric materials 1426 and 1426' are formed after ) . However, trenches 1301, 1302 and 1303 ( Figure 13 Dielectric materials 1426 and 1426' were formed prior to this. For example, with... Figure 12The associated processes may include forming semiconductor materials 1210, 1211, 1210' and 1211'. Figure 12 After that, and after the formation of trenches 1301, 1302 and 1303 ( Figure 13 Dielectric materials 1426 and 1426' were formed prior to this.

[0117] Figure 15 Display relative to Figure 14 A top view of the memory device 700 in the XY direction. For simplicity, this is not repeated. Figure 14 and Figure 15 The description of the same components shown in the image. Figure 15 As shown, the elements of memory device 700 may comprise strips (e.g., lines) of material having a length extending in the Y direction. Subsequent processes forming memory device 700 may include removing material downwards (e.g., cutting (e.g., etching) in the Z direction) from portions 1561, 1562, 1563, and 1564 (1561 to 1564) up to (terminating at) data lines 1319, 1320, 1321, and 1322 (…). Figure 13 In this manner, each of the data lines 1319, 1320, 1321, and 1322 (which have lengths extending in the Y direction) can be maintained to extend continuously in the Y direction and electrically coupled to the memory cells (e.g., in a row) in the Y direction. The material of the memory device 700 at locations 1571, 1572, and 1573 can be retained (and will be the part of the structure forming the respective memory cells of the memory device 700). Figure 16 The image shows a view of the memory device 700 along line 16-16 after material has been removed (e.g., cut) from locations 1561 to 1564.

[0118] Figure 16 Displayed in grooves (e.g., openings) 1661, 1662, 1663, and 1664 (1661 to 1664) respectively formed at portions 1561 to 1564. Figure 15 After point ) along the YZ direction Figure 15 A side view of the memory device 700 with lines 16-16. (See attached image.) Figure 16 As shown, material is removed from grooves 1661 to 1664 (locations 1561 to 1564), terminating at data line 1321 (e.g., downwards down to the data line) (and also at data lines 1319, 1320, and 1322). Figure 13 End at ) Figure 16 (Not shown in the text).

[0119] Grooves 1661 to 1664 can be formed by removing (e.g., cutting in the X direction) a portion of each of the materials at locations 1561 to 1564, said materials comprising dielectric material 715, material 702 (in... Figure 15 The middle is below material 715, and in Figure 15 Materials 720 (located below material 702), dielectric materials 1431, 1432 and 1433, dielectric materials 1426 and 1426', dielectric materials 1015, 1015', 1025 and 1025', and semiconductor materials 1210, 1210', 1211 and 1211'. Figure 16 In the structure (e.g., device structure) 1671, 1672 and 1673, portions 1615, 1602 and 1620 respectively form Figure 16 The dielectric materials 715, 702, and 720 following the trenches 1661 to 1664 in the middle ( Figure 15 The remainder of ). Each of structures 1671, 1672 and 1673 may be part of a memory cell in a subsequent process forming memory device 700.

[0120] Figure 17 The diagram shows dielectric materials (e.g., gate oxides) 1718B, 1718F, 1718B', 1718F', 1718B” and 1718F”, conductors (e.g., conductive regions) 1701, 1702, 1703, 1704, 1705 and 1706 (1701 to 1706), and dielectric materials 1706, 1707, 1708 and 1709 (1706 to 1709) formed in corresponding trenches 1661 to 1664. Figure 16 After the middle marker) Figure 16 The memory device 700. Each of the dielectric materials 1718B, 1718F, 1718B', 1718F', 1718B” and 1718F”, and dielectric materials 1706 to 1709 may comprise silicon dioxide or other dielectric materials. Each of the conductive wires 1701 to 1706 may comprise metal, conductive doped polysilicon, or other conductive materials.

[0121] Conductors 1701 to 1706 may form portions of access lines (e.g., word lines) to access memory cells 210', 212', and 214' of the memory device 700. Memory cells 210', 212', and 214' may respectively correspond to... Figure 2 The memory units 210, 212 and 214 of the memory device 200.

[0122] exist Figure 17In this context, wires 1701 and 1702 may form portions of access lines (e.g., word lines) to access memory cells 210' and other memory cells of the memory device 700. Figure 17 (Not shown in the image). Other such memory cells may be located in the same row as memory cell 210' in the X direction (e.g., Figure 18 (Memory cells 208', 209' and 211' shown in the figure).

[0123] exist Figure 17 In this context, wires 1703 and 1704 may form portions of access lines (e.g., word lines) to access memory cells 212' and other memory cells (not shown) of the memory device 700. Figure 17 The wires 1705 and 1706 in the memory device 700 may form portions of access lines (e.g., word lines) to access memory cells 214' and other memory cells (not shown).

[0124] like Figure 17 As shown, wire 1701 may have a portion adjacent to one side (e.g., the right side in the Y direction) of the channel region (e.g., portion 1620) of memory cell 210'. Wire 1702 may have a portion adjacent to the other side (e.g., the left side in the Y direction, opposite to the right side) of the channel region (e.g., portion 1620) of memory cell 210'.

[0125] Similarly, wires 1703 and 1704 may have corresponding portions (e.g., corresponding conductive regions) on the corresponding side (opposite side) in the Y direction adjacent to the channel region (e.g., read channel region) of memory cell 212'. Wires 1705 and 1706 may have corresponding portions (e.g., corresponding conductive regions) on the corresponding side (opposite side) in the Y direction adjacent to the channel region (e.g., read channel region) of memory cell 214'. Figure 18 Another view of the memory device 700 along line 18-18 is shown in the image.

[0126] Figure 18 Showing along the XZ direction Figure 17 The side view of line 18-18. Figure 18 In the image, wires 1701 and 1702 are partially shown to avoid interfering with other components of the memory device 700. For example... Figure 18 As shown, each of the conductors may have a length in the X direction, a width in the Z direction, and a thickness in the Y direction (e.g., less than the width) (shown in...). Figure 17 middle).

[0127] exist Figure 18In the middle, parts (semiconductor parts) 1610, 1611, 1610' and 1611' are respectively in Figure 16 After removing (e.g., cutting) a portion of each of 1210, 1211, 1210', and 1211' in the process (and in Figure 17 The process of forming conductors 1701 to 1706 in the process Figure 14 The remaining parts of 1210, 1211, 1210' and 1211'.

[0128] exist Figure 18 In the middle, the semiconductor parts 1615, 1625, 1615' and 1625' are respectively in Figure 16 After removing (e.g., cutting) a portion of each of 1015, 1025, 1015' and 1025' in the process (and in Figure 17 The process of forming conductors 1701 to 1706 in the process Figure 14 The remaining portions of 1015, 1025, 1015' and 1025'.

[0129] exist Figure 18 In the middle, dielectrics 1631, 1632 and 1633 are respectively in Figure 16 After removing (e.g., cutting) a portion of each of dielectric materials 1431, 1432, and 1433 in the process (and in Figure 17 The process of forming conductors 1701 to 1706 in the process Figure 14 The remaining portion of dielectric materials 1431, 1432 and 1433.

[0130] exist Figure 18 In the middle, dielectrics 1626 and 1626' are respectively in Figure 16 After removing (e.g., cutting) a portion of each of dielectric materials 1426 and 1426' in the process (and in Figure 17 The process of forming conductors 1701 to 1706 in the process Figure 14 The remaining portions of dielectric materials 1426 and 1426'. Each of dielectrics 1626 and 1626' may be formed into a structure for electrically separating (e.g., isolating) portions of two adjacent (in the X direction) memory cells of the memory device 200. Figure 16As shown, each of dielectrics 1626 and 1626' may include a side (e.g., the right and left sides in the X direction) that contacts a read channel region of an adjacent memory cell. For example, dielectric 1626 may include a side (e.g., the left side in the X direction) that contacts a portion 1610 (e.g., a read channel region) of memory cell 210' and a side (e.g., the right side in the X direction) that contacts a portion 1611 (e.g., a read channel region) of memory cell 211'.

[0131] exist Figure 18 In this process, each of the portions 1602 may form a charge storage structure (e.g., a memory element) for a corresponding memory cell among memory cells 208', 209', 210', and 211'. Each of the memory cells 208', 209', 210', and 211' may have a charge storage structure (e.g., a memory element) similar to... Figure 5 The memory device 200 has transistors T1 and T2. For simplicity, in Figure 18 Only transistors T1 and T2 of memory cell 210' are marked.

[0132] Each of portions 1610, 1611, 1610', and 1611' may form a channel region (e.g., a read channel region) of transistor T1 in a corresponding memory cell among memory cells 208', 209', 210', and 211'. Each of portions 1620 may form a channel region (e.g., a write channel region) of transistor T2 in a corresponding memory cell among memory cells 208', 209', 210', and 211'.

[0133] exist Figure 18 In this context, wires 1701 and 1702 may be portions of access lines (e.g., word lines) 1741 (which can receive signals (e.g., word line signals) WL1) to access memory cells 208', 209', 210', and 211' during operation of the memory device 700. Access line 1741 may correspond to... Figure 2 Access line 241 of memory device 200.

[0134] like Figure 18 As shown, a portion of wire 1701 may cross (e.g., overlap in the X direction) portions of portion 1610 and portion 1620 of memory cell 210'. As described above, portion 1610 may form a portion of the read channel region of transistor T1 of memory cell 210', and portion 1620 of memory cell 210' may form a portion of the write channel region of transistor T2 of memory cell 210'. Therefore, as Figure 18As shown, portions of wire 1701 may respectively cross (e.g., overlap) portions of both the read channel regions and write channel regions of transistors T1 and T2 in memory cell 210' (e.g., on one side (e.g., the front side) in the Y direction). Although from Figure 18 The view shown is hidden, but a portion of wire 1702 may cross (e.g., overlap in the X direction) a portion of portion 1610 of memory cell 210' (e.g., on the other side in the Y direction (e.g., the rear side opposite the front side)) and a portion of portion 1620 (e.g., the read channel region and write channel region of transistors T1 and T2, respectively).

[0135] Similarly, a portion of each of wires 1701 and 1702 may span a portion of the read channel region (e.g., portions 1610', 1611', or 1611) and a portion of the write channel region (e.g., portion 1620 above data lines 1319, 1320, or 1322) of each of memory cells 208', 209', and 211'.

[0136] form Figure 18 The process of forming the memory device 700 may include forming a conductive connection 1701' (which may comprise a conductive material (e.g., a metal)) for electrically coupling wires 1701 and 1702 to each other. Similarly, the process of forming the memory device 700 may include forming a conductive connection 1703 and 1704 for electrically coupling wires 1701 and 1702 to each other. Figure 17 Electrically coupled conductive connections (not shown) to each other and forming a connection for conductors 1705 and 1706 ( Figure 17 Electrically coupled conductive connections (not shown).

[0137] Figure 19 The memory device 700 is shown after a conductive plate 1997 has been formed (e.g., deposited) over other elements of the memory device 700 (e.g., memory cells 208', 209', 210', and 211'). Examples of materials used for the conductive plate 1997 include metals, conductive doped polysilicon, or other conductive materials. Figure 19 As shown, the conductive plate 1997 can contact (e.g., electrically couple to) portions (e.g., read channel regions) 1610, 1611, 1610' and 1611' of memory cells 208', 209', 210' and 211' respectively.

[0138] See Figures 11 to 19 The description of forming the memory device 700 may include other processes used to form the entire memory device. These processes are omitted from the above description to avoid obscuring the subject matter described herein.

[0139] Compared to some conventional processes, the process for forming the memory device 200, as described above, can have a relatively smaller number of masks (e.g., a smaller number of key masks). For example, by using... Figure 8 In the associated processes, trenches 801 and 802 are formed, and in conjunction with... Figure 16 Forming trenches 1661 to 1664 in the associated process reduces the number of critical masks used to form the memory cells of the memory device. This reduction in the number of masks simplifies the process of forming the memory device 200, reducing costs, or both. Furthermore, forming some of the elements (e.g., charge storage structures and write channel regions) using the techniques described herein is more advantageous than using other techniques. For example, some of the structures of the memory cells described herein (e.g., charge storage structures and write channel regions) can be formed by depositing one material over (e.g., on) another material instead of using other methods (e.g., atomic layer deposition). Using the techniques described herein can result in a more defined structure of the described memory cells (e.g., charge storage structures and write channel regions).

[0140] Figures 20 to 26 Different views of elements during the process of forming memory device 2000 according to some embodiments described herein are shown. The process of forming memory device 2000 may be forming memory device 700 ( Figures 7 to 19 The process is a variation of the process. Therefore, similar elements (with the same markings) between the processes of forming memory devices 700 and 2000 are not repeated.

[0141] Figure 20 The display can be used to form from Figures 7 to 12 The elements of the memory device 700 are formed using similar or identical processes to those of the memory device 2000. Therefore, Figure 20 The components of the memory device 2000 shown herein can be similar to Figure 12 The components of the memory device 700 shown in the figure.

[0142] like Figure 20 As shown, the memory device 2000 may include data lines 2020, 2021, and 2022 in corresponding structures 811, 812, and 813. Each of the data lines 2020, 2021, and 2022 is formed of a conductive material, which may be... Figure 12 The conductive material 782 is included in the respective structures of structures 811, 812, and 813, as shown in the diagram. Data lines 2020, 2021, and 2022 are electrically separated from each other. Each of data lines 2020, 2021, and 2022 may have a length in the Y direction (from...). Figure 20(View hidden in the middle). Data lines 2021 and 2022 may correspond to memory device 200 ( Figure 2 and Figure 5 Data cables 221 and 222.

[0143] Figure 21 A memory device 700 is shown after dielectric materials 2131 and 2132 have been formed. Dielectric material 2131 may be formed between semiconductor materials 1210' and 1211'. Dielectric material 2132 may be formed between semiconductor materials 1210 and 1211.

[0144] Figure 22 Display relative to Figure 21 A top view of the memory device 2000 in the XY direction. Subsequent processes forming the memory device 2000 may include removing material downwards (e.g., cutting (e.g., etching) in the Z direction) from portions 1561 to 1564 up to (terminating at) data lines 2020, 2021, and 2022. Figure 21 In this way, each of the data lines 2020, 2021 and 2022 (which have lengths extending in the Y direction) can be kept to extend continuously in the Y direction and electrically coupled to the memory cells (e.g., in a row) in the Y direction. Figure 23 The image shows a view of the memory device 2000 along line 22-22 after the material at locations 1561 to 1564 has been removed.

[0145] Figure 23 The grooves 1661 to 1664 are formed at locations 1561 to 1564 respectively. Figure 22 The position after which, relative to the YZ direction Figure 22 The side view along line 23-23. (See also...) Figure 23 As shown, material is removed from grooves 1661 to 1664, terminating (e.g., downwards until) data line 2021 (and also terminating at data lines 2020 and 2022). Figure 20 ), Figure 23 (Not shown in the text). The material at locations 1561 to 1564 (as mentioned above) can be removed (including dielectric material 715, material 702 (in...). Figure 22 The middle is below material 715, and in Figure 22 The portions of each of the materials 720 located below material 702 are used to form grooves 1661 to 1664. Figure 23 In the structures (e.g., device structures) 1671, 1672, and 1673, portions 1615, 1602, and 1620 are respectively the remaining portions of dielectric material 715, material 702, and material 720 after the trenches 1661 to 1664 are formed. Figure 22 Each of structures 1671, 1672, and 1673 may be part of a memory cell in a subsequent process forming memory device 700.

[0146] Figure 24 The diagram shows dielectric materials (e.g., gate oxides) 1718B, 1718F, 1718B', 1718F', 1718B” and 1718F”, conductors (e.g., conductive regions) 1701, 1702, 1703, 1704, 1705 and 1706 (1701 to 1706), and dielectric materials 1706, 1707, 1708 and 1709 (1706 to 1709) formed in corresponding trenches 1661 to 1664. Figure 23 The memory device 2000 is marked with a middle label. Wires 1701 to 1706 may form portions of access lines (e.g., word lines) to access memory cells 210', 212', and 214' of the memory device 2000. Memory cells 210', 212', and 214' may respectively correspond to... Figure 2 The memory units 210, 212 and 214 of the memory device 200. Figure 25 Another view of the memory device 2000 along line 25-25 is shown in the image.

[0147] Figure 25 Showing along the XZ direction Figure 24 The side view of line 25-25. In Figure 25 Partially showing wires 1701 and 1702 to avoid interfering with other components of the memory device 2000. Wires 1701 and 1702 are electrically connected to 1701' (see above). Figure 17 and Figure 18 (As described) electrically coupled to each other.

[0148] exist Figure 25 In this process, each of the portions 1602 may form a charge storage structure (e.g., a memory element) for a corresponding memory cell among memory cells 209', 210', and 211'. Each of the memory cells 209', 210', and 211' may have a charge storage structure similar to... Figure 5 The memory device 200 has transistors T1 and T2. For simplicity, in Figure 25 Only transistors T1 and T2 of memory cell 210' are marked.

[0149] Each of the portions 1620 may form a portion of the channel region (e.g., write channel region) of the transistor T2 of the corresponding memory cell in memory cells 209', 210', and 211'. For example, the portion 1620 above the data line 2021 may form a portion of the channel region (e.g., write channel region) of the transistor T2 of memory cell 210'.

[0150] A combination of portions 1610 and 1611' (e.g., two semiconductor portions) can form a portion of the channel region (e.g., read channel region) of the transistor T1 of memory cell 210'. Each of the memory cells 209' and 211' of memory device 200 may also include two semiconductor portions that can form the channel region (e.g., read channel region) of the transistor T1 of the memory cell. However, Figure 25 Only one of the two semiconductor portions of transistor T1 (unlabeled) in each of memory cells 209' and 211' is shown. For example, Figure 25 A portion 1610' of the channel region of transistor T1 that can form memory cell 209' and a portion 1611 of the channel region of transistor T1 that can form memory cell 211' are shown.

[0151] therefore, Figure 25 Each of the memory cells in the memory device 2000 may have two separate semiconductor portions (e.g., Figure 25 The portions 1610 and 1611' of the memory cell 210' form a channel region (e.g., a read channel region) in the corresponding memory cell. Compared to Figure 18 The memory device 700 shown herein may have each of its memory cells having a (e.g., a single) semiconductor portion (e.g., Figure 18 The portion 1610 of the memory cell 210' forms the channel region (e.g., the read channel region) of the corresponding memory cell.

[0152] exist Figure 25 In this context, wires 1701 and 1702 may be portions of access lines (e.g., word lines) 1741 (which can receive signals (e.g., word line signals) WL1) to access memory cells 209', 210', and 211' during operation of the memory device 700. Access line 1741 may correspond to... Figure 2 Access lines 241 of the memory device 200. For example... Figure 25 As shown, a portion of wire 1701 may cross (e.g., overlap in the X direction) portions 1610 and 1611' of memory cell 210' and a portion 1620. Therefore, as Figure 25As shown, a portion of wire 1701 may span (e.g., overlap) portions of both the read channel region and write channel region of transistors T1 and T2 in memory cell 210' (e.g., on one side in the Y direction (e.g., the front side)). A portion of wire 1702 may span (e.g., overlap in the X direction) portions of portions 1610 and 1611' of memory cell 210' (e.g., on the other side in the Y direction (e.g., the rear side opposite the front side) and portions of portion 1620 (e.g., the read channel region and write channel region of transistors T1 and T2, respectively). Similarly, portions of each of wires 1701 and 1702 may span portions of the read channel region and write channel region of each of memory cells 209' and 211'.

[0153] Figure 26 The memory device 2000 is shown after a conductive plate 2697 has been formed (e.g., deposited) over other elements of the memory device 2000 (e.g., memory cells 209', 210', and 211'). The conductive plate 2697 may correspond to... Figure 19 The conductive plate from 1997. (For example...) Figure 26 As shown, conductive plate 2697 can contact (e.g., electrically coupled to) portions of memory cell 210' (e.g., read channel regions) 1610 and 1611' (e.g., in...). Figure 25 (in the middle mark), a portion of memory cell 209' (e.g., a portion of the read channel region) 1610' (e.g., in the middle mark), Figure 25 (marked in the middle) and parts (e.g., reading a portion of the channel region) 1611 (e.g., in Figure 25 (marked in the middle).

[0154] See Figures 20 to 26 The description of the formation of the memory device 2000 may include other processes used to form the entire memory device. These processes are omitted from the above description to avoid obscuring the subject matter described herein.

[0155] Figure 27A , Figure 27B and Figure 27C Different views are shown illustrating the structure of a memory device 2700 according to some embodiments described herein, the memory device comprising multiple stacks of memory cells. Figure 27A An exploded view of the memory device 2700 is shown (e.g., in the Z direction). Figure 27B The memory device 2700 is shown in a side view (e.g., a cross-sectional view) in the X and Z directions. Figure 27C The memory device 2700 is shown in side views (e.g., cross-sectional views) in the Y and Z directions.

[0156] like Figure 27AAs shown, the memory device 2700 may comprise stacks (stacks of memory cells) 27050, 27051, 27052, and 27053, shown separately in the exploded view to facilitate easy inspection of the stack structure of the memory device 2700. In practice, stacks 27050, 27051, 27052, and 27053 may be attached to each other on a substrate (e.g., a semiconductor (e.g., silicon) substrate) 2799 in an arrangement where one stack may be formed on (e.g., stacked on) another stack. For example, as... Figure 27A As shown, stacks 27050, 27051, 27052 and 27053 can be formed in the Z direction perpendicular to the substrate 2799 (e.g., formed perpendicularly to the Z direction relative to the substrate 2799).

[0157] like Figure 27A As shown, each of stacks 27050, 27051, 27052, and 27053 may have memory cells arranged in both the X and Y directions (e.g., in rows in the X direction and in columns in the Y direction). For example, stack 27050 may include memory cells 27100, 27110, 27120, and 27130 (e.g., arranged in rows), memory cells 27200, 27210, 27220, and 27230 (e.g., arranged in rows), and memory cells 27300, 27310, 27320, and 27330 (e.g., arranged in rows).

[0158] Stack 27051 may include memory cells 27101, 27111, 27121 and 27131 (e.g., arranged in rows), memory cells 27201, 27211, 27221 and 27231 (e.g., arranged in rows), and memory cells 27301, 27311, 27321 and 27331 (e.g., arranged in rows).

[0159] Stack 27052 may include memory cells 27102, 27112, 27122 and 27132 (e.g., arranged in rows), memory cells 27202, 27212, 27222 and 27232 (e.g., arranged in rows), and memory cells 27302, 27312, 27322 and 27332 (e.g., arranged in rows).

[0160] Stack 27053 may include memory cells 27103, 27113, 27123 and 27133 (e.g., arranged in rows), memory cells 27203, 27213, 27223 and 27233 (e.g., arranged in rows), and memory cells 27303, 27313, 27323 and 27333 (e.g., arranged in rows).

[0161] like Figure 27A As shown, stacks 27050, 27051, 27052, and 27053 may be located on layers (e.g., portions) 2750, 2751, 2752, and 2753 of the memory device 2700 (e.g., formed vertically in the Z direction). The arrangement of stacks 27050, 27051, 27052, and 27053 forms a 3D structure of the memory cells of the memory device 2700, because different layers of the memory cells of the memory device 2700 may be located (e.g., formed on) different layers (e.g., different vertical portions) 2750, 2751, 2752, and 2753 of the memory device 2700.

[0162] Stacks 27050, 27051, 27052, and 27053 can be formed one stack at a time. For example, stacks 27050, 27051, 27052, and 27053 can be formed sequentially in the order of stacks 27050, 27051, 27052, and 27053 (e.g., stack 27050 is formed first and stack 27053 is formed last). In this example, the memory cells of one stack (e.g., stack 27051) can be formed after the memory cells of another stack (e.g., stack 27050) are formed or before the memory cells of another stack (e.g., stack 27052) are formed. Alternatively, stacks 27050, 27051, 27052, and 27053 can be formed simultaneously (e.g., synchronously) so that memory cells of stacks 27050, 27051, 27052, and 27053 can be formed simultaneously. For example, memory cells in levels 2750, 2751, 2752, and 2753 of memory device 2700 can be formed simultaneously.

[0163] The structure of the memory cells in each of stacks 27050, 27051, 27052, and 27053 may include the structure described above. Figures 1 to 26 The structure of the memory cells described. For example, the structure of the memory cells in stacks 27050, 27051, 27052 and 27053 may include the structure of the memory cells in memory devices 200, 700 and 2000.

[0164] Memory device 2700 may include data lines (e.g., bit lines) and access lines (e.g., word lines) to access memory cells of stacks 27050, 27051, 27052, and 27053. For simplicity, from Figure 27A The data lines and access lines of the memory cells are omitted. However, the data lines and access lines of the memory device 2700 can be similar to those described above. Figures 1 to 26 The data lines and access lines of the described memory device.

[0165] Figure 27A A memory device 2700 comprising four stacks (e.g., 27050, 27051, 27052, and 27053) is shown as an example. However, the number of stacks may be different from four. Figure 27A Each of stacks 27050, 27051, 27052, and 27053 is shown as an example containing one level (e.g., a layer) of memory cells. However, at least one of the stacks (e.g., one or more of stacks 27050, 27051, 27052, and 27053) may have two (or more) levels of memory cells. Figure 27A Examples of stacks 27050, 27051, 27052, and 27053 are shown, each containing four memory cells in the X direction (e.g., in a row) and three memory cells in the Y direction (e.g., in a column). However, the number of memory cells in a row, a column, or both can vary.

[0166] The description of devices (e.g., memory devices 100, 200, 700, 2000, and 2700) and methods (e.g., operation of memory devices 100 and 200 and methods of forming memory devices 700 and 2700) is intended to provide a general understanding of the structure of the various embodiments and is not intended to provide a complete description of all elements and features of devices that may utilize the structures described herein. Device herein refers to, for example, an apparatus (e.g., any of memory devices 100, 200, 700, 2000, and 2700) or a system (e.g., an electronic article that may include any of memory devices 100, 200, 700, 2000, and 2700).

[0167] See above Figures 1 to 27C Any of the components described can be implemented in a variety of ways, including via software simulation. Therefore, a portion of any device (e.g., memory devices 100, 200, 700, 2000, and 2700) or any of the memory devices described above can be characterized herein as a “multiple module” (or “module”). Depending on need and / or suitability for specific implementations of various embodiments, such modules may include hardware circuitry systems, single-processor and / or multi-processor circuitry, memory circuitry, software program modules and objects and / or firmware, and combinations thereof. For example, such modules may be included in system operation simulation packages, such as software electrical signal simulation packages, power usage and range simulation packages, capacitor-inductor simulation packages, power / heat dissipation simulation packages, signal transmit-receive simulation packages, and / or combinations of software and hardware for operating or simulating the operation of various possible embodiments.

[0168] The memory devices described herein (e.g., memory devices 100, 200, 700, 2000, and 2700) may be included in devices (e.g., electronic circuit systems) such as: high-speed computers, communication and signal processing circuit systems, single-processor or multi-processor modules, single or multiple embedded processors, multi-core processors, message exchangers, and dedicated modules comprising multi-layer, multi-chip modules. Such devices may be further included as sub-components within a variety of other devices (e.g., electronic systems) such as: televisions, cellular phones, personal computers (e.g., laptops, desktops, handhelds, tablets, etc.), workstations, radios, video players, audio players (e.g., MP3 players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, and others.

[0169] See above Figures 1 to 27C The described embodiments include an apparatus and a method of forming said apparatus. One of the apparatuses includes: a substrate; a conductive plate located above the substrate for coupled ground connection; a data line located between the substrate and the conductive plate; a memory cell; and a wire. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The wire is electrically separated from the first and second regions and traverses a portion of the first region of the first transistor and a portion of the second region of the second transistor, and forms the gate of the first and second transistors. Other embodiments including additional apparatus and methods are described.

[0170] In the embodiments and claims, the term "on" (one on another) used with respect to two or more elements (e.g., materials) means at least some contact between the elements (e.g., between materials). The term "over" means that the elements (e.g., materials) are close together, but may have one or more additional intervening elements (e.g., materials) that make contact possible but not required. Unless stated otherwise, neither "on" nor "over" implies any directionality as used herein.

[0171] In the embodiments and claims, a list of items joined by the term "at least one of..." can mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0172] In the embodiments and claims, a list of items joined by the term "one of..." can mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means only A (excluding B) or only B (excluding A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0173] The foregoing description and figures illustrate some embodiments of the subject matter of this invention to enable those skilled in the art to practice these embodiments. Other embodiments may incorporate structural changes, logical changes, electrical changes, process changes, and other modifications. Examples represent only possible variations. Parts and features of some embodiments may be included in or replace those parts and features of other embodiments. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the foregoing description.

Claims

1. A memory device comprising: Substrate; A conductive plate is located above the substrate and is coupled to ground. A data line located between the substrate and the conductive plate; A memory cell comprising: A first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure separate from the first region; and The second transistor includes a second region electrically coupled to the charge storage structure and the data line; and A wire, electrically separate from the first region and the second region, a portion of the wire crossing a portion of the first region of the first transistor and forming the gate of the first transistor and the second transistor, wherein: The charge storage structure is stacked on the second region; The second region is stacked on the data line; The first region is adjacent to one side of the charge storage structure; The first region is adjacent to one side of the second region; and The first region is located on one side of the data line and contacts that side of the data line.

2. The memory device of claim 1, wherein the first region comprises a p-type semiconductor material and the second region comprises an n-type semiconductor material.

3. The memory device of claim 1, wherein the second region comprises a semiconductive oxide material.

4. The memory device according to claim 1, further comprising: Additional data lines, located between the substrate and the conductive plate; and Additional memory unit, the additional memory unit comprising: A first additional transistor includes a first additional region electrically coupled to the additional data line and the conductive plate, and an additional charge storage structure separate from the first additional region; and The second additional transistor includes a second additional region electrically coupled to the additional charge storage structure and the additional data line; The wire is electrically separated from the first additional region and the second additional region, and the additional portion of the wire spans a portion of the first additional region of the first additional transistor and a portion of the second additional region of the second additional transistor.

5. The memory device of claim 1, wherein the first transistor and the second transistor have different threshold voltages.

6. The memory device of claim 1, wherein when the charge storage structure is in a first state, the first transistor has a first threshold voltage less than zero, and when the charge storage structure is in a second state, the first transistor has a second threshold voltage less than zero, and the first state and the second state represent different values ​​of information stored in the memory cell.

7. The memory device of claim 1, further comprising additional memory cells, wherein the memory cells are included in a first stack of memory cells of the memory device, the additional memory cells are included in a second stack of additional memory cells of the memory device, and the first stack of memory cells and the second stack of memory cells are located in different levels of the memory device.

8. A memory device comprising: A first conductive region, located in the first level of the memory device; A second conductive region is located in the first layer of the memory device and is electrically separated from the first conductive region; A conductive plate, located in the second layer of the memory device; A first memory cell includes: a first charge storage structure; and a first region for conducting current between the first conductive region and the conductive plate during a first operation of the memory device. and a second region for conducting current between the first conductive region and the first charge storage structure during a second operation of the memory device, wherein: The first charge storage structure is stacked on the second region; The second region is stacked on top of the first conductive region; The first region is adjacent to one side of the first charge storage structure; The first region is adjacent to one side of the second region; and The first region is located on one side of the first conductive region and contacts the same side of the first conductive region; A second memory cell includes: a second charge storage structure; a first additional region for conducting current between the second conductive region and the conductive plate during a third operation of the memory device; and a second additional region for conducting current between the second conductive region and the second charge storage structure during a fourth operation of the memory device, wherein: The second charge storage structure is stacked on the second additional region; The second additional region is stacked on top of the second conductive region; The first additional region is adjacent to one side of the second charge storage structure; The first additional region is adjacent to one side of the second additional region; and The first additional region is located on one side of the second conductive region and contacts said side of the second conductive region; A dielectric material located between the first memory cell and the second memory cell, the dielectric material including a first side contacting the first region and a second side contacting the first additional region; and A conductor electrically separated from the first region and the second region, as well as the first additional region and the second additional region, and a portion of the conductor spans a portion of the first region and the second region, as well as a portion of the first additional region and the second additional region.

9. The memory device of claim 8, further comprising a substrate, wherein the first conductive region and the second conductive region are located between the conductive plate and the substrate.

10. The memory device of claim 9, wherein the conductive plate comprises a ground plane.

11. The memory device of claim 8, wherein the first region and the second region comprise materials of different conductivity types, and the first additional region and the second additional region comprise materials of different conductivity types.

12. The memory device according to claim 8, wherein: The first conductive region is a portion of the first data line of the memory device; The second conductive region is a portion of the second data line of the memory device; and The conductor is a portion of the word line of the memory device.

13. The memory device of claim 8, further comprising an additional wire opposite to the wire, wherein: The additional conductor is electrically separated from the first region and the second region, as well as the first additional region and the second additional region, and a portion of the conductor crosses a portion of the first region and the second region, as well as a portion of the first additional region and the second additional region.

14. The memory device of claim 13, wherein the additional wire is electrically coupled to the wire.

15. The memory device of claim 8, wherein each of the second region and the second additional region comprises at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO). x Indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO) x In₂O₃), tin oxide (SnO₂), titanium oxide (TiO₂), zinc oxide (ZnO₂) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O z Indium gallium zinc oxide (In) x Ga y Zn z O a Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf) x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ), silicon indium zinc (Si) x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum oxide zinc tin (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconia zinc tin (Zr) x Zn y Sn z O a Indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

16. A method for forming a memory device, the method comprising: Data lines are formed above the substrate; A memory cell is formed above the substrate, such that each of the memory cells includes a first transistor and a second transistor, the first transistor including a charge storage structure located above the data line in the data line and a first channel region contacting the data line, and the second transistor including a second channel region separate from the first channel region and formed above the charge storage structure and the data line and contacting the charge storage structure and the data line. A wire is formed such that each of the wires is electrically separated from the first channel region and the second channel region of the corresponding memory cell in the memory cell, and a portion of each of the wires crosses a portion of each of the first channel region and the second channel region of the corresponding memory cell in the memory cell. and A ground plane is formed above the wire and in contact with the first channel region of the first transistor in each of the memory cells, wherein in the respective memory cells: The charge storage structure is stacked on the second channel region; The second channel region is stacked on the data line; The first channel region is adjacent to one side of the charge storage structure; The first channel region is adjacent to one side of the second channel region; and The first channel region is located on one side of the data line and contacts that side of the data line.

17. A method for forming a memory device, the method comprising: Data lines are formed above the substrate; A memory cell is formed above the substrate, such that each of the memory cells includes a first transistor and a second transistor, the first transistor including a charge storage structure located above the data line in the data line and a first channel region contacting the data line, and the second transistor including a second channel region separate from the first channel region and formed above the charge storage structure and the data line and contacting the charge storage structure and the data line. A wire is formed such that each of the wires is electrically separated from the first channel region and the second channel region of the corresponding memory cell in the memory cell, and a portion of each of the wires crosses a portion of each of the first channel region and the second channel region of the corresponding memory cell in the memory cell. and A ground plane is formed above the conductor and in contact with each of the memory cells in the first channel region of the first transistor, wherein forming the memory cell comprises: A material hierarchy is formed above the substrate; Grooves are formed in the material hierarchy such that each of the grooves includes a sidewall of length in a first direction, formed by a portion of the remainder of each of the material hierarchy, and the sidewall includes a sidewall portion formed by a portion of a corresponding data line among the data lines. and A first channel region is formed in a corresponding trench in the trench for each of the memory cells, such that the first channel region contacts the sidewall portion of the sidewall of the corresponding trench in the trench.

18. The method of claim 17, wherein forming the wire comprises: Additional grooves are formed in the remaining portion of each of the material layers, such that each of the additional grooves includes a length in the second direction; and The conductors are formed in the additional trench, such that each of the conductors is formed in a corresponding trench in the additional trench.

19. The method of claim 17, wherein forming the material layer over the substrate comprises: Forming the first semiconductor material; A conductive material is formed on top of the first semiconductor material; A second semiconductor material is formed on top of the conductive material; and A charge storage material is formed on top of an additional semiconductor material.

20. The method of claim 19, wherein forming the data line comprises: When the trench is formed, a portion of the conductive material at the location of the trench is removed to form the data line from the remaining portion of the conductive material.

21. The method of claim 19, wherein forming the memory cell comprises: When the trench is formed, a portion of the second semiconductor material at the location of the trench is removed to form the second channel region of each of the memory cells from the remaining portion of the second semiconductor material; and When the trench is formed, a portion of the charge storage material at the location of the trench is removed to form the charge storage structure of each of the memory cells from the remaining portion of the charge storage material.

22. The method of claim 19, wherein the second semiconductor material comprises a semiconducting oxide material.

23. A method for forming a memory device, the method comprising: A material hierarchy is formed above the substrate; A first trench is formed in the material layer by removing a portion of the material layer, such that each of the first trenches includes a length in a first direction, a first sidewall formed by a first portion of the remaining portion of each of the material layers, and a second sidewall formed by a second portion of the remaining portion of each of the material layers. A first dielectric is formed on a first portion of the first sidewall of each of the first trenches; A first additional dielectric is formed on a first portion of the second sidewall of each of the first trenches; A first semiconductor material is formed in the second portion of the first sidewall adjacent to the first dielectric and in contact with each of the first trenches; A first additional semiconductor material is formed in a second portion of the second sidewall adjacent to the first additional dielectric and in contact with each of the first trenches; In each of the first trenches, a second dielectric is formed between the first semiconductor material and the first additional semiconductor material; and A second trench is formed in a second direction to form a memory cell by removing a portion of the remaining portion of each of the material layers, a portion of each of the first dielectric, a portion of the first additional dielectric, a portion of the second dielectric, a portion of the first semiconductor material, and a portion of the first additional semiconductor material, such that a first memory cell in the memory cell contains at least a portion of the remaining portion of the semiconductor material, and a second memory cell in the memory cell contains at least a portion of the remaining portion of the first additional semiconductor material.

24. The method of claim 23, wherein forming the material layer over the substrate comprises: Forming semiconductor materials; A conductive material is formed on top of the semiconductor material; An additional semiconductor material is formed on top of the conductive material; and A charge storage material is formed on top of the additional semiconductor material.

25. The method of claim 24, wherein the semiconductor material has p-type conductivity.

26. The method of claim 24, wherein the additional semiconductor material comprises a semiconducting oxide material.

27. The method of claim 24, wherein the additional semiconductor material comprises at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO). x Indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO) x In₂O₃), tin oxide (SnO₂), titanium oxide (TiO₂), zinc oxide (ZnO₂) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O z Indium gallium zinc oxide (In) x Ga y Zn z O a Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf) x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ), silicon indium zinc (Si) x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum oxide zinc tin (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconia zinc tin (Zr) x Zn y Sn z O a Indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

28. The method of claim 24, wherein the second portion of the first sidewall is formed by the first portion of the conductive material, and the second portion of the second sidewall is formed by the second portion of the conductive material.

29. The method according to claim 24, wherein: The first memory cell includes a charge storage structure formed by one of the material layers of the first portion of the first sidewall of the trench adjacent to the first trench; and The second memory cell includes a charge storage structure formed by one of the material layers of the first portion of the second sidewall of the trench adjacent to the first trench.

30. The method of claim 24, further comprising: A conductive plate is formed that contacts the remaining portion of the semiconductor material and the remaining portion of the additional semiconductor material.

31. The method of claim 24, further comprising: A wire is formed in each of the second trenches such that the wire has a length in the second direction and is electrically separated from the memory cell.

32. The method of claim 24, further comprising: An additional wire is formed in each of the second trenches, such that the additional wire has a length in the second direction and is electrically separate from the memory cell.

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